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You searched for +publisher:"Virginia Tech" +contributor:("Schaumont, Patrick Robert"). Showing records 1 – 30 of 117 total matches.

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Virginia Tech

1. Huang, Sinan. Hardware Evaluation of SHA-3 Candidates.

Degree: MS, Electrical and Computer Engineering, 2011, Virginia Tech

 Cryptographic hash functions are used extensively in information security, most notably in digital authentication and data integrity verification. Their performance is an important factor of… (more)

Subjects/Keywords: Cryptography; Security; SHA-3; Hardware Evaluation

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APA (6th Edition):

Huang, S. (2011). Hardware Evaluation of SHA-3 Candidates. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/32932

Chicago Manual of Style (16th Edition):

Huang, Sinan. “Hardware Evaluation of SHA-3 Candidates.” 2011. Masters Thesis, Virginia Tech. Accessed February 23, 2020. http://hdl.handle.net/10919/32932.

MLA Handbook (7th Edition):

Huang, Sinan. “Hardware Evaluation of SHA-3 Candidates.” 2011. Web. 23 Feb 2020.

Vancouver:

Huang S. Hardware Evaluation of SHA-3 Candidates. [Internet] [Masters thesis]. Virginia Tech; 2011. [cited 2020 Feb 23]. Available from: http://hdl.handle.net/10919/32932.

Council of Science Editors:

Huang S. Hardware Evaluation of SHA-3 Candidates. [Masters Thesis]. Virginia Tech; 2011. Available from: http://hdl.handle.net/10919/32932


Virginia Tech

2. Nanjundappa, Mahesh. Accelerating Hardware Simulation on Multi-cores.

Degree: MS, Electrical and Computer Engineering, 2010, Virginia Tech

 Electronic design automation (EDA) tools play a central role in bridging the productivity gap for designing complex hardware systems. However, with an increase in the… (more)

Subjects/Keywords: POSIX threads; Discrete Event Simulation (DES); CUDA; SystemC Simulation; GPGPU; Multi-core simulation; Threading Building Blocks

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APA (6th Edition):

Nanjundappa, M. (2010). Accelerating Hardware Simulation on Multi-cores. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/33002

Chicago Manual of Style (16th Edition):

Nanjundappa, Mahesh. “Accelerating Hardware Simulation on Multi-cores.” 2010. Masters Thesis, Virginia Tech. Accessed February 23, 2020. http://hdl.handle.net/10919/33002.

MLA Handbook (7th Edition):

Nanjundappa, Mahesh. “Accelerating Hardware Simulation on Multi-cores.” 2010. Web. 23 Feb 2020.

Vancouver:

Nanjundappa M. Accelerating Hardware Simulation on Multi-cores. [Internet] [Masters thesis]. Virginia Tech; 2010. [cited 2020 Feb 23]. Available from: http://hdl.handle.net/10919/33002.

Council of Science Editors:

Nanjundappa M. Accelerating Hardware Simulation on Multi-cores. [Masters Thesis]. Virginia Tech; 2010. Available from: http://hdl.handle.net/10919/33002


Virginia Tech

3. Zuo, Yongbo. Fair Comparison of ASIC Performance for SHA-3 Finalists.

Degree: MS, Electrical and Computer Engineering, 2012, Virginia Tech

 In the last few decades, secure algorithms have played an irreplaceable role in the protection of private information, such as applications of AES on modems,… (more)

Subjects/Keywords: SHA; NIST; ASIC; Finalist; Hardware; Encryption; Hash; Cipher; Key

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APA (6th Edition):

Zuo, Y. (2012). Fair Comparison of ASIC Performance for SHA-3 Finalists. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/33446

Chicago Manual of Style (16th Edition):

Zuo, Yongbo. “Fair Comparison of ASIC Performance for SHA-3 Finalists.” 2012. Masters Thesis, Virginia Tech. Accessed February 23, 2020. http://hdl.handle.net/10919/33446.

MLA Handbook (7th Edition):

Zuo, Yongbo. “Fair Comparison of ASIC Performance for SHA-3 Finalists.” 2012. Web. 23 Feb 2020.

Vancouver:

Zuo Y. Fair Comparison of ASIC Performance for SHA-3 Finalists. [Internet] [Masters thesis]. Virginia Tech; 2012. [cited 2020 Feb 23]. Available from: http://hdl.handle.net/10919/33446.

Council of Science Editors:

Zuo Y. Fair Comparison of ASIC Performance for SHA-3 Finalists. [Masters Thesis]. Virginia Tech; 2012. Available from: http://hdl.handle.net/10919/33446


Virginia Tech

4. Gora, Michael Arthur. Securing Software Intellectual Property on Commodity and Legacy Embedded Systems.

Degree: MS, Electrical and Computer Engineering, 2010, Virginia Tech

 The proliferation of embedded systems into nearly every aspect of modern infrastructure and society has seen their deployment in such diverse roles as monitoring the… (more)

Subjects/Keywords: Secure Embedded Systems; Software; Intellectual Property; Firmware; Security; FPGA; Design Flow; Physical Unclonable Function

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APA (6th Edition):

Gora, M. A. (2010). Securing Software Intellectual Property on Commodity and Legacy Embedded Systems. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/33473

Chicago Manual of Style (16th Edition):

Gora, Michael Arthur. “Securing Software Intellectual Property on Commodity and Legacy Embedded Systems.” 2010. Masters Thesis, Virginia Tech. Accessed February 23, 2020. http://hdl.handle.net/10919/33473.

MLA Handbook (7th Edition):

Gora, Michael Arthur. “Securing Software Intellectual Property on Commodity and Legacy Embedded Systems.” 2010. Web. 23 Feb 2020.

Vancouver:

Gora MA. Securing Software Intellectual Property on Commodity and Legacy Embedded Systems. [Internet] [Masters thesis]. Virginia Tech; 2010. [cited 2020 Feb 23]. Available from: http://hdl.handle.net/10919/33473.

Council of Science Editors:

Gora MA. Securing Software Intellectual Property on Commodity and Legacy Embedded Systems. [Masters Thesis]. Virginia Tech; 2010. Available from: http://hdl.handle.net/10919/33473


Virginia Tech

5. Irick, Charles Robert. Enhancing GNU Radio for Hardware Accelerated Radio Design.

Degree: MS, Electrical and Computer Engineering, 2010, Virginia Tech

 As technology evolves and new methods for designing radios arise, it becomes necessary to continue the search for fast and flexible development environments. Some of… (more)

Subjects/Keywords: Virtex-5; FPGA; GNU Radio; SDR

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APA (6th Edition):

Irick, C. R. (2010). Enhancing GNU Radio for Hardware Accelerated Radio Design. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/33474

Chicago Manual of Style (16th Edition):

Irick, Charles Robert. “Enhancing GNU Radio for Hardware Accelerated Radio Design.” 2010. Masters Thesis, Virginia Tech. Accessed February 23, 2020. http://hdl.handle.net/10919/33474.

MLA Handbook (7th Edition):

Irick, Charles Robert. “Enhancing GNU Radio for Hardware Accelerated Radio Design.” 2010. Web. 23 Feb 2020.

Vancouver:

Irick CR. Enhancing GNU Radio for Hardware Accelerated Radio Design. [Internet] [Masters thesis]. Virginia Tech; 2010. [cited 2020 Feb 23]. Available from: http://hdl.handle.net/10919/33474.

Council of Science Editors:

Irick CR. Enhancing GNU Radio for Hardware Accelerated Radio Design. [Masters Thesis]. Virginia Tech; 2010. Available from: http://hdl.handle.net/10919/33474


Virginia Tech

6. Tavaragiri, Abhay. A Management Paradigm for FPGA Design Flow Acceleration.

Degree: MS, Electrical and Computer Engineering, 2011, Virginia Tech

 Advances in FPGA density and complexity have not been matched by a corresponding improvement in the performance of the implementation tools. Knowledge of incremental changes… (more)

Subjects/Keywords: FPGA Management Technique; XML; Productivity; TORC

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APA (6th Edition):

Tavaragiri, A. (2011). A Management Paradigm for FPGA Design Flow Acceleration. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/33923

Chicago Manual of Style (16th Edition):

Tavaragiri, Abhay. “A Management Paradigm for FPGA Design Flow Acceleration.” 2011. Masters Thesis, Virginia Tech. Accessed February 23, 2020. http://hdl.handle.net/10919/33923.

MLA Handbook (7th Edition):

Tavaragiri, Abhay. “A Management Paradigm for FPGA Design Flow Acceleration.” 2011. Web. 23 Feb 2020.

Vancouver:

Tavaragiri A. A Management Paradigm for FPGA Design Flow Acceleration. [Internet] [Masters thesis]. Virginia Tech; 2011. [cited 2020 Feb 23]. Available from: http://hdl.handle.net/10919/33923.

Council of Science Editors:

Tavaragiri A. A Management Paradigm for FPGA Design Flow Acceleration. [Masters Thesis]. Virginia Tech; 2011. Available from: http://hdl.handle.net/10919/33923


Virginia Tech

7. Krishnamoorthy, Saparya. Strategies for Scalable Symbolic Execution-based Test Generation.

Degree: MS, Electrical and Computer Engineering, 2010, Virginia Tech

 With the advent of advanced program analysis and constraint solving techniques, several test generation tools use variants of symbolic execution. Symbolic techniques have been shown… (more)

Subjects/Keywords: symbolic execution; software verification; dynamic test generation; path explosion; satisfiability modulo theories

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APA (6th Edition):

Krishnamoorthy, S. (2010). Strategies for Scalable Symbolic Execution-based Test Generation. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/33997

Chicago Manual of Style (16th Edition):

Krishnamoorthy, Saparya. “Strategies for Scalable Symbolic Execution-based Test Generation.” 2010. Masters Thesis, Virginia Tech. Accessed February 23, 2020. http://hdl.handle.net/10919/33997.

MLA Handbook (7th Edition):

Krishnamoorthy, Saparya. “Strategies for Scalable Symbolic Execution-based Test Generation.” 2010. Web. 23 Feb 2020.

Vancouver:

Krishnamoorthy S. Strategies for Scalable Symbolic Execution-based Test Generation. [Internet] [Masters thesis]. Virginia Tech; 2010. [cited 2020 Feb 23]. Available from: http://hdl.handle.net/10919/33997.

Council of Science Editors:

Krishnamoorthy S. Strategies for Scalable Symbolic Execution-based Test Generation. [Masters Thesis]. Virginia Tech; 2010. Available from: http://hdl.handle.net/10919/33997


Virginia Tech

8. Sinha, Ambuj Sudhir. Design Techniques for Side-channel Resistant Embedded Software.

Degree: MS, Electrical and Computer Engineering, 2011, Virginia Tech

 Side Channel Attacks (SCA) are a class of passive attacks on cryptosystems that exploit implementation characteristics of the system. Currently, a lot of research is… (more)

Subjects/Keywords: Bitslice Cryptography; Side Channel Attacks; Virtual Secure Circuit; Secure Embedded Systems; Side-channel Countermeasures

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APA (6th Edition):

Sinha, A. S. (2011). Design Techniques for Side-channel Resistant Embedded Software. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/34465

Chicago Manual of Style (16th Edition):

Sinha, Ambuj Sudhir. “Design Techniques for Side-channel Resistant Embedded Software.” 2011. Masters Thesis, Virginia Tech. Accessed February 23, 2020. http://hdl.handle.net/10919/34465.

MLA Handbook (7th Edition):

Sinha, Ambuj Sudhir. “Design Techniques for Side-channel Resistant Embedded Software.” 2011. Web. 23 Feb 2020.

Vancouver:

Sinha AS. Design Techniques for Side-channel Resistant Embedded Software. [Internet] [Masters thesis]. Virginia Tech; 2011. [cited 2020 Feb 23]. Available from: http://hdl.handle.net/10919/34465.

Council of Science Editors:

Sinha AS. Design Techniques for Side-channel Resistant Embedded Software. [Masters Thesis]. Virginia Tech; 2011. Available from: http://hdl.handle.net/10919/34465


Virginia Tech

9. Pimenta Pereira, Karl Savio. Characterization of FPGA-based High Performance Computers.

Degree: MS, Electrical and Computer Engineering, 2011, Virginia Tech

 As CPU clock frequencies plateau and the doubling of CPU cores per processor exacerbate the memory wall, hybrid core computing, utilizing CPUs augmented with FPGAs… (more)

Subjects/Keywords: FFT; molecular dynamics; integer-point; floating-point; GPU; HPC; FPGA

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APA (6th Edition):

Pimenta Pereira, K. S. (2011). Characterization of FPGA-based High Performance Computers. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/34483

Chicago Manual of Style (16th Edition):

Pimenta Pereira, Karl Savio. “Characterization of FPGA-based High Performance Computers.” 2011. Masters Thesis, Virginia Tech. Accessed February 23, 2020. http://hdl.handle.net/10919/34483.

MLA Handbook (7th Edition):

Pimenta Pereira, Karl Savio. “Characterization of FPGA-based High Performance Computers.” 2011. Web. 23 Feb 2020.

Vancouver:

Pimenta Pereira KS. Characterization of FPGA-based High Performance Computers. [Internet] [Masters thesis]. Virginia Tech; 2011. [cited 2020 Feb 23]. Available from: http://hdl.handle.net/10919/34483.

Council of Science Editors:

Pimenta Pereira KS. Characterization of FPGA-based High Performance Computers. [Masters Thesis]. Virginia Tech; 2011. Available from: http://hdl.handle.net/10919/34483


Virginia Tech

10. Couch, Jacob Donald. Applications of TORC: An Open Toolkit for Reconfigurable Computing.

Degree: MS, Electrical and Computer Engineering, 2011, Virginia Tech

 Two research projects are proposed that rely on Tools for open Reconfigurable Computing (TORC) and the openness of the Xilinx tool chain. The first project,… (more)

Subjects/Keywords: Xilinx; TORC; qFlow; tFlow; Unconventional Transmitters; FPGA

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APA (6th Edition):

Couch, J. D. (2011). Applications of TORC: An Open Toolkit for Reconfigurable Computing. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/34624

Chicago Manual of Style (16th Edition):

Couch, Jacob Donald. “Applications of TORC: An Open Toolkit for Reconfigurable Computing.” 2011. Masters Thesis, Virginia Tech. Accessed February 23, 2020. http://hdl.handle.net/10919/34624.

MLA Handbook (7th Edition):

Couch, Jacob Donald. “Applications of TORC: An Open Toolkit for Reconfigurable Computing.” 2011. Web. 23 Feb 2020.

Vancouver:

Couch JD. Applications of TORC: An Open Toolkit for Reconfigurable Computing. [Internet] [Masters thesis]. Virginia Tech; 2011. [cited 2020 Feb 23]. Available from: http://hdl.handle.net/10919/34624.

Council of Science Editors:

Couch JD. Applications of TORC: An Open Toolkit for Reconfigurable Computing. [Masters Thesis]. Virginia Tech; 2011. Available from: http://hdl.handle.net/10919/34624


Virginia Tech

11. Iyer, Srikrishna. A Unifying Interface Abstraction for Accelerated Computing in Sensor Nodes.

Degree: MS, Electrical and Computer Engineering, 2011, Virginia Tech

 Hardware-software co-design techniques are very suitable to develop the next generation of sensornet applications, which have high computational demands. By making use of a low… (more)

Subjects/Keywords: Communication Interface-Abstraction Architecture; automatic code-generation; TinyOS; nesC; GEZEL; hardware/software co-design; co-processor; wireless sensor nodes; CPU; FPGA

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APA (6th Edition):

Iyer, S. (2011). A Unifying Interface Abstraction for Accelerated Computing in Sensor Nodes. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/34625

Chicago Manual of Style (16th Edition):

Iyer, Srikrishna. “A Unifying Interface Abstraction for Accelerated Computing in Sensor Nodes.” 2011. Masters Thesis, Virginia Tech. Accessed February 23, 2020. http://hdl.handle.net/10919/34625.

MLA Handbook (7th Edition):

Iyer, Srikrishna. “A Unifying Interface Abstraction for Accelerated Computing in Sensor Nodes.” 2011. Web. 23 Feb 2020.

Vancouver:

Iyer S. A Unifying Interface Abstraction for Accelerated Computing in Sensor Nodes. [Internet] [Masters thesis]. Virginia Tech; 2011. [cited 2020 Feb 23]. Available from: http://hdl.handle.net/10919/34625.

Council of Science Editors:

Iyer S. A Unifying Interface Abstraction for Accelerated Computing in Sensor Nodes. [Masters Thesis]. Virginia Tech; 2011. Available from: http://hdl.handle.net/10919/34625


Virginia Tech

12. Shagrithaya, Kavya Subraya. Enabling Development of OpenCL Applications on FPGA platforms.

Degree: MS, Electrical and Computer Engineering, 2012, Virginia Tech

 FPGAs can potentially deliver tremendous acceleration in high-performance server and em- bedded computing applications. Whether used to augment a processor or as a stand-alone device,… (more)

Subjects/Keywords: FPGA; AutoESL; OpenCL; Convey; HPC

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APA (6th Edition):

Shagrithaya, K. S. (2012). Enabling Development of OpenCL Applications on FPGA platforms. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/34669

Chicago Manual of Style (16th Edition):

Shagrithaya, Kavya Subraya. “Enabling Development of OpenCL Applications on FPGA platforms.” 2012. Masters Thesis, Virginia Tech. Accessed February 23, 2020. http://hdl.handle.net/10919/34669.

MLA Handbook (7th Edition):

Shagrithaya, Kavya Subraya. “Enabling Development of OpenCL Applications on FPGA platforms.” 2012. Web. 23 Feb 2020.

Vancouver:

Shagrithaya KS. Enabling Development of OpenCL Applications on FPGA platforms. [Internet] [Masters thesis]. Virginia Tech; 2012. [cited 2020 Feb 23]. Available from: http://hdl.handle.net/10919/34669.

Council of Science Editors:

Shagrithaya KS. Enabling Development of OpenCL Applications on FPGA platforms. [Masters Thesis]. Virginia Tech; 2012. Available from: http://hdl.handle.net/10919/34669


Virginia Tech

13. Priya, Kanu. Study of Physical Unclonable Functions at Low Voltage on FPGA.

Degree: MS, Electrical and Computer Engineering, 2011, Virginia Tech

 Physical Unclonable Functions (PUFs) provide a secure, power efficient and non-volatile means of chip identification. These are analogous to one-way functions that are easy to… (more)

Subjects/Keywords: Low Power; Stability; Physical Unclonable Functions; Ring Oscillator; Process Variation; Uniqueness

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APA (6th Edition):

Priya, K. (2011). Study of Physical Unclonable Functions at Low Voltage on FPGA. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/34709

Chicago Manual of Style (16th Edition):

Priya, Kanu. “Study of Physical Unclonable Functions at Low Voltage on FPGA.” 2011. Masters Thesis, Virginia Tech. Accessed February 23, 2020. http://hdl.handle.net/10919/34709.

MLA Handbook (7th Edition):

Priya, Kanu. “Study of Physical Unclonable Functions at Low Voltage on FPGA.” 2011. Web. 23 Feb 2020.

Vancouver:

Priya K. Study of Physical Unclonable Functions at Low Voltage on FPGA. [Internet] [Masters thesis]. Virginia Tech; 2011. [cited 2020 Feb 23]. Available from: http://hdl.handle.net/10919/34709.

Council of Science Editors:

Priya K. Study of Physical Unclonable Functions at Low Voltage on FPGA. [Masters Thesis]. Virginia Tech; 2011. Available from: http://hdl.handle.net/10919/34709


Virginia Tech

14. Vivekraja, Vignesh. Low-Power, Stable and Secure On-Chip Identifiers Design.

Degree: MS, Electrical and Computer Engineering, 2010, Virginia Tech

 Trustworthy authentication of an object is of extreme importance for secure protocols. Traditional methods of storing the identity of an object using non-volatile memory is… (more)

Subjects/Keywords: Hardware Security; Low Power; Process Variation; PUF

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APA (6th Edition):

Vivekraja, V. (2010). Low-Power, Stable and Secure On-Chip Identifiers Design. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/34854

Chicago Manual of Style (16th Edition):

Vivekraja, Vignesh. “Low-Power, Stable and Secure On-Chip Identifiers Design.” 2010. Masters Thesis, Virginia Tech. Accessed February 23, 2020. http://hdl.handle.net/10919/34854.

MLA Handbook (7th Edition):

Vivekraja, Vignesh. “Low-Power, Stable and Secure On-Chip Identifiers Design.” 2010. Web. 23 Feb 2020.

Vancouver:

Vivekraja V. Low-Power, Stable and Secure On-Chip Identifiers Design. [Internet] [Masters thesis]. Virginia Tech; 2010. [cited 2020 Feb 23]. Available from: http://hdl.handle.net/10919/34854.

Council of Science Editors:

Vivekraja V. Low-Power, Stable and Secure On-Chip Identifiers Design. [Masters Thesis]. Virginia Tech; 2010. Available from: http://hdl.handle.net/10919/34854


Virginia Tech

15. Morozov, Sergey Victorovich. Elliptic Curve Cryptography on Heterogeneous Multicore Platform.

Degree: MS, Electrical and Computer Engineering, 2010, Virginia Tech

 Elliptic curve cryptography (ECC) is becoming the algorithm of choice for digital signature generation and authentication in embedded context. However, performance of ECC and the… (more)

Subjects/Keywords: Binary Field; DSP; ARM; Cryptography; Elliptic Curve; Prime Field; Multiprocessor; Point Multiplication; Multicore

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APA (6th Edition):

Morozov, S. V. (2010). Elliptic Curve Cryptography on Heterogeneous Multicore Platform. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/34872

Chicago Manual of Style (16th Edition):

Morozov, Sergey Victorovich. “Elliptic Curve Cryptography on Heterogeneous Multicore Platform.” 2010. Masters Thesis, Virginia Tech. Accessed February 23, 2020. http://hdl.handle.net/10919/34872.

MLA Handbook (7th Edition):

Morozov, Sergey Victorovich. “Elliptic Curve Cryptography on Heterogeneous Multicore Platform.” 2010. Web. 23 Feb 2020.

Vancouver:

Morozov SV. Elliptic Curve Cryptography on Heterogeneous Multicore Platform. [Internet] [Masters thesis]. Virginia Tech; 2010. [cited 2020 Feb 23]. Available from: http://hdl.handle.net/10919/34872.

Council of Science Editors:

Morozov SV. Elliptic Curve Cryptography on Heterogeneous Multicore Platform. [Masters Thesis]. Virginia Tech; 2010. Available from: http://hdl.handle.net/10919/34872


Virginia Tech

16. Agrawal, Ambuj. Implementation of Application Layer Protocol for an Active RFID System.

Degree: MS, Electrical and Computer Engineering, 2011, Virginia Tech

 The emerging technology of active RFID tags has strong potential in the areas of real time health monitoring, sorting of cargo, and large scale inventory… (more)

Subjects/Keywords: TagSense Inc.; accelerometer; CC2591; CC2520; ATmega328P

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APA (6th Edition):

Agrawal, A. (2011). Implementation of Application Layer Protocol for an Active RFID System. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/34961

Chicago Manual of Style (16th Edition):

Agrawal, Ambuj. “Implementation of Application Layer Protocol for an Active RFID System.” 2011. Masters Thesis, Virginia Tech. Accessed February 23, 2020. http://hdl.handle.net/10919/34961.

MLA Handbook (7th Edition):

Agrawal, Ambuj. “Implementation of Application Layer Protocol for an Active RFID System.” 2011. Web. 23 Feb 2020.

Vancouver:

Agrawal A. Implementation of Application Layer Protocol for an Active RFID System. [Internet] [Masters thesis]. Virginia Tech; 2011. [cited 2020 Feb 23]. Available from: http://hdl.handle.net/10919/34961.

Council of Science Editors:

Agrawal A. Implementation of Application Layer Protocol for an Active RFID System. [Masters Thesis]. Virginia Tech; 2011. Available from: http://hdl.handle.net/10919/34961


Virginia Tech

17. Bakshi, Dhrumeel. Techniques for Seed Computation and Testability Enhancement for Logic Built-In Self Test.

Degree: MS, Electrical and Computer Engineering, 2012, Virginia Tech

 With the increase of device complexity and test-data volume required to guarantee adequate defect coverage, external testing is becoming increasingly difficult and expensive. Logic Built-in… (more)

Subjects/Keywords: Satisfiability Modulo Theories (SMT); LFSR Reseeding; Logic Built-In Self Test (LBIST); Integer Linear Programming (ILP); Test-point Insertion

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APA (6th Edition):

Bakshi, D. (2012). Techniques for Seed Computation and Testability Enhancement for Logic Built-In Self Test. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/35474

Chicago Manual of Style (16th Edition):

Bakshi, Dhrumeel. “Techniques for Seed Computation and Testability Enhancement for Logic Built-In Self Test.” 2012. Masters Thesis, Virginia Tech. Accessed February 23, 2020. http://hdl.handle.net/10919/35474.

MLA Handbook (7th Edition):

Bakshi, Dhrumeel. “Techniques for Seed Computation and Testability Enhancement for Logic Built-In Self Test.” 2012. Web. 23 Feb 2020.

Vancouver:

Bakshi D. Techniques for Seed Computation and Testability Enhancement for Logic Built-In Self Test. [Internet] [Masters thesis]. Virginia Tech; 2012. [cited 2020 Feb 23]. Available from: http://hdl.handle.net/10919/35474.

Council of Science Editors:

Bakshi D. Techniques for Seed Computation and Testability Enhancement for Logic Built-In Self Test. [Masters Thesis]. Virginia Tech; 2012. Available from: http://hdl.handle.net/10919/35474


Virginia Tech

18. Rahagude, Nikhil Prakash. Integrated Enhancement of Testability and Diagnosability for Digital Circuits.

Degree: MS, Electrical and Computer Engineering, 2010, Virginia Tech

 While conventional test point insertions commonly used in design for testability can improve fault coverage, the test points selected may not necessarily be the best… (more)

Subjects/Keywords: Fault Coverage; Diagnostic Resolution; Weighted Average; Test Point Insertion; Design for Testability; Design for Diagnosability; Built-in Self Test

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APA (6th Edition):

Rahagude, N. P. (2010). Integrated Enhancement of Testability and Diagnosability for Digital Circuits. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/35609

Chicago Manual of Style (16th Edition):

Rahagude, Nikhil Prakash. “Integrated Enhancement of Testability and Diagnosability for Digital Circuits.” 2010. Masters Thesis, Virginia Tech. Accessed February 23, 2020. http://hdl.handle.net/10919/35609.

MLA Handbook (7th Edition):

Rahagude, Nikhil Prakash. “Integrated Enhancement of Testability and Diagnosability for Digital Circuits.” 2010. Web. 23 Feb 2020.

Vancouver:

Rahagude NP. Integrated Enhancement of Testability and Diagnosability for Digital Circuits. [Internet] [Masters thesis]. Virginia Tech; 2010. [cited 2020 Feb 23]. Available from: http://hdl.handle.net/10919/35609.

Council of Science Editors:

Rahagude NP. Integrated Enhancement of Testability and Diagnosability for Digital Circuits. [Masters Thesis]. Virginia Tech; 2010. Available from: http://hdl.handle.net/10919/35609


Virginia Tech

19. Parekh, Umang Kumar. A Toolkit for Rapid FPGA System Deployment.

Degree: MS, Electrical and Computer Engineering, 2010, Virginia Tech

 FPGA implementation tools have not kept pace with growing FPGA density. It is common for non-trivial designs to take multiple hours to go through the… (more)

Subjects/Keywords: Router; Virtex-4; Toolkit; Autonomous; FPGA

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APA (6th Edition):

Parekh, U. K. (2010). A Toolkit for Rapid FPGA System Deployment. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/35703

Chicago Manual of Style (16th Edition):

Parekh, Umang Kumar. “A Toolkit for Rapid FPGA System Deployment.” 2010. Masters Thesis, Virginia Tech. Accessed February 23, 2020. http://hdl.handle.net/10919/35703.

MLA Handbook (7th Edition):

Parekh, Umang Kumar. “A Toolkit for Rapid FPGA System Deployment.” 2010. Web. 23 Feb 2020.

Vancouver:

Parekh UK. A Toolkit for Rapid FPGA System Deployment. [Internet] [Masters thesis]. Virginia Tech; 2010. [cited 2020 Feb 23]. Available from: http://hdl.handle.net/10919/35703.

Council of Science Editors:

Parekh UK. A Toolkit for Rapid FPGA System Deployment. [Masters Thesis]. Virginia Tech; 2010. Available from: http://hdl.handle.net/10919/35703


Virginia Tech

20. Bhardwaj, Prabhaav. Framework for Hardware Agility on FPGAs.

Degree: MS, Electrical and Computer Engineering, 2010, Virginia Tech

 As hardware applications become increasingly complex, the supporting technology needs to evolve and adapt to the demands. Field Programmable Gate Array (FPGA), Application Specific Integrated… (more)

Subjects/Keywords: Virtex 5; Dynamic Routing; FPGA; Reconfigurable Computing

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APA (6th Edition):

Bhardwaj, P. (2010). Framework for Hardware Agility on FPGAs. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/36347

Chicago Manual of Style (16th Edition):

Bhardwaj, Prabhaav. “Framework for Hardware Agility on FPGAs.” 2010. Masters Thesis, Virginia Tech. Accessed February 23, 2020. http://hdl.handle.net/10919/36347.

MLA Handbook (7th Edition):

Bhardwaj, Prabhaav. “Framework for Hardware Agility on FPGAs.” 2010. Web. 23 Feb 2020.

Vancouver:

Bhardwaj P. Framework for Hardware Agility on FPGAs. [Internet] [Masters thesis]. Virginia Tech; 2010. [cited 2020 Feb 23]. Available from: http://hdl.handle.net/10919/36347.

Council of Science Editors:

Bhardwaj P. Framework for Hardware Agility on FPGAs. [Masters Thesis]. Virginia Tech; 2010. Available from: http://hdl.handle.net/10919/36347


Virginia Tech

21. Sohanghpurwala, Ali Asgar Ali Akbar. OpenPR: An Open-Source Partial Reconfiguration Tool-Kit for Xilinx FPGAs.

Degree: MS, Electrical and Computer Engineering, 2010, Virginia Tech

 The Xilinx Partial Reconfiguration tool kits have been instrumental for performing a wide variety of research on Xilinx FPGAs. These tool kits provide a methodology… (more)

Subjects/Keywords: open-source; FPGA; partial-reconfiguration

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APA (6th Edition):

Sohanghpurwala, A. A. A. A. (2010). OpenPR: An Open-Source Partial Reconfiguration Tool-Kit for Xilinx FPGAs. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/36348

Chicago Manual of Style (16th Edition):

Sohanghpurwala, Ali Asgar Ali Akbar. “OpenPR: An Open-Source Partial Reconfiguration Tool-Kit for Xilinx FPGAs.” 2010. Masters Thesis, Virginia Tech. Accessed February 23, 2020. http://hdl.handle.net/10919/36348.

MLA Handbook (7th Edition):

Sohanghpurwala, Ali Asgar Ali Akbar. “OpenPR: An Open-Source Partial Reconfiguration Tool-Kit for Xilinx FPGAs.” 2010. Web. 23 Feb 2020.

Vancouver:

Sohanghpurwala AAAA. OpenPR: An Open-Source Partial Reconfiguration Tool-Kit for Xilinx FPGAs. [Internet] [Masters thesis]. Virginia Tech; 2010. [cited 2020 Feb 23]. Available from: http://hdl.handle.net/10919/36348.

Council of Science Editors:

Sohanghpurwala AAAA. OpenPR: An Open-Source Partial Reconfiguration Tool-Kit for Xilinx FPGAs. [Masters Thesis]. Virginia Tech; 2010. Available from: http://hdl.handle.net/10919/36348


Virginia Tech

22. Asthana, Rohit Mohan. High-Level CSP Model Compiler for FPGAs.

Degree: MS, Electrical and Computer Engineering, 2010, Virginia Tech

 The ever-growing competition in current electronics industry has resulted in stringent time-to-market goals and reduced design time available to engineers. Lesser design time has subsequently… (more)

Subjects/Keywords: High-Level Synthesis; FPGAs; Models of Computation (MoC); Communicating Sequential Processes (CSP); Autocode Generation

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APA (6th Edition):

Asthana, R. M. (2010). High-Level CSP Model Compiler for FPGAs. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/36428

Chicago Manual of Style (16th Edition):

Asthana, Rohit Mohan. “High-Level CSP Model Compiler for FPGAs.” 2010. Masters Thesis, Virginia Tech. Accessed February 23, 2020. http://hdl.handle.net/10919/36428.

MLA Handbook (7th Edition):

Asthana, Rohit Mohan. “High-Level CSP Model Compiler for FPGAs.” 2010. Web. 23 Feb 2020.

Vancouver:

Asthana RM. High-Level CSP Model Compiler for FPGAs. [Internet] [Masters thesis]. Virginia Tech; 2010. [cited 2020 Feb 23]. Available from: http://hdl.handle.net/10919/36428.

Council of Science Editors:

Asthana RM. High-Level CSP Model Compiler for FPGAs. [Masters Thesis]. Virginia Tech; 2010. Available from: http://hdl.handle.net/10919/36428


Virginia Tech

23. Tang, Yi. SUNSHINE: Integrate TOSSIM and P-Sim.

Degree: MS, Electrical and Computer Engineering, 2011, Virginia Tech

 Simulators are important tools for wireless sensor network (sensornet) design and evaluation. However, existing simulators only support evaluations of protocols and software aspects of sensornet… (more)

Subjects/Keywords: Sensor networks; cross-domain simulator; hardware-software co-simulation

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APA (6th Edition):

Tang, Y. (2011). SUNSHINE: Integrate TOSSIM and P-Sim. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/40721

Chicago Manual of Style (16th Edition):

Tang, Yi. “SUNSHINE: Integrate TOSSIM and P-Sim.” 2011. Masters Thesis, Virginia Tech. Accessed February 23, 2020. http://hdl.handle.net/10919/40721.

MLA Handbook (7th Edition):

Tang, Yi. “SUNSHINE: Integrate TOSSIM and P-Sim.” 2011. Web. 23 Feb 2020.

Vancouver:

Tang Y. SUNSHINE: Integrate TOSSIM and P-Sim. [Internet] [Masters thesis]. Virginia Tech; 2011. [cited 2020 Feb 23]. Available from: http://hdl.handle.net/10919/40721.

Council of Science Editors:

Tang Y. SUNSHINE: Integrate TOSSIM and P-Sim. [Masters Thesis]. Virginia Tech; 2011. Available from: http://hdl.handle.net/10919/40721


Virginia Tech

24. Pabbuleti, Krishna Chaitanya. Performance Optimization of Public Key Cryptography on Embedded Platforms.

Degree: MS, Electrical and Computer Engineering, 2014, Virginia Tech

 Embedded systems are so ubiquitous that they account for almost 90% of all the computing devices. They range from very small scale devices with an… (more)

Subjects/Keywords: Elliptic Curve Cryptography; Modular Arithmetic; SIMD; Hash-based Signatures; MSP430; Wireless Sensor Node

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APA (6th Edition):

Pabbuleti, K. C. (2014). Performance Optimization of Public Key Cryptography on Embedded Platforms. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/48120

Chicago Manual of Style (16th Edition):

Pabbuleti, Krishna Chaitanya. “Performance Optimization of Public Key Cryptography on Embedded Platforms.” 2014. Masters Thesis, Virginia Tech. Accessed February 23, 2020. http://hdl.handle.net/10919/48120.

MLA Handbook (7th Edition):

Pabbuleti, Krishna Chaitanya. “Performance Optimization of Public Key Cryptography on Embedded Platforms.” 2014. Web. 23 Feb 2020.

Vancouver:

Pabbuleti KC. Performance Optimization of Public Key Cryptography on Embedded Platforms. [Internet] [Masters thesis]. Virginia Tech; 2014. [cited 2020 Feb 23]. Available from: http://hdl.handle.net/10919/48120.

Council of Science Editors:

Pabbuleti KC. Performance Optimization of Public Key Cryptography on Embedded Platforms. [Masters Thesis]. Virginia Tech; 2014. Available from: http://hdl.handle.net/10919/48120


Virginia Tech

25. Mane, Deepak Hanamant. Energy-harvested Lightweight Cryptosystems.

Degree: MS, Electrical and Computer Engineering, 2014, Virginia Tech

 The Internet of Things will include many resource-constrained lightweight wireless sensing devices, hungry for energy, bandwidth and compute cycles. The sheer amount of devices involved… (more)

Subjects/Keywords: Public Key Cryptography; Elliptic Curves; RFID; Wireless Sensor Node; Energy Harvesting; Throughput; Digital signatures

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APA (6th Edition):

Mane, D. H. (2014). Energy-harvested Lightweight Cryptosystems. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/48124

Chicago Manual of Style (16th Edition):

Mane, Deepak Hanamant. “Energy-harvested Lightweight Cryptosystems.” 2014. Masters Thesis, Virginia Tech. Accessed February 23, 2020. http://hdl.handle.net/10919/48124.

MLA Handbook (7th Edition):

Mane, Deepak Hanamant. “Energy-harvested Lightweight Cryptosystems.” 2014. Web. 23 Feb 2020.

Vancouver:

Mane DH. Energy-harvested Lightweight Cryptosystems. [Internet] [Masters thesis]. Virginia Tech; 2014. [cited 2020 Feb 23]. Available from: http://hdl.handle.net/10919/48124.

Council of Science Editors:

Mane DH. Energy-harvested Lightweight Cryptosystems. [Masters Thesis]. Virginia Tech; 2014. Available from: http://hdl.handle.net/10919/48124


Virginia Tech

26. Zhou, Dao. Ultra Low-Power Wireless Sensor Node for Structural Health Monitoring.

Degree: MS, Electrical and Computer Engineering, 2010, Virginia Tech

 Structural Health Monitoring (SHM) is the technology of monitoring and assessing the condition of aerospace, civil, and mechanical infrastructures using a sensing system integrated into… (more)

Subjects/Keywords: Structural Health Monitoring; wireless sensor; impedance-based mothed; low power; temperature compesation

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APA (6th Edition):

Zhou, D. (2010). Ultra Low-Power Wireless Sensor Node for Structural Health Monitoring. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/31103

Chicago Manual of Style (16th Edition):

Zhou, Dao. “Ultra Low-Power Wireless Sensor Node for Structural Health Monitoring.” 2010. Masters Thesis, Virginia Tech. Accessed February 23, 2020. http://hdl.handle.net/10919/31103.

MLA Handbook (7th Edition):

Zhou, Dao. “Ultra Low-Power Wireless Sensor Node for Structural Health Monitoring.” 2010. Web. 23 Feb 2020.

Vancouver:

Zhou D. Ultra Low-Power Wireless Sensor Node for Structural Health Monitoring. [Internet] [Masters thesis]. Virginia Tech; 2010. [cited 2020 Feb 23]. Available from: http://hdl.handle.net/10919/31103.

Council of Science Editors:

Zhou D. Ultra Low-Power Wireless Sensor Node for Structural Health Monitoring. [Masters Thesis]. Virginia Tech; 2010. Available from: http://hdl.handle.net/10919/31103


Virginia Tech

27. Hu, Wei. Sufficiency-based Filtering of Invariants for Sequential Equivalence Checking.

Degree: MS, Electrical and Computer Engineering, 2011, Virginia Tech

 Verification, as opposed to Testing and Post-Silicon Validation, is a critical step for Integrated Circuits (IC) Design, answering the question â Are we designing the… (more)

Subjects/Keywords: Invariant filtering; Assume and Verify; Boolean Satisfiability(SAT); Sequential Equivalence Checking(SEC)

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APA (6th Edition):

Hu, W. (2011). Sufficiency-based Filtering of Invariants for Sequential Equivalence Checking. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/31121

Chicago Manual of Style (16th Edition):

Hu, Wei. “Sufficiency-based Filtering of Invariants for Sequential Equivalence Checking.” 2011. Masters Thesis, Virginia Tech. Accessed February 23, 2020. http://hdl.handle.net/10919/31121.

MLA Handbook (7th Edition):

Hu, Wei. “Sufficiency-based Filtering of Invariants for Sequential Equivalence Checking.” 2011. Web. 23 Feb 2020.

Vancouver:

Hu W. Sufficiency-based Filtering of Invariants for Sequential Equivalence Checking. [Internet] [Masters thesis]. Virginia Tech; 2011. [cited 2020 Feb 23]. Available from: http://hdl.handle.net/10919/31121.

Council of Science Editors:

Hu W. Sufficiency-based Filtering of Invariants for Sequential Equivalence Checking. [Masters Thesis]. Virginia Tech; 2011. Available from: http://hdl.handle.net/10919/31121


Virginia Tech

28. Demma, James Daniel. A Hardware Generator for Factor Graph Applications.

Degree: MS, Electrical and Computer Engineering, 2014, Virginia Tech

 A Factor Graph (FG  – http://en.wikipedia.org/wiki/Factor_graph) is a structure used to find solutions to problems that can be represented as a Probabilistic Graphical Model (PGM).… (more)

Subjects/Keywords: Factor Graph; Probabilistic Graphical Model; Digital Design; Sum-Product; Min-Sum; Belief Propagation; Hardware Generator

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APA (6th Edition):

Demma, J. D. (2014). A Hardware Generator for Factor Graph Applications. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/48599

Chicago Manual of Style (16th Edition):

Demma, James Daniel. “A Hardware Generator for Factor Graph Applications.” 2014. Masters Thesis, Virginia Tech. Accessed February 23, 2020. http://hdl.handle.net/10919/48599.

MLA Handbook (7th Edition):

Demma, James Daniel. “A Hardware Generator for Factor Graph Applications.” 2014. Web. 23 Feb 2020.

Vancouver:

Demma JD. A Hardware Generator for Factor Graph Applications. [Internet] [Masters thesis]. Virginia Tech; 2014. [cited 2020 Feb 23]. Available from: http://hdl.handle.net/10919/48599.

Council of Science Editors:

Demma JD. A Hardware Generator for Factor Graph Applications. [Masters Thesis]. Virginia Tech; 2014. Available from: http://hdl.handle.net/10919/48599


Virginia Tech

29. Rooks, Kurtis M. A Zynq-based Cluster Cognitive Radio.

Degree: MS, Electrical and Computer Engineering, 2014, Virginia Tech

 Traditional hardware radios provide very rigid solutions to radio problems. Intelligent software defined radios, also known as cognitive radios, provide flexibility and agility compared to… (more)

Subjects/Keywords: cogntive radio; Xilinx Zynq; tFlow; FPGA; GNU Radio; cluster

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APA (6th Edition):

Rooks, K. M. (2014). A Zynq-based Cluster Cognitive Radio. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/49682

Chicago Manual of Style (16th Edition):

Rooks, Kurtis M. “A Zynq-based Cluster Cognitive Radio.” 2014. Masters Thesis, Virginia Tech. Accessed February 23, 2020. http://hdl.handle.net/10919/49682.

MLA Handbook (7th Edition):

Rooks, Kurtis M. “A Zynq-based Cluster Cognitive Radio.” 2014. Web. 23 Feb 2020.

Vancouver:

Rooks KM. A Zynq-based Cluster Cognitive Radio. [Internet] [Masters thesis]. Virginia Tech; 2014. [cited 2020 Feb 23]. Available from: http://hdl.handle.net/10919/49682.

Council of Science Editors:

Rooks KM. A Zynq-based Cluster Cognitive Radio. [Masters Thesis]. Virginia Tech; 2014. Available from: http://hdl.handle.net/10919/49682


Virginia Tech

30. Pahlavan Yali, Moein. FPGA-Roofline: An Insightful Model for FGPA-based Hardware Acceleration in Modern Embedded Systems.

Degree: MS, Electrical and Computer Engineering, 2015, Virginia Tech

 The quick growth of embedded systems and their increasing computing power has made them suitable for a wider range of applications. Despite the increasing performance… (more)

Subjects/Keywords: Embedded Systems; FPGA; Hardware Accelerator; Performance Model

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APA (6th Edition):

Pahlavan Yali, M. (2015). FPGA-Roofline: An Insightful Model for FGPA-based Hardware Acceleration in Modern Embedded Systems. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/51193

Chicago Manual of Style (16th Edition):

Pahlavan Yali, Moein. “FPGA-Roofline: An Insightful Model for FGPA-based Hardware Acceleration in Modern Embedded Systems.” 2015. Masters Thesis, Virginia Tech. Accessed February 23, 2020. http://hdl.handle.net/10919/51193.

MLA Handbook (7th Edition):

Pahlavan Yali, Moein. “FPGA-Roofline: An Insightful Model for FGPA-based Hardware Acceleration in Modern Embedded Systems.” 2015. Web. 23 Feb 2020.

Vancouver:

Pahlavan Yali M. FPGA-Roofline: An Insightful Model for FGPA-based Hardware Acceleration in Modern Embedded Systems. [Internet] [Masters thesis]. Virginia Tech; 2015. [cited 2020 Feb 23]. Available from: http://hdl.handle.net/10919/51193.

Council of Science Editors:

Pahlavan Yali M. FPGA-Roofline: An Insightful Model for FGPA-based Hardware Acceleration in Modern Embedded Systems. [Masters Thesis]. Virginia Tech; 2015. Available from: http://hdl.handle.net/10919/51193

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