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You searched for +publisher:"Virginia Tech" +contributor:("Ravindran, Binoy"). Showing records 1 – 30 of 72 total matches.

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Virginia Tech

1. Drescher, Michael Stuart. A Flattened Hierarchical Scheduler for Real-Time Virtual Machines.

Degree: MS, Electrical and Computer Engineering, 2015, Virginia Tech

 The recent trend of migrating legacy computer systems to a virtualized, cloud-based environment has expanded to real-time systems. Unfortunately, modern hypervisors have no mechanism in… (more)

Subjects/Keywords: Linux; KVM; Scheduling; Virtualization; Real-Time

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APA (6th Edition):

Drescher, M. S. (2015). A Flattened Hierarchical Scheduler for Real-Time Virtual Machines. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/78125

Chicago Manual of Style (16th Edition):

Drescher, Michael Stuart. “A Flattened Hierarchical Scheduler for Real-Time Virtual Machines.” 2015. Masters Thesis, Virginia Tech. Accessed April 01, 2020. http://hdl.handle.net/10919/78125.

MLA Handbook (7th Edition):

Drescher, Michael Stuart. “A Flattened Hierarchical Scheduler for Real-Time Virtual Machines.” 2015. Web. 01 Apr 2020.

Vancouver:

Drescher MS. A Flattened Hierarchical Scheduler for Real-Time Virtual Machines. [Internet] [Masters thesis]. Virginia Tech; 2015. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/10919/78125.

Council of Science Editors:

Drescher MS. A Flattened Hierarchical Scheduler for Real-Time Virtual Machines. [Masters Thesis]. Virginia Tech; 2015. Available from: http://hdl.handle.net/10919/78125


Virginia Tech

2. Lyerly, Robert Frantz. Automatic Scheduling of Compute Kernels Across Heterogeneous Architectures.

Degree: MS, Electrical and Computer Engineering, 2014, Virginia Tech

 The world of high-performance computing has shifted from increasing single-core performance to extracting performance from heterogeneous multi- and many-core processors due to the power, memory… (more)

Subjects/Keywords: High-Performance Computing; Runtime Systems; Heterogeneous Architectures; Compilers; Scheduling

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APA (6th Edition):

Lyerly, R. F. (2014). Automatic Scheduling of Compute Kernels Across Heterogeneous Architectures. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/78130

Chicago Manual of Style (16th Edition):

Lyerly, Robert Frantz. “Automatic Scheduling of Compute Kernels Across Heterogeneous Architectures.” 2014. Masters Thesis, Virginia Tech. Accessed April 01, 2020. http://hdl.handle.net/10919/78130.

MLA Handbook (7th Edition):

Lyerly, Robert Frantz. “Automatic Scheduling of Compute Kernels Across Heterogeneous Architectures.” 2014. Web. 01 Apr 2020.

Vancouver:

Lyerly RF. Automatic Scheduling of Compute Kernels Across Heterogeneous Architectures. [Internet] [Masters thesis]. Virginia Tech; 2014. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/10919/78130.

Council of Science Editors:

Lyerly RF. Automatic Scheduling of Compute Kernels Across Heterogeneous Architectures. [Masters Thesis]. Virginia Tech; 2014. Available from: http://hdl.handle.net/10919/78130


Virginia Tech

3. Moore, Sean Ryan. Mutex Locking versus Hardware Transactional Memory: An Experimental Evaluation.

Degree: MS, Electrical and Computer Engineering, 2015, Virginia Tech

 It has historically been the case that CPUs have run programs ever faster without significant intervention on the behalf of the programmer. However, this "free… (more)

Subjects/Keywords: Hardware Transactional Memory; Global Lock; GNU C Library

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APA (6th Edition):

Moore, S. R. (2015). Mutex Locking versus Hardware Transactional Memory: An Experimental Evaluation. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/78164

Chicago Manual of Style (16th Edition):

Moore, Sean Ryan. “Mutex Locking versus Hardware Transactional Memory: An Experimental Evaluation.” 2015. Masters Thesis, Virginia Tech. Accessed April 01, 2020. http://hdl.handle.net/10919/78164.

MLA Handbook (7th Edition):

Moore, Sean Ryan. “Mutex Locking versus Hardware Transactional Memory: An Experimental Evaluation.” 2015. Web. 01 Apr 2020.

Vancouver:

Moore SR. Mutex Locking versus Hardware Transactional Memory: An Experimental Evaluation. [Internet] [Masters thesis]. Virginia Tech; 2015. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/10919/78164.

Council of Science Editors:

Moore SR. Mutex Locking versus Hardware Transactional Memory: An Experimental Evaluation. [Masters Thesis]. Virginia Tech; 2015. Available from: http://hdl.handle.net/10919/78164


Virginia Tech

4. Ansary, B M Saif. High Performance Inter-kernel Communication and Networking in a Replicated-kernel Operating System.

Degree: MS, Electrical and Computer Engineering, 2016, Virginia Tech

 Modern computer hardware platforms are moving towards high core-count and heterogeneous Instruction Set Architecture (ISA) processors to achieve improved performance as single core performance has… (more)

Subjects/Keywords: Operating System; System Sofware; Network Stack; Replicated Kernels; Filesystem

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APA (6th Edition):

Ansary, B. M. S. (2016). High Performance Inter-kernel Communication and Networking in a Replicated-kernel Operating System. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/78338

Chicago Manual of Style (16th Edition):

Ansary, B M Saif. “High Performance Inter-kernel Communication and Networking in a Replicated-kernel Operating System.” 2016. Masters Thesis, Virginia Tech. Accessed April 01, 2020. http://hdl.handle.net/10919/78338.

MLA Handbook (7th Edition):

Ansary, B M Saif. “High Performance Inter-kernel Communication and Networking in a Replicated-kernel Operating System.” 2016. Web. 01 Apr 2020.

Vancouver:

Ansary BMS. High Performance Inter-kernel Communication and Networking in a Replicated-kernel Operating System. [Internet] [Masters thesis]. Virginia Tech; 2016. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/10919/78338.

Council of Science Editors:

Ansary BMS. High Performance Inter-kernel Communication and Networking in a Replicated-kernel Operating System. [Masters Thesis]. Virginia Tech; 2016. Available from: http://hdl.handle.net/10919/78338


Virginia Tech

5. Dhoke, Aditya Anil. On Partial Aborts and Reducing Validation Costs in Fault-tolerant Distributed Transactional Memory.

Degree: MS, Computer Science, 2013, Virginia Tech

 Distributed Transactional Memory (DTM) is an emerging synchronization abstraction thatpromises to alleviate the scalability, programmability, and composability challenges of lock-based distributed synchronization. With DTM, programmers… (more)

Subjects/Keywords: Software Transactional Memory; Partial Abort; Validation; Closed Nesting; Checkpointing

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APA (6th Edition):

Dhoke, A. A. (2013). On Partial Aborts and Reducing Validation Costs in Fault-tolerant Distributed Transactional Memory. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/23890

Chicago Manual of Style (16th Edition):

Dhoke, Aditya Anil. “On Partial Aborts and Reducing Validation Costs in Fault-tolerant Distributed Transactional Memory.” 2013. Masters Thesis, Virginia Tech. Accessed April 01, 2020. http://hdl.handle.net/10919/23890.

MLA Handbook (7th Edition):

Dhoke, Aditya Anil. “On Partial Aborts and Reducing Validation Costs in Fault-tolerant Distributed Transactional Memory.” 2013. Web. 01 Apr 2020.

Vancouver:

Dhoke AA. On Partial Aborts and Reducing Validation Costs in Fault-tolerant Distributed Transactional Memory. [Internet] [Masters thesis]. Virginia Tech; 2013. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/10919/23890.

Council of Science Editors:

Dhoke AA. On Partial Aborts and Reducing Validation Costs in Fault-tolerant Distributed Transactional Memory. [Masters Thesis]. Virginia Tech; 2013. Available from: http://hdl.handle.net/10919/23890

6. Mehrab, A K M Fazla. Cross-ISA Execution Migration of Unikernels: Build Toolchain, Memory Alignment, and VM State Transfer Techniques.

Degree: MS, Electrical and Computer Engineering, 2018, Virginia Tech

 Cloud computing providers run data centers which are composed of thousands of server machines. Servers are robust, scalable, and thus capable of executing many jobs… (more)

Subjects/Keywords: Operating Systems; Unikernels; Virtualization; Heterogeneous Systems

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APA (6th Edition):

Mehrab, A. K. M. F. (2018). Cross-ISA Execution Migration of Unikernels: Build Toolchain, Memory Alignment, and VM State Transfer Techniques. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/86485

Chicago Manual of Style (16th Edition):

Mehrab, A K M Fazla. “Cross-ISA Execution Migration of Unikernels: Build Toolchain, Memory Alignment, and VM State Transfer Techniques.” 2018. Masters Thesis, Virginia Tech. Accessed April 01, 2020. http://hdl.handle.net/10919/86485.

MLA Handbook (7th Edition):

Mehrab, A K M Fazla. “Cross-ISA Execution Migration of Unikernels: Build Toolchain, Memory Alignment, and VM State Transfer Techniques.” 2018. Web. 01 Apr 2020.

Vancouver:

Mehrab AKMF. Cross-ISA Execution Migration of Unikernels: Build Toolchain, Memory Alignment, and VM State Transfer Techniques. [Internet] [Masters thesis]. Virginia Tech; 2018. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/10919/86485.

Council of Science Editors:

Mehrab AKMF. Cross-ISA Execution Migration of Unikernels: Build Toolchain, Memory Alignment, and VM State Transfer Techniques. [Masters Thesis]. Virginia Tech; 2018. Available from: http://hdl.handle.net/10919/86485


Virginia Tech

7. Sung, Mincheol. Design and Implementation of a Network Server in LibrettOS.

Degree: MS, Computer Engineering, 2018, Virginia Tech

 When it comes to reliability and security in networking systems, concerns have been shown in traditional operating systems (OSs) such as Windows, MacOS, NetBSD, and… (more)

Subjects/Keywords: multiserver OS; microkernel; hypervisor; Xen

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APA (6th Edition):

Sung, M. (2018). Design and Implementation of a Network Server in LibrettOS. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/87066

Chicago Manual of Style (16th Edition):

Sung, Mincheol. “Design and Implementation of a Network Server in LibrettOS.” 2018. Masters Thesis, Virginia Tech. Accessed April 01, 2020. http://hdl.handle.net/10919/87066.

MLA Handbook (7th Edition):

Sung, Mincheol. “Design and Implementation of a Network Server in LibrettOS.” 2018. Web. 01 Apr 2020.

Vancouver:

Sung M. Design and Implementation of a Network Server in LibrettOS. [Internet] [Masters thesis]. Virginia Tech; 2018. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/10919/87066.

Council of Science Editors:

Sung M. Design and Implementation of a Network Server in LibrettOS. [Masters Thesis]. Virginia Tech; 2018. Available from: http://hdl.handle.net/10919/87066


Virginia Tech

8. Dellinger, Matthew Aalseth. An Experimental Evaluation of the Scalability of Real-Time Scheduling Algorithms on Large-Scale Multicore Platforms.

Degree: MS, Electrical and Computer Engineering, 2011, Virginia Tech

 This thesis studies the problem of experimentally evaluating the scaling behaviors of existing multicore real-time task scheduling algorithms on large-scale multicore platforms. As chip manufacturers… (more)

Subjects/Keywords: Linux; Utility Accrual; Scheduling; Real-Time; Multiprocessors

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APA (6th Edition):

Dellinger, M. A. (2011). An Experimental Evaluation of the Scalability of Real-Time Scheduling Algorithms on Large-Scale Multicore Platforms. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/32674

Chicago Manual of Style (16th Edition):

Dellinger, Matthew Aalseth. “An Experimental Evaluation of the Scalability of Real-Time Scheduling Algorithms on Large-Scale Multicore Platforms.” 2011. Masters Thesis, Virginia Tech. Accessed April 01, 2020. http://hdl.handle.net/10919/32674.

MLA Handbook (7th Edition):

Dellinger, Matthew Aalseth. “An Experimental Evaluation of the Scalability of Real-Time Scheduling Algorithms on Large-Scale Multicore Platforms.” 2011. Web. 01 Apr 2020.

Vancouver:

Dellinger MA. An Experimental Evaluation of the Scalability of Real-Time Scheduling Algorithms on Large-Scale Multicore Platforms. [Internet] [Masters thesis]. Virginia Tech; 2011. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/10919/32674.

Council of Science Editors:

Dellinger MA. An Experimental Evaluation of the Scalability of Real-Time Scheduling Algorithms on Large-Scale Multicore Platforms. [Masters Thesis]. Virginia Tech; 2011. Available from: http://hdl.handle.net/10919/32674


Virginia Tech

9. Lindsay, Aaron Charles. LWFG: A Cache-Aware Multi-core Real-Time Scheduling Algorithm.

Degree: MS, Computer Science, 2012, Virginia Tech

 As the number of processing cores contained in modern processors continues to increase, cache hierarchies are becoming more complex. This added complexity has the effect… (more)

Subjects/Keywords: Linux; Real-Time; Scheduling; Multiprocessors; Cache-aware; Partitioning

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APA (6th Edition):

Lindsay, A. C. (2012). LWFG: A Cache-Aware Multi-core Real-Time Scheduling Algorithm. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/33541

Chicago Manual of Style (16th Edition):

Lindsay, Aaron Charles. “LWFG: A Cache-Aware Multi-core Real-Time Scheduling Algorithm.” 2012. Masters Thesis, Virginia Tech. Accessed April 01, 2020. http://hdl.handle.net/10919/33541.

MLA Handbook (7th Edition):

Lindsay, Aaron Charles. “LWFG: A Cache-Aware Multi-core Real-Time Scheduling Algorithm.” 2012. Web. 01 Apr 2020.

Vancouver:

Lindsay AC. LWFG: A Cache-Aware Multi-core Real-Time Scheduling Algorithm. [Internet] [Masters thesis]. Virginia Tech; 2012. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/10919/33541.

Council of Science Editors:

Lindsay AC. LWFG: A Cache-Aware Multi-core Real-Time Scheduling Algorithm. [Masters Thesis]. Virginia Tech; 2012. Available from: http://hdl.handle.net/10919/33541


Virginia Tech

10. Garyali, Piyush. On Best-Effort Utility Accrual Real-Time Scheduling on Multiprocessors.

Degree: MS, Electrical and Computer Engineering, 2010, Virginia Tech

 We consider the problem of scheduling real-time tasks on a multiprocessor system. Our primary focus is scheduling on multiprocessor systems where the total task utilization… (more)

Subjects/Keywords: Time/Utility Functions; Utility Accrual Scheduling; Multiprocessor Real-Time Scheduling; Real-Time Linux

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APA (6th Edition):

Garyali, P. (2010). On Best-Effort Utility Accrual Real-Time Scheduling on Multiprocessors. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/34112

Chicago Manual of Style (16th Edition):

Garyali, Piyush. “On Best-Effort Utility Accrual Real-Time Scheduling on Multiprocessors.” 2010. Masters Thesis, Virginia Tech. Accessed April 01, 2020. http://hdl.handle.net/10919/34112.

MLA Handbook (7th Edition):

Garyali, Piyush. “On Best-Effort Utility Accrual Real-Time Scheduling on Multiprocessors.” 2010. Web. 01 Apr 2020.

Vancouver:

Garyali P. On Best-Effort Utility Accrual Real-Time Scheduling on Multiprocessors. [Internet] [Masters thesis]. Virginia Tech; 2010. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/10919/34112.

Council of Science Editors:

Garyali P. On Best-Effort Utility Accrual Real-Time Scheduling on Multiprocessors. [Masters Thesis]. Virginia Tech; 2010. Available from: http://hdl.handle.net/10919/34112


Virginia Tech

11. Saha, Sonal. An Experimental Evaluation of Real-Time DVFS Scheduling Algorithms.

Degree: MS, Electrical and Computer Engineering, 2011, Virginia Tech

 Dynamic voltage and frequency scaling (DVFS) is an extensively studied energy manage- ment technique, which aims to reduce the energy consumption of computing platforms by… (more)

Subjects/Keywords: Dynamic Voltage and Frequency Scaling; Real-Time Linux

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APA (6th Edition):

Saha, S. (2011). An Experimental Evaluation of Real-Time DVFS Scheduling Algorithms. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/35035

Chicago Manual of Style (16th Edition):

Saha, Sonal. “An Experimental Evaluation of Real-Time DVFS Scheduling Algorithms.” 2011. Masters Thesis, Virginia Tech. Accessed April 01, 2020. http://hdl.handle.net/10919/35035.

MLA Handbook (7th Edition):

Saha, Sonal. “An Experimental Evaluation of Real-Time DVFS Scheduling Algorithms.” 2011. Web. 01 Apr 2020.

Vancouver:

Saha S. An Experimental Evaluation of Real-Time DVFS Scheduling Algorithms. [Internet] [Masters thesis]. Virginia Tech; 2011. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/10919/35035.

Council of Science Editors:

Saha S. An Experimental Evaluation of Real-Time DVFS Scheduling Algorithms. [Masters Thesis]. Virginia Tech; 2011. Available from: http://hdl.handle.net/10919/35035


Virginia Tech

12. Albert, Frank Curtis. Applying Source Level Auto-Vectorization to Aparapi Java.

Degree: MS, Electrical and Computer Engineering, 2014, Virginia Tech

 Ever since chip manufacturers hit the power wall preventing them from increasing processor clock speed, there has been an increased push towards parallelism for performance… (more)

Subjects/Keywords: Auto-Vectorization; Aparapi; Java; GPGPU Computing; SIMD; Parallelism; Threaded

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APA (6th Edition):

Albert, F. C. (2014). Applying Source Level Auto-Vectorization to Aparapi Java. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/49022

Chicago Manual of Style (16th Edition):

Albert, Frank Curtis. “Applying Source Level Auto-Vectorization to Aparapi Java.” 2014. Masters Thesis, Virginia Tech. Accessed April 01, 2020. http://hdl.handle.net/10919/49022.

MLA Handbook (7th Edition):

Albert, Frank Curtis. “Applying Source Level Auto-Vectorization to Aparapi Java.” 2014. Web. 01 Apr 2020.

Vancouver:

Albert FC. Applying Source Level Auto-Vectorization to Aparapi Java. [Internet] [Masters thesis]. Virginia Tech; 2014. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/10919/49022.

Council of Science Editors:

Albert FC. Applying Source Level Auto-Vectorization to Aparapi Java. [Masters Thesis]. Virginia Tech; 2014. Available from: http://hdl.handle.net/10919/49022


Virginia Tech

13. Burns, Kevin Patrick. Real-Time Hierarchical Scheduling of Virtualized Systems.

Degree: MS, Electrical and Computer Engineering, 2014, Virginia Tech

 In industry there has been a large focus on system integration and server consolidation, even for real-time systems, leading to an interest in virtualization. However,… (more)

Subjects/Keywords: Real-time; Virtualization; KairosVM; KVM; Linux

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APA (6th Edition):

Burns, K. P. (2014). Real-Time Hierarchical Scheduling of Virtualized Systems. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/51790

Chicago Manual of Style (16th Edition):

Burns, Kevin Patrick. “Real-Time Hierarchical Scheduling of Virtualized Systems.” 2014. Masters Thesis, Virginia Tech. Accessed April 01, 2020. http://hdl.handle.net/10919/51790.

MLA Handbook (7th Edition):

Burns, Kevin Patrick. “Real-Time Hierarchical Scheduling of Virtualized Systems.” 2014. Web. 01 Apr 2020.

Vancouver:

Burns KP. Real-Time Hierarchical Scheduling of Virtualized Systems. [Internet] [Masters thesis]. Virginia Tech; 2014. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/10919/51790.

Council of Science Editors:

Burns KP. Real-Time Hierarchical Scheduling of Virtualized Systems. [Masters Thesis]. Virginia Tech; 2014. Available from: http://hdl.handle.net/10919/51790


Virginia Tech

14. Katz, David Gabriel. Popcorn Linux: Cross Kernel Process and Thread Migration in a Linux-Based Multikernel.

Degree: MS, Electrical and Computer Engineering, 2014, Virginia Tech

 Proliferation of new computing hardware platforms that support increasing numbers of cores, as well as increasing ISA heterogeneity, is creating opportunity for systems software developers… (more)

Subjects/Keywords: OS; Multikernel

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APA (6th Edition):

Katz, D. G. (2014). Popcorn Linux: Cross Kernel Process and Thread Migration in a Linux-Based Multikernel. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/52561

Chicago Manual of Style (16th Edition):

Katz, David Gabriel. “Popcorn Linux: Cross Kernel Process and Thread Migration in a Linux-Based Multikernel.” 2014. Masters Thesis, Virginia Tech. Accessed April 01, 2020. http://hdl.handle.net/10919/52561.

MLA Handbook (7th Edition):

Katz, David Gabriel. “Popcorn Linux: Cross Kernel Process and Thread Migration in a Linux-Based Multikernel.” 2014. Web. 01 Apr 2020.

Vancouver:

Katz DG. Popcorn Linux: Cross Kernel Process and Thread Migration in a Linux-Based Multikernel. [Internet] [Masters thesis]. Virginia Tech; 2014. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/10919/52561.

Council of Science Editors:

Katz DG. Popcorn Linux: Cross Kernel Process and Thread Migration in a Linux-Based Multikernel. [Masters Thesis]. Virginia Tech; 2014. Available from: http://hdl.handle.net/10919/52561


Virginia Tech

15. Khoshnood, Sepideh. Constraint Solving for Diagnosing Concurrency Bugs.

Degree: MS, Electrical and Computer Engineering, 2015, Virginia Tech

 Programmers often have to spend a significant amount of time inspecting the software code and execution traces to identify the root cause of a software… (more)

Subjects/Keywords: Concurrency; Bug Localization; Bounded Model Checking; MAX-SAT

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APA (6th Edition):

Khoshnood, S. (2015). Constraint Solving for Diagnosing Concurrency Bugs. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/52784

Chicago Manual of Style (16th Edition):

Khoshnood, Sepideh. “Constraint Solving for Diagnosing Concurrency Bugs.” 2015. Masters Thesis, Virginia Tech. Accessed April 01, 2020. http://hdl.handle.net/10919/52784.

MLA Handbook (7th Edition):

Khoshnood, Sepideh. “Constraint Solving for Diagnosing Concurrency Bugs.” 2015. Web. 01 Apr 2020.

Vancouver:

Khoshnood S. Constraint Solving for Diagnosing Concurrency Bugs. [Internet] [Masters thesis]. Virginia Tech; 2015. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/10919/52784.

Council of Science Editors:

Khoshnood S. Constraint Solving for Diagnosing Concurrency Bugs. [Masters Thesis]. Virginia Tech; 2015. Available from: http://hdl.handle.net/10919/52784


Virginia Tech

16. Ravichandran, Akshay Giridhar. Single System Image in a Linux-based Replicated Operating System Kernel.

Degree: MS, Electrical and Computer Engineering, 2015, Virginia Tech

 Recent trends in the computer market suggest that emerging computing platforms will be increasingly parallel and heterogeneous, in order to satisfy the user demand for… (more)

Subjects/Keywords: Linux; Multikernel; Thread Synchronization; Signals; Process Management

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APA (6th Edition):

Ravichandran, A. G. (2015). Single System Image in a Linux-based Replicated Operating System Kernel. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/56654

Chicago Manual of Style (16th Edition):

Ravichandran, Akshay Giridhar. “Single System Image in a Linux-based Replicated Operating System Kernel.” 2015. Masters Thesis, Virginia Tech. Accessed April 01, 2020. http://hdl.handle.net/10919/56654.

MLA Handbook (7th Edition):

Ravichandran, Akshay Giridhar. “Single System Image in a Linux-based Replicated Operating System Kernel.” 2015. Web. 01 Apr 2020.

Vancouver:

Ravichandran AG. Single System Image in a Linux-based Replicated Operating System Kernel. [Internet] [Masters thesis]. Virginia Tech; 2015. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/10919/56654.

Council of Science Editors:

Ravichandran AG. Single System Image in a Linux-based Replicated Operating System Kernel. [Masters Thesis]. Virginia Tech; 2015. Available from: http://hdl.handle.net/10919/56654


Virginia Tech

17. Wen, Yuzhong. Replication of Concurrent Applications in a Shared Memory Multikernel.

Degree: MS, Computer Science, 2016, Virginia Tech

 State Machine Replication (SMR) has become the de-facto methodology of building a replication based fault-tolerance system. Current SMR systems usually have multiple machines involved, each… (more)

Subjects/Keywords: State Machine Replication; Runtime Systems; Deterministic System; System Software

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APA (6th Edition):

Wen, Y. (2016). Replication of Concurrent Applications in a Shared Memory Multikernel. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/71813

Chicago Manual of Style (16th Edition):

Wen, Yuzhong. “Replication of Concurrent Applications in a Shared Memory Multikernel.” 2016. Masters Thesis, Virginia Tech. Accessed April 01, 2020. http://hdl.handle.net/10919/71813.

MLA Handbook (7th Edition):

Wen, Yuzhong. “Replication of Concurrent Applications in a Shared Memory Multikernel.” 2016. Web. 01 Apr 2020.

Vancouver:

Wen Y. Replication of Concurrent Applications in a Shared Memory Multikernel. [Internet] [Masters thesis]. Virginia Tech; 2016. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/10919/71813.

Council of Science Editors:

Wen Y. Replication of Concurrent Applications in a Shared Memory Multikernel. [Masters Thesis]. Virginia Tech; 2016. Available from: http://hdl.handle.net/10919/71813


Virginia Tech

18. Woyak, Jeremy. Software Architecture Considerations for Facilitating Electric Power System Planning Incorporating a Variety of Design Categories.

Degree: MS, Electrical and Computer Engineering, 2012, Virginia Tech

 This work investigates some of the features of existing software applications for electric power system planning as well as some of the limitations that keep… (more)

Subjects/Keywords: software; planning; electric power system

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APA (6th Edition):

Woyak, J. (2012). Software Architecture Considerations for Facilitating Electric Power System Planning Incorporating a Variety of Design Categories. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/31457

Chicago Manual of Style (16th Edition):

Woyak, Jeremy. “Software Architecture Considerations for Facilitating Electric Power System Planning Incorporating a Variety of Design Categories.” 2012. Masters Thesis, Virginia Tech. Accessed April 01, 2020. http://hdl.handle.net/10919/31457.

MLA Handbook (7th Edition):

Woyak, Jeremy. “Software Architecture Considerations for Facilitating Electric Power System Planning Incorporating a Variety of Design Categories.” 2012. Web. 01 Apr 2020.

Vancouver:

Woyak J. Software Architecture Considerations for Facilitating Electric Power System Planning Incorporating a Variety of Design Categories. [Internet] [Masters thesis]. Virginia Tech; 2012. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/10919/31457.

Council of Science Editors:

Woyak J. Software Architecture Considerations for Facilitating Electric Power System Planning Incorporating a Variety of Design Categories. [Masters Thesis]. Virginia Tech; 2012. Available from: http://hdl.handle.net/10919/31457


Virginia Tech

19. Mishra, Sudhanshu. HyflowCPP: A Distributed Software Transactional Memory Framework for C++.

Degree: MS, Electrical and Computer Engineering, 2013, Virginia Tech

 The distributed transactional memory (DTM) abstraction aims to simplify the development of distributed concurrent programs. It frees programmers from the complicated and error-prone task of… (more)

Subjects/Keywords: Distributed Transactional Memory; Transactional Framework; C++; Distributed Concurrency

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APA (6th Edition):

Mishra, S. (2013). HyflowCPP: A Distributed Software Transactional Memory Framework for C++. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/19265

Chicago Manual of Style (16th Edition):

Mishra, Sudhanshu. “HyflowCPP: A Distributed Software Transactional Memory Framework for C++.” 2013. Masters Thesis, Virginia Tech. Accessed April 01, 2020. http://hdl.handle.net/10919/19265.

MLA Handbook (7th Edition):

Mishra, Sudhanshu. “HyflowCPP: A Distributed Software Transactional Memory Framework for C++.” 2013. Web. 01 Apr 2020.

Vancouver:

Mishra S. HyflowCPP: A Distributed Software Transactional Memory Framework for C++. [Internet] [Masters thesis]. Virginia Tech; 2013. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/10919/19265.

Council of Science Editors:

Mishra S. HyflowCPP: A Distributed Software Transactional Memory Framework for C++. [Masters Thesis]. Virginia Tech; 2013. Available from: http://hdl.handle.net/10919/19265


Virginia Tech

20. Shelton, Benjamin H. Popcorn Linux: enabling efficient inter-core communication in a Linux-based multikernel operating system.

Degree: MS, Electrical and Computer Engineering, 2013, Virginia Tech

 As manufacturers introduce new machines with more cores, more NUMA-like architectures, and more tightly integrated heterogeneous processors, the traditional abstraction of a monolithic OS running… (more)

Subjects/Keywords: Operating systems; multikernel; high-performance computing; heterogeneous computing; multicore; scalability; message passing

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APA (6th Edition):

Shelton, B. H. (2013). Popcorn Linux: enabling efficient inter-core communication in a Linux-based multikernel operating system. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/23119

Chicago Manual of Style (16th Edition):

Shelton, Benjamin H. “Popcorn Linux: enabling efficient inter-core communication in a Linux-based multikernel operating system.” 2013. Masters Thesis, Virginia Tech. Accessed April 01, 2020. http://hdl.handle.net/10919/23119.

MLA Handbook (7th Edition):

Shelton, Benjamin H. “Popcorn Linux: enabling efficient inter-core communication in a Linux-based multikernel operating system.” 2013. Web. 01 Apr 2020.

Vancouver:

Shelton BH. Popcorn Linux: enabling efficient inter-core communication in a Linux-based multikernel operating system. [Internet] [Masters thesis]. Virginia Tech; 2013. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/10919/23119.

Council of Science Editors:

Shelton BH. Popcorn Linux: enabling efficient inter-core communication in a Linux-based multikernel operating system. [Masters Thesis]. Virginia Tech; 2013. Available from: http://hdl.handle.net/10919/23119


Virginia Tech

21. Chiba, Daniel Juzer. Optimizing Boot Times and Enhancing Binary Compatibility for Unikernels.

Degree: MS, Electrical and Computer Engineering, 2018, Virginia Tech

 Unikernels are lightweight, single-purpose virtual machines designed for the cloud. They provide enhanced security, minimal resource utilisation, fast boot times, and the ability to optimize… (more)

Subjects/Keywords: Virtualization; Unikernel; Hypervisor

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APA (6th Edition):

Chiba, D. J. (2018). Optimizing Boot Times and Enhancing Binary Compatibility for Unikernels. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/88865

Chicago Manual of Style (16th Edition):

Chiba, Daniel Juzer. “Optimizing Boot Times and Enhancing Binary Compatibility for Unikernels.” 2018. Masters Thesis, Virginia Tech. Accessed April 01, 2020. http://hdl.handle.net/10919/88865.

MLA Handbook (7th Edition):

Chiba, Daniel Juzer. “Optimizing Boot Times and Enhancing Binary Compatibility for Unikernels.” 2018. Web. 01 Apr 2020.

Vancouver:

Chiba DJ. Optimizing Boot Times and Enhancing Binary Compatibility for Unikernels. [Internet] [Masters thesis]. Virginia Tech; 2018. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/10919/88865.

Council of Science Editors:

Chiba DJ. Optimizing Boot Times and Enhancing Binary Compatibility for Unikernels. [Masters Thesis]. Virginia Tech; 2018. Available from: http://hdl.handle.net/10919/88865


Virginia Tech

22. Wang, Lingyun. Feeder Performance Analysis with Distributed Algorithm.

Degree: MS, Electrical and Computer Engineering, 2011, Virginia Tech

 How to evaluate the performance of an electric power distribution system unambiguously and quantitatively is not easy. How to accurately measure the efficiency of it… (more)

Subjects/Keywords: Electric Power Distribution System; Locational Marginal Price (LMP); Diakoptics; Distributed Computing; Feeder Performance

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APA (6th Edition):

Wang, L. (2011). Feeder Performance Analysis with Distributed Algorithm. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/31949

Chicago Manual of Style (16th Edition):

Wang, Lingyun. “Feeder Performance Analysis with Distributed Algorithm.” 2011. Masters Thesis, Virginia Tech. Accessed April 01, 2020. http://hdl.handle.net/10919/31949.

MLA Handbook (7th Edition):

Wang, Lingyun. “Feeder Performance Analysis with Distributed Algorithm.” 2011. Web. 01 Apr 2020.

Vancouver:

Wang L. Feeder Performance Analysis with Distributed Algorithm. [Internet] [Masters thesis]. Virginia Tech; 2011. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/10919/31949.

Council of Science Editors:

Wang L. Feeder Performance Analysis with Distributed Algorithm. [Masters Thesis]. Virginia Tech; 2011. Available from: http://hdl.handle.net/10919/31949

23. Bockenek, Joshua A. USIMPL: An Extension of Isabelle/UTP with Simpl-like Control Flow.

Degree: MS, Electrical and Computer Engineering, 2017, Virginia Tech

 Writing bug-free code is fraught with difficulty, and existing tools for the formal verification of programs do not scale well to large, complicated codebases such… (more)

Subjects/Keywords: Formal Verification; Formal Methods; Isabelle; Unifying Theories of Programming; Verification Condition Generation

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APA (6th Edition):

Bockenek, J. A. (2017). USIMPL: An Extension of Isabelle/UTP with Simpl-like Control Flow. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/81710

Chicago Manual of Style (16th Edition):

Bockenek, Joshua A. “USIMPL: An Extension of Isabelle/UTP with Simpl-like Control Flow.” 2017. Masters Thesis, Virginia Tech. Accessed April 01, 2020. http://hdl.handle.net/10919/81710.

MLA Handbook (7th Edition):

Bockenek, Joshua A. “USIMPL: An Extension of Isabelle/UTP with Simpl-like Control Flow.” 2017. Web. 01 Apr 2020.

Vancouver:

Bockenek JA. USIMPL: An Extension of Isabelle/UTP with Simpl-like Control Flow. [Internet] [Masters thesis]. Virginia Tech; 2017. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/10919/81710.

Council of Science Editors:

Bockenek JA. USIMPL: An Extension of Isabelle/UTP with Simpl-like Control Flow. [Masters Thesis]. Virginia Tech; 2017. Available from: http://hdl.handle.net/10919/81710


Virginia Tech

24. Mahmoud Mohamedin, Mohamed Ahmed. ByteSTM: Java Software Transactional Memory at the Virtual Machine Level.

Degree: MS, Electrical and Computer Engineering, 2012, Virginia Tech

 As chip vendors are increasingly manufacturing a new generation of multi-processor chips called multicores, improving software performance requires exposing greater concurrency in software. Since code… (more)

Subjects/Keywords: Synchronization; Virtual Machine; Java; Multiprocessor; Concurrency; Software Transactional Memory

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APA (6th Edition):

Mahmoud Mohamedin, M. A. (2012). ByteSTM: Java Software Transactional Memory at the Virtual Machine Level. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/31314

Chicago Manual of Style (16th Edition):

Mahmoud Mohamedin, Mohamed Ahmed. “ByteSTM: Java Software Transactional Memory at the Virtual Machine Level.” 2012. Masters Thesis, Virginia Tech. Accessed April 01, 2020. http://hdl.handle.net/10919/31314.

MLA Handbook (7th Edition):

Mahmoud Mohamedin, Mohamed Ahmed. “ByteSTM: Java Software Transactional Memory at the Virtual Machine Level.” 2012. Web. 01 Apr 2020.

Vancouver:

Mahmoud Mohamedin MA. ByteSTM: Java Software Transactional Memory at the Virtual Machine Level. [Internet] [Masters thesis]. Virginia Tech; 2012. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/10919/31314.

Council of Science Editors:

Mahmoud Mohamedin MA. ByteSTM: Java Software Transactional Memory at the Virtual Machine Level. [Masters Thesis]. Virginia Tech; 2012. Available from: http://hdl.handle.net/10919/31314

25. Pang, Yihan. Leveraging Processor-diversity For Improved Performance In Heterogeneous-ISA Systems.

Degree: MS, Computer Engineering, 2019, Virginia Tech

 The author of this thesis has a family full of non-engineers. To persuade family members that the work of this thesis is meaningful, aka the… (more)

Subjects/Keywords: System Software; Heterogeneous Architectures; SIMD; Scheduling; ISA

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APA (6th Edition):

Pang, Y. (2019). Leveraging Processor-diversity For Improved Performance In Heterogeneous-ISA Systems. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/95299

Chicago Manual of Style (16th Edition):

Pang, Yihan. “Leveraging Processor-diversity For Improved Performance In Heterogeneous-ISA Systems.” 2019. Masters Thesis, Virginia Tech. Accessed April 01, 2020. http://hdl.handle.net/10919/95299.

MLA Handbook (7th Edition):

Pang, Yihan. “Leveraging Processor-diversity For Improved Performance In Heterogeneous-ISA Systems.” 2019. Web. 01 Apr 2020.

Vancouver:

Pang Y. Leveraging Processor-diversity For Improved Performance In Heterogeneous-ISA Systems. [Internet] [Masters thesis]. Virginia Tech; 2019. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/10919/95299.

Council of Science Editors:

Pang Y. Leveraging Processor-diversity For Improved Performance In Heterogeneous-ISA Systems. [Masters Thesis]. Virginia Tech; 2019. Available from: http://hdl.handle.net/10919/95299


Virginia Tech

26. Liu, Beichen. SlimGuard: Design and Implementation of a Memory Efficient and Secure Heap Allocator.

Degree: MS, Computer Engineering, 2020, Virginia Tech

 Attacks targeting on the runtime memory (heap allocator) are severe threats to software safety. Statistical results shown that the numbers of heap-related attacks has doubled… (more)

Subjects/Keywords: Dynamic Memory Allocation; Memory Safety

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APA (6th Edition):

Liu, B. (2020). SlimGuard: Design and Implementation of a Memory Efficient and Secure Heap Allocator. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/96291

Chicago Manual of Style (16th Edition):

Liu, Beichen. “SlimGuard: Design and Implementation of a Memory Efficient and Secure Heap Allocator.” 2020. Masters Thesis, Virginia Tech. Accessed April 01, 2020. http://hdl.handle.net/10919/96291.

MLA Handbook (7th Edition):

Liu, Beichen. “SlimGuard: Design and Implementation of a Memory Efficient and Secure Heap Allocator.” 2020. Web. 01 Apr 2020.

Vancouver:

Liu B. SlimGuard: Design and Implementation of a Memory Efficient and Secure Heap Allocator. [Internet] [Masters thesis]. Virginia Tech; 2020. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/10919/96291.

Council of Science Editors:

Liu B. SlimGuard: Design and Implementation of a Memory Efficient and Secure Heap Allocator. [Masters Thesis]. Virginia Tech; 2020. Available from: http://hdl.handle.net/10919/96291


Virginia Tech

27. Li, Peng. Utility Accrual Real-Time Scheduling: Models and Algorithms.

Degree: PhD, Electrical and Computer Engineering, 2004, Virginia Tech

 This dissertation first presents an uniprocessor real-time scheduling algorithm called the Generic Benefit Scheduling algorithm (or GBS). GBS solves a previously open real-time scheduling problem:… (more)

Subjects/Keywords: performance assurance; real-time scheduling; utility accrual scheduling; Time/utility functions; resource management; overload scheduling

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APA (6th Edition):

Li, P. (2004). Utility Accrual Real-Time Scheduling: Models and Algorithms. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/11220

Chicago Manual of Style (16th Edition):

Li, Peng. “Utility Accrual Real-Time Scheduling: Models and Algorithms.” 2004. Doctoral Dissertation, Virginia Tech. Accessed April 01, 2020. http://hdl.handle.net/10919/11220.

MLA Handbook (7th Edition):

Li, Peng. “Utility Accrual Real-Time Scheduling: Models and Algorithms.” 2004. Web. 01 Apr 2020.

Vancouver:

Li P. Utility Accrual Real-Time Scheduling: Models and Algorithms. [Internet] [Doctoral dissertation]. Virginia Tech; 2004. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/10919/11220.

Council of Science Editors:

Li P. Utility Accrual Real-Time Scheduling: Models and Algorithms. [Doctoral Dissertation]. Virginia Tech; 2004. Available from: http://hdl.handle.net/10919/11220

28. Jelesnianski, Christopher Stanisław. A Compiler Framework to Support and Exploit Heterogeneous Overlapping-ISA Multiprocessor Platforms.

Degree: MS, Electrical and Computer Engineering, 2015, Virginia Tech

 As the demand for ever increasingly powerful machines continues, new architectures are sought to be the next route of breaking past the brick wall that… (more)

Subjects/Keywords: Compilers; Heterogeneous Architecture; Performance Profiling; Runtime; Code Transformation; System Software

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APA (6th Edition):

Jelesnianski, C. S. (2015). A Compiler Framework to Support and Exploit Heterogeneous Overlapping-ISA Multiprocessor Platforms. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/78177

Chicago Manual of Style (16th Edition):

Jelesnianski, Christopher Stanisław. “A Compiler Framework to Support and Exploit Heterogeneous Overlapping-ISA Multiprocessor Platforms.” 2015. Masters Thesis, Virginia Tech. Accessed April 01, 2020. http://hdl.handle.net/10919/78177.

MLA Handbook (7th Edition):

Jelesnianski, Christopher Stanisław. “A Compiler Framework to Support and Exploit Heterogeneous Overlapping-ISA Multiprocessor Platforms.” 2015. Web. 01 Apr 2020.

Vancouver:

Jelesnianski CS. A Compiler Framework to Support and Exploit Heterogeneous Overlapping-ISA Multiprocessor Platforms. [Internet] [Masters thesis]. Virginia Tech; 2015. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/10919/78177.

Council of Science Editors:

Jelesnianski CS. A Compiler Framework to Support and Exploit Heterogeneous Overlapping-ISA Multiprocessor Platforms. [Masters Thesis]. Virginia Tech; 2015. Available from: http://hdl.handle.net/10919/78177

29. Niles Jr, Duane Francis. Improving Performance of Highly-Programmable Concurrent Applications by Leveraging Parallel Nesting and Weaker Isolation Levels.

Degree: MS, Electrical and Computer Engineering, 2015, Virginia Tech

 The recent development of multi-core computer architectures has largely affected the creation of everyday applications, requiring the adoption of concurrent programming to significantly utilize the… (more)

Subjects/Keywords: Concurrency; Transactional Memory; Parallel Nesting; Distributed Systems; Databases; Transactions; Serializability; Weaker Isolation Levels

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APA (6th Edition):

Niles Jr, D. F. (2015). Improving Performance of Highly-Programmable Concurrent Applications by Leveraging Parallel Nesting and Weaker Isolation Levels. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/54557

Chicago Manual of Style (16th Edition):

Niles Jr, Duane Francis. “Improving Performance of Highly-Programmable Concurrent Applications by Leveraging Parallel Nesting and Weaker Isolation Levels.” 2015. Masters Thesis, Virginia Tech. Accessed April 01, 2020. http://hdl.handle.net/10919/54557.

MLA Handbook (7th Edition):

Niles Jr, Duane Francis. “Improving Performance of Highly-Programmable Concurrent Applications by Leveraging Parallel Nesting and Weaker Isolation Levels.” 2015. Web. 01 Apr 2020.

Vancouver:

Niles Jr DF. Improving Performance of Highly-Programmable Concurrent Applications by Leveraging Parallel Nesting and Weaker Isolation Levels. [Internet] [Masters thesis]. Virginia Tech; 2015. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/10919/54557.

Council of Science Editors:

Niles Jr DF. Improving Performance of Highly-Programmable Concurrent Applications by Leveraging Parallel Nesting and Weaker Isolation Levels. [Masters Thesis]. Virginia Tech; 2015. Available from: http://hdl.handle.net/10919/54557

30. Yang, Robin S. Shipboard MVDC Voltage Stabilization by Negative Load Energy Storage Compensated Virtual Capacitance.

Degree: MS, Computer Engineering, 2019, Virginia Tech

 Future ships will have a special shipboard power grid and power converters to power future electronics. Most of these power converters will have an internal… (more)

Subjects/Keywords: Shipboard MVDC; Pulsed Load; Voltage Stability; Virtual Stabilizer

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APA (6th Edition):

Yang, R. S. (2019). Shipboard MVDC Voltage Stabilization by Negative Load Energy Storage Compensated Virtual Capacitance. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/94129

Chicago Manual of Style (16th Edition):

Yang, Robin S. “Shipboard MVDC Voltage Stabilization by Negative Load Energy Storage Compensated Virtual Capacitance.” 2019. Masters Thesis, Virginia Tech. Accessed April 01, 2020. http://hdl.handle.net/10919/94129.

MLA Handbook (7th Edition):

Yang, Robin S. “Shipboard MVDC Voltage Stabilization by Negative Load Energy Storage Compensated Virtual Capacitance.” 2019. Web. 01 Apr 2020.

Vancouver:

Yang RS. Shipboard MVDC Voltage Stabilization by Negative Load Energy Storage Compensated Virtual Capacitance. [Internet] [Masters thesis]. Virginia Tech; 2019. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/10919/94129.

Council of Science Editors:

Yang RS. Shipboard MVDC Voltage Stabilization by Negative Load Energy Storage Compensated Virtual Capacitance. [Masters Thesis]. Virginia Tech; 2019. Available from: http://hdl.handle.net/10919/94129

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