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You searched for +publisher:"Virginia Tech" +contributor:("Plassmann, Paul E."). Showing records 1 – 30 of 50 total matches.

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Virginia Tech

1. Dellinger, Matthew Aalseth. An Experimental Evaluation of the Scalability of Real-Time Scheduling Algorithms on Large-Scale Multicore Platforms.

Degree: MS, Electrical and Computer Engineering, 2011, Virginia Tech

 This thesis studies the problem of experimentally evaluating the scaling behaviors of existing multicore real-time task scheduling algorithms on large-scale multicore platforms. As chip manufacturers… (more)

Subjects/Keywords: Linux; Utility Accrual; Scheduling; Real-Time; Multiprocessors

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APA (6th Edition):

Dellinger, M. A. (2011). An Experimental Evaluation of the Scalability of Real-Time Scheduling Algorithms on Large-Scale Multicore Platforms. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/32674

Chicago Manual of Style (16th Edition):

Dellinger, Matthew Aalseth. “An Experimental Evaluation of the Scalability of Real-Time Scheduling Algorithms on Large-Scale Multicore Platforms.” 2011. Masters Thesis, Virginia Tech. Accessed October 17, 2019. http://hdl.handle.net/10919/32674.

MLA Handbook (7th Edition):

Dellinger, Matthew Aalseth. “An Experimental Evaluation of the Scalability of Real-Time Scheduling Algorithms on Large-Scale Multicore Platforms.” 2011. Web. 17 Oct 2019.

Vancouver:

Dellinger MA. An Experimental Evaluation of the Scalability of Real-Time Scheduling Algorithms on Large-Scale Multicore Platforms. [Internet] [Masters thesis]. Virginia Tech; 2011. [cited 2019 Oct 17]. Available from: http://hdl.handle.net/10919/32674.

Council of Science Editors:

Dellinger MA. An Experimental Evaluation of the Scalability of Real-Time Scheduling Algorithms on Large-Scale Multicore Platforms. [Masters Thesis]. Virginia Tech; 2011. Available from: http://hdl.handle.net/10919/32674


Virginia Tech

2. Krishnamoorthy, Saparya. Strategies for Scalable Symbolic Execution-based Test Generation.

Degree: MS, Electrical and Computer Engineering, 2010, Virginia Tech

 With the advent of advanced program analysis and constraint solving techniques, several test generation tools use variants of symbolic execution. Symbolic techniques have been shown… (more)

Subjects/Keywords: symbolic execution; software verification; dynamic test generation; path explosion; satisfiability modulo theories

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APA (6th Edition):

Krishnamoorthy, S. (2010). Strategies for Scalable Symbolic Execution-based Test Generation. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/33997

Chicago Manual of Style (16th Edition):

Krishnamoorthy, Saparya. “Strategies for Scalable Symbolic Execution-based Test Generation.” 2010. Masters Thesis, Virginia Tech. Accessed October 17, 2019. http://hdl.handle.net/10919/33997.

MLA Handbook (7th Edition):

Krishnamoorthy, Saparya. “Strategies for Scalable Symbolic Execution-based Test Generation.” 2010. Web. 17 Oct 2019.

Vancouver:

Krishnamoorthy S. Strategies for Scalable Symbolic Execution-based Test Generation. [Internet] [Masters thesis]. Virginia Tech; 2010. [cited 2019 Oct 17]. Available from: http://hdl.handle.net/10919/33997.

Council of Science Editors:

Krishnamoorthy S. Strategies for Scalable Symbolic Execution-based Test Generation. [Masters Thesis]. Virginia Tech; 2010. Available from: http://hdl.handle.net/10919/33997


Virginia Tech

3. Garyali, Piyush. On Best-Effort Utility Accrual Real-Time Scheduling on Multiprocessors.

Degree: MS, Electrical and Computer Engineering, 2010, Virginia Tech

 We consider the problem of scheduling real-time tasks on a multiprocessor system. Our primary focus is scheduling on multiprocessor systems where the total task utilization… (more)

Subjects/Keywords: Time/Utility Functions; Utility Accrual Scheduling; Multiprocessor Real-Time Scheduling; Real-Time Linux

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APA (6th Edition):

Garyali, P. (2010). On Best-Effort Utility Accrual Real-Time Scheduling on Multiprocessors. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/34112

Chicago Manual of Style (16th Edition):

Garyali, Piyush. “On Best-Effort Utility Accrual Real-Time Scheduling on Multiprocessors.” 2010. Masters Thesis, Virginia Tech. Accessed October 17, 2019. http://hdl.handle.net/10919/34112.

MLA Handbook (7th Edition):

Garyali, Piyush. “On Best-Effort Utility Accrual Real-Time Scheduling on Multiprocessors.” 2010. Web. 17 Oct 2019.

Vancouver:

Garyali P. On Best-Effort Utility Accrual Real-Time Scheduling on Multiprocessors. [Internet] [Masters thesis]. Virginia Tech; 2010. [cited 2019 Oct 17]. Available from: http://hdl.handle.net/10919/34112.

Council of Science Editors:

Garyali P. On Best-Effort Utility Accrual Real-Time Scheduling on Multiprocessors. [Masters Thesis]. Virginia Tech; 2010. Available from: http://hdl.handle.net/10919/34112


Virginia Tech

4. Narayanaswamy, Ramya Priyadharshini. Design of a Power-aware Dataflow Processor Architecture.

Degree: MS, Electrical and Computer Engineering, 2010, Virginia Tech

 In a sensor monitoring embedded computing environment, the data from a sensor is an event that triggers the execution of an application. A sensor node… (more)

Subjects/Keywords: UPF; E-textiles; Dataflow; Power-aware

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APA (6th Edition):

Narayanaswamy, R. P. (2010). Design of a Power-aware Dataflow Processor Architecture. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/34192

Chicago Manual of Style (16th Edition):

Narayanaswamy, Ramya Priyadharshini. “Design of a Power-aware Dataflow Processor Architecture.” 2010. Masters Thesis, Virginia Tech. Accessed October 17, 2019. http://hdl.handle.net/10919/34192.

MLA Handbook (7th Edition):

Narayanaswamy, Ramya Priyadharshini. “Design of a Power-aware Dataflow Processor Architecture.” 2010. Web. 17 Oct 2019.

Vancouver:

Narayanaswamy RP. Design of a Power-aware Dataflow Processor Architecture. [Internet] [Masters thesis]. Virginia Tech; 2010. [cited 2019 Oct 17]. Available from: http://hdl.handle.net/10919/34192.

Council of Science Editors:

Narayanaswamy RP. Design of a Power-aware Dataflow Processor Architecture. [Masters Thesis]. Virginia Tech; 2010. Available from: http://hdl.handle.net/10919/34192


Virginia Tech

5. Lakshmanan, Karthick. Design of an Automation Framework for a Novel Data-Flow Processor Architecture.

Degree: MS, Electrical and Computer Engineering, 2010, Virginia Tech

 Improved process technology has resulted in the integration of computing elements into multiple application areas. General purpose micro-controllers are designed to assist in this integration… (more)

Subjects/Keywords: Electronic Textiles; Automation Framework; Data-Flow

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APA (6th Edition):

Lakshmanan, K. (2010). Design of an Automation Framework for a Novel Data-Flow Processor Architecture. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/34193

Chicago Manual of Style (16th Edition):

Lakshmanan, Karthick. “Design of an Automation Framework for a Novel Data-Flow Processor Architecture.” 2010. Masters Thesis, Virginia Tech. Accessed October 17, 2019. http://hdl.handle.net/10919/34193.

MLA Handbook (7th Edition):

Lakshmanan, Karthick. “Design of an Automation Framework for a Novel Data-Flow Processor Architecture.” 2010. Web. 17 Oct 2019.

Vancouver:

Lakshmanan K. Design of an Automation Framework for a Novel Data-Flow Processor Architecture. [Internet] [Masters thesis]. Virginia Tech; 2010. [cited 2019 Oct 17]. Available from: http://hdl.handle.net/10919/34193.

Council of Science Editors:

Lakshmanan K. Design of an Automation Framework for a Novel Data-Flow Processor Architecture. [Masters Thesis]. Virginia Tech; 2010. Available from: http://hdl.handle.net/10919/34193


Virginia Tech

6. Mandlekar, Anup Shrikant. An Application Framework for a Power-Aware Processor Architecture.

Degree: MS, Electrical and Computer Engineering, 2012, Virginia Tech

 The instruction-set based general purpose processors are not energy-efficient for event-driven applications. The E-textiles group at Virginia Tech proposed a novel data-flow processor architecture design… (more)

Subjects/Keywords: Low Power Flash Memory Cells; Model Driven Engineering; Simulink; Dataflow Architecture

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APA (6th Edition):

Mandlekar, A. S. (2012). An Application Framework for a Power-Aware Processor Architecture. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/34484

Chicago Manual of Style (16th Edition):

Mandlekar, Anup Shrikant. “An Application Framework for a Power-Aware Processor Architecture.” 2012. Masters Thesis, Virginia Tech. Accessed October 17, 2019. http://hdl.handle.net/10919/34484.

MLA Handbook (7th Edition):

Mandlekar, Anup Shrikant. “An Application Framework for a Power-Aware Processor Architecture.” 2012. Web. 17 Oct 2019.

Vancouver:

Mandlekar AS. An Application Framework for a Power-Aware Processor Architecture. [Internet] [Masters thesis]. Virginia Tech; 2012. [cited 2019 Oct 17]. Available from: http://hdl.handle.net/10919/34484.

Council of Science Editors:

Mandlekar AS. An Application Framework for a Power-Aware Processor Architecture. [Masters Thesis]. Virginia Tech; 2012. Available from: http://hdl.handle.net/10919/34484


Virginia Tech

7. Chandrasekharan, Athira. Accelerating Incremental Floorplanning of Partially Reconfigurable Designs to Improve FPGA Productivity.

Degree: MS, Electrical and Computer Engineering, 2010, Virginia Tech

 FPGA implementation tool turnaround time has unfortunately not kept pace with FPGA density advances. It is difficult to parallelize place-and-route algorithms without sacrificing determinism or… (more)

Subjects/Keywords: Reconfigurable Computing; Incremental Floorplanning; FPGAs

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APA (6th Edition):

Chandrasekharan, A. (2010). Accelerating Incremental Floorplanning of Partially Reconfigurable Designs to Improve FPGA Productivity. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/34499

Chicago Manual of Style (16th Edition):

Chandrasekharan, Athira. “Accelerating Incremental Floorplanning of Partially Reconfigurable Designs to Improve FPGA Productivity.” 2010. Masters Thesis, Virginia Tech. Accessed October 17, 2019. http://hdl.handle.net/10919/34499.

MLA Handbook (7th Edition):

Chandrasekharan, Athira. “Accelerating Incremental Floorplanning of Partially Reconfigurable Designs to Improve FPGA Productivity.” 2010. Web. 17 Oct 2019.

Vancouver:

Chandrasekharan A. Accelerating Incremental Floorplanning of Partially Reconfigurable Designs to Improve FPGA Productivity. [Internet] [Masters thesis]. Virginia Tech; 2010. [cited 2019 Oct 17]. Available from: http://hdl.handle.net/10919/34499.

Council of Science Editors:

Chandrasekharan A. Accelerating Incremental Floorplanning of Partially Reconfigurable Designs to Improve FPGA Productivity. [Masters Thesis]. Virginia Tech; 2010. Available from: http://hdl.handle.net/10919/34499


Virginia Tech

8. Shagrithaya, Kavya Subraya. Enabling Development of OpenCL Applications on FPGA platforms.

Degree: MS, Electrical and Computer Engineering, 2012, Virginia Tech

 FPGAs can potentially deliver tremendous acceleration in high-performance server and em- bedded computing applications. Whether used to augment a processor or as a stand-alone device,… (more)

Subjects/Keywords: FPGA; AutoESL; OpenCL; Convey; HPC

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APA (6th Edition):

Shagrithaya, K. S. (2012). Enabling Development of OpenCL Applications on FPGA platforms. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/34669

Chicago Manual of Style (16th Edition):

Shagrithaya, Kavya Subraya. “Enabling Development of OpenCL Applications on FPGA platforms.” 2012. Masters Thesis, Virginia Tech. Accessed October 17, 2019. http://hdl.handle.net/10919/34669.

MLA Handbook (7th Edition):

Shagrithaya, Kavya Subraya. “Enabling Development of OpenCL Applications on FPGA platforms.” 2012. Web. 17 Oct 2019.

Vancouver:

Shagrithaya KS. Enabling Development of OpenCL Applications on FPGA platforms. [Internet] [Masters thesis]. Virginia Tech; 2012. [cited 2019 Oct 17]. Available from: http://hdl.handle.net/10919/34669.

Council of Science Editors:

Shagrithaya KS. Enabling Development of OpenCL Applications on FPGA platforms. [Masters Thesis]. Virginia Tech; 2012. Available from: http://hdl.handle.net/10919/34669


Virginia Tech

9. Raja Gopalan, Sureshwar. Timing-Aware Automatic Floorplanning of Partially Reconfigurable Designs for Accelerating FPGA Productivity.

Degree: MS, Electrical and Computer Engineering, 2010, Virginia Tech

 FPGA implementation tool speed has not kept pace with the increase in design size and FPGA density. It is difficult to parallelize place-and-route algorithms without… (more)

Subjects/Keywords: FPGAs; Reconfigurable Computing; Automatic Floorplanning

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APA (6th Edition):

Raja Gopalan, S. (2010). Timing-Aware Automatic Floorplanning of Partially Reconfigurable Designs for Accelerating FPGA Productivity. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/34993

Chicago Manual of Style (16th Edition):

Raja Gopalan, Sureshwar. “Timing-Aware Automatic Floorplanning of Partially Reconfigurable Designs for Accelerating FPGA Productivity.” 2010. Masters Thesis, Virginia Tech. Accessed October 17, 2019. http://hdl.handle.net/10919/34993.

MLA Handbook (7th Edition):

Raja Gopalan, Sureshwar. “Timing-Aware Automatic Floorplanning of Partially Reconfigurable Designs for Accelerating FPGA Productivity.” 2010. Web. 17 Oct 2019.

Vancouver:

Raja Gopalan S. Timing-Aware Automatic Floorplanning of Partially Reconfigurable Designs for Accelerating FPGA Productivity. [Internet] [Masters thesis]. Virginia Tech; 2010. [cited 2019 Oct 17]. Available from: http://hdl.handle.net/10919/34993.

Council of Science Editors:

Raja Gopalan S. Timing-Aware Automatic Floorplanning of Partially Reconfigurable Designs for Accelerating FPGA Productivity. [Masters Thesis]. Virginia Tech; 2010. Available from: http://hdl.handle.net/10919/34993


Virginia Tech

10. Saha, Sonal. An Experimental Evaluation of Real-Time DVFS Scheduling Algorithms.

Degree: MS, Electrical and Computer Engineering, 2011, Virginia Tech

 Dynamic voltage and frequency scaling (DVFS) is an extensively studied energy manage- ment technique, which aims to reduce the energy consumption of computing platforms by… (more)

Subjects/Keywords: Dynamic Voltage and Frequency Scaling; Real-Time Linux

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APA (6th Edition):

Saha, S. (2011). An Experimental Evaluation of Real-Time DVFS Scheduling Algorithms. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/35035

Chicago Manual of Style (16th Edition):

Saha, Sonal. “An Experimental Evaluation of Real-Time DVFS Scheduling Algorithms.” 2011. Masters Thesis, Virginia Tech. Accessed October 17, 2019. http://hdl.handle.net/10919/35035.

MLA Handbook (7th Edition):

Saha, Sonal. “An Experimental Evaluation of Real-Time DVFS Scheduling Algorithms.” 2011. Web. 17 Oct 2019.

Vancouver:

Saha S. An Experimental Evaluation of Real-Time DVFS Scheduling Algorithms. [Internet] [Masters thesis]. Virginia Tech; 2011. [cited 2019 Oct 17]. Available from: http://hdl.handle.net/10919/35035.

Council of Science Editors:

Saha S. An Experimental Evaluation of Real-Time DVFS Scheduling Algorithms. [Masters Thesis]. Virginia Tech; 2011. Available from: http://hdl.handle.net/10919/35035


Virginia Tech

11. Parekh, Umang Kumar. A Toolkit for Rapid FPGA System Deployment.

Degree: MS, Electrical and Computer Engineering, 2010, Virginia Tech

 FPGA implementation tools have not kept pace with growing FPGA density. It is common for non-trivial designs to take multiple hours to go through the… (more)

Subjects/Keywords: Router; Virtex-4; Toolkit; Autonomous; FPGA

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APA (6th Edition):

Parekh, U. K. (2010). A Toolkit for Rapid FPGA System Deployment. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/35703

Chicago Manual of Style (16th Edition):

Parekh, Umang Kumar. “A Toolkit for Rapid FPGA System Deployment.” 2010. Masters Thesis, Virginia Tech. Accessed October 17, 2019. http://hdl.handle.net/10919/35703.

MLA Handbook (7th Edition):

Parekh, Umang Kumar. “A Toolkit for Rapid FPGA System Deployment.” 2010. Web. 17 Oct 2019.

Vancouver:

Parekh UK. A Toolkit for Rapid FPGA System Deployment. [Internet] [Masters thesis]. Virginia Tech; 2010. [cited 2019 Oct 17]. Available from: http://hdl.handle.net/10919/35703.

Council of Science Editors:

Parekh UK. A Toolkit for Rapid FPGA System Deployment. [Masters Thesis]. Virginia Tech; 2010. Available from: http://hdl.handle.net/10919/35703


Virginia Tech

12. Bhardwaj, Prabhaav. Framework for Hardware Agility on FPGAs.

Degree: MS, Electrical and Computer Engineering, 2010, Virginia Tech

 As hardware applications become increasingly complex, the supporting technology needs to evolve and adapt to the demands. Field Programmable Gate Array (FPGA), Application Specific Integrated… (more)

Subjects/Keywords: Virtex 5; Dynamic Routing; FPGA; Reconfigurable Computing

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APA (6th Edition):

Bhardwaj, P. (2010). Framework for Hardware Agility on FPGAs. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/36347

Chicago Manual of Style (16th Edition):

Bhardwaj, Prabhaav. “Framework for Hardware Agility on FPGAs.” 2010. Masters Thesis, Virginia Tech. Accessed October 17, 2019. http://hdl.handle.net/10919/36347.

MLA Handbook (7th Edition):

Bhardwaj, Prabhaav. “Framework for Hardware Agility on FPGAs.” 2010. Web. 17 Oct 2019.

Vancouver:

Bhardwaj P. Framework for Hardware Agility on FPGAs. [Internet] [Masters thesis]. Virginia Tech; 2010. [cited 2019 Oct 17]. Available from: http://hdl.handle.net/10919/36347.

Council of Science Editors:

Bhardwaj P. Framework for Hardware Agility on FPGAs. [Masters Thesis]. Virginia Tech; 2010. Available from: http://hdl.handle.net/10919/36347


Virginia Tech

13. Asthana, Rohit Mohan. High-Level CSP Model Compiler for FPGAs.

Degree: MS, Electrical and Computer Engineering, 2010, Virginia Tech

 The ever-growing competition in current electronics industry has resulted in stringent time-to-market goals and reduced design time available to engineers. Lesser design time has subsequently… (more)

Subjects/Keywords: High-Level Synthesis; FPGAs; Models of Computation (MoC); Communicating Sequential Processes (CSP); Autocode Generation

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APA (6th Edition):

Asthana, R. M. (2010). High-Level CSP Model Compiler for FPGAs. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/36428

Chicago Manual of Style (16th Edition):

Asthana, Rohit Mohan. “High-Level CSP Model Compiler for FPGAs.” 2010. Masters Thesis, Virginia Tech. Accessed October 17, 2019. http://hdl.handle.net/10919/36428.

MLA Handbook (7th Edition):

Asthana, Rohit Mohan. “High-Level CSP Model Compiler for FPGAs.” 2010. Web. 17 Oct 2019.

Vancouver:

Asthana RM. High-Level CSP Model Compiler for FPGAs. [Internet] [Masters thesis]. Virginia Tech; 2010. [cited 2019 Oct 17]. Available from: http://hdl.handle.net/10919/36428.

Council of Science Editors:

Asthana RM. High-Level CSP Model Compiler for FPGAs. [Masters Thesis]. Virginia Tech; 2010. Available from: http://hdl.handle.net/10919/36428


Virginia Tech

14. Jain, Aditya. Impact of Electrical Contacting Scheme on Performance of InGaN/GaN Schottky Solar Cells.

Degree: MS, Electrical and Computer Engineering, 2014, Virginia Tech

 Realization of low-resistance electrical contacts on both sides of a solar cell is essential for obtaining the best possible performance. A key component of a… (more)

Subjects/Keywords: Transparent conductive layer; Schottky solar cell; Device characterization

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APA (6th Edition):

Jain, A. (2014). Impact of Electrical Contacting Scheme on Performance of InGaN/GaN Schottky Solar Cells. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/50527

Chicago Manual of Style (16th Edition):

Jain, Aditya. “Impact of Electrical Contacting Scheme on Performance of InGaN/GaN Schottky Solar Cells.” 2014. Masters Thesis, Virginia Tech. Accessed October 17, 2019. http://hdl.handle.net/10919/50527.

MLA Handbook (7th Edition):

Jain, Aditya. “Impact of Electrical Contacting Scheme on Performance of InGaN/GaN Schottky Solar Cells.” 2014. Web. 17 Oct 2019.

Vancouver:

Jain A. Impact of Electrical Contacting Scheme on Performance of InGaN/GaN Schottky Solar Cells. [Internet] [Masters thesis]. Virginia Tech; 2014. [cited 2019 Oct 17]. Available from: http://hdl.handle.net/10919/50527.

Council of Science Editors:

Jain A. Impact of Electrical Contacting Scheme on Performance of InGaN/GaN Schottky Solar Cells. [Masters Thesis]. Virginia Tech; 2014. Available from: http://hdl.handle.net/10919/50527


Virginia Tech

15. Lee, Kevin. Module Shaping and Exploration in Rapid FPGA Design and Assembly Workflows.

Degree: MS, Electrical and Computer Engineering, 2015, Virginia Tech

 The modular design methodology has been widely adopted to harness the complexity of large FPGA-based systems. As a result, a number of commercial and academic… (more)

Subjects/Keywords: FPGA; Productivity; Rapid Compilation; Modular Workflow

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APA (6th Edition):

Lee, K. (2015). Module Shaping and Exploration in Rapid FPGA Design and Assembly Workflows. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/53705

Chicago Manual of Style (16th Edition):

Lee, Kevin. “Module Shaping and Exploration in Rapid FPGA Design and Assembly Workflows.” 2015. Masters Thesis, Virginia Tech. Accessed October 17, 2019. http://hdl.handle.net/10919/53705.

MLA Handbook (7th Edition):

Lee, Kevin. “Module Shaping and Exploration in Rapid FPGA Design and Assembly Workflows.” 2015. Web. 17 Oct 2019.

Vancouver:

Lee K. Module Shaping and Exploration in Rapid FPGA Design and Assembly Workflows. [Internet] [Masters thesis]. Virginia Tech; 2015. [cited 2019 Oct 17]. Available from: http://hdl.handle.net/10919/53705.

Council of Science Editors:

Lee K. Module Shaping and Exploration in Rapid FPGA Design and Assembly Workflows. [Masters Thesis]. Virginia Tech; 2015. Available from: http://hdl.handle.net/10919/53705


Virginia Tech

16. Vigraham, Sushrutha. Design and Analysis of a Real-time Data Monitoring Prototype for the LWA Radio Telescope.

Degree: MS, Electrical and Computer Engineering, 2011, Virginia Tech

 Increasing computing power has been helping researchers understand many complex scientific problems. Scientific computing helps to model and visualize complex processes such as molecular modelling,… (more)

Subjects/Keywords: data-centric computing; PCIe; data streaming; FPGA

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APA (6th Edition):

Vigraham, S. (2011). Design and Analysis of a Real-time Data Monitoring Prototype for the LWA Radio Telescope. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/31306

Chicago Manual of Style (16th Edition):

Vigraham, Sushrutha. “Design and Analysis of a Real-time Data Monitoring Prototype for the LWA Radio Telescope.” 2011. Masters Thesis, Virginia Tech. Accessed October 17, 2019. http://hdl.handle.net/10919/31306.

MLA Handbook (7th Edition):

Vigraham, Sushrutha. “Design and Analysis of a Real-time Data Monitoring Prototype for the LWA Radio Telescope.” 2011. Web. 17 Oct 2019.

Vancouver:

Vigraham S. Design and Analysis of a Real-time Data Monitoring Prototype for the LWA Radio Telescope. [Internet] [Masters thesis]. Virginia Tech; 2011. [cited 2019 Oct 17]. Available from: http://hdl.handle.net/10919/31306.

Council of Science Editors:

Vigraham S. Design and Analysis of a Real-time Data Monitoring Prototype for the LWA Radio Telescope. [Masters Thesis]. Virginia Tech; 2011. Available from: http://hdl.handle.net/10919/31306


Virginia Tech

17. Mahmoud Mohamedin, Mohamed Ahmed. ByteSTM: Java Software Transactional Memory at the Virtual Machine Level.

Degree: MS, Electrical and Computer Engineering, 2012, Virginia Tech

 As chip vendors are increasingly manufacturing a new generation of multi-processor chips called multicores, improving software performance requires exposing greater concurrency in software. Since code… (more)

Subjects/Keywords: Synchronization; Virtual Machine; Java; Multiprocessor; Concurrency; Software Transactional Memory

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APA (6th Edition):

Mahmoud Mohamedin, M. A. (2012). ByteSTM: Java Software Transactional Memory at the Virtual Machine Level. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/31314

Chicago Manual of Style (16th Edition):

Mahmoud Mohamedin, Mohamed Ahmed. “ByteSTM: Java Software Transactional Memory at the Virtual Machine Level.” 2012. Masters Thesis, Virginia Tech. Accessed October 17, 2019. http://hdl.handle.net/10919/31314.

MLA Handbook (7th Edition):

Mahmoud Mohamedin, Mohamed Ahmed. “ByteSTM: Java Software Transactional Memory at the Virtual Machine Level.” 2012. Web. 17 Oct 2019.

Vancouver:

Mahmoud Mohamedin MA. ByteSTM: Java Software Transactional Memory at the Virtual Machine Level. [Internet] [Masters thesis]. Virginia Tech; 2012. [cited 2019 Oct 17]. Available from: http://hdl.handle.net/10919/31314.

Council of Science Editors:

Mahmoud Mohamedin MA. ByteSTM: Java Software Transactional Memory at the Virtual Machine Level. [Masters Thesis]. Virginia Tech; 2012. Available from: http://hdl.handle.net/10919/31314


Virginia Tech

18. Rawat, Hemendra Kumar. Vector Instruction Set Extensions for Efficient and Reliable Computation of Keccak.

Degree: MS, Electrical and Computer Engineering, 2016, Virginia Tech

 Recent processor architectures such as Intel Westmere (and later) and ARMv8 include instruction-level support for the Advanced Encryption Standard (AES), for the Secure Hashing Standard… (more)

Subjects/Keywords: SIMD; Instruction Set Extensions; SHA-3; Hashing; Authenticated Encryption; Software Integrity

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APA (6th Edition):

Rawat, H. K. (2016). Vector Instruction Set Extensions for Efficient and Reliable Computation of Keccak. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/72857

Chicago Manual of Style (16th Edition):

Rawat, Hemendra Kumar. “Vector Instruction Set Extensions for Efficient and Reliable Computation of Keccak.” 2016. Masters Thesis, Virginia Tech. Accessed October 17, 2019. http://hdl.handle.net/10919/72857.

MLA Handbook (7th Edition):

Rawat, Hemendra Kumar. “Vector Instruction Set Extensions for Efficient and Reliable Computation of Keccak.” 2016. Web. 17 Oct 2019.

Vancouver:

Rawat HK. Vector Instruction Set Extensions for Efficient and Reliable Computation of Keccak. [Internet] [Masters thesis]. Virginia Tech; 2016. [cited 2019 Oct 17]. Available from: http://hdl.handle.net/10919/72857.

Council of Science Editors:

Rawat HK. Vector Instruction Set Extensions for Efficient and Reliable Computation of Keccak. [Masters Thesis]. Virginia Tech; 2016. Available from: http://hdl.handle.net/10919/72857


Virginia Tech

19. Malayattil, Sarosh Aravind. Design of a Multibus Data-Flow Processor Architecture.

Degree: MS, Electrical and Computer Engineering, 2012, Virginia Tech

 General purpose microcontrollers have been used as computational elements in various spheres of technology. Because of the distinct requirements of specific application areas, however, general… (more)

Subjects/Keywords: Automation Framework; Multibus; Electronic Textiles

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APA (6th Edition):

Malayattil, S. A. (2012). Design of a Multibus Data-Flow Processor Architecture. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/31379

Chicago Manual of Style (16th Edition):

Malayattil, Sarosh Aravind. “Design of a Multibus Data-Flow Processor Architecture.” 2012. Masters Thesis, Virginia Tech. Accessed October 17, 2019. http://hdl.handle.net/10919/31379.

MLA Handbook (7th Edition):

Malayattil, Sarosh Aravind. “Design of a Multibus Data-Flow Processor Architecture.” 2012. Web. 17 Oct 2019.

Vancouver:

Malayattil SA. Design of a Multibus Data-Flow Processor Architecture. [Internet] [Masters thesis]. Virginia Tech; 2012. [cited 2019 Oct 17]. Available from: http://hdl.handle.net/10919/31379.

Council of Science Editors:

Malayattil SA. Design of a Multibus Data-Flow Processor Architecture. [Masters Thesis]. Virginia Tech; 2012. Available from: http://hdl.handle.net/10919/31379


Virginia Tech

20. Shelton, Benjamin H. Popcorn Linux: enabling efficient inter-core communication in a Linux-based multikernel operating system.

Degree: MS, Electrical and Computer Engineering, 2013, Virginia Tech

 As manufacturers introduce new machines with more cores, more NUMA-like architectures, and more tightly integrated heterogeneous processors, the traditional abstraction of a monolithic OS running… (more)

Subjects/Keywords: Operating systems; multikernel; high-performance computing; heterogeneous computing; multicore; scalability; message passing

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APA (6th Edition):

Shelton, B. H. (2013). Popcorn Linux: enabling efficient inter-core communication in a Linux-based multikernel operating system. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/23119

Chicago Manual of Style (16th Edition):

Shelton, Benjamin H. “Popcorn Linux: enabling efficient inter-core communication in a Linux-based multikernel operating system.” 2013. Masters Thesis, Virginia Tech. Accessed October 17, 2019. http://hdl.handle.net/10919/23119.

MLA Handbook (7th Edition):

Shelton, Benjamin H. “Popcorn Linux: enabling efficient inter-core communication in a Linux-based multikernel operating system.” 2013. Web. 17 Oct 2019.

Vancouver:

Shelton BH. Popcorn Linux: enabling efficient inter-core communication in a Linux-based multikernel operating system. [Internet] [Masters thesis]. Virginia Tech; 2013. [cited 2019 Oct 17]. Available from: http://hdl.handle.net/10919/23119.

Council of Science Editors:

Shelton BH. Popcorn Linux: enabling efficient inter-core communication in a Linux-based multikernel operating system. [Masters Thesis]. Virginia Tech; 2013. Available from: http://hdl.handle.net/10919/23119


Virginia Tech

21. Keezhanatham Seshadri, Jayashree. Uniform Field Distribution Using Distributed Magnetic Structure.

Degree: MS, Electrical and Computer Engineering, 2014, Virginia Tech

 Energy distribution in a conventional magnetic component is generally not at a designer's disposal. In a conventional toroidal inductor, the energy density is inversely proportional… (more)

Subjects/Keywords: constant flux; constant-flux inductor; low temperature co-fired ceramic; low-profile magnetics; quality factor; transformer

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APA (6th Edition):

Keezhanatham Seshadri, J. (2014). Uniform Field Distribution Using Distributed Magnetic Structure. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/24820

Chicago Manual of Style (16th Edition):

Keezhanatham Seshadri, Jayashree. “Uniform Field Distribution Using Distributed Magnetic Structure.” 2014. Masters Thesis, Virginia Tech. Accessed October 17, 2019. http://hdl.handle.net/10919/24820.

MLA Handbook (7th Edition):

Keezhanatham Seshadri, Jayashree. “Uniform Field Distribution Using Distributed Magnetic Structure.” 2014. Web. 17 Oct 2019.

Vancouver:

Keezhanatham Seshadri J. Uniform Field Distribution Using Distributed Magnetic Structure. [Internet] [Masters thesis]. Virginia Tech; 2014. [cited 2019 Oct 17]. Available from: http://hdl.handle.net/10919/24820.

Council of Science Editors:

Keezhanatham Seshadri J. Uniform Field Distribution Using Distributed Magnetic Structure. [Masters Thesis]. Virginia Tech; 2014. Available from: http://hdl.handle.net/10919/24820


Virginia Tech

22. Kini, Akshatha Jagannath. Implementation of a Trusted I/O Processor on a Nascent SoC-FPGA Based Flight Controller for Unmanned Aerial Systems.

Degree: MS, Electrical and Computer Engineering, 2018, Virginia Tech

 Unmanned Aerial Systems (UAS) are aircraft without a human pilot on board. They are comprised of a ground-based autonomous or human operated control system, an… (more)

Subjects/Keywords: SoC; UAV; FPGA; ZYNQ; MicroBlaze; autopilot; ArduPilot; ArduPlane; GPS; Mission Planner; Sensor; Vulnerabilities; Mailbox

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APA (6th Edition):

Kini, A. J. (2018). Implementation of a Trusted I/O Processor on a Nascent SoC-FPGA Based Flight Controller for Unmanned Aerial Systems. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/82666

Chicago Manual of Style (16th Edition):

Kini, Akshatha Jagannath. “Implementation of a Trusted I/O Processor on a Nascent SoC-FPGA Based Flight Controller for Unmanned Aerial Systems.” 2018. Masters Thesis, Virginia Tech. Accessed October 17, 2019. http://hdl.handle.net/10919/82666.

MLA Handbook (7th Edition):

Kini, Akshatha Jagannath. “Implementation of a Trusted I/O Processor on a Nascent SoC-FPGA Based Flight Controller for Unmanned Aerial Systems.” 2018. Web. 17 Oct 2019.

Vancouver:

Kini AJ. Implementation of a Trusted I/O Processor on a Nascent SoC-FPGA Based Flight Controller for Unmanned Aerial Systems. [Internet] [Masters thesis]. Virginia Tech; 2018. [cited 2019 Oct 17]. Available from: http://hdl.handle.net/10919/82666.

Council of Science Editors:

Kini AJ. Implementation of a Trusted I/O Processor on a Nascent SoC-FPGA Based Flight Controller for Unmanned Aerial Systems. [Masters Thesis]. Virginia Tech; 2018. Available from: http://hdl.handle.net/10919/82666


Virginia Tech

23. Toubeh, Maymoonah I. Risk-Aware Planning by Extracting Uncertainty from Deep Learning-Based Perception.

Degree: MS, Electrical and Computer Engineering, 2018, Virginia Tech

 Deep learning (DL) is the phrase used to refer to the use of large hierarchical structures, often called neural networks, to approximate semantic information from… (more)

Subjects/Keywords: Risk-Aware Planning; Uncertainty Approximation; Deep Learning

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APA (6th Edition):

Toubeh, M. I. (2018). Risk-Aware Planning by Extracting Uncertainty from Deep Learning-Based Perception. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/86884

Chicago Manual of Style (16th Edition):

Toubeh, Maymoonah I. “Risk-Aware Planning by Extracting Uncertainty from Deep Learning-Based Perception.” 2018. Masters Thesis, Virginia Tech. Accessed October 17, 2019. http://hdl.handle.net/10919/86884.

MLA Handbook (7th Edition):

Toubeh, Maymoonah I. “Risk-Aware Planning by Extracting Uncertainty from Deep Learning-Based Perception.” 2018. Web. 17 Oct 2019.

Vancouver:

Toubeh MI. Risk-Aware Planning by Extracting Uncertainty from Deep Learning-Based Perception. [Internet] [Masters thesis]. Virginia Tech; 2018. [cited 2019 Oct 17]. Available from: http://hdl.handle.net/10919/86884.

Council of Science Editors:

Toubeh MI. Risk-Aware Planning by Extracting Uncertainty from Deep Learning-Based Perception. [Masters Thesis]. Virginia Tech; 2018. Available from: http://hdl.handle.net/10919/86884


Virginia Tech

24. Wang, Dong. Image-based Vehicle Localization.

Degree: MS, Electrical and Computer Engineering, 2019, Virginia Tech

 Localization is a crucial topic in navigation, especially in autonomous vehicles navigation. It is usually done by using a global positioning system (GPS) sensor. Even… (more)

Subjects/Keywords: image-based; vehicle localization; text landmark

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APA (6th Edition):

Wang, D. (2019). Image-based Vehicle Localization. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/90795

Chicago Manual of Style (16th Edition):

Wang, Dong. “Image-based Vehicle Localization.” 2019. Masters Thesis, Virginia Tech. Accessed October 17, 2019. http://hdl.handle.net/10919/90795.

MLA Handbook (7th Edition):

Wang, Dong. “Image-based Vehicle Localization.” 2019. Web. 17 Oct 2019.

Vancouver:

Wang D. Image-based Vehicle Localization. [Internet] [Masters thesis]. Virginia Tech; 2019. [cited 2019 Oct 17]. Available from: http://hdl.handle.net/10919/90795.

Council of Science Editors:

Wang D. Image-based Vehicle Localization. [Masters Thesis]. Virginia Tech; 2019. Available from: http://hdl.handle.net/10919/90795

25. Sun, Chang. Scalability Analysis of Synchronous Data-Parallel Artificial Neural Network (ANN) Learners.

Degree: MS, Electrical and Computer Engineering, 2018, Virginia Tech

 Artificial Neural Networks (ANNs) have been established as one of the most important algorithmic tools in the Machine Learning (ML) toolbox over the past few… (more)

Subjects/Keywords: artificial neural networks; machine learning; heterogenous computing; parallel computing

…because MPI is the standard message-passing scheme available on the clusters from Virginia Tech… 

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APA (6th Edition):

Sun, C. (2018). Scalability Analysis of Synchronous Data-Parallel Artificial Neural Network (ANN) Learners. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/85020

Chicago Manual of Style (16th Edition):

Sun, Chang. “Scalability Analysis of Synchronous Data-Parallel Artificial Neural Network (ANN) Learners.” 2018. Masters Thesis, Virginia Tech. Accessed October 17, 2019. http://hdl.handle.net/10919/85020.

MLA Handbook (7th Edition):

Sun, Chang. “Scalability Analysis of Synchronous Data-Parallel Artificial Neural Network (ANN) Learners.” 2018. Web. 17 Oct 2019.

Vancouver:

Sun C. Scalability Analysis of Synchronous Data-Parallel Artificial Neural Network (ANN) Learners. [Internet] [Masters thesis]. Virginia Tech; 2018. [cited 2019 Oct 17]. Available from: http://hdl.handle.net/10919/85020.

Council of Science Editors:

Sun C. Scalability Analysis of Synchronous Data-Parallel Artificial Neural Network (ANN) Learners. [Masters Thesis]. Virginia Tech; 2018. Available from: http://hdl.handle.net/10919/85020


Virginia Tech

26. Linford, John Christian. Accelerating Atmospheric Modeling Through Emerging Multi-core Technologies.

Degree: PhD, Computer Science, 2010, Virginia Tech

 The new generations of multi-core chipset architectures achieve unprecedented levels of computational power while respecting physical and economical constraints. The cost of this power is… (more)

Subjects/Keywords: hardware; high performance computing; software

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APA (6th Edition):

Linford, J. C. (2010). Accelerating Atmospheric Modeling Through Emerging Multi-core Technologies. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/27599

Chicago Manual of Style (16th Edition):

Linford, John Christian. “Accelerating Atmospheric Modeling Through Emerging Multi-core Technologies.” 2010. Doctoral Dissertation, Virginia Tech. Accessed October 17, 2019. http://hdl.handle.net/10919/27599.

MLA Handbook (7th Edition):

Linford, John Christian. “Accelerating Atmospheric Modeling Through Emerging Multi-core Technologies.” 2010. Web. 17 Oct 2019.

Vancouver:

Linford JC. Accelerating Atmospheric Modeling Through Emerging Multi-core Technologies. [Internet] [Doctoral dissertation]. Virginia Tech; 2010. [cited 2019 Oct 17]. Available from: http://hdl.handle.net/10919/27599.

Council of Science Editors:

Linford JC. Accelerating Atmospheric Modeling Through Emerging Multi-core Technologies. [Doctoral Dissertation]. Virginia Tech; 2010. Available from: http://hdl.handle.net/10919/27599


Virginia Tech

27. Zhang, Bo. Supporting Software Transactional Memory in Distributed Systems: Protocols for Cache-Coherence, Conflict Resolution and Replication.

Degree: PhD, Electrical and Computer Engineering, 2011, Virginia Tech

 Lock-based synchronization on multiprocessors is inherently non-scalable, non-composable, and error-prone. These problems are exacerbated in distributed systems due to an additional layer of complexity: multinode… (more)

Subjects/Keywords: Cache-Coherence; Distributed Queuing; Contention Management; Software Transactional Memory; Replication; Quorum System

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APA (6th Edition):

Zhang, B. (2011). Supporting Software Transactional Memory in Distributed Systems: Protocols for Cache-Coherence, Conflict Resolution and Replication. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/29571

Chicago Manual of Style (16th Edition):

Zhang, Bo. “Supporting Software Transactional Memory in Distributed Systems: Protocols for Cache-Coherence, Conflict Resolution and Replication.” 2011. Doctoral Dissertation, Virginia Tech. Accessed October 17, 2019. http://hdl.handle.net/10919/29571.

MLA Handbook (7th Edition):

Zhang, Bo. “Supporting Software Transactional Memory in Distributed Systems: Protocols for Cache-Coherence, Conflict Resolution and Replication.” 2011. Web. 17 Oct 2019.

Vancouver:

Zhang B. Supporting Software Transactional Memory in Distributed Systems: Protocols for Cache-Coherence, Conflict Resolution and Replication. [Internet] [Doctoral dissertation]. Virginia Tech; 2011. [cited 2019 Oct 17]. Available from: http://hdl.handle.net/10919/29571.

Council of Science Editors:

Zhang B. Supporting Software Transactional Memory in Distributed Systems: Protocols for Cache-Coherence, Conflict Resolution and Replication. [Doctoral Dissertation]. Virginia Tech; 2011. Available from: http://hdl.handle.net/10919/29571


Virginia Tech

28. Saad Ibrahim, Mohamed Mohamed. HyFlow: A High Performance Distributed Software Transactional Memory Framework.

Degree: MS, Electrical and Computer Engineering, 2011, Virginia Tech

 We present HyFlow - a distributed software transactional memory (D-STM) framework for distributed concurrency control. Lock-based concurrency control suffers from drawbacks including deadlocks, livelocks, and… (more)

Subjects/Keywords: Directory Protocols; Cache Coherence; Contention Management; Control-Flow; Dataflow; Software Transactional Memory; Distributed Systems

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APA (6th Edition):

Saad Ibrahim, M. M. (2011). HyFlow: A High Performance Distributed Software Transactional Memory Framework. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/32966

Chicago Manual of Style (16th Edition):

Saad Ibrahim, Mohamed Mohamed. “HyFlow: A High Performance Distributed Software Transactional Memory Framework.” 2011. Masters Thesis, Virginia Tech. Accessed October 17, 2019. http://hdl.handle.net/10919/32966.

MLA Handbook (7th Edition):

Saad Ibrahim, Mohamed Mohamed. “HyFlow: A High Performance Distributed Software Transactional Memory Framework.” 2011. Web. 17 Oct 2019.

Vancouver:

Saad Ibrahim MM. HyFlow: A High Performance Distributed Software Transactional Memory Framework. [Internet] [Masters thesis]. Virginia Tech; 2011. [cited 2019 Oct 17]. Available from: http://hdl.handle.net/10919/32966.

Council of Science Editors:

Saad Ibrahim MM. HyFlow: A High Performance Distributed Software Transactional Memory Framework. [Masters Thesis]. Virginia Tech; 2011. Available from: http://hdl.handle.net/10919/32966


Virginia Tech

29. Lai, Shouwen. Duty-Cycled Wireless Sensor Networks: Wakeup Scheduling, Routing, and Broadcasting.

Degree: PhD, Electrical and Computer Engineering, 2010, Virginia Tech

 In order to save energy consumption in idle states, low duty-cycled operation is widely used in Wireless Sensor Networks (WSNs), where each node periodically switches… (more)

Subjects/Keywords: Wireless Sensor Network; Duty Cycle; MAC; Routing; Broadcast; Quorum System

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APA (6th Edition):

Lai, S. (2010). Duty-Cycled Wireless Sensor Networks: Wakeup Scheduling, Routing, and Broadcasting. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/27333

Chicago Manual of Style (16th Edition):

Lai, Shouwen. “Duty-Cycled Wireless Sensor Networks: Wakeup Scheduling, Routing, and Broadcasting.” 2010. Doctoral Dissertation, Virginia Tech. Accessed October 17, 2019. http://hdl.handle.net/10919/27333.

MLA Handbook (7th Edition):

Lai, Shouwen. “Duty-Cycled Wireless Sensor Networks: Wakeup Scheduling, Routing, and Broadcasting.” 2010. Web. 17 Oct 2019.

Vancouver:

Lai S. Duty-Cycled Wireless Sensor Networks: Wakeup Scheduling, Routing, and Broadcasting. [Internet] [Doctoral dissertation]. Virginia Tech; 2010. [cited 2019 Oct 17]. Available from: http://hdl.handle.net/10919/27333.

Council of Science Editors:

Lai S. Duty-Cycled Wireless Sensor Networks: Wakeup Scheduling, Routing, and Broadcasting. [Doctoral Dissertation]. Virginia Tech; 2010. Available from: http://hdl.handle.net/10919/27333


Virginia Tech

30. Lu, Peng. Resilire: Achieving High Availability Through Virtual Machine Live Migration.

Degree: PhD, Electrical and Computer Engineering, 2013, Virginia Tech

 High availability is a critical feature of data centers, cloud, and cluster computing environments. Replication is a classical approach to increase service availability by providing… (more)

Subjects/Keywords: High Availability; Virtual Machine; Live Migration; Checkpointing; Load Balancing; Downtime; Xen; Hypervisor

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APA (6th Edition):

Lu, P. (2013). Resilire: Achieving High Availability Through Virtual Machine Live Migration. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/25434

Chicago Manual of Style (16th Edition):

Lu, Peng. “Resilire: Achieving High Availability Through Virtual Machine Live Migration.” 2013. Doctoral Dissertation, Virginia Tech. Accessed October 17, 2019. http://hdl.handle.net/10919/25434.

MLA Handbook (7th Edition):

Lu, Peng. “Resilire: Achieving High Availability Through Virtual Machine Live Migration.” 2013. Web. 17 Oct 2019.

Vancouver:

Lu P. Resilire: Achieving High Availability Through Virtual Machine Live Migration. [Internet] [Doctoral dissertation]. Virginia Tech; 2013. [cited 2019 Oct 17]. Available from: http://hdl.handle.net/10919/25434.

Council of Science Editors:

Lu P. Resilire: Achieving High Availability Through Virtual Machine Live Migration. [Doctoral Dissertation]. Virginia Tech; 2013. Available from: http://hdl.handle.net/10919/25434

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