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You searched for +publisher:"Virginia Tech" +contributor:("Patterson, Cameron D."). Showing records 1 – 30 of 94 total matches.

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Virginia Tech

1. Dellinger, Matthew Aalseth. An Experimental Evaluation of the Scalability of Real-Time Scheduling Algorithms on Large-Scale Multicore Platforms.

Degree: MS, Electrical and Computer Engineering, 2011, Virginia Tech

 This thesis studies the problem of experimentally evaluating the scaling behaviors of existing multicore real-time task scheduling algorithms on large-scale multicore platforms. As chip manufacturers… (more)

Subjects/Keywords: Linux; Utility Accrual; Scheduling; Real-Time; Multiprocessors

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APA (6th Edition):

Dellinger, M. A. (2011). An Experimental Evaluation of the Scalability of Real-Time Scheduling Algorithms on Large-Scale Multicore Platforms. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/32674

Chicago Manual of Style (16th Edition):

Dellinger, Matthew Aalseth. “An Experimental Evaluation of the Scalability of Real-Time Scheduling Algorithms on Large-Scale Multicore Platforms.” 2011. Masters Thesis, Virginia Tech. Accessed April 03, 2020. http://hdl.handle.net/10919/32674.

MLA Handbook (7th Edition):

Dellinger, Matthew Aalseth. “An Experimental Evaluation of the Scalability of Real-Time Scheduling Algorithms on Large-Scale Multicore Platforms.” 2011. Web. 03 Apr 2020.

Vancouver:

Dellinger MA. An Experimental Evaluation of the Scalability of Real-Time Scheduling Algorithms on Large-Scale Multicore Platforms. [Internet] [Masters thesis]. Virginia Tech; 2011. [cited 2020 Apr 03]. Available from: http://hdl.handle.net/10919/32674.

Council of Science Editors:

Dellinger MA. An Experimental Evaluation of the Scalability of Real-Time Scheduling Algorithms on Large-Scale Multicore Platforms. [Masters Thesis]. Virginia Tech; 2011. Available from: http://hdl.handle.net/10919/32674


Virginia Tech

2. Limaye, Chinmay Avinash. Formal Verification Techniques for Reversible Circuits.

Degree: MS, Electrical and Computer Engineering, 2011, Virginia Tech

 As the number of transistors per unit chip area increases, the power dissipation of the chip becomes a bottleneck. New nano-technology materials have been proposed… (more)

Subjects/Keywords: Binary Decision Diagram (BDD); Reversible Circuits; Redundancy; Equivalence Checking

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APA (6th Edition):

Limaye, C. A. (2011). Formal Verification Techniques for Reversible Circuits. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/33406

Chicago Manual of Style (16th Edition):

Limaye, Chinmay Avinash. “Formal Verification Techniques for Reversible Circuits.” 2011. Masters Thesis, Virginia Tech. Accessed April 03, 2020. http://hdl.handle.net/10919/33406.

MLA Handbook (7th Edition):

Limaye, Chinmay Avinash. “Formal Verification Techniques for Reversible Circuits.” 2011. Web. 03 Apr 2020.

Vancouver:

Limaye CA. Formal Verification Techniques for Reversible Circuits. [Internet] [Masters thesis]. Virginia Tech; 2011. [cited 2020 Apr 03]. Available from: http://hdl.handle.net/10919/33406.

Council of Science Editors:

Limaye CA. Formal Verification Techniques for Reversible Circuits. [Masters Thesis]. Virginia Tech; 2011. Available from: http://hdl.handle.net/10919/33406


Virginia Tech

3. Stroop, Richard Henry Lee. Enhancing GNU Radio for Run-Time Assembly of FPGA-Based Accelerators.

Degree: MS, Electrical and Computer Engineering, 2012, Virginia Tech

 Software defined radios (SDRs) have changed the paradigm of slowly designing custom ra- dios, instead allowing designers to quickly iterate designs with a large range… (more)

Subjects/Keywords: FPGA; SDR; qFlow; GNU Radio

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APA (6th Edition):

Stroop, R. H. L. (2012). Enhancing GNU Radio for Run-Time Assembly of FPGA-Based Accelerators. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/34426

Chicago Manual of Style (16th Edition):

Stroop, Richard Henry Lee. “Enhancing GNU Radio for Run-Time Assembly of FPGA-Based Accelerators.” 2012. Masters Thesis, Virginia Tech. Accessed April 03, 2020. http://hdl.handle.net/10919/34426.

MLA Handbook (7th Edition):

Stroop, Richard Henry Lee. “Enhancing GNU Radio for Run-Time Assembly of FPGA-Based Accelerators.” 2012. Web. 03 Apr 2020.

Vancouver:

Stroop RHL. Enhancing GNU Radio for Run-Time Assembly of FPGA-Based Accelerators. [Internet] [Masters thesis]. Virginia Tech; 2012. [cited 2020 Apr 03]. Available from: http://hdl.handle.net/10919/34426.

Council of Science Editors:

Stroop RHL. Enhancing GNU Radio for Run-Time Assembly of FPGA-Based Accelerators. [Masters Thesis]. Virginia Tech; 2012. Available from: http://hdl.handle.net/10919/34426


Virginia Tech

4. Chandrasekharan, Athira. Accelerating Incremental Floorplanning of Partially Reconfigurable Designs to Improve FPGA Productivity.

Degree: MS, Electrical and Computer Engineering, 2010, Virginia Tech

 FPGA implementation tool turnaround time has unfortunately not kept pace with FPGA density advances. It is difficult to parallelize place-and-route algorithms without sacrificing determinism or… (more)

Subjects/Keywords: Reconfigurable Computing; Incremental Floorplanning; FPGAs

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APA (6th Edition):

Chandrasekharan, A. (2010). Accelerating Incremental Floorplanning of Partially Reconfigurable Designs to Improve FPGA Productivity. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/34499

Chicago Manual of Style (16th Edition):

Chandrasekharan, Athira. “Accelerating Incremental Floorplanning of Partially Reconfigurable Designs to Improve FPGA Productivity.” 2010. Masters Thesis, Virginia Tech. Accessed April 03, 2020. http://hdl.handle.net/10919/34499.

MLA Handbook (7th Edition):

Chandrasekharan, Athira. “Accelerating Incremental Floorplanning of Partially Reconfigurable Designs to Improve FPGA Productivity.” 2010. Web. 03 Apr 2020.

Vancouver:

Chandrasekharan A. Accelerating Incremental Floorplanning of Partially Reconfigurable Designs to Improve FPGA Productivity. [Internet] [Masters thesis]. Virginia Tech; 2010. [cited 2020 Apr 03]. Available from: http://hdl.handle.net/10919/34499.

Council of Science Editors:

Chandrasekharan A. Accelerating Incremental Floorplanning of Partially Reconfigurable Designs to Improve FPGA Productivity. [Masters Thesis]. Virginia Tech; 2010. Available from: http://hdl.handle.net/10919/34499


Virginia Tech

5. Surendra, Kanchana. Modeling and Design of a Three-dimensional Inductor with Magnetic Core.

Degree: MS, Electrical and Computer Engineering, 2011, Virginia Tech

 As the demand for portable electronic devices increase, the need to replace off-chip discrete devices with on-chip devices is imperative. Inductors are one such passive… (more)

Subjects/Keywords: inductance; quality factor; parasitics

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APA (6th Edition):

Surendra, K. (2011). Modeling and Design of a Three-dimensional Inductor with Magnetic Core. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/34565

Chicago Manual of Style (16th Edition):

Surendra, Kanchana. “Modeling and Design of a Three-dimensional Inductor with Magnetic Core.” 2011. Masters Thesis, Virginia Tech. Accessed April 03, 2020. http://hdl.handle.net/10919/34565.

MLA Handbook (7th Edition):

Surendra, Kanchana. “Modeling and Design of a Three-dimensional Inductor with Magnetic Core.” 2011. Web. 03 Apr 2020.

Vancouver:

Surendra K. Modeling and Design of a Three-dimensional Inductor with Magnetic Core. [Internet] [Masters thesis]. Virginia Tech; 2011. [cited 2020 Apr 03]. Available from: http://hdl.handle.net/10919/34565.

Council of Science Editors:

Surendra K. Modeling and Design of a Three-dimensional Inductor with Magnetic Core. [Masters Thesis]. Virginia Tech; 2011. Available from: http://hdl.handle.net/10919/34565


Virginia Tech

6. Raja Gopalan, Sureshwar. Timing-Aware Automatic Floorplanning of Partially Reconfigurable Designs for Accelerating FPGA Productivity.

Degree: MS, Electrical and Computer Engineering, 2010, Virginia Tech

 FPGA implementation tool speed has not kept pace with the increase in design size and FPGA density. It is difficult to parallelize place-and-route algorithms without… (more)

Subjects/Keywords: FPGAs; Reconfigurable Computing; Automatic Floorplanning

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APA (6th Edition):

Raja Gopalan, S. (2010). Timing-Aware Automatic Floorplanning of Partially Reconfigurable Designs for Accelerating FPGA Productivity. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/34993

Chicago Manual of Style (16th Edition):

Raja Gopalan, Sureshwar. “Timing-Aware Automatic Floorplanning of Partially Reconfigurable Designs for Accelerating FPGA Productivity.” 2010. Masters Thesis, Virginia Tech. Accessed April 03, 2020. http://hdl.handle.net/10919/34993.

MLA Handbook (7th Edition):

Raja Gopalan, Sureshwar. “Timing-Aware Automatic Floorplanning of Partially Reconfigurable Designs for Accelerating FPGA Productivity.” 2010. Web. 03 Apr 2020.

Vancouver:

Raja Gopalan S. Timing-Aware Automatic Floorplanning of Partially Reconfigurable Designs for Accelerating FPGA Productivity. [Internet] [Masters thesis]. Virginia Tech; 2010. [cited 2020 Apr 03]. Available from: http://hdl.handle.net/10919/34993.

Council of Science Editors:

Raja Gopalan S. Timing-Aware Automatic Floorplanning of Partially Reconfigurable Designs for Accelerating FPGA Productivity. [Masters Thesis]. Virginia Tech; 2010. Available from: http://hdl.handle.net/10919/34993


Virginia Tech

7. Marballie, Gladstone Washington. Symbol Timing and Coarse Classification of Phase Modulated Signals on a Standalone SDR Platform.

Degree: MS, Electrical and Computer Engineering, 2010, Virginia Tech

 The Universal Classifier Synchronizer (UCS) is a Cognitive Radio system/sensor that can detect, classify, and extract the relevant parameters from a received signal to establish… (more)

Subjects/Keywords: FPGA; Signal Classification; Symbol Timing; DSP; SDR; Cognitive Radio

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APA (6th Edition):

Marballie, G. W. (2010). Symbol Timing and Coarse Classification of Phase Modulated Signals on a Standalone SDR Platform. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/35409

Chicago Manual of Style (16th Edition):

Marballie, Gladstone Washington. “Symbol Timing and Coarse Classification of Phase Modulated Signals on a Standalone SDR Platform.” 2010. Masters Thesis, Virginia Tech. Accessed April 03, 2020. http://hdl.handle.net/10919/35409.

MLA Handbook (7th Edition):

Marballie, Gladstone Washington. “Symbol Timing and Coarse Classification of Phase Modulated Signals on a Standalone SDR Platform.” 2010. Web. 03 Apr 2020.

Vancouver:

Marballie GW. Symbol Timing and Coarse Classification of Phase Modulated Signals on a Standalone SDR Platform. [Internet] [Masters thesis]. Virginia Tech; 2010. [cited 2020 Apr 03]. Available from: http://hdl.handle.net/10919/35409.

Council of Science Editors:

Marballie GW. Symbol Timing and Coarse Classification of Phase Modulated Signals on a Standalone SDR Platform. [Masters Thesis]. Virginia Tech; 2010. Available from: http://hdl.handle.net/10919/35409


Virginia Tech

8. Subbarayan, Guruprasad. Automatic Instantiation and Timing-Aware Placement of Bus Macros for Partially Reconfigurable FPGA Designs.

Degree: MS, Electrical and Computer Engineering, 2010, Virginia Tech

 FPGA design implementation and debug tools have not kept pace with the advances in FPGA device density. The emphasis on area optimization and circuit speed… (more)

Subjects/Keywords: FPGAs; Partial Reconfiguration; Bus macros

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APA (6th Edition):

Subbarayan, G. (2010). Automatic Instantiation and Timing-Aware Placement of Bus Macros for Partially Reconfigurable FPGA Designs. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/46033

Chicago Manual of Style (16th Edition):

Subbarayan, Guruprasad. “Automatic Instantiation and Timing-Aware Placement of Bus Macros for Partially Reconfigurable FPGA Designs.” 2010. Masters Thesis, Virginia Tech. Accessed April 03, 2020. http://hdl.handle.net/10919/46033.

MLA Handbook (7th Edition):

Subbarayan, Guruprasad. “Automatic Instantiation and Timing-Aware Placement of Bus Macros for Partially Reconfigurable FPGA Designs.” 2010. Web. 03 Apr 2020.

Vancouver:

Subbarayan G. Automatic Instantiation and Timing-Aware Placement of Bus Macros for Partially Reconfigurable FPGA Designs. [Internet] [Masters thesis]. Virginia Tech; 2010. [cited 2020 Apr 03]. Available from: http://hdl.handle.net/10919/46033.

Council of Science Editors:

Subbarayan G. Automatic Instantiation and Timing-Aware Placement of Bus Macros for Partially Reconfigurable FPGA Designs. [Masters Thesis]. Virginia Tech; 2010. Available from: http://hdl.handle.net/10919/46033


Virginia Tech

9. Pabbuleti, Krishna Chaitanya. Performance Optimization of Public Key Cryptography on Embedded Platforms.

Degree: MS, Electrical and Computer Engineering, 2014, Virginia Tech

 Embedded systems are so ubiquitous that they account for almost 90% of all the computing devices. They range from very small scale devices with an… (more)

Subjects/Keywords: Elliptic Curve Cryptography; Modular Arithmetic; SIMD; Hash-based Signatures; MSP430; Wireless Sensor Node

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APA (6th Edition):

Pabbuleti, K. C. (2014). Performance Optimization of Public Key Cryptography on Embedded Platforms. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/48120

Chicago Manual of Style (16th Edition):

Pabbuleti, Krishna Chaitanya. “Performance Optimization of Public Key Cryptography on Embedded Platforms.” 2014. Masters Thesis, Virginia Tech. Accessed April 03, 2020. http://hdl.handle.net/10919/48120.

MLA Handbook (7th Edition):

Pabbuleti, Krishna Chaitanya. “Performance Optimization of Public Key Cryptography on Embedded Platforms.” 2014. Web. 03 Apr 2020.

Vancouver:

Pabbuleti KC. Performance Optimization of Public Key Cryptography on Embedded Platforms. [Internet] [Masters thesis]. Virginia Tech; 2014. [cited 2020 Apr 03]. Available from: http://hdl.handle.net/10919/48120.

Council of Science Editors:

Pabbuleti KC. Performance Optimization of Public Key Cryptography on Embedded Platforms. [Masters Thesis]. Virginia Tech; 2014. Available from: http://hdl.handle.net/10919/48120


Virginia Tech

10. Balasubramanian, Harish. Incremental Design Migration Support in Industrial Control Systems Development.

Degree: MS, Electrical and Computer Engineering, 2014, Virginia Tech

 Industrial control systems (ICS) play an extremely important role in the world around us. They have helped in reducing human effort and contributed to automation… (more)

Subjects/Keywords: Industrial control systems; incremental migration; model-based design; interface abstraction

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APA (6th Edition):

Balasubramanian, H. (2014). Incremental Design Migration Support in Industrial Control Systems Development. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/50990

Chicago Manual of Style (16th Edition):

Balasubramanian, Harish. “Incremental Design Migration Support in Industrial Control Systems Development.” 2014. Masters Thesis, Virginia Tech. Accessed April 03, 2020. http://hdl.handle.net/10919/50990.

MLA Handbook (7th Edition):

Balasubramanian, Harish. “Incremental Design Migration Support in Industrial Control Systems Development.” 2014. Web. 03 Apr 2020.

Vancouver:

Balasubramanian H. Incremental Design Migration Support in Industrial Control Systems Development. [Internet] [Masters thesis]. Virginia Tech; 2014. [cited 2020 Apr 03]. Available from: http://hdl.handle.net/10919/50990.

Council of Science Editors:

Balasubramanian H. Incremental Design Migration Support in Industrial Control Systems Development. [Masters Thesis]. Virginia Tech; 2014. Available from: http://hdl.handle.net/10919/50990


Virginia Tech

11. Quesenberry, Joshua Daniel. Communication Synthesis for MIMO Decoder Matrices.

Degree: MS, Electrical and Computer Engineering, 2011, Virginia Tech

 The design in this work provides an easy and cost-efficient way of performing an FPGA implementation of a specific algorithm through use of a custom… (more)

Subjects/Keywords: Communication Synthesis; MIMO; FPGA; Xilinx

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APA (6th Edition):

Quesenberry, J. D. (2011). Communication Synthesis for MIMO Decoder Matrices. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/51149

Chicago Manual of Style (16th Edition):

Quesenberry, Joshua Daniel. “Communication Synthesis for MIMO Decoder Matrices.” 2011. Masters Thesis, Virginia Tech. Accessed April 03, 2020. http://hdl.handle.net/10919/51149.

MLA Handbook (7th Edition):

Quesenberry, Joshua Daniel. “Communication Synthesis for MIMO Decoder Matrices.” 2011. Web. 03 Apr 2020.

Vancouver:

Quesenberry JD. Communication Synthesis for MIMO Decoder Matrices. [Internet] [Masters thesis]. Virginia Tech; 2011. [cited 2020 Apr 03]. Available from: http://hdl.handle.net/10919/51149.

Council of Science Editors:

Quesenberry JD. Communication Synthesis for MIMO Decoder Matrices. [Masters Thesis]. Virginia Tech; 2011. Available from: http://hdl.handle.net/10919/51149


Virginia Tech

12. Burns, Kevin Patrick. Real-Time Hierarchical Scheduling of Virtualized Systems.

Degree: MS, Electrical and Computer Engineering, 2014, Virginia Tech

 In industry there has been a large focus on system integration and server consolidation, even for real-time systems, leading to an interest in virtualization. However,… (more)

Subjects/Keywords: Real-time; Virtualization; KairosVM; KVM; Linux

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APA (6th Edition):

Burns, K. P. (2014). Real-Time Hierarchical Scheduling of Virtualized Systems. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/51790

Chicago Manual of Style (16th Edition):

Burns, Kevin Patrick. “Real-Time Hierarchical Scheduling of Virtualized Systems.” 2014. Masters Thesis, Virginia Tech. Accessed April 03, 2020. http://hdl.handle.net/10919/51790.

MLA Handbook (7th Edition):

Burns, Kevin Patrick. “Real-Time Hierarchical Scheduling of Virtualized Systems.” 2014. Web. 03 Apr 2020.

Vancouver:

Burns KP. Real-Time Hierarchical Scheduling of Virtualized Systems. [Internet] [Masters thesis]. Virginia Tech; 2014. [cited 2020 Apr 03]. Available from: http://hdl.handle.net/10919/51790.

Council of Science Editors:

Burns KP. Real-Time Hierarchical Scheduling of Virtualized Systems. [Masters Thesis]. Virginia Tech; 2014. Available from: http://hdl.handle.net/10919/51790


Virginia Tech

13. Harshe, Omkar Anand. Preemptive Detection of Cyber Attacks on Industrial Control Systems.

Degree: MS, Electrical and Computer Engineering, 2015, Virginia Tech

 Industrial Control Systems (ICSes), networked through conventional IT infrastructures, are vulnerable to attacks originating from network channels. Perimeter security techniques such as access control and… (more)

Subjects/Keywords: Industrial control systems; malware resilience; real-time prediction; classifier-based intrusion detection

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APA (6th Edition):

Harshe, O. A. (2015). Preemptive Detection of Cyber Attacks on Industrial Control Systems. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/54005

Chicago Manual of Style (16th Edition):

Harshe, Omkar Anand. “Preemptive Detection of Cyber Attacks on Industrial Control Systems.” 2015. Masters Thesis, Virginia Tech. Accessed April 03, 2020. http://hdl.handle.net/10919/54005.

MLA Handbook (7th Edition):

Harshe, Omkar Anand. “Preemptive Detection of Cyber Attacks on Industrial Control Systems.” 2015. Web. 03 Apr 2020.

Vancouver:

Harshe OA. Preemptive Detection of Cyber Attacks on Industrial Control Systems. [Internet] [Masters thesis]. Virginia Tech; 2015. [cited 2020 Apr 03]. Available from: http://hdl.handle.net/10919/54005.

Council of Science Editors:

Harshe OA. Preemptive Detection of Cyber Attacks on Industrial Control Systems. [Masters Thesis]. Virginia Tech; 2015. Available from: http://hdl.handle.net/10919/54005


Virginia Tech

14. Sayed, Shereef. Black-Box Fuzzing of the REDHAWK Software Communications Architecture.

Degree: MS, Electrical and Computer Engineering, 2015, Virginia Tech

 As the complexity of software increases, so does the complexity of software testing. This challenge is especially true for modern military communications as radio functionality… (more)

Subjects/Keywords: Security; Fuzzing; SCA; OSSIE; REDHAWK

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APA (6th Edition):

Sayed, S. (2015). Black-Box Fuzzing of the REDHAWK Software Communications Architecture. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/54566

Chicago Manual of Style (16th Edition):

Sayed, Shereef. “Black-Box Fuzzing of the REDHAWK Software Communications Architecture.” 2015. Masters Thesis, Virginia Tech. Accessed April 03, 2020. http://hdl.handle.net/10919/54566.

MLA Handbook (7th Edition):

Sayed, Shereef. “Black-Box Fuzzing of the REDHAWK Software Communications Architecture.” 2015. Web. 03 Apr 2020.

Vancouver:

Sayed S. Black-Box Fuzzing of the REDHAWK Software Communications Architecture. [Internet] [Masters thesis]. Virginia Tech; 2015. [cited 2020 Apr 03]. Available from: http://hdl.handle.net/10919/54566.

Council of Science Editors:

Sayed S. Black-Box Fuzzing of the REDHAWK Software Communications Architecture. [Masters Thesis]. Virginia Tech; 2015. Available from: http://hdl.handle.net/10919/54566


Virginia Tech

15. Vigraham, Sushrutha. Design and Analysis of a Real-time Data Monitoring Prototype for the LWA Radio Telescope.

Degree: MS, Electrical and Computer Engineering, 2011, Virginia Tech

 Increasing computing power has been helping researchers understand many complex scientific problems. Scientific computing helps to model and visualize complex processes such as molecular modelling,… (more)

Subjects/Keywords: data-centric computing; PCIe; data streaming; FPGA

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APA (6th Edition):

Vigraham, S. (2011). Design and Analysis of a Real-time Data Monitoring Prototype for the LWA Radio Telescope. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/31306

Chicago Manual of Style (16th Edition):

Vigraham, Sushrutha. “Design and Analysis of a Real-time Data Monitoring Prototype for the LWA Radio Telescope.” 2011. Masters Thesis, Virginia Tech. Accessed April 03, 2020. http://hdl.handle.net/10919/31306.

MLA Handbook (7th Edition):

Vigraham, Sushrutha. “Design and Analysis of a Real-time Data Monitoring Prototype for the LWA Radio Telescope.” 2011. Web. 03 Apr 2020.

Vancouver:

Vigraham S. Design and Analysis of a Real-time Data Monitoring Prototype for the LWA Radio Telescope. [Internet] [Masters thesis]. Virginia Tech; 2011. [cited 2020 Apr 03]. Available from: http://hdl.handle.net/10919/31306.

Council of Science Editors:

Vigraham S. Design and Analysis of a Real-time Data Monitoring Prototype for the LWA Radio Telescope. [Masters Thesis]. Virginia Tech; 2011. Available from: http://hdl.handle.net/10919/31306


Virginia Tech

16. Deshmukh, Pallavi Prafulla. A Hands-on Modular Laboratory Environment to Foster Learning in Control System Security.

Degree: MS, Electrical and Computer Engineering, 2016, Virginia Tech

 Cyber-Physical Systems (CPSes) form the core of Industrial Control Systems (ICS) and critical infrastructures. These systems use computers to control and monitor physical processes in… (more)

Subjects/Keywords: cybersecurity; trust; embedded security; modular education; security lab; hands-on learning; embedded systems; cyber-physical systems; control systems

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APA (6th Edition):

Deshmukh, P. P. (2016). A Hands-on Modular Laboratory Environment to Foster Learning in Control System Security. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/71755

Chicago Manual of Style (16th Edition):

Deshmukh, Pallavi Prafulla. “A Hands-on Modular Laboratory Environment to Foster Learning in Control System Security.” 2016. Masters Thesis, Virginia Tech. Accessed April 03, 2020. http://hdl.handle.net/10919/71755.

MLA Handbook (7th Edition):

Deshmukh, Pallavi Prafulla. “A Hands-on Modular Laboratory Environment to Foster Learning in Control System Security.” 2016. Web. 03 Apr 2020.

Vancouver:

Deshmukh PP. A Hands-on Modular Laboratory Environment to Foster Learning in Control System Security. [Internet] [Masters thesis]. Virginia Tech; 2016. [cited 2020 Apr 03]. Available from: http://hdl.handle.net/10919/71755.

Council of Science Editors:

Deshmukh PP. A Hands-on Modular Laboratory Environment to Foster Learning in Control System Security. [Masters Thesis]. Virginia Tech; 2016. Available from: http://hdl.handle.net/10919/71755

17. Kedia, Namrata Rajiv. GUCCI: Ground station Uplink Command and Control Interpreter.

Degree: MS, Electrical and Computer Engineering, 2016, Virginia Tech

 For a successful CubeSat mission, it is imperative to schedule events in a fashion that will generate maximum useful science data. Intuitive uplink commanding software… (more)

Subjects/Keywords: Up-link; Ground Station; User Interface; Scheduler; Spacecraft

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APA (6th Edition):

Kedia, N. R. (2016). GUCCI: Ground station Uplink Command and Control Interpreter. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/71885

Chicago Manual of Style (16th Edition):

Kedia, Namrata Rajiv. “GUCCI: Ground station Uplink Command and Control Interpreter.” 2016. Masters Thesis, Virginia Tech. Accessed April 03, 2020. http://hdl.handle.net/10919/71885.

MLA Handbook (7th Edition):

Kedia, Namrata Rajiv. “GUCCI: Ground station Uplink Command and Control Interpreter.” 2016. Web. 03 Apr 2020.

Vancouver:

Kedia NR. GUCCI: Ground station Uplink Command and Control Interpreter. [Internet] [Masters thesis]. Virginia Tech; 2016. [cited 2020 Apr 03]. Available from: http://hdl.handle.net/10919/71885.

Council of Science Editors:

Kedia NR. GUCCI: Ground station Uplink Command and Control Interpreter. [Masters Thesis]. Virginia Tech; 2016. Available from: http://hdl.handle.net/10919/71885


Virginia Tech

18. Zeng, Kevin. Enhancing Productivity with Back-End Similarity Matching of Digital Circuits for IP Reuse.

Degree: MS, Electrical and Computer Engineering, 2013, Virginia Tech

 Productivity for digital circuit design is being outpaced currently by the rate at which silicon is growing such as FPGAs. Complex designs take a large… (more)

Subjects/Keywords: FPGA; Productivity; Digital Circuits; Graph Matching; Similarity; IP Reuse

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APA (6th Edition):

Zeng, K. (2013). Enhancing Productivity with Back-End Similarity Matching of Digital Circuits for IP Reuse. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/23144

Chicago Manual of Style (16th Edition):

Zeng, Kevin. “Enhancing Productivity with Back-End Similarity Matching of Digital Circuits for IP Reuse.” 2013. Masters Thesis, Virginia Tech. Accessed April 03, 2020. http://hdl.handle.net/10919/23144.

MLA Handbook (7th Edition):

Zeng, Kevin. “Enhancing Productivity with Back-End Similarity Matching of Digital Circuits for IP Reuse.” 2013. Web. 03 Apr 2020.

Vancouver:

Zeng K. Enhancing Productivity with Back-End Similarity Matching of Digital Circuits for IP Reuse. [Internet] [Masters thesis]. Virginia Tech; 2013. [cited 2020 Apr 03]. Available from: http://hdl.handle.net/10919/23144.

Council of Science Editors:

Zeng K. Enhancing Productivity with Back-End Similarity Matching of Digital Circuits for IP Reuse. [Masters Thesis]. Virginia Tech; 2013. Available from: http://hdl.handle.net/10919/23144


Virginia Tech

19. Blake, Madison Thomas. An Ambulatory Monitoring Algorithm to Unify Diverse E-Textile Garments.

Degree: MS, Electrical and Computer Engineering, 2014, Virginia Tech

 In this thesis, an activity classification algorithm is developed to support a human ambulatory monitoring system. This algorithm, to be deployed on an e-textile garment,… (more)

Subjects/Keywords: Activity Classification; Wearable Computing; User-indepdendence

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APA (6th Edition):

Blake, M. T. (2014). An Ambulatory Monitoring Algorithm to Unify Diverse E-Textile Garments. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/25876

Chicago Manual of Style (16th Edition):

Blake, Madison Thomas. “An Ambulatory Monitoring Algorithm to Unify Diverse E-Textile Garments.” 2014. Masters Thesis, Virginia Tech. Accessed April 03, 2020. http://hdl.handle.net/10919/25876.

MLA Handbook (7th Edition):

Blake, Madison Thomas. “An Ambulatory Monitoring Algorithm to Unify Diverse E-Textile Garments.” 2014. Web. 03 Apr 2020.

Vancouver:

Blake MT. An Ambulatory Monitoring Algorithm to Unify Diverse E-Textile Garments. [Internet] [Masters thesis]. Virginia Tech; 2014. [cited 2020 Apr 03]. Available from: http://hdl.handle.net/10919/25876.

Council of Science Editors:

Blake MT. An Ambulatory Monitoring Algorithm to Unify Diverse E-Textile Garments. [Masters Thesis]. Virginia Tech; 2014. Available from: http://hdl.handle.net/10919/25876


Virginia Tech

20. Fayez, Almohanad Samir. Designing a Software Defined Radio to Run on a Heterogeneous Processor.

Degree: MS, Electrical and Computer Engineering, 2011, Virginia Tech

 Software Defined Radios (SDRs) are radio implementations in software versus the classic method of using discrete electronics. Considering the various classes of radio applications ranging… (more)

Subjects/Keywords: DSP; Cognitive Radio; Software Defined Radio; OMAP; Heterogeneous Processors

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APA (6th Edition):

Fayez, A. S. (2011). Designing a Software Defined Radio to Run on a Heterogeneous Processor. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/32196

Chicago Manual of Style (16th Edition):

Fayez, Almohanad Samir. “Designing a Software Defined Radio to Run on a Heterogeneous Processor.” 2011. Masters Thesis, Virginia Tech. Accessed April 03, 2020. http://hdl.handle.net/10919/32196.

MLA Handbook (7th Edition):

Fayez, Almohanad Samir. “Designing a Software Defined Radio to Run on a Heterogeneous Processor.” 2011. Web. 03 Apr 2020.

Vancouver:

Fayez AS. Designing a Software Defined Radio to Run on a Heterogeneous Processor. [Internet] [Masters thesis]. Virginia Tech; 2011. [cited 2020 Apr 03]. Available from: http://hdl.handle.net/10919/32196.

Council of Science Editors:

Fayez AS. Designing a Software Defined Radio to Run on a Heterogeneous Processor. [Masters Thesis]. Virginia Tech; 2011. Available from: http://hdl.handle.net/10919/32196

21. Kini, Akshatha Jagannath. Implementation of a Trusted I/O Processor on a Nascent SoC-FPGA Based Flight Controller for Unmanned Aerial Systems.

Degree: MS, Electrical and Computer Engineering, 2018, Virginia Tech

 Unmanned Aerial Systems (UAS) are aircraft without a human pilot on board. They are comprised of a ground-based autonomous or human operated control system, an… (more)

Subjects/Keywords: SoC; UAV; FPGA; ZYNQ; MicroBlaze; autopilot; ArduPilot; ArduPlane; GPS; Mission Planner; Sensor; Vulnerabilities; Mailbox

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APA (6th Edition):

Kini, A. J. (2018). Implementation of a Trusted I/O Processor on a Nascent SoC-FPGA Based Flight Controller for Unmanned Aerial Systems. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/82666

Chicago Manual of Style (16th Edition):

Kini, Akshatha Jagannath. “Implementation of a Trusted I/O Processor on a Nascent SoC-FPGA Based Flight Controller for Unmanned Aerial Systems.” 2018. Masters Thesis, Virginia Tech. Accessed April 03, 2020. http://hdl.handle.net/10919/82666.

MLA Handbook (7th Edition):

Kini, Akshatha Jagannath. “Implementation of a Trusted I/O Processor on a Nascent SoC-FPGA Based Flight Controller for Unmanned Aerial Systems.” 2018. Web. 03 Apr 2020.

Vancouver:

Kini AJ. Implementation of a Trusted I/O Processor on a Nascent SoC-FPGA Based Flight Controller for Unmanned Aerial Systems. [Internet] [Masters thesis]. Virginia Tech; 2018. [cited 2020 Apr 03]. Available from: http://hdl.handle.net/10919/82666.

Council of Science Editors:

Kini AJ. Implementation of a Trusted I/O Processor on a Nascent SoC-FPGA Based Flight Controller for Unmanned Aerial Systems. [Masters Thesis]. Virginia Tech; 2018. Available from: http://hdl.handle.net/10919/82666


Virginia Tech

22. Kakusa, Takondwa Lisungu. Use of Assembly Inspired Instructions in the Allowance of Natural Language Processing in ROS.

Degree: MS, Electrical and Computer Engineering, 2018, Virginia Tech

 Natural Language processing is a growing field and widely used in both industrial and and commercial cases. Though it is difficult to create a natural… (more)

Subjects/Keywords: Natural Language Processing; Robotics; ROS

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APA (6th Edition):

Kakusa, T. L. (2018). Use of Assembly Inspired Instructions in the Allowance of Natural Language Processing in ROS. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/84521

Chicago Manual of Style (16th Edition):

Kakusa, Takondwa Lisungu. “Use of Assembly Inspired Instructions in the Allowance of Natural Language Processing in ROS.” 2018. Masters Thesis, Virginia Tech. Accessed April 03, 2020. http://hdl.handle.net/10919/84521.

MLA Handbook (7th Edition):

Kakusa, Takondwa Lisungu. “Use of Assembly Inspired Instructions in the Allowance of Natural Language Processing in ROS.” 2018. Web. 03 Apr 2020.

Vancouver:

Kakusa TL. Use of Assembly Inspired Instructions in the Allowance of Natural Language Processing in ROS. [Internet] [Masters thesis]. Virginia Tech; 2018. [cited 2020 Apr 03]. Available from: http://hdl.handle.net/10919/84521.

Council of Science Editors:

Kakusa TL. Use of Assembly Inspired Instructions in the Allowance of Natural Language Processing in ROS. [Masters Thesis]. Virginia Tech; 2018. Available from: http://hdl.handle.net/10919/84521


Virginia Tech

23. Bansal, Shamit. Optimal Implementation of Simulink Models on Multicore Architectures with Partitioned Fixed Priority Scheduling.

Degree: MS, Electrical and Computer Engineering, 2018, Virginia Tech

 Model-based design based on the Simulink modeling formalism and the associated toolchain has gained its popularity in the development of complex embedded control systems. However,the… (more)

Subjects/Keywords: Simulink; Multicore; Software Synthesis; Partitioned scheduling

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APA (6th Edition):

Bansal, S. (2018). Optimal Implementation of Simulink Models on Multicore Architectures with Partitioned Fixed Priority Scheduling. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/85057

Chicago Manual of Style (16th Edition):

Bansal, Shamit. “Optimal Implementation of Simulink Models on Multicore Architectures with Partitioned Fixed Priority Scheduling.” 2018. Masters Thesis, Virginia Tech. Accessed April 03, 2020. http://hdl.handle.net/10919/85057.

MLA Handbook (7th Edition):

Bansal, Shamit. “Optimal Implementation of Simulink Models on Multicore Architectures with Partitioned Fixed Priority Scheduling.” 2018. Web. 03 Apr 2020.

Vancouver:

Bansal S. Optimal Implementation of Simulink Models on Multicore Architectures with Partitioned Fixed Priority Scheduling. [Internet] [Masters thesis]. Virginia Tech; 2018. [cited 2020 Apr 03]. Available from: http://hdl.handle.net/10919/85057.

Council of Science Editors:

Bansal S. Optimal Implementation of Simulink Models on Multicore Architectures with Partitioned Fixed Priority Scheduling. [Masters Thesis]. Virginia Tech; 2018. Available from: http://hdl.handle.net/10919/85057


Virginia Tech

24. Brar, Gurkanwal Singh. Malleable Contextual Partitioning and Computational Dreaming.

Degree: MS, Electrical and Computer Engineering, 2015, Virginia Tech

 Computer Architecture is entering an era where hundreds of Processing Elements (PE) can be integrated onto single chips even as decades-long, steady advances in instruction,… (more)

Subjects/Keywords: Parallel Computing; Context Aware Computing; Computational Dreaming; Multiple Instruction Single Datastream (MISD) Computing; Brain Inspired Computer Architecture; Speech Recognition

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APA (6th Edition):

Brar, G. S. (2015). Malleable Contextual Partitioning and Computational Dreaming. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/51201

Chicago Manual of Style (16th Edition):

Brar, Gurkanwal Singh. “Malleable Contextual Partitioning and Computational Dreaming.” 2015. Masters Thesis, Virginia Tech. Accessed April 03, 2020. http://hdl.handle.net/10919/51201.

MLA Handbook (7th Edition):

Brar, Gurkanwal Singh. “Malleable Contextual Partitioning and Computational Dreaming.” 2015. Web. 03 Apr 2020.

Vancouver:

Brar GS. Malleable Contextual Partitioning and Computational Dreaming. [Internet] [Masters thesis]. Virginia Tech; 2015. [cited 2020 Apr 03]. Available from: http://hdl.handle.net/10919/51201.

Council of Science Editors:

Brar GS. Malleable Contextual Partitioning and Computational Dreaming. [Masters Thesis]. Virginia Tech; 2015. Available from: http://hdl.handle.net/10919/51201


Virginia Tech

25. Tolley, Joseph D. Implementation and Evaluation of an Algorithm for User Identity and Permissions for Situational Awareness Analysis.

Degree: MS, Computer Engineering, 2019, Virginia Tech

 The thesis analyzes the steps and actions necessary to develop an application using a user identity management system, user permissions system, message distribution system, and… (more)

Subjects/Keywords: emergency response; computer system; mobile device; organization; identity; user permissions

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APA (6th Edition):

Tolley, J. D. (2019). Implementation and Evaluation of an Algorithm for User Identity and Permissions for Situational Awareness Analysis. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/89907

Chicago Manual of Style (16th Edition):

Tolley, Joseph D. “Implementation and Evaluation of an Algorithm for User Identity and Permissions for Situational Awareness Analysis.” 2019. Masters Thesis, Virginia Tech. Accessed April 03, 2020. http://hdl.handle.net/10919/89907.

MLA Handbook (7th Edition):

Tolley, Joseph D. “Implementation and Evaluation of an Algorithm for User Identity and Permissions for Situational Awareness Analysis.” 2019. Web. 03 Apr 2020.

Vancouver:

Tolley JD. Implementation and Evaluation of an Algorithm for User Identity and Permissions for Situational Awareness Analysis. [Internet] [Masters thesis]. Virginia Tech; 2019. [cited 2020 Apr 03]. Available from: http://hdl.handle.net/10919/89907.

Council of Science Editors:

Tolley JD. Implementation and Evaluation of an Algorithm for User Identity and Permissions for Situational Awareness Analysis. [Masters Thesis]. Virginia Tech; 2019. Available from: http://hdl.handle.net/10919/89907

26. Pang, Yihan. Leveraging Processor-diversity For Improved Performance In Heterogeneous-ISA Systems.

Degree: MS, Computer Engineering, 2019, Virginia Tech

 The author of this thesis has a family full of non-engineers. To persuade family members that the work of this thesis is meaningful, aka the… (more)

Subjects/Keywords: System Software; Heterogeneous Architectures; SIMD; Scheduling; ISA

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APA (6th Edition):

Pang, Y. (2019). Leveraging Processor-diversity For Improved Performance In Heterogeneous-ISA Systems. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/95299

Chicago Manual of Style (16th Edition):

Pang, Yihan. “Leveraging Processor-diversity For Improved Performance In Heterogeneous-ISA Systems.” 2019. Masters Thesis, Virginia Tech. Accessed April 03, 2020. http://hdl.handle.net/10919/95299.

MLA Handbook (7th Edition):

Pang, Yihan. “Leveraging Processor-diversity For Improved Performance In Heterogeneous-ISA Systems.” 2019. Web. 03 Apr 2020.

Vancouver:

Pang Y. Leveraging Processor-diversity For Improved Performance In Heterogeneous-ISA Systems. [Internet] [Masters thesis]. Virginia Tech; 2019. [cited 2020 Apr 03]. Available from: http://hdl.handle.net/10919/95299.

Council of Science Editors:

Pang Y. Leveraging Processor-diversity For Improved Performance In Heterogeneous-ISA Systems. [Masters Thesis]. Virginia Tech; 2019. Available from: http://hdl.handle.net/10919/95299


Virginia Tech

27. Burrow, Ryan David. Enhancing Input/Output Correctness, Protection, Performance, and Scalability for Process Control Platforms.

Degree: MS, Computer Engineering, 2019, Virginia Tech

 Complex modern systems, from unmanned aircraft system to industrial plants are almost always controlled digitally. These digital control systems (DCSes) need to be verified for… (more)

Subjects/Keywords: digital control system; programmable system-on-chip; model checking; input/output processor; malware resilience

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APA (6th Edition):

Burrow, R. D. (2019). Enhancing Input/Output Correctness, Protection, Performance, and Scalability for Process Control Platforms. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/89903

Chicago Manual of Style (16th Edition):

Burrow, Ryan David. “Enhancing Input/Output Correctness, Protection, Performance, and Scalability for Process Control Platforms.” 2019. Masters Thesis, Virginia Tech. Accessed April 03, 2020. http://hdl.handle.net/10919/89903.

MLA Handbook (7th Edition):

Burrow, Ryan David. “Enhancing Input/Output Correctness, Protection, Performance, and Scalability for Process Control Platforms.” 2019. Web. 03 Apr 2020.

Vancouver:

Burrow RD. Enhancing Input/Output Correctness, Protection, Performance, and Scalability for Process Control Platforms. [Internet] [Masters thesis]. Virginia Tech; 2019. [cited 2020 Apr 03]. Available from: http://hdl.handle.net/10919/89903.

Council of Science Editors:

Burrow RD. Enhancing Input/Output Correctness, Protection, Performance, and Scalability for Process Control Platforms. [Masters Thesis]. Virginia Tech; 2019. Available from: http://hdl.handle.net/10919/89903


Virginia Tech

28. Malik, Akshat. Monitoring and Preventing Data Exfiltration in Android-hosted Unmanned Aircraft System Applications.

Degree: MS, Computer Engineering, 2019, Virginia Tech

 Advances in smartphone technology has led major consumer and commercial unmanned aircraft system (UAS) manufacturers to provide users with the feature to fly the UAS… (more)

Subjects/Keywords: Android; UAS; data exfiltration

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APA (6th Edition):

Malik, A. (2019). Monitoring and Preventing Data Exfiltration in Android-hosted Unmanned Aircraft System Applications. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/92874

Chicago Manual of Style (16th Edition):

Malik, Akshat. “Monitoring and Preventing Data Exfiltration in Android-hosted Unmanned Aircraft System Applications.” 2019. Masters Thesis, Virginia Tech. Accessed April 03, 2020. http://hdl.handle.net/10919/92874.

MLA Handbook (7th Edition):

Malik, Akshat. “Monitoring and Preventing Data Exfiltration in Android-hosted Unmanned Aircraft System Applications.” 2019. Web. 03 Apr 2020.

Vancouver:

Malik A. Monitoring and Preventing Data Exfiltration in Android-hosted Unmanned Aircraft System Applications. [Internet] [Masters thesis]. Virginia Tech; 2019. [cited 2020 Apr 03]. Available from: http://hdl.handle.net/10919/92874.

Council of Science Editors:

Malik A. Monitoring and Preventing Data Exfiltration in Android-hosted Unmanned Aircraft System Applications. [Masters Thesis]. Virginia Tech; 2019. Available from: http://hdl.handle.net/10919/92874


Virginia Tech

29. Liu, Beichen. SlimGuard: Design and Implementation of a Memory Efficient and Secure Heap Allocator.

Degree: MS, Computer Engineering, 2020, Virginia Tech

 Attacks targeting on the runtime memory (heap allocator) are severe threats to software safety. Statistical results shown that the numbers of heap-related attacks has doubled… (more)

Subjects/Keywords: Dynamic Memory Allocation; Memory Safety

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APA (6th Edition):

Liu, B. (2020). SlimGuard: Design and Implementation of a Memory Efficient and Secure Heap Allocator. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/96291

Chicago Manual of Style (16th Edition):

Liu, Beichen. “SlimGuard: Design and Implementation of a Memory Efficient and Secure Heap Allocator.” 2020. Masters Thesis, Virginia Tech. Accessed April 03, 2020. http://hdl.handle.net/10919/96291.

MLA Handbook (7th Edition):

Liu, Beichen. “SlimGuard: Design and Implementation of a Memory Efficient and Secure Heap Allocator.” 2020. Web. 03 Apr 2020.

Vancouver:

Liu B. SlimGuard: Design and Implementation of a Memory Efficient and Secure Heap Allocator. [Internet] [Masters thesis]. Virginia Tech; 2020. [cited 2020 Apr 03]. Available from: http://hdl.handle.net/10919/96291.

Council of Science Editors:

Liu B. SlimGuard: Design and Implementation of a Memory Efficient and Secure Heap Allocator. [Masters Thesis]. Virginia Tech; 2020. Available from: http://hdl.handle.net/10919/96291


Virginia Tech

30. Gunjal, Abhinav Shivram. Trusted Software Updates for Secure Enclaves in Industrial Control Systems.

Degree: MS, Computer Engineering, 2017, Virginia Tech

 Industrial Control Systems (ICSs) manage critical infrastructures such as water treatment facilities, petroleum refineries, and power plants. ICSs are networked through Information Technology (IT) infrastructure… (more)

Subjects/Keywords: Industrial control systems; programmable logic controller; industrial control systems security; secure enclaves; software updates; configurable system-on-chip

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APA (6th Edition):

Gunjal, A. S. (2017). Trusted Software Updates for Secure Enclaves in Industrial Control Systems. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/79130

Chicago Manual of Style (16th Edition):

Gunjal, Abhinav Shivram. “Trusted Software Updates for Secure Enclaves in Industrial Control Systems.” 2017. Masters Thesis, Virginia Tech. Accessed April 03, 2020. http://hdl.handle.net/10919/79130.

MLA Handbook (7th Edition):

Gunjal, Abhinav Shivram. “Trusted Software Updates for Secure Enclaves in Industrial Control Systems.” 2017. Web. 03 Apr 2020.

Vancouver:

Gunjal AS. Trusted Software Updates for Secure Enclaves in Industrial Control Systems. [Internet] [Masters thesis]. Virginia Tech; 2017. [cited 2020 Apr 03]. Available from: http://hdl.handle.net/10919/79130.

Council of Science Editors:

Gunjal AS. Trusted Software Updates for Secure Enclaves in Industrial Control Systems. [Masters Thesis]. Virginia Tech; 2017. Available from: http://hdl.handle.net/10919/79130

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