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You searched for +publisher:"Virginia Tech" +contributor:("Nazhandali, Leyla"). Showing records 1 – 30 of 52 total matches.

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Virginia Tech

1. Garg, Apoorva. Zebra GC: A Fully Integrated Micro Gas Chromatography System.

Degree: MS, Computer Engineering, 2014, Virginia Tech

 A ready-to-deploy implementation of microfabricated gas chromatography (microGC) system characterized for detecting hazardous air pollutants (HAPs) at parts-per-billion (ppb) concentrations in complex mixtures has been… (more)

Subjects/Keywords: Micro Gas Chromatography; Environmental Monitoring; Embedded Systems

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APA (6th Edition):

Garg, A. (2014). Zebra GC: A Fully Integrated Micro Gas Chromatography System. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/64854

Chicago Manual of Style (16th Edition):

Garg, Apoorva. “Zebra GC: A Fully Integrated Micro Gas Chromatography System.” 2014. Masters Thesis, Virginia Tech. Accessed December 04, 2020. http://hdl.handle.net/10919/64854.

MLA Handbook (7th Edition):

Garg, Apoorva. “Zebra GC: A Fully Integrated Micro Gas Chromatography System.” 2014. Web. 04 Dec 2020.

Vancouver:

Garg A. Zebra GC: A Fully Integrated Micro Gas Chromatography System. [Internet] [Masters thesis]. Virginia Tech; 2014. [cited 2020 Dec 04]. Available from: http://hdl.handle.net/10919/64854.

Council of Science Editors:

Garg A. Zebra GC: A Fully Integrated Micro Gas Chromatography System. [Masters Thesis]. Virginia Tech; 2014. Available from: http://hdl.handle.net/10919/64854


Virginia Tech

2. El-Helw, Sarah Reda. Designing and Fabricating MEMS Cantilever Switches.

Degree: MS, Electrical Engineering, 2016, Virginia Tech

 In this thesis, MEMS switches actuated using electrostatic actuation is explored. MEMS switches that are lateral switches and clamped-clamped switches are designed, fabricated, and tested… (more)

Subjects/Keywords: MEMS; Lateral Switches; Clamped-Clamped Switches; Electrostatic Actuation; Contact Resistance

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APA (6th Edition):

El-Helw, S. R. (2016). Designing and Fabricating MEMS Cantilever Switches. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/82524

Chicago Manual of Style (16th Edition):

El-Helw, Sarah Reda. “Designing and Fabricating MEMS Cantilever Switches.” 2016. Masters Thesis, Virginia Tech. Accessed December 04, 2020. http://hdl.handle.net/10919/82524.

MLA Handbook (7th Edition):

El-Helw, Sarah Reda. “Designing and Fabricating MEMS Cantilever Switches.” 2016. Web. 04 Dec 2020.

Vancouver:

El-Helw SR. Designing and Fabricating MEMS Cantilever Switches. [Internet] [Masters thesis]. Virginia Tech; 2016. [cited 2020 Dec 04]. Available from: http://hdl.handle.net/10919/82524.

Council of Science Editors:

El-Helw SR. Designing and Fabricating MEMS Cantilever Switches. [Masters Thesis]. Virginia Tech; 2016. Available from: http://hdl.handle.net/10919/82524


Virginia Tech

3. Skoff, Nicholas Michael. Performance Analysis of Sampled Values-Based Protection in IEC 61850 Process Bus Networks.

Degree: MS, Electrical Engineering, 2020, Virginia Tech

 Power system infrastrcutures are changing rapidly from analog arrangements to entirely digital methods. This offers numeous benefits such as increased efficiency, lower cost, higher accuracy,… (more)

Subjects/Keywords: Digital Substations; Sampled Measured Values; Protection Automation

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APA (6th Edition):

Skoff, N. M. (2020). Performance Analysis of Sampled Values-Based Protection in IEC 61850 Process Bus Networks. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/98591

Chicago Manual of Style (16th Edition):

Skoff, Nicholas Michael. “Performance Analysis of Sampled Values-Based Protection in IEC 61850 Process Bus Networks.” 2020. Masters Thesis, Virginia Tech. Accessed December 04, 2020. http://hdl.handle.net/10919/98591.

MLA Handbook (7th Edition):

Skoff, Nicholas Michael. “Performance Analysis of Sampled Values-Based Protection in IEC 61850 Process Bus Networks.” 2020. Web. 04 Dec 2020.

Vancouver:

Skoff NM. Performance Analysis of Sampled Values-Based Protection in IEC 61850 Process Bus Networks. [Internet] [Masters thesis]. Virginia Tech; 2020. [cited 2020 Dec 04]. Available from: http://hdl.handle.net/10919/98591.

Council of Science Editors:

Skoff NM. Performance Analysis of Sampled Values-Based Protection in IEC 61850 Process Bus Networks. [Masters Thesis]. Virginia Tech; 2020. Available from: http://hdl.handle.net/10919/98591


Virginia Tech

4. Kindel, David Garret. Reducing Subthreshold Leakage Power Through Hybrid MOSFET-NEMS Power Gating.

Degree: MS, Computer Engineering, 2016, Virginia Tech

 Modern devices such as smartphones and smartwatches spend a large amount of their life idle, waiting for external events. During this time, they are expending… (more)

Subjects/Keywords: NEMS; Power Gating; Low Power; Simulator; Computer Architecture

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APA (6th Edition):

Kindel, D. G. (2016). Reducing Subthreshold Leakage Power Through Hybrid MOSFET-NEMS Power Gating. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/72871

Chicago Manual of Style (16th Edition):

Kindel, David Garret. “Reducing Subthreshold Leakage Power Through Hybrid MOSFET-NEMS Power Gating.” 2016. Masters Thesis, Virginia Tech. Accessed December 04, 2020. http://hdl.handle.net/10919/72871.

MLA Handbook (7th Edition):

Kindel, David Garret. “Reducing Subthreshold Leakage Power Through Hybrid MOSFET-NEMS Power Gating.” 2016. Web. 04 Dec 2020.

Vancouver:

Kindel DG. Reducing Subthreshold Leakage Power Through Hybrid MOSFET-NEMS Power Gating. [Internet] [Masters thesis]. Virginia Tech; 2016. [cited 2020 Dec 04]. Available from: http://hdl.handle.net/10919/72871.

Council of Science Editors:

Kindel DG. Reducing Subthreshold Leakage Power Through Hybrid MOSFET-NEMS Power Gating. [Masters Thesis]. Virginia Tech; 2016. Available from: http://hdl.handle.net/10919/72871


Virginia Tech

5. Mane, Suvarna Hanamant. Implementation of SCA-Resistant CPU and an ECDLP Engine on FPGA Platform.

Degree: MS, Electrical and Computer Engineering, 2012, Virginia Tech

 The rapid increase in the use of embedded systems for performing secure transactions, has proportionally increased the security threat, faced by such devices. Security threats… (more)

Subjects/Keywords: Prime-field arithmetic

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APA (6th Edition):

Mane, S. H. (2012). Implementation of SCA-Resistant CPU and an ECDLP Engine on FPGA Platform. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/32198

Chicago Manual of Style (16th Edition):

Mane, Suvarna Hanamant. “Implementation of SCA-Resistant CPU and an ECDLP Engine on FPGA Platform.” 2012. Masters Thesis, Virginia Tech. Accessed December 04, 2020. http://hdl.handle.net/10919/32198.

MLA Handbook (7th Edition):

Mane, Suvarna Hanamant. “Implementation of SCA-Resistant CPU and an ECDLP Engine on FPGA Platform.” 2012. Web. 04 Dec 2020.

Vancouver:

Mane SH. Implementation of SCA-Resistant CPU and an ECDLP Engine on FPGA Platform. [Internet] [Masters thesis]. Virginia Tech; 2012. [cited 2020 Dec 04]. Available from: http://hdl.handle.net/10919/32198.

Council of Science Editors:

Mane SH. Implementation of SCA-Resistant CPU and an ECDLP Engine on FPGA Platform. [Masters Thesis]. Virginia Tech; 2012. Available from: http://hdl.handle.net/10919/32198


Virginia Tech

6. Coleman, Flora Anne. A Hardware Evaluation of a NIST Lightweight Cryptography Candidate.

Degree: MS, Computer Engineering, 2020, Virginia Tech

 In today's society, interactions with connected, data-sharing devices have become common. For example, devices like "smart" watches, remote access home security systems, and even connected… (more)

Subjects/Keywords: Lightweight Cryptography; Side Channel Analysis; FPGA; ARX

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APA (6th Edition):

Coleman, F. A. (2020). A Hardware Evaluation of a NIST Lightweight Cryptography Candidate. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/98758

Chicago Manual of Style (16th Edition):

Coleman, Flora Anne. “A Hardware Evaluation of a NIST Lightweight Cryptography Candidate.” 2020. Masters Thesis, Virginia Tech. Accessed December 04, 2020. http://hdl.handle.net/10919/98758.

MLA Handbook (7th Edition):

Coleman, Flora Anne. “A Hardware Evaluation of a NIST Lightweight Cryptography Candidate.” 2020. Web. 04 Dec 2020.

Vancouver:

Coleman FA. A Hardware Evaluation of a NIST Lightweight Cryptography Candidate. [Internet] [Masters thesis]. Virginia Tech; 2020. [cited 2020 Dec 04]. Available from: http://hdl.handle.net/10919/98758.

Council of Science Editors:

Coleman FA. A Hardware Evaluation of a NIST Lightweight Cryptography Candidate. [Masters Thesis]. Virginia Tech; 2020. Available from: http://hdl.handle.net/10919/98758


Virginia Tech

7. Zuo, Yongbo. Fair Comparison of ASIC Performance for SHA-3 Finalists.

Degree: MS, Electrical and Computer Engineering, 2012, Virginia Tech

 In the last few decades, secure algorithms have played an irreplaceable role in the protection of private information, such as applications of AES on modems,… (more)

Subjects/Keywords: SHA; NIST; ASIC; Finalist; Hardware; Encryption; Hash; Cipher; Key

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APA (6th Edition):

Zuo, Y. (2012). Fair Comparison of ASIC Performance for SHA-3 Finalists. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/33446

Chicago Manual of Style (16th Edition):

Zuo, Yongbo. “Fair Comparison of ASIC Performance for SHA-3 Finalists.” 2012. Masters Thesis, Virginia Tech. Accessed December 04, 2020. http://hdl.handle.net/10919/33446.

MLA Handbook (7th Edition):

Zuo, Yongbo. “Fair Comparison of ASIC Performance for SHA-3 Finalists.” 2012. Web. 04 Dec 2020.

Vancouver:

Zuo Y. Fair Comparison of ASIC Performance for SHA-3 Finalists. [Internet] [Masters thesis]. Virginia Tech; 2012. [cited 2020 Dec 04]. Available from: http://hdl.handle.net/10919/33446.

Council of Science Editors:

Zuo Y. Fair Comparison of ASIC Performance for SHA-3 Finalists. [Masters Thesis]. Virginia Tech; 2012. Available from: http://hdl.handle.net/10919/33446


Virginia Tech

8. Mane, Deepak Hanamant. Energy-harvested Lightweight Cryptosystems.

Degree: MS, Computer Engineering, 2014, Virginia Tech

 The Internet of Things will include many resource-constrained lightweight wireless sensing devices, hungry for energy, bandwidth and compute cycles. The sheer amount of devices involved… (more)

Subjects/Keywords: Public Key Cryptography; Elliptic Curves; RFID; Wireless Sensor Node; Energy Harvesting; Throughput; Digital signatures

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APA (6th Edition):

Mane, D. H. (2014). Energy-harvested Lightweight Cryptosystems. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/48124

Chicago Manual of Style (16th Edition):

Mane, Deepak Hanamant. “Energy-harvested Lightweight Cryptosystems.” 2014. Masters Thesis, Virginia Tech. Accessed December 04, 2020. http://hdl.handle.net/10919/48124.

MLA Handbook (7th Edition):

Mane, Deepak Hanamant. “Energy-harvested Lightweight Cryptosystems.” 2014. Web. 04 Dec 2020.

Vancouver:

Mane DH. Energy-harvested Lightweight Cryptosystems. [Internet] [Masters thesis]. Virginia Tech; 2014. [cited 2020 Dec 04]. Available from: http://hdl.handle.net/10919/48124.

Council of Science Editors:

Mane DH. Energy-harvested Lightweight Cryptosystems. [Masters Thesis]. Virginia Tech; 2014. Available from: http://hdl.handle.net/10919/48124


Virginia Tech

9. Mahmoud Mohamedin, Mohamed Ahmed. ByteSTM: Java Software Transactional Memory at the Virtual Machine Level.

Degree: MS, Electrical and Computer Engineering, 2012, Virginia Tech

 As chip vendors are increasingly manufacturing a new generation of multi-processor chips called multicores, improving software performance requires exposing greater concurrency in software. Since code… (more)

Subjects/Keywords: Synchronization; Virtual Machine; Java; Multiprocessor; Concurrency; Software Transactional Memory

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APA (6th Edition):

Mahmoud Mohamedin, M. A. (2012). ByteSTM: Java Software Transactional Memory at the Virtual Machine Level. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/31314

Chicago Manual of Style (16th Edition):

Mahmoud Mohamedin, Mohamed Ahmed. “ByteSTM: Java Software Transactional Memory at the Virtual Machine Level.” 2012. Masters Thesis, Virginia Tech. Accessed December 04, 2020. http://hdl.handle.net/10919/31314.

MLA Handbook (7th Edition):

Mahmoud Mohamedin, Mohamed Ahmed. “ByteSTM: Java Software Transactional Memory at the Virtual Machine Level.” 2012. Web. 04 Dec 2020.

Vancouver:

Mahmoud Mohamedin MA. ByteSTM: Java Software Transactional Memory at the Virtual Machine Level. [Internet] [Masters thesis]. Virginia Tech; 2012. [cited 2020 Dec 04]. Available from: http://hdl.handle.net/10919/31314.

Council of Science Editors:

Mahmoud Mohamedin MA. ByteSTM: Java Software Transactional Memory at the Virtual Machine Level. [Masters Thesis]. Virginia Tech; 2012. Available from: http://hdl.handle.net/10919/31314


Virginia Tech

10. Rafeei, Lalleh. Fast Approximation Framework for Timing and Power Analysis of Ultra-Low-Voltage Circuits.

Degree: MS, Electrical and Computer Engineering, 2012, Virginia Tech

 Ultra-Low-Voltage operation, which can be considered an extreme case of voltage scaling, can greatly reduce the power consumption of circuits. Despite the fact that Ultra-Low-Voltage… (more)

Subjects/Keywords: subthreshold; approximation framework; power; timing; CMOS; VLSI; Ultra-Low-Voltage

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APA (6th Edition):

Rafeei, L. (2012). Fast Approximation Framework for Timing and Power Analysis of Ultra-Low-Voltage Circuits. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/31678

Chicago Manual of Style (16th Edition):

Rafeei, Lalleh. “Fast Approximation Framework for Timing and Power Analysis of Ultra-Low-Voltage Circuits.” 2012. Masters Thesis, Virginia Tech. Accessed December 04, 2020. http://hdl.handle.net/10919/31678.

MLA Handbook (7th Edition):

Rafeei, Lalleh. “Fast Approximation Framework for Timing and Power Analysis of Ultra-Low-Voltage Circuits.” 2012. Web. 04 Dec 2020.

Vancouver:

Rafeei L. Fast Approximation Framework for Timing and Power Analysis of Ultra-Low-Voltage Circuits. [Internet] [Masters thesis]. Virginia Tech; 2012. [cited 2020 Dec 04]. Available from: http://hdl.handle.net/10919/31678.

Council of Science Editors:

Rafeei L. Fast Approximation Framework for Timing and Power Analysis of Ultra-Low-Voltage Circuits. [Masters Thesis]. Virginia Tech; 2012. Available from: http://hdl.handle.net/10919/31678


Virginia Tech

11. Priya, Kanu. Study of Physical Unclonable Functions at Low Voltage on FPGA.

Degree: MS, Electrical and Computer Engineering, 2011, Virginia Tech

 Physical Unclonable Functions (PUFs) provide a secure, power efficient and non-volatile means of chip identification. These are analogous to one-way functions that are easy to… (more)

Subjects/Keywords: Low Power; Stability; Physical Unclonable Functions; Ring Oscillator; Process Variation; Uniqueness

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APA (6th Edition):

Priya, K. (2011). Study of Physical Unclonable Functions at Low Voltage on FPGA. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/34709

Chicago Manual of Style (16th Edition):

Priya, Kanu. “Study of Physical Unclonable Functions at Low Voltage on FPGA.” 2011. Masters Thesis, Virginia Tech. Accessed December 04, 2020. http://hdl.handle.net/10919/34709.

MLA Handbook (7th Edition):

Priya, Kanu. “Study of Physical Unclonable Functions at Low Voltage on FPGA.” 2011. Web. 04 Dec 2020.

Vancouver:

Priya K. Study of Physical Unclonable Functions at Low Voltage on FPGA. [Internet] [Masters thesis]. Virginia Tech; 2011. [cited 2020 Dec 04]. Available from: http://hdl.handle.net/10919/34709.

Council of Science Editors:

Priya K. Study of Physical Unclonable Functions at Low Voltage on FPGA. [Masters Thesis]. Virginia Tech; 2011. Available from: http://hdl.handle.net/10919/34709


Virginia Tech

12. Gulcan, Ege. Flexible and Lightweight Cryptographic Engines for Constrained Systems.

Degree: MS, Computer Engineering, 2015, Virginia Tech

 There is a significant effort in building lightweight cryptographic operations, yet the proposed solutions are typically single purpose modules that can only provide a fixed… (more)

Subjects/Keywords: Lightweight Cryptography; Block Ciphers; Flexible Architectures; SIMON; FPGA

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APA (6th Edition):

Gulcan, E. (2015). Flexible and Lightweight Cryptographic Engines for Constrained Systems. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/52913

Chicago Manual of Style (16th Edition):

Gulcan, Ege. “Flexible and Lightweight Cryptographic Engines for Constrained Systems.” 2015. Masters Thesis, Virginia Tech. Accessed December 04, 2020. http://hdl.handle.net/10919/52913.

MLA Handbook (7th Edition):

Gulcan, Ege. “Flexible and Lightweight Cryptographic Engines for Constrained Systems.” 2015. Web. 04 Dec 2020.

Vancouver:

Gulcan E. Flexible and Lightweight Cryptographic Engines for Constrained Systems. [Internet] [Masters thesis]. Virginia Tech; 2015. [cited 2020 Dec 04]. Available from: http://hdl.handle.net/10919/52913.

Council of Science Editors:

Gulcan E. Flexible and Lightweight Cryptographic Engines for Constrained Systems. [Masters Thesis]. Virginia Tech; 2015. Available from: http://hdl.handle.net/10919/52913


Virginia Tech

13. Gujar, Surabhi Satyajit. Detecting Electromagnetic Injection Attack on FPGAs Using In Situ Timing Sensors.

Degree: MS, Computer Engineering, 2018, Virginia Tech

 Nowadays, security is one of the foremost concerns as the confidence in a system is mostly dependent on its ability to protect itself against any… (more)

Subjects/Keywords: Hardware Security; FPGA; Electromagnetic Injection; Fault Attacks

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APA (6th Edition):

Gujar, S. S. (2018). Detecting Electromagnetic Injection Attack on FPGAs Using In Situ Timing Sensors. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/97006

Chicago Manual of Style (16th Edition):

Gujar, Surabhi Satyajit. “Detecting Electromagnetic Injection Attack on FPGAs Using In Situ Timing Sensors.” 2018. Masters Thesis, Virginia Tech. Accessed December 04, 2020. http://hdl.handle.net/10919/97006.

MLA Handbook (7th Edition):

Gujar, Surabhi Satyajit. “Detecting Electromagnetic Injection Attack on FPGAs Using In Situ Timing Sensors.” 2018. Web. 04 Dec 2020.

Vancouver:

Gujar SS. Detecting Electromagnetic Injection Attack on FPGAs Using In Situ Timing Sensors. [Internet] [Masters thesis]. Virginia Tech; 2018. [cited 2020 Dec 04]. Available from: http://hdl.handle.net/10919/97006.

Council of Science Editors:

Gujar SS. Detecting Electromagnetic Injection Attack on FPGAs Using In Situ Timing Sensors. [Masters Thesis]. Virginia Tech; 2018. Available from: http://hdl.handle.net/10919/97006


Virginia Tech

14. Patrick, Conor Persson. Software Protection Against Fault and Side Channel Attacks.

Degree: MS, Computer Engineering, 2017, Virginia Tech

 Embedded systems are increasingly ubiquitous. Many of them have security requirements such as smart cards, mobile phones, and internet connected appliances. It can be a… (more)

Subjects/Keywords: Fault attacks; side channel analysis; countermeasure

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APA (6th Edition):

Patrick, C. P. (2017). Software Protection Against Fault and Side Channel Attacks. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/78685

Chicago Manual of Style (16th Edition):

Patrick, Conor Persson. “Software Protection Against Fault and Side Channel Attacks.” 2017. Masters Thesis, Virginia Tech. Accessed December 04, 2020. http://hdl.handle.net/10919/78685.

MLA Handbook (7th Edition):

Patrick, Conor Persson. “Software Protection Against Fault and Side Channel Attacks.” 2017. Web. 04 Dec 2020.

Vancouver:

Patrick CP. Software Protection Against Fault and Side Channel Attacks. [Internet] [Masters thesis]. Virginia Tech; 2017. [cited 2020 Dec 04]. Available from: http://hdl.handle.net/10919/78685.

Council of Science Editors:

Patrick CP. Software Protection Against Fault and Side Channel Attacks. [Masters Thesis]. Virginia Tech; 2017. Available from: http://hdl.handle.net/10919/78685


Virginia Tech

15. Moudgil, Rashmi. A Statistical and Circuit Based Technique for Counterfeit Detection in Existing ICs.

Degree: MS, Computer Engineering, 2013, Virginia Tech

 Counterfeit Integrated Circuits (ICs) are previously used ICs that are resold as new. They have become a serious problem in modern electronic devices. They cause… (more)

Subjects/Keywords: Counterfeits; Aging; Process Variation

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APA (6th Edition):

Moudgil, R. (2013). A Statistical and Circuit Based Technique for Counterfeit Detection in Existing ICs. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/23177

Chicago Manual of Style (16th Edition):

Moudgil, Rashmi. “A Statistical and Circuit Based Technique for Counterfeit Detection in Existing ICs.” 2013. Masters Thesis, Virginia Tech. Accessed December 04, 2020. http://hdl.handle.net/10919/23177.

MLA Handbook (7th Edition):

Moudgil, Rashmi. “A Statistical and Circuit Based Technique for Counterfeit Detection in Existing ICs.” 2013. Web. 04 Dec 2020.

Vancouver:

Moudgil R. A Statistical and Circuit Based Technique for Counterfeit Detection in Existing ICs. [Internet] [Masters thesis]. Virginia Tech; 2013. [cited 2020 Dec 04]. Available from: http://hdl.handle.net/10919/23177.

Council of Science Editors:

Moudgil R. A Statistical and Circuit Based Technique for Counterfeit Detection in Existing ICs. [Masters Thesis]. Virginia Tech; 2013. Available from: http://hdl.handle.net/10919/23177


Virginia Tech

16. Mandadi, Harsha. Remote Integrity Checking using Multiple PUF based Component Identifiers.

Degree: MS, Computer Engineering, 2017, Virginia Tech

 Modern Printed Circuit Boards (PCB) contain sophisticated and valuable electronic components, and this makes them a prime target for counterfeiting. In this thesis, we consider… (more)

Subjects/Keywords: Physical Unclonable Functions; Fuzzy Extractors; Authentic Protocol

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APA (6th Edition):

Mandadi, H. (2017). Remote Integrity Checking using Multiple PUF based Component Identifiers. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/78200

Chicago Manual of Style (16th Edition):

Mandadi, Harsha. “Remote Integrity Checking using Multiple PUF based Component Identifiers.” 2017. Masters Thesis, Virginia Tech. Accessed December 04, 2020. http://hdl.handle.net/10919/78200.

MLA Handbook (7th Edition):

Mandadi, Harsha. “Remote Integrity Checking using Multiple PUF based Component Identifiers.” 2017. Web. 04 Dec 2020.

Vancouver:

Mandadi H. Remote Integrity Checking using Multiple PUF based Component Identifiers. [Internet] [Masters thesis]. Virginia Tech; 2017. [cited 2020 Dec 04]. Available from: http://hdl.handle.net/10919/78200.

Council of Science Editors:

Mandadi H. Remote Integrity Checking using Multiple PUF based Component Identifiers. [Masters Thesis]. Virginia Tech; 2017. Available from: http://hdl.handle.net/10919/78200


Virginia Tech

17. Rawat, Hemendra Kumar. Vector Instruction Set Extensions for Efficient and Reliable Computation of Keccak.

Degree: MS, Computer Engineering, 2016, Virginia Tech

 Recent processor architectures such as Intel Westmere (and later) and ARMv8 include instruction-level support for the Advanced Encryption Standard (AES), for the Secure Hashing Standard… (more)

Subjects/Keywords: SIMD; Instruction Set Extensions; SHA-3; Hashing; Authenticated Encryption; Software Integrity

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APA (6th Edition):

Rawat, H. K. (2016). Vector Instruction Set Extensions for Efficient and Reliable Computation of Keccak. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/72857

Chicago Manual of Style (16th Edition):

Rawat, Hemendra Kumar. “Vector Instruction Set Extensions for Efficient and Reliable Computation of Keccak.” 2016. Masters Thesis, Virginia Tech. Accessed December 04, 2020. http://hdl.handle.net/10919/72857.

MLA Handbook (7th Edition):

Rawat, Hemendra Kumar. “Vector Instruction Set Extensions for Efficient and Reliable Computation of Keccak.” 2016. Web. 04 Dec 2020.

Vancouver:

Rawat HK. Vector Instruction Set Extensions for Efficient and Reliable Computation of Keccak. [Internet] [Masters thesis]. Virginia Tech; 2016. [cited 2020 Dec 04]. Available from: http://hdl.handle.net/10919/72857.

Council of Science Editors:

Rawat HK. Vector Instruction Set Extensions for Efficient and Reliable Computation of Keccak. [Masters Thesis]. Virginia Tech; 2016. Available from: http://hdl.handle.net/10919/72857


Virginia Tech

18. Kiaei, Pantea. Architecture Support for Countermeasures against Side-Channel Analysis and Fault Attack.

Degree: MS, Computer Engineering, 2019, Virginia Tech

 Ciphers are algorithms designed by mathematicians. They protect data by encrypting them. In one of the main categories of these ciphers, called symmetric-key ciphers, a… (more)

Subjects/Keywords: Side-channel attacks; Fault attacks; Custom-instruction extensions; Bitslicing; Software countermeasures

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APA (6th Edition):

Kiaei, P. (2019). Architecture Support for Countermeasures against Side-Channel Analysis and Fault Attack. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/93537

Chicago Manual of Style (16th Edition):

Kiaei, Pantea. “Architecture Support for Countermeasures against Side-Channel Analysis and Fault Attack.” 2019. Masters Thesis, Virginia Tech. Accessed December 04, 2020. http://hdl.handle.net/10919/93537.

MLA Handbook (7th Edition):

Kiaei, Pantea. “Architecture Support for Countermeasures against Side-Channel Analysis and Fault Attack.” 2019. Web. 04 Dec 2020.

Vancouver:

Kiaei P. Architecture Support for Countermeasures against Side-Channel Analysis and Fault Attack. [Internet] [Masters thesis]. Virginia Tech; 2019. [cited 2020 Dec 04]. Available from: http://hdl.handle.net/10919/93537.

Council of Science Editors:

Kiaei P. Architecture Support for Countermeasures against Side-Channel Analysis and Fault Attack. [Masters Thesis]. Virginia Tech; 2019. Available from: http://hdl.handle.net/10919/93537


Virginia Tech

19. Gaddam, Shravya. Design and Implementation of PUF Based Protocols for Remote Integrity Verification.

Degree: MS, Computer Engineering, 2016, Virginia Tech

 In recent years, there has been a drastic increase in the prevalence of counterfeiting within the electronics supply chain. At the same time, high-end commercial… (more)

Subjects/Keywords: Physical Unclonable Functions; ECDSA; Elliptic Curve Cryptography; Fuzzy Extraction; Strong Extraction

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APA (6th Edition):

Gaddam, S. (2016). Design and Implementation of PUF Based Protocols for Remote Integrity Verification. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/71865

Chicago Manual of Style (16th Edition):

Gaddam, Shravya. “Design and Implementation of PUF Based Protocols for Remote Integrity Verification.” 2016. Masters Thesis, Virginia Tech. Accessed December 04, 2020. http://hdl.handle.net/10919/71865.

MLA Handbook (7th Edition):

Gaddam, Shravya. “Design and Implementation of PUF Based Protocols for Remote Integrity Verification.” 2016. Web. 04 Dec 2020.

Vancouver:

Gaddam S. Design and Implementation of PUF Based Protocols for Remote Integrity Verification. [Internet] [Masters thesis]. Virginia Tech; 2016. [cited 2020 Dec 04]. Available from: http://hdl.handle.net/10919/71865.

Council of Science Editors:

Gaddam S. Design and Implementation of PUF Based Protocols for Remote Integrity Verification. [Masters Thesis]. Virginia Tech; 2016. Available from: http://hdl.handle.net/10919/71865


Virginia Tech

20. Desai, Avinash R. Anti-Counterfeit and Anti-Tamper Hardware Implementation using Hardware Obfuscation.

Degree: MS, Computer Engineering, 2013, Virginia Tech

 Tampering and Reverse Engineering of a chip to extract the hardware Intellectual Property (IP) core or to inject malicious alterations is a major concern. First,… (more)

Subjects/Keywords: Anti-Counterfeit; Anti-Tamper; Trojan Detection Integrated Circuits; Seal; Time-Stamp

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APA (6th Edition):

Desai, A. R. (2013). Anti-Counterfeit and Anti-Tamper Hardware Implementation using Hardware Obfuscation. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/23756

Chicago Manual of Style (16th Edition):

Desai, Avinash R. “Anti-Counterfeit and Anti-Tamper Hardware Implementation using Hardware Obfuscation.” 2013. Masters Thesis, Virginia Tech. Accessed December 04, 2020. http://hdl.handle.net/10919/23756.

MLA Handbook (7th Edition):

Desai, Avinash R. “Anti-Counterfeit and Anti-Tamper Hardware Implementation using Hardware Obfuscation.” 2013. Web. 04 Dec 2020.

Vancouver:

Desai AR. Anti-Counterfeit and Anti-Tamper Hardware Implementation using Hardware Obfuscation. [Internet] [Masters thesis]. Virginia Tech; 2013. [cited 2020 Dec 04]. Available from: http://hdl.handle.net/10919/23756.

Council of Science Editors:

Desai AR. Anti-Counterfeit and Anti-Tamper Hardware Implementation using Hardware Obfuscation. [Masters Thesis]. Virginia Tech; 2013. Available from: http://hdl.handle.net/10919/23756


Virginia Tech

21. Huang, Sinan. Hardware Evaluation of SHA-3 Candidates.

Degree: MS, Electrical and Computer Engineering, 2011, Virginia Tech

 Cryptographic hash functions are used extensively in information security, most notably in digital authentication and data integrity verification. Their performance is an important factor of… (more)

Subjects/Keywords: Cryptography; Security; SHA-3; Hardware Evaluation

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APA (6th Edition):

Huang, S. (2011). Hardware Evaluation of SHA-3 Candidates. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/32932

Chicago Manual of Style (16th Edition):

Huang, Sinan. “Hardware Evaluation of SHA-3 Candidates.” 2011. Masters Thesis, Virginia Tech. Accessed December 04, 2020. http://hdl.handle.net/10919/32932.

MLA Handbook (7th Edition):

Huang, Sinan. “Hardware Evaluation of SHA-3 Candidates.” 2011. Web. 04 Dec 2020.

Vancouver:

Huang S. Hardware Evaluation of SHA-3 Candidates. [Internet] [Masters thesis]. Virginia Tech; 2011. [cited 2020 Dec 04]. Available from: http://hdl.handle.net/10919/32932.

Council of Science Editors:

Huang S. Hardware Evaluation of SHA-3 Candidates. [Masters Thesis]. Virginia Tech; 2011. Available from: http://hdl.handle.net/10919/32932

22. Deshpande, Chinmay Ravindra. Hardware Fault Attack Detection Methods for Secure Embedded Systems.

Degree: MS, Computer Engineering, 2018, Virginia Tech

 In our daily life, we are increasingly putting our trust in embedded software applications, which run on a range of processor-based embedded systems from smartcards… (more)

Subjects/Keywords: Fault Attack; Countermeasures; Detection; Clock glitching; Electromagnetic Fault Injection

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APA (6th Edition):

Deshpande, C. R. (2018). Hardware Fault Attack Detection Methods for Secure Embedded Systems. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/82141

Chicago Manual of Style (16th Edition):

Deshpande, Chinmay Ravindra. “Hardware Fault Attack Detection Methods for Secure Embedded Systems.” 2018. Masters Thesis, Virginia Tech. Accessed December 04, 2020. http://hdl.handle.net/10919/82141.

MLA Handbook (7th Edition):

Deshpande, Chinmay Ravindra. “Hardware Fault Attack Detection Methods for Secure Embedded Systems.” 2018. Web. 04 Dec 2020.

Vancouver:

Deshpande CR. Hardware Fault Attack Detection Methods for Secure Embedded Systems. [Internet] [Masters thesis]. Virginia Tech; 2018. [cited 2020 Dec 04]. Available from: http://hdl.handle.net/10919/82141.

Council of Science Editors:

Deshpande CR. Hardware Fault Attack Detection Methods for Secure Embedded Systems. [Masters Thesis]. Virginia Tech; 2018. Available from: http://hdl.handle.net/10919/82141

23. Judge, Lyndon Virginia. Design Methods for Cryptanalysis.

Degree: MS, Electrical and Computer Engineering, 2012, Virginia Tech

 Security of cryptographic algorithms relies on the computational difficulty of deriving the secret key using public information. Cryptanalysis, including logical and implementation attacks, plays an… (more)

Subjects/Keywords: Implementation attack; Design method; Bluespec; Prime field arithmetic; Pollard rho; Elliptic curve cryptography (ECC); FPGA; Hardware software co-design; Fault attack; Side-channel analysis (SCA)

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APA (6th Edition):

Judge, L. V. (2012). Design Methods for Cryptanalysis. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/35980

Chicago Manual of Style (16th Edition):

Judge, Lyndon Virginia. “Design Methods for Cryptanalysis.” 2012. Masters Thesis, Virginia Tech. Accessed December 04, 2020. http://hdl.handle.net/10919/35980.

MLA Handbook (7th Edition):

Judge, Lyndon Virginia. “Design Methods for Cryptanalysis.” 2012. Web. 04 Dec 2020.

Vancouver:

Judge LV. Design Methods for Cryptanalysis. [Internet] [Masters thesis]. Virginia Tech; 2012. [cited 2020 Dec 04]. Available from: http://hdl.handle.net/10919/35980.

Council of Science Editors:

Judge LV. Design Methods for Cryptanalysis. [Masters Thesis]. Virginia Tech; 2012. Available from: http://hdl.handle.net/10919/35980

24. Raghuraman, Shashank. Efficiency of Logic Minimization Techniques for Cryptographic Hardware Implementation.

Degree: MS, Computer Engineering, 2019, Virginia Tech

 The proliferation of embedded smart devices for the Internet-of-Things necessitates a constant search for smaller and power-efficient hardware. The need to ensure security of such… (more)

Subjects/Keywords: Logic synthesis; Cryptographic hardware; Circuit minimization; Leon-3; System-on-Chip; Authenticated encryption hardware

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APA (6th Edition):

Raghuraman, S. (2019). Efficiency of Logic Minimization Techniques for Cryptographic Hardware Implementation. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/91462

Chicago Manual of Style (16th Edition):

Raghuraman, Shashank. “Efficiency of Logic Minimization Techniques for Cryptographic Hardware Implementation.” 2019. Masters Thesis, Virginia Tech. Accessed December 04, 2020. http://hdl.handle.net/10919/91462.

MLA Handbook (7th Edition):

Raghuraman, Shashank. “Efficiency of Logic Minimization Techniques for Cryptographic Hardware Implementation.” 2019. Web. 04 Dec 2020.

Vancouver:

Raghuraman S. Efficiency of Logic Minimization Techniques for Cryptographic Hardware Implementation. [Internet] [Masters thesis]. Virginia Tech; 2019. [cited 2020 Dec 04]. Available from: http://hdl.handle.net/10919/91462.

Council of Science Editors:

Raghuraman S. Efficiency of Logic Minimization Techniques for Cryptographic Hardware Implementation. [Masters Thesis]. Virginia Tech; 2019. Available from: http://hdl.handle.net/10919/91462

25. Ghodrati, Marjan. Thwarting Electromagnetic Fault Injection Attack Utilizing Timing Attack Countermeasure.

Degree: MS, Computer Engineering, 2018, Virginia Tech

 The extent of embedded systems' role in modern life has continuously increased over the years. Moreover, embedded systems are assuming highly critical functions with security… (more)

Subjects/Keywords: Electromagnetic Fault Injection; Countermeasure; Attack

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APA (6th Edition):

Ghodrati, M. (2018). Thwarting Electromagnetic Fault Injection Attack Utilizing Timing Attack Countermeasure. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/81906

Chicago Manual of Style (16th Edition):

Ghodrati, Marjan. “Thwarting Electromagnetic Fault Injection Attack Utilizing Timing Attack Countermeasure.” 2018. Masters Thesis, Virginia Tech. Accessed December 04, 2020. http://hdl.handle.net/10919/81906.

MLA Handbook (7th Edition):

Ghodrati, Marjan. “Thwarting Electromagnetic Fault Injection Attack Utilizing Timing Attack Countermeasure.” 2018. Web. 04 Dec 2020.

Vancouver:

Ghodrati M. Thwarting Electromagnetic Fault Injection Attack Utilizing Timing Attack Countermeasure. [Internet] [Masters thesis]. Virginia Tech; 2018. [cited 2020 Dec 04]. Available from: http://hdl.handle.net/10919/81906.

Council of Science Editors:

Ghodrati M. Thwarting Electromagnetic Fault Injection Attack Utilizing Timing Attack Countermeasure. [Masters Thesis]. Virginia Tech; 2018. Available from: http://hdl.handle.net/10919/81906

26. Pinto, Carol Suman. Optimization of Physical Unclonable Function Protocols for Lightweight Processing.

Degree: MS, Computer Engineering, 2016, Virginia Tech

 Physically unclonable functions are increasingly used as security primitives for device identification and anti-counterfeiting. However, PUFs are associated with noise and bias which in turn… (more)

Subjects/Keywords: Physical Unclonable Functions (PUFs); Static Random Access Memory (SRAM); Cryptographic protocols

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APA (6th Edition):

Pinto, C. S. (2016). Optimization of Physical Unclonable Function Protocols for Lightweight Processing. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/72868

Chicago Manual of Style (16th Edition):

Pinto, Carol Suman. “Optimization of Physical Unclonable Function Protocols for Lightweight Processing.” 2016. Masters Thesis, Virginia Tech. Accessed December 04, 2020. http://hdl.handle.net/10919/72868.

MLA Handbook (7th Edition):

Pinto, Carol Suman. “Optimization of Physical Unclonable Function Protocols for Lightweight Processing.” 2016. Web. 04 Dec 2020.

Vancouver:

Pinto CS. Optimization of Physical Unclonable Function Protocols for Lightweight Processing. [Internet] [Masters thesis]. Virginia Tech; 2016. [cited 2020 Dec 04]. Available from: http://hdl.handle.net/10919/72868.

Council of Science Editors:

Pinto CS. Optimization of Physical Unclonable Function Protocols for Lightweight Processing. [Masters Thesis]. Virginia Tech; 2016. Available from: http://hdl.handle.net/10919/72868


Virginia Tech

27. Helal, Ahmed Elmohamadi Mohamed. Automated Runtime Analysis and Adaptation for Scalable Heterogeneous Computing.

Degree: PhD, Computer Engineering, 2020, Virginia Tech

 Current supercomputers integrate a massive number of heterogeneous compute units with varying speed, computational throughput, memory bandwidth, and memory access latency. This trend represents a… (more)

Subjects/Keywords: Parallel Architectures; Accelerators; Heterogeneous Computing; Performance Modeling; Runtime Adaptation; Scheduling; Performance Portability; MPI; GPU; LLVM

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APA (6th Edition):

Helal, A. E. M. (2020). Automated Runtime Analysis and Adaptation for Scalable Heterogeneous Computing. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/96607

Chicago Manual of Style (16th Edition):

Helal, Ahmed Elmohamadi Mohamed. “Automated Runtime Analysis and Adaptation for Scalable Heterogeneous Computing.” 2020. Doctoral Dissertation, Virginia Tech. Accessed December 04, 2020. http://hdl.handle.net/10919/96607.

MLA Handbook (7th Edition):

Helal, Ahmed Elmohamadi Mohamed. “Automated Runtime Analysis and Adaptation for Scalable Heterogeneous Computing.” 2020. Web. 04 Dec 2020.

Vancouver:

Helal AEM. Automated Runtime Analysis and Adaptation for Scalable Heterogeneous Computing. [Internet] [Doctoral dissertation]. Virginia Tech; 2020. [cited 2020 Dec 04]. Available from: http://hdl.handle.net/10919/96607.

Council of Science Editors:

Helal AEM. Automated Runtime Analysis and Adaptation for Scalable Heterogeneous Computing. [Doctoral Dissertation]. Virginia Tech; 2020. Available from: http://hdl.handle.net/10919/96607


Virginia Tech

28. Love, Andrew R. A Modular Flow for Rapid FPGA Design Implementation.

Degree: PhD, Computer Engineering, 2015, Virginia Tech

 This dissertation proposes an alternative FPGA design compilation flow to reduce the back-end time required to implement an FPGA design to below the level at… (more)

Subjects/Keywords: FPGA Productivity; Modular Design; Instant Gratification; Attention Span; Design Assembly Flow

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APA (6th Edition):

Love, A. R. (2015). A Modular Flow for Rapid FPGA Design Implementation. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/51608

Chicago Manual of Style (16th Edition):

Love, Andrew R. “A Modular Flow for Rapid FPGA Design Implementation.” 2015. Doctoral Dissertation, Virginia Tech. Accessed December 04, 2020. http://hdl.handle.net/10919/51608.

MLA Handbook (7th Edition):

Love, Andrew R. “A Modular Flow for Rapid FPGA Design Implementation.” 2015. Web. 04 Dec 2020.

Vancouver:

Love AR. A Modular Flow for Rapid FPGA Design Implementation. [Internet] [Doctoral dissertation]. Virginia Tech; 2015. [cited 2020 Dec 04]. Available from: http://hdl.handle.net/10919/51608.

Council of Science Editors:

Love AR. A Modular Flow for Rapid FPGA Design Implementation. [Doctoral Dissertation]. Virginia Tech; 2015. Available from: http://hdl.handle.net/10919/51608


Virginia Tech

29. Sreedharan Nair, Shree Narayanan. MicroGC: Of Detectors and their Integration.

Degree: PhD, Electrical Engineering, 2014, Virginia Tech

 Gaseous phase is a critical state of matter around us. It mediates between the solid crust on earth and inter-stellar vacuum. Apart from the atmosphere… (more)

Subjects/Keywords: micro gas chromatography; gas detector; thermal conductivity; ionization

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Sreedharan Nair, S. N. (2014). MicroGC: Of Detectors and their Integration. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/47785

Chicago Manual of Style (16th Edition):

Sreedharan Nair, Shree Narayanan. “MicroGC: Of Detectors and their Integration.” 2014. Doctoral Dissertation, Virginia Tech. Accessed December 04, 2020. http://hdl.handle.net/10919/47785.

MLA Handbook (7th Edition):

Sreedharan Nair, Shree Narayanan. “MicroGC: Of Detectors and their Integration.” 2014. Web. 04 Dec 2020.

Vancouver:

Sreedharan Nair SN. MicroGC: Of Detectors and their Integration. [Internet] [Doctoral dissertation]. Virginia Tech; 2014. [cited 2020 Dec 04]. Available from: http://hdl.handle.net/10919/47785.

Council of Science Editors:

Sreedharan Nair SN. MicroGC: Of Detectors and their Integration. [Doctoral Dissertation]. Virginia Tech; 2014. Available from: http://hdl.handle.net/10919/47785


Virginia Tech

30. Akbar, Muhammad. Chip-Scale Gas Chromatography.

Degree: PhD, Electrical Engineering, 2015, Virginia Tech

 Instrument miniaturization is led by the desire to perform rapid diagnosis in remote areas with high throughput and low cost. In addition, miniaturized instruments hold… (more)

Subjects/Keywords: MEMS; Gas Chromatography; Nanotechnology; Chemical Detectors; Lab-on-a-Chip; Microfluidics; Separation Column

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APA (6th Edition):

Akbar, M. (2015). Chip-Scale Gas Chromatography. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/56566

Chicago Manual of Style (16th Edition):

Akbar, Muhammad. “Chip-Scale Gas Chromatography.” 2015. Doctoral Dissertation, Virginia Tech. Accessed December 04, 2020. http://hdl.handle.net/10919/56566.

MLA Handbook (7th Edition):

Akbar, Muhammad. “Chip-Scale Gas Chromatography.” 2015. Web. 04 Dec 2020.

Vancouver:

Akbar M. Chip-Scale Gas Chromatography. [Internet] [Doctoral dissertation]. Virginia Tech; 2015. [cited 2020 Dec 04]. Available from: http://hdl.handle.net/10919/56566.

Council of Science Editors:

Akbar M. Chip-Scale Gas Chromatography. [Doctoral Dissertation]. Virginia Tech; 2015. Available from: http://hdl.handle.net/10919/56566

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