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You searched for +publisher:"Virginia Tech" +contributor:("Hsiao, Michael S."). Showing records 1 – 30 of 135 total matches.

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Virginia Tech

1. Limaye, Chinmay Avinash. Formal Verification Techniques for Reversible Circuits.

Degree: MS, Electrical and Computer Engineering, 2011, Virginia Tech

 As the number of transistors per unit chip area increases, the power dissipation of the chip becomes a bottleneck. New nano-technology materials have been proposed… (more)

Subjects/Keywords: Binary Decision Diagram (BDD); Reversible Circuits; Redundancy; Equivalence Checking

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APA (6th Edition):

Limaye, C. A. (2011). Formal Verification Techniques for Reversible Circuits. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/33406

Chicago Manual of Style (16th Edition):

Limaye, Chinmay Avinash. “Formal Verification Techniques for Reversible Circuits.” 2011. Masters Thesis, Virginia Tech. Accessed February 16, 2020. http://hdl.handle.net/10919/33406.

MLA Handbook (7th Edition):

Limaye, Chinmay Avinash. “Formal Verification Techniques for Reversible Circuits.” 2011. Web. 16 Feb 2020.

Vancouver:

Limaye CA. Formal Verification Techniques for Reversible Circuits. [Internet] [Masters thesis]. Virginia Tech; 2011. [cited 2020 Feb 16]. Available from: http://hdl.handle.net/10919/33406.

Council of Science Editors:

Limaye CA. Formal Verification Techniques for Reversible Circuits. [Masters Thesis]. Virginia Tech; 2011. Available from: http://hdl.handle.net/10919/33406


Virginia Tech

2. Krishnamoorthy, Saparya. Strategies for Scalable Symbolic Execution-based Test Generation.

Degree: MS, Electrical and Computer Engineering, 2010, Virginia Tech

 With the advent of advanced program analysis and constraint solving techniques, several test generation tools use variants of symbolic execution. Symbolic techniques have been shown… (more)

Subjects/Keywords: symbolic execution; software verification; dynamic test generation; path explosion; satisfiability modulo theories

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APA (6th Edition):

Krishnamoorthy, S. (2010). Strategies for Scalable Symbolic Execution-based Test Generation. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/33997

Chicago Manual of Style (16th Edition):

Krishnamoorthy, Saparya. “Strategies for Scalable Symbolic Execution-based Test Generation.” 2010. Masters Thesis, Virginia Tech. Accessed February 16, 2020. http://hdl.handle.net/10919/33997.

MLA Handbook (7th Edition):

Krishnamoorthy, Saparya. “Strategies for Scalable Symbolic Execution-based Test Generation.” 2010. Web. 16 Feb 2020.

Vancouver:

Krishnamoorthy S. Strategies for Scalable Symbolic Execution-based Test Generation. [Internet] [Masters thesis]. Virginia Tech; 2010. [cited 2020 Feb 16]. Available from: http://hdl.handle.net/10919/33997.

Council of Science Editors:

Krishnamoorthy S. Strategies for Scalable Symbolic Execution-based Test Generation. [Masters Thesis]. Virginia Tech; 2010. Available from: http://hdl.handle.net/10919/33997


Virginia Tech

3. Hoyle, Kevin. Minutiae Triplet-based Features with Extended Ridge Information for Determining Sufficiency in Fingerprints.

Degree: MS, Electrical and Computer Engineering, 2011, Virginia Tech

 In order to deliver statistical and qualitative backing to latent fingerprint evidence, algorithms are proposed (1) to perform fingerprint matching to aid in quality assessment,… (more)

Subjects/Keywords: minutia; sufficiency; latent; quality; fingerprints; friction ridges; triangles; triplets

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APA (6th Edition):

Hoyle, K. (2011). Minutiae Triplet-based Features with Extended Ridge Information for Determining Sufficiency in Fingerprints. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/34010

Chicago Manual of Style (16th Edition):

Hoyle, Kevin. “Minutiae Triplet-based Features with Extended Ridge Information for Determining Sufficiency in Fingerprints.” 2011. Masters Thesis, Virginia Tech. Accessed February 16, 2020. http://hdl.handle.net/10919/34010.

MLA Handbook (7th Edition):

Hoyle, Kevin. “Minutiae Triplet-based Features with Extended Ridge Information for Determining Sufficiency in Fingerprints.” 2011. Web. 16 Feb 2020.

Vancouver:

Hoyle K. Minutiae Triplet-based Features with Extended Ridge Information for Determining Sufficiency in Fingerprints. [Internet] [Masters thesis]. Virginia Tech; 2011. [cited 2020 Feb 16]. Available from: http://hdl.handle.net/10919/34010.

Council of Science Editors:

Hoyle K. Minutiae Triplet-based Features with Extended Ridge Information for Determining Sufficiency in Fingerprints. [Masters Thesis]. Virginia Tech; 2011. Available from: http://hdl.handle.net/10919/34010


Virginia Tech

4. Sinha, Ambuj Sudhir. Design Techniques for Side-channel Resistant Embedded Software.

Degree: MS, Electrical and Computer Engineering, 2011, Virginia Tech

 Side Channel Attacks (SCA) are a class of passive attacks on cryptosystems that exploit implementation characteristics of the system. Currently, a lot of research is… (more)

Subjects/Keywords: Bitslice Cryptography; Side Channel Attacks; Virtual Secure Circuit; Secure Embedded Systems; Side-channel Countermeasures

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APA (6th Edition):

Sinha, A. S. (2011). Design Techniques for Side-channel Resistant Embedded Software. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/34465

Chicago Manual of Style (16th Edition):

Sinha, Ambuj Sudhir. “Design Techniques for Side-channel Resistant Embedded Software.” 2011. Masters Thesis, Virginia Tech. Accessed February 16, 2020. http://hdl.handle.net/10919/34465.

MLA Handbook (7th Edition):

Sinha, Ambuj Sudhir. “Design Techniques for Side-channel Resistant Embedded Software.” 2011. Web. 16 Feb 2020.

Vancouver:

Sinha AS. Design Techniques for Side-channel Resistant Embedded Software. [Internet] [Masters thesis]. Virginia Tech; 2011. [cited 2020 Feb 16]. Available from: http://hdl.handle.net/10919/34465.

Council of Science Editors:

Sinha AS. Design Techniques for Side-channel Resistant Embedded Software. [Masters Thesis]. Virginia Tech; 2011. Available from: http://hdl.handle.net/10919/34465


Virginia Tech

5. Morozov, Sergey Victorovich. Elliptic Curve Cryptography on Heterogeneous Multicore Platform.

Degree: MS, Electrical and Computer Engineering, 2010, Virginia Tech

 Elliptic curve cryptography (ECC) is becoming the algorithm of choice for digital signature generation and authentication in embedded context. However, performance of ECC and the… (more)

Subjects/Keywords: Binary Field; DSP; ARM; Cryptography; Elliptic Curve; Prime Field; Multiprocessor; Point Multiplication; Multicore

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APA (6th Edition):

Morozov, S. V. (2010). Elliptic Curve Cryptography on Heterogeneous Multicore Platform. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/34872

Chicago Manual of Style (16th Edition):

Morozov, Sergey Victorovich. “Elliptic Curve Cryptography on Heterogeneous Multicore Platform.” 2010. Masters Thesis, Virginia Tech. Accessed February 16, 2020. http://hdl.handle.net/10919/34872.

MLA Handbook (7th Edition):

Morozov, Sergey Victorovich. “Elliptic Curve Cryptography on Heterogeneous Multicore Platform.” 2010. Web. 16 Feb 2020.

Vancouver:

Morozov SV. Elliptic Curve Cryptography on Heterogeneous Multicore Platform. [Internet] [Masters thesis]. Virginia Tech; 2010. [cited 2020 Feb 16]. Available from: http://hdl.handle.net/10919/34872.

Council of Science Editors:

Morozov SV. Elliptic Curve Cryptography on Heterogeneous Multicore Platform. [Masters Thesis]. Virginia Tech; 2010. Available from: http://hdl.handle.net/10919/34872


Virginia Tech

6. Bakshi, Dhrumeel. Techniques for Seed Computation and Testability Enhancement for Logic Built-In Self Test.

Degree: MS, Electrical and Computer Engineering, 2012, Virginia Tech

 With the increase of device complexity and test-data volume required to guarantee adequate defect coverage, external testing is becoming increasingly difficult and expensive. Logic Built-in… (more)

Subjects/Keywords: Satisfiability Modulo Theories (SMT); LFSR Reseeding; Logic Built-In Self Test (LBIST); Integer Linear Programming (ILP); Test-point Insertion

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APA (6th Edition):

Bakshi, D. (2012). Techniques for Seed Computation and Testability Enhancement for Logic Built-In Self Test. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/35474

Chicago Manual of Style (16th Edition):

Bakshi, Dhrumeel. “Techniques for Seed Computation and Testability Enhancement for Logic Built-In Self Test.” 2012. Masters Thesis, Virginia Tech. Accessed February 16, 2020. http://hdl.handle.net/10919/35474.

MLA Handbook (7th Edition):

Bakshi, Dhrumeel. “Techniques for Seed Computation and Testability Enhancement for Logic Built-In Self Test.” 2012. Web. 16 Feb 2020.

Vancouver:

Bakshi D. Techniques for Seed Computation and Testability Enhancement for Logic Built-In Self Test. [Internet] [Masters thesis]. Virginia Tech; 2012. [cited 2020 Feb 16]. Available from: http://hdl.handle.net/10919/35474.

Council of Science Editors:

Bakshi D. Techniques for Seed Computation and Testability Enhancement for Logic Built-In Self Test. [Masters Thesis]. Virginia Tech; 2012. Available from: http://hdl.handle.net/10919/35474


Virginia Tech

7. Rahagude, Nikhil Prakash. Integrated Enhancement of Testability and Diagnosability for Digital Circuits.

Degree: MS, Electrical and Computer Engineering, 2010, Virginia Tech

 While conventional test point insertions commonly used in design for testability can improve fault coverage, the test points selected may not necessarily be the best… (more)

Subjects/Keywords: Fault Coverage; Diagnostic Resolution; Weighted Average; Test Point Insertion; Design for Testability; Design for Diagnosability; Built-in Self Test

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APA (6th Edition):

Rahagude, N. P. (2010). Integrated Enhancement of Testability and Diagnosability for Digital Circuits. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/35609

Chicago Manual of Style (16th Edition):

Rahagude, Nikhil Prakash. “Integrated Enhancement of Testability and Diagnosability for Digital Circuits.” 2010. Masters Thesis, Virginia Tech. Accessed February 16, 2020. http://hdl.handle.net/10919/35609.

MLA Handbook (7th Edition):

Rahagude, Nikhil Prakash. “Integrated Enhancement of Testability and Diagnosability for Digital Circuits.” 2010. Web. 16 Feb 2020.

Vancouver:

Rahagude NP. Integrated Enhancement of Testability and Diagnosability for Digital Circuits. [Internet] [Masters thesis]. Virginia Tech; 2010. [cited 2020 Feb 16]. Available from: http://hdl.handle.net/10919/35609.

Council of Science Editors:

Rahagude NP. Integrated Enhancement of Testability and Diagnosability for Digital Circuits. [Masters Thesis]. Virginia Tech; 2010. Available from: http://hdl.handle.net/10919/35609


Virginia Tech

8. Prabhu, Sarvesh P. An Efficient 2-Phase Strategy to Achieve High Branch Coverage.

Degree: MS, Electrical and Computer Engineering, 2012, Virginia Tech

 Symbolic execution-based test generation is gaining popularity for software test generation. The increasing complexity of the software program is posing new challenges in software execution-based… (more)

Subjects/Keywords: Branch Coverage; Conflict-driven Learning; Symbolic Execution; Software Testing

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APA (6th Edition):

Prabhu, S. P. (2012). An Efficient 2-Phase Strategy to Achieve High Branch Coverage. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/40931

Chicago Manual of Style (16th Edition):

Prabhu, Sarvesh P. “An Efficient 2-Phase Strategy to Achieve High Branch Coverage.” 2012. Masters Thesis, Virginia Tech. Accessed February 16, 2020. http://hdl.handle.net/10919/40931.

MLA Handbook (7th Edition):

Prabhu, Sarvesh P. “An Efficient 2-Phase Strategy to Achieve High Branch Coverage.” 2012. Web. 16 Feb 2020.

Vancouver:

Prabhu SP. An Efficient 2-Phase Strategy to Achieve High Branch Coverage. [Internet] [Masters thesis]. Virginia Tech; 2012. [cited 2020 Feb 16]. Available from: http://hdl.handle.net/10919/40931.

Council of Science Editors:

Prabhu SP. An Efficient 2-Phase Strategy to Achieve High Branch Coverage. [Masters Thesis]. Virginia Tech; 2012. Available from: http://hdl.handle.net/10919/40931


Virginia Tech

9. Subbarayan, Guruprasad. Automatic Instantiation and Timing-Aware Placement of Bus Macros for Partially Reconfigurable FPGA Designs.

Degree: MS, Electrical and Computer Engineering, 2010, Virginia Tech

 FPGA design implementation and debug tools have not kept pace with the advances in FPGA device density. The emphasis on area optimization and circuit speed… (more)

Subjects/Keywords: FPGAs; Partial Reconfiguration; Bus macros

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APA (6th Edition):

Subbarayan, G. (2010). Automatic Instantiation and Timing-Aware Placement of Bus Macros for Partially Reconfigurable FPGA Designs. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/46033

Chicago Manual of Style (16th Edition):

Subbarayan, Guruprasad. “Automatic Instantiation and Timing-Aware Placement of Bus Macros for Partially Reconfigurable FPGA Designs.” 2010. Masters Thesis, Virginia Tech. Accessed February 16, 2020. http://hdl.handle.net/10919/46033.

MLA Handbook (7th Edition):

Subbarayan, Guruprasad. “Automatic Instantiation and Timing-Aware Placement of Bus Macros for Partially Reconfigurable FPGA Designs.” 2010. Web. 16 Feb 2020.

Vancouver:

Subbarayan G. Automatic Instantiation and Timing-Aware Placement of Bus Macros for Partially Reconfigurable FPGA Designs. [Internet] [Masters thesis]. Virginia Tech; 2010. [cited 2020 Feb 16]. Available from: http://hdl.handle.net/10919/46033.

Council of Science Editors:

Subbarayan G. Automatic Instantiation and Timing-Aware Placement of Bus Macros for Partially Reconfigurable FPGA Designs. [Masters Thesis]. Virginia Tech; 2010. Available from: http://hdl.handle.net/10919/46033


Virginia Tech

10. Bruce, Jacob Robert. Mathematical Expression Detection and Segmentation in Document Images.

Degree: MS, Electrical and Computer Engineering, 2014, Virginia Tech

 Various document layout analysis techniques are employed in order to enhance the accuracy of optical character recognition (OCR) in document images. Type-specific document layout analysis… (more)

Subjects/Keywords: document layout analysis; optical character recognition; mathematical expression detection and segmentation; document image; type-specific layout analysis

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APA (6th Edition):

Bruce, J. R. (2014). Mathematical Expression Detection and Segmentation in Document Images. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/46724

Chicago Manual of Style (16th Edition):

Bruce, Jacob Robert. “Mathematical Expression Detection and Segmentation in Document Images.” 2014. Masters Thesis, Virginia Tech. Accessed February 16, 2020. http://hdl.handle.net/10919/46724.

MLA Handbook (7th Edition):

Bruce, Jacob Robert. “Mathematical Expression Detection and Segmentation in Document Images.” 2014. Web. 16 Feb 2020.

Vancouver:

Bruce JR. Mathematical Expression Detection and Segmentation in Document Images. [Internet] [Masters thesis]. Virginia Tech; 2014. [cited 2020 Feb 16]. Available from: http://hdl.handle.net/10919/46724.

Council of Science Editors:

Bruce JR. Mathematical Expression Detection and Segmentation in Document Images. [Masters Thesis]. Virginia Tech; 2014. Available from: http://hdl.handle.net/10919/46724


Virginia Tech

11. Pabbuleti, Krishna Chaitanya. Performance Optimization of Public Key Cryptography on Embedded Platforms.

Degree: MS, Electrical and Computer Engineering, 2014, Virginia Tech

 Embedded systems are so ubiquitous that they account for almost 90% of all the computing devices. They range from very small scale devices with an… (more)

Subjects/Keywords: Elliptic Curve Cryptography; Modular Arithmetic; SIMD; Hash-based Signatures; MSP430; Wireless Sensor Node

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APA (6th Edition):

Pabbuleti, K. C. (2014). Performance Optimization of Public Key Cryptography on Embedded Platforms. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/48120

Chicago Manual of Style (16th Edition):

Pabbuleti, Krishna Chaitanya. “Performance Optimization of Public Key Cryptography on Embedded Platforms.” 2014. Masters Thesis, Virginia Tech. Accessed February 16, 2020. http://hdl.handle.net/10919/48120.

MLA Handbook (7th Edition):

Pabbuleti, Krishna Chaitanya. “Performance Optimization of Public Key Cryptography on Embedded Platforms.” 2014. Web. 16 Feb 2020.

Vancouver:

Pabbuleti KC. Performance Optimization of Public Key Cryptography on Embedded Platforms. [Internet] [Masters thesis]. Virginia Tech; 2014. [cited 2020 Feb 16]. Available from: http://hdl.handle.net/10919/48120.

Council of Science Editors:

Pabbuleti KC. Performance Optimization of Public Key Cryptography on Embedded Platforms. [Masters Thesis]. Virginia Tech; 2014. Available from: http://hdl.handle.net/10919/48120


Virginia Tech

12. Hu, Wei. Sufficiency-based Filtering of Invariants for Sequential Equivalence Checking.

Degree: MS, Electrical and Computer Engineering, 2011, Virginia Tech

 Verification, as opposed to Testing and Post-Silicon Validation, is a critical step for Integrated Circuits (IC) Design, answering the question â Are we designing the… (more)

Subjects/Keywords: Invariant filtering; Assume and Verify; Boolean Satisfiability(SAT); Sequential Equivalence Checking(SEC)

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APA (6th Edition):

Hu, W. (2011). Sufficiency-based Filtering of Invariants for Sequential Equivalence Checking. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/31121

Chicago Manual of Style (16th Edition):

Hu, Wei. “Sufficiency-based Filtering of Invariants for Sequential Equivalence Checking.” 2011. Masters Thesis, Virginia Tech. Accessed February 16, 2020. http://hdl.handle.net/10919/31121.

MLA Handbook (7th Edition):

Hu, Wei. “Sufficiency-based Filtering of Invariants for Sequential Equivalence Checking.” 2011. Web. 16 Feb 2020.

Vancouver:

Hu W. Sufficiency-based Filtering of Invariants for Sequential Equivalence Checking. [Internet] [Masters thesis]. Virginia Tech; 2011. [cited 2020 Feb 16]. Available from: http://hdl.handle.net/10919/31121.

Council of Science Editors:

Hu W. Sufficiency-based Filtering of Invariants for Sequential Equivalence Checking. [Masters Thesis]. Virginia Tech; 2011. Available from: http://hdl.handle.net/10919/31121


Virginia Tech

13. Pandit, Shuchi. Novel Architectures for Trace Buffer Design to facilitate Post-Silicon Validation and Test.

Degree: MS, Electrical and Computer Engineering, 2014, Virginia Tech

 Post-Silicon validation is playing an increasingly important role as more chips are failing in the functional mode due to either manufacturing defects escaped during scan-based… (more)

Subjects/Keywords: Trace Buffer Architecture; Signal Restoration; Invariants

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APA (6th Edition):

Pandit, S. (2014). Novel Architectures for Trace Buffer Design to facilitate Post-Silicon Validation and Test. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/49151

Chicago Manual of Style (16th Edition):

Pandit, Shuchi. “Novel Architectures for Trace Buffer Design to facilitate Post-Silicon Validation and Test.” 2014. Masters Thesis, Virginia Tech. Accessed February 16, 2020. http://hdl.handle.net/10919/49151.

MLA Handbook (7th Edition):

Pandit, Shuchi. “Novel Architectures for Trace Buffer Design to facilitate Post-Silicon Validation and Test.” 2014. Web. 16 Feb 2020.

Vancouver:

Pandit S. Novel Architectures for Trace Buffer Design to facilitate Post-Silicon Validation and Test. [Internet] [Masters thesis]. Virginia Tech; 2014. [cited 2020 Feb 16]. Available from: http://hdl.handle.net/10919/49151.

Council of Science Editors:

Pandit S. Novel Architectures for Trace Buffer Design to facilitate Post-Silicon Validation and Test. [Masters Thesis]. Virginia Tech; 2014. Available from: http://hdl.handle.net/10919/49151


Virginia Tech

14. Messaoud, Safa. Translating Discrete Time SIMULINK to SIGNAL.

Degree: MS, Electrical and Computer Engineering, 2014, Virginia Tech

 As Cyber Physical Systems (CPS) are getting more complex and safety critical, Model Based Design (MBD), which consists of building formal models of a system… (more)

Subjects/Keywords: SIMULINK; SIGNAL; Embedded Software; Code Generation

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APA (6th Edition):

Messaoud, S. (2014). Translating Discrete Time SIMULINK to SIGNAL. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/49299

Chicago Manual of Style (16th Edition):

Messaoud, Safa. “Translating Discrete Time SIMULINK to SIGNAL.” 2014. Masters Thesis, Virginia Tech. Accessed February 16, 2020. http://hdl.handle.net/10919/49299.

MLA Handbook (7th Edition):

Messaoud, Safa. “Translating Discrete Time SIMULINK to SIGNAL.” 2014. Web. 16 Feb 2020.

Vancouver:

Messaoud S. Translating Discrete Time SIMULINK to SIGNAL. [Internet] [Masters thesis]. Virginia Tech; 2014. [cited 2020 Feb 16]. Available from: http://hdl.handle.net/10919/49299.

Council of Science Editors:

Messaoud S. Translating Discrete Time SIMULINK to SIGNAL. [Masters Thesis]. Virginia Tech; 2014. Available from: http://hdl.handle.net/10919/49299


Virginia Tech

15. Balasubramanian, Harish. Incremental Design Migration Support in Industrial Control Systems Development.

Degree: MS, Electrical and Computer Engineering, 2014, Virginia Tech

 Industrial control systems (ICS) play an extremely important role in the world around us. They have helped in reducing human effort and contributed to automation… (more)

Subjects/Keywords: Industrial control systems; incremental migration; model-based design; interface abstraction

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APA (6th Edition):

Balasubramanian, H. (2014). Incremental Design Migration Support in Industrial Control Systems Development. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/50990

Chicago Manual of Style (16th Edition):

Balasubramanian, Harish. “Incremental Design Migration Support in Industrial Control Systems Development.” 2014. Masters Thesis, Virginia Tech. Accessed February 16, 2020. http://hdl.handle.net/10919/50990.

MLA Handbook (7th Edition):

Balasubramanian, Harish. “Incremental Design Migration Support in Industrial Control Systems Development.” 2014. Web. 16 Feb 2020.

Vancouver:

Balasubramanian H. Incremental Design Migration Support in Industrial Control Systems Development. [Internet] [Masters thesis]. Virginia Tech; 2014. [cited 2020 Feb 16]. Available from: http://hdl.handle.net/10919/50990.

Council of Science Editors:

Balasubramanian H. Incremental Design Migration Support in Industrial Control Systems Development. [Masters Thesis]. Virginia Tech; 2014. Available from: http://hdl.handle.net/10919/50990


Virginia Tech

16. Quesenberry, Joshua Daniel. Communication Synthesis for MIMO Decoder Matrices.

Degree: MS, Electrical and Computer Engineering, 2011, Virginia Tech

 The design in this work provides an easy and cost-efficient way of performing an FPGA implementation of a specific algorithm through use of a custom… (more)

Subjects/Keywords: Communication Synthesis; MIMO; FPGA; Xilinx

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APA (6th Edition):

Quesenberry, J. D. (2011). Communication Synthesis for MIMO Decoder Matrices. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/51149

Chicago Manual of Style (16th Edition):

Quesenberry, Joshua Daniel. “Communication Synthesis for MIMO Decoder Matrices.” 2011. Masters Thesis, Virginia Tech. Accessed February 16, 2020. http://hdl.handle.net/10919/51149.

MLA Handbook (7th Edition):

Quesenberry, Joshua Daniel. “Communication Synthesis for MIMO Decoder Matrices.” 2011. Web. 16 Feb 2020.

Vancouver:

Quesenberry JD. Communication Synthesis for MIMO Decoder Matrices. [Internet] [Masters thesis]. Virginia Tech; 2011. [cited 2020 Feb 16]. Available from: http://hdl.handle.net/10919/51149.

Council of Science Editors:

Quesenberry JD. Communication Synthesis for MIMO Decoder Matrices. [Masters Thesis]. Virginia Tech; 2011. Available from: http://hdl.handle.net/10919/51149


Virginia Tech

17. Khoshnood, Sepideh. Constraint Solving for Diagnosing Concurrency Bugs.

Degree: MS, Electrical and Computer Engineering, 2015, Virginia Tech

 Programmers often have to spend a significant amount of time inspecting the software code and execution traces to identify the root cause of a software… (more)

Subjects/Keywords: Concurrency; Bug Localization; Bounded Model Checking; MAX-SAT

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APA (6th Edition):

Khoshnood, S. (2015). Constraint Solving for Diagnosing Concurrency Bugs. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/52784

Chicago Manual of Style (16th Edition):

Khoshnood, Sepideh. “Constraint Solving for Diagnosing Concurrency Bugs.” 2015. Masters Thesis, Virginia Tech. Accessed February 16, 2020. http://hdl.handle.net/10919/52784.

MLA Handbook (7th Edition):

Khoshnood, Sepideh. “Constraint Solving for Diagnosing Concurrency Bugs.” 2015. Web. 16 Feb 2020.

Vancouver:

Khoshnood S. Constraint Solving for Diagnosing Concurrency Bugs. [Internet] [Masters thesis]. Virginia Tech; 2015. [cited 2020 Feb 16]. Available from: http://hdl.handle.net/10919/52784.

Council of Science Editors:

Khoshnood S. Constraint Solving for Diagnosing Concurrency Bugs. [Masters Thesis]. Virginia Tech; 2015. Available from: http://hdl.handle.net/10919/52784


Virginia Tech

18. Gulcan, Ege. Flexible and Lightweight Cryptographic Engines for Constrained Systems.

Degree: MS, Electrical and Computer Engineering, 2015, Virginia Tech

 There is a significant effort in building lightweight cryptographic operations, yet the proposed solutions are typically single purpose modules that can only provide a fixed… (more)

Subjects/Keywords: Lightweight Cryptography; Block Ciphers; Flexible Architectures; SIMON; FPGA

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APA (6th Edition):

Gulcan, E. (2015). Flexible and Lightweight Cryptographic Engines for Constrained Systems. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/52913

Chicago Manual of Style (16th Edition):

Gulcan, Ege. “Flexible and Lightweight Cryptographic Engines for Constrained Systems.” 2015. Masters Thesis, Virginia Tech. Accessed February 16, 2020. http://hdl.handle.net/10919/52913.

MLA Handbook (7th Edition):

Gulcan, Ege. “Flexible and Lightweight Cryptographic Engines for Constrained Systems.” 2015. Web. 16 Feb 2020.

Vancouver:

Gulcan E. Flexible and Lightweight Cryptographic Engines for Constrained Systems. [Internet] [Masters thesis]. Virginia Tech; 2015. [cited 2020 Feb 16]. Available from: http://hdl.handle.net/10919/52913.

Council of Science Editors:

Gulcan E. Flexible and Lightweight Cryptographic Engines for Constrained Systems. [Masters Thesis]. Virginia Tech; 2015. Available from: http://hdl.handle.net/10919/52913


Virginia Tech

19. Misra, Supratik Kumar. Efficient Graph Techniques for Partial Scan Pattern Debug and Bounded Model Checkers.

Degree: MS, Electrical and Computer Engineering, 2012, Virginia Tech

 Continuous advances in VLSI technology have led to more complex digital designs and shrinking transistor sizes. Due to these developments, design verification and manufacturing test… (more)

Subjects/Keywords: Directed Acyclic Graph; Partial Scan Design; Pattern Debugger; Implication Graphs

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APA (6th Edition):

Misra, S. K. (2012). Efficient Graph Techniques for Partial Scan Pattern Debug and Bounded Model Checkers. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/31153

Chicago Manual of Style (16th Edition):

Misra, Supratik Kumar. “Efficient Graph Techniques for Partial Scan Pattern Debug and Bounded Model Checkers.” 2012. Masters Thesis, Virginia Tech. Accessed February 16, 2020. http://hdl.handle.net/10919/31153.

MLA Handbook (7th Edition):

Misra, Supratik Kumar. “Efficient Graph Techniques for Partial Scan Pattern Debug and Bounded Model Checkers.” 2012. Web. 16 Feb 2020.

Vancouver:

Misra SK. Efficient Graph Techniques for Partial Scan Pattern Debug and Bounded Model Checkers. [Internet] [Masters thesis]. Virginia Tech; 2012. [cited 2020 Feb 16]. Available from: http://hdl.handle.net/10919/31153.

Council of Science Editors:

Misra SK. Efficient Graph Techniques for Partial Scan Pattern Debug and Bounded Model Checkers. [Masters Thesis]. Virginia Tech; 2012. Available from: http://hdl.handle.net/10919/31153


Virginia Tech

20. Puri, Prateek. Design Validation of RTL Circuits using Binary Particle Swarm Optimization and Symbolic Execution.

Degree: MS, Electrical and Computer Engineering, 2015, Virginia Tech

 Over the last two decades, chip design has been conducted at the register transfer (RT) Level using Hardware Descriptive Languages (HDL), such as VHDL and… (more)

Subjects/Keywords: Design Verification; Particle Swarm Optimization; Static Analysis; Symbolic Backward Execution; Satisfiability Modulo Theory; Pattern Search Methods

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APA (6th Edition):

Puri, P. (2015). Design Validation of RTL Circuits using Binary Particle Swarm Optimization and Symbolic Execution. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/55815

Chicago Manual of Style (16th Edition):

Puri, Prateek. “Design Validation of RTL Circuits using Binary Particle Swarm Optimization and Symbolic Execution.” 2015. Masters Thesis, Virginia Tech. Accessed February 16, 2020. http://hdl.handle.net/10919/55815.

MLA Handbook (7th Edition):

Puri, Prateek. “Design Validation of RTL Circuits using Binary Particle Swarm Optimization and Symbolic Execution.” 2015. Web. 16 Feb 2020.

Vancouver:

Puri P. Design Validation of RTL Circuits using Binary Particle Swarm Optimization and Symbolic Execution. [Internet] [Masters thesis]. Virginia Tech; 2015. [cited 2020 Feb 16]. Available from: http://hdl.handle.net/10919/55815.

Council of Science Editors:

Puri P. Design Validation of RTL Circuits using Binary Particle Swarm Optimization and Symbolic Execution. [Masters Thesis]. Virginia Tech; 2015. Available from: http://hdl.handle.net/10919/55815


Virginia Tech

21. Duong, Khanh Viet. On Enhancing Deterministic Sequential ATPG.

Degree: MS, Electrical and Computer Engineering, 2011, Virginia Tech

 This thesis presents four different techniques for improving the average-case performance of deterministic sequential circuit Automatic Test Patterns Generators (ATPG). Three techniques make use of… (more)

Subjects/Keywords: Automatic Test Pattern Generation; Logic Testing; Sequential Circuits

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APA (6th Edition):

Duong, K. V. (2011). On Enhancing Deterministic Sequential ATPG. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/31283

Chicago Manual of Style (16th Edition):

Duong, Khanh Viet. “On Enhancing Deterministic Sequential ATPG.” 2011. Masters Thesis, Virginia Tech. Accessed February 16, 2020. http://hdl.handle.net/10919/31283.

MLA Handbook (7th Edition):

Duong, Khanh Viet. “On Enhancing Deterministic Sequential ATPG.” 2011. Web. 16 Feb 2020.

Vancouver:

Duong KV. On Enhancing Deterministic Sequential ATPG. [Internet] [Masters thesis]. Virginia Tech; 2011. [cited 2020 Feb 16]. Available from: http://hdl.handle.net/10919/31283.

Council of Science Editors:

Duong KV. On Enhancing Deterministic Sequential ATPG. [Masters Thesis]. Virginia Tech; 2011. Available from: http://hdl.handle.net/10919/31283


Virginia Tech

22. Harekoppa, Pooja Puttaswamygowda. Application of Computer Vision Techniques for Railroad Inspection using UAVs.

Degree: MS, Electrical and Computer Engineering, 2016, Virginia Tech

 The task of railroad inspection is a tedious one. It requires a lot of skilled experts and long hours of frequent on-field inspection. Automated ground… (more)

Subjects/Keywords: Computer Vision; Machine Learning; Railroad inspection; Unmanned Aerial Vehicle (UAV)

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APA (6th Edition):

Harekoppa, P. P. (2016). Application of Computer Vision Techniques for Railroad Inspection using UAVs. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/72273

Chicago Manual of Style (16th Edition):

Harekoppa, Pooja Puttaswamygowda. “Application of Computer Vision Techniques for Railroad Inspection using UAVs.” 2016. Masters Thesis, Virginia Tech. Accessed February 16, 2020. http://hdl.handle.net/10919/72273.

MLA Handbook (7th Edition):

Harekoppa, Pooja Puttaswamygowda. “Application of Computer Vision Techniques for Railroad Inspection using UAVs.” 2016. Web. 16 Feb 2020.

Vancouver:

Harekoppa PP. Application of Computer Vision Techniques for Railroad Inspection using UAVs. [Internet] [Masters thesis]. Virginia Tech; 2016. [cited 2020 Feb 16]. Available from: http://hdl.handle.net/10919/72273.

Council of Science Editors:

Harekoppa PP. Application of Computer Vision Techniques for Railroad Inspection using UAVs. [Masters Thesis]. Virginia Tech; 2016. Available from: http://hdl.handle.net/10919/72273


Virginia Tech

23. Kindel, David Garret. Reducing Subthreshold Leakage Power Through Hybrid MOSFET-NEMS Power Gating.

Degree: MS, Electrical and Computer Engineering, 2016, Virginia Tech

 Modern devices such as smartphones and smartwatches spend a large amount of their life idle, waiting for external events. During this time, they are expending… (more)

Subjects/Keywords: NEMS; Power Gating; Low Power; Simulator; Computer Architecture

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APA (6th Edition):

Kindel, D. G. (2016). Reducing Subthreshold Leakage Power Through Hybrid MOSFET-NEMS Power Gating. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/72871

Chicago Manual of Style (16th Edition):

Kindel, David Garret. “Reducing Subthreshold Leakage Power Through Hybrid MOSFET-NEMS Power Gating.” 2016. Masters Thesis, Virginia Tech. Accessed February 16, 2020. http://hdl.handle.net/10919/72871.

MLA Handbook (7th Edition):

Kindel, David Garret. “Reducing Subthreshold Leakage Power Through Hybrid MOSFET-NEMS Power Gating.” 2016. Web. 16 Feb 2020.

Vancouver:

Kindel DG. Reducing Subthreshold Leakage Power Through Hybrid MOSFET-NEMS Power Gating. [Internet] [Masters thesis]. Virginia Tech; 2016. [cited 2020 Feb 16]. Available from: http://hdl.handle.net/10919/72871.

Council of Science Editors:

Kindel DG. Reducing Subthreshold Leakage Power Through Hybrid MOSFET-NEMS Power Gating. [Masters Thesis]. Virginia Tech; 2016. Available from: http://hdl.handle.net/10919/72871


Virginia Tech

24. Marcellino, Brendan Adrian. Partitioning Strategies to Enhance Symbolic Execution.

Degree: MS, Electrical and Computer Engineering, 2015, Virginia Tech

 Software testing is a fundamental part of the software development process. However, testing is still costly and consumes about half of the development cost. The… (more)

Subjects/Keywords: Symbolic Execution; Software Testing; Static Analysis; Partitioning Strategies

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APA (6th Edition):

Marcellino, B. A. (2015). Partitioning Strategies to Enhance Symbolic Execution. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/74883

Chicago Manual of Style (16th Edition):

Marcellino, Brendan Adrian. “Partitioning Strategies to Enhance Symbolic Execution.” 2015. Masters Thesis, Virginia Tech. Accessed February 16, 2020. http://hdl.handle.net/10919/74883.

MLA Handbook (7th Edition):

Marcellino, Brendan Adrian. “Partitioning Strategies to Enhance Symbolic Execution.” 2015. Web. 16 Feb 2020.

Vancouver:

Marcellino BA. Partitioning Strategies to Enhance Symbolic Execution. [Internet] [Masters thesis]. Virginia Tech; 2015. [cited 2020 Feb 16]. Available from: http://hdl.handle.net/10919/74883.

Council of Science Editors:

Marcellino BA. Partitioning Strategies to Enhance Symbolic Execution. [Masters Thesis]. Virginia Tech; 2015. Available from: http://hdl.handle.net/10919/74883


Virginia Tech

25. Goel, Neha. Mining Multinode Constraints and Complex Boolean Expressions for Sequential Equivalence Checking.

Degree: MS, Electrical and Computer Engineering, 2010, Virginia Tech

 Integrated circuit design has progressed significantly over the last few decades. This increasing complexity of hardware systems poses several challenges to the digital hardware verification.… (more)

Subjects/Keywords: Inductive invariants; Implications; Data Mining; Formal verification; Finite state machines

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APA (6th Edition):

Goel, N. (2010). Mining Multinode Constraints and Complex Boolean Expressions for Sequential Equivalence Checking. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/76840

Chicago Manual of Style (16th Edition):

Goel, Neha. “Mining Multinode Constraints and Complex Boolean Expressions for Sequential Equivalence Checking.” 2010. Masters Thesis, Virginia Tech. Accessed February 16, 2020. http://hdl.handle.net/10919/76840.

MLA Handbook (7th Edition):

Goel, Neha. “Mining Multinode Constraints and Complex Boolean Expressions for Sequential Equivalence Checking.” 2010. Web. 16 Feb 2020.

Vancouver:

Goel N. Mining Multinode Constraints and Complex Boolean Expressions for Sequential Equivalence Checking. [Internet] [Masters thesis]. Virginia Tech; 2010. [cited 2020 Feb 16]. Available from: http://hdl.handle.net/10919/76840.

Council of Science Editors:

Goel N. Mining Multinode Constraints and Complex Boolean Expressions for Sequential Equivalence Checking. [Masters Thesis]. Virginia Tech; 2010. Available from: http://hdl.handle.net/10919/76840


Virginia Tech

26. Bhal, Siddharth. Fog computing for robotics system with adaptive task allocation.

Degree: MS, Electrical and Computer Engineering, 2017, Virginia Tech

 The evolution of cloud computing has finally started to affect robotics. Indeed, there have been several real-time cloud applications making their way into robotics as… (more)

Subjects/Keywords: cloud robotics; fog computing; task allocation; multi-robot systems

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APA (6th Edition):

Bhal, S. (2017). Fog computing for robotics system with adaptive task allocation. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/78723

Chicago Manual of Style (16th Edition):

Bhal, Siddharth. “Fog computing for robotics system with adaptive task allocation.” 2017. Masters Thesis, Virginia Tech. Accessed February 16, 2020. http://hdl.handle.net/10919/78723.

MLA Handbook (7th Edition):

Bhal, Siddharth. “Fog computing for robotics system with adaptive task allocation.” 2017. Web. 16 Feb 2020.

Vancouver:

Bhal S. Fog computing for robotics system with adaptive task allocation. [Internet] [Masters thesis]. Virginia Tech; 2017. [cited 2020 Feb 16]. Available from: http://hdl.handle.net/10919/78723.

Council of Science Editors:

Bhal S. Fog computing for robotics system with adaptive task allocation. [Masters Thesis]. Virginia Tech; 2017. Available from: http://hdl.handle.net/10919/78723


Virginia Tech

27. Roy, Tonmoy. Reachability Analysis of RTL Circuits Using k-Induction Bounded Model Checking and Test Vector Compaction.

Degree: MS, Electrical and Computer Engineering, 2017, Virginia Tech

 In the first half of this thesis, a novel approach for k-induction bounded model checking using signal domain constraints and property partitioning for proving unreachability… (more)

Subjects/Keywords: RTL Verification; Reachability; k-Induction; Bounded Model Checking; Test Vector Compaction

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APA (6th Edition):

Roy, T. (2017). Reachability Analysis of RTL Circuits Using k-Induction Bounded Model Checking and Test Vector Compaction. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/78801

Chicago Manual of Style (16th Edition):

Roy, Tonmoy. “Reachability Analysis of RTL Circuits Using k-Induction Bounded Model Checking and Test Vector Compaction.” 2017. Masters Thesis, Virginia Tech. Accessed February 16, 2020. http://hdl.handle.net/10919/78801.

MLA Handbook (7th Edition):

Roy, Tonmoy. “Reachability Analysis of RTL Circuits Using k-Induction Bounded Model Checking and Test Vector Compaction.” 2017. Web. 16 Feb 2020.

Vancouver:

Roy T. Reachability Analysis of RTL Circuits Using k-Induction Bounded Model Checking and Test Vector Compaction. [Internet] [Masters thesis]. Virginia Tech; 2017. [cited 2020 Feb 16]. Available from: http://hdl.handle.net/10919/78801.

Council of Science Editors:

Roy T. Reachability Analysis of RTL Circuits Using k-Induction Bounded Model Checking and Test Vector Compaction. [Masters Thesis]. Virginia Tech; 2017. Available from: http://hdl.handle.net/10919/78801


Virginia Tech

28. Gabriel, Matthew Frederick. An Expanded Speedup Model for the Early Phases of High Performance Computing Cluster (HPCC) Design.

Degree: MS, Electrical and Computer Engineering, 2013, Virginia Tech

 The size and complexity of many scientific and enterprise-level applications require a high degree of parallelization in order to produce outputs within an acceptable period… (more)

Subjects/Keywords: High Performance Computing; Speedup; Amdahl; Gustafson

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APA (6th Edition):

Gabriel, M. F. (2013). An Expanded Speedup Model for the Early Phases of High Performance Computing Cluster (HPCC) Design. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/22053

Chicago Manual of Style (16th Edition):

Gabriel, Matthew Frederick. “An Expanded Speedup Model for the Early Phases of High Performance Computing Cluster (HPCC) Design.” 2013. Masters Thesis, Virginia Tech. Accessed February 16, 2020. http://hdl.handle.net/10919/22053.

MLA Handbook (7th Edition):

Gabriel, Matthew Frederick. “An Expanded Speedup Model for the Early Phases of High Performance Computing Cluster (HPCC) Design.” 2013. Web. 16 Feb 2020.

Vancouver:

Gabriel MF. An Expanded Speedup Model for the Early Phases of High Performance Computing Cluster (HPCC) Design. [Internet] [Masters thesis]. Virginia Tech; 2013. [cited 2020 Feb 16]. Available from: http://hdl.handle.net/10919/22053.

Council of Science Editors:

Gabriel MF. An Expanded Speedup Model for the Early Phases of High Performance Computing Cluster (HPCC) Design. [Masters Thesis]. Virginia Tech; 2013. Available from: http://hdl.handle.net/10919/22053


Virginia Tech

29. Moudgil, Rashmi. A Statistical and Circuit Based Technique for Counterfeit Detection in Existing ICs.

Degree: MS, Electrical and Computer Engineering, 2013, Virginia Tech

 Counterfeit Integrated Circuits (ICs) are previously used ICs that are resold as new. They have become a serious problem in modern electronic devices. They cause… (more)

Subjects/Keywords: Counterfeits; Aging; Process Variation

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APA (6th Edition):

Moudgil, R. (2013). A Statistical and Circuit Based Technique for Counterfeit Detection in Existing ICs. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/23177

Chicago Manual of Style (16th Edition):

Moudgil, Rashmi. “A Statistical and Circuit Based Technique for Counterfeit Detection in Existing ICs.” 2013. Masters Thesis, Virginia Tech. Accessed February 16, 2020. http://hdl.handle.net/10919/23177.

MLA Handbook (7th Edition):

Moudgil, Rashmi. “A Statistical and Circuit Based Technique for Counterfeit Detection in Existing ICs.” 2013. Web. 16 Feb 2020.

Vancouver:

Moudgil R. A Statistical and Circuit Based Technique for Counterfeit Detection in Existing ICs. [Internet] [Masters thesis]. Virginia Tech; 2013. [cited 2020 Feb 16]. Available from: http://hdl.handle.net/10919/23177.

Council of Science Editors:

Moudgil R. A Statistical and Circuit Based Technique for Counterfeit Detection in Existing ICs. [Masters Thesis]. Virginia Tech; 2013. Available from: http://hdl.handle.net/10919/23177


Virginia Tech

30. Adhikari, Kiran. Verifying a Quantitative Relaxation of Linearizability via Refinement.

Degree: MS, Electrical and Computer Engineering, 2013, Virginia Tech

 Concurrent data structures have found increasingly widespread use in both multicore and distributed computing environments, thereby escalating the priority for verifying their correctness. The thread… (more)

Subjects/Keywords: Quasi Linearizability; Refinement; Model Checking

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APA (6th Edition):

Adhikari, K. (2013). Verifying a Quantitative Relaxation of Linearizability via Refinement. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/23222

Chicago Manual of Style (16th Edition):

Adhikari, Kiran. “Verifying a Quantitative Relaxation of Linearizability via Refinement.” 2013. Masters Thesis, Virginia Tech. Accessed February 16, 2020. http://hdl.handle.net/10919/23222.

MLA Handbook (7th Edition):

Adhikari, Kiran. “Verifying a Quantitative Relaxation of Linearizability via Refinement.” 2013. Web. 16 Feb 2020.

Vancouver:

Adhikari K. Verifying a Quantitative Relaxation of Linearizability via Refinement. [Internet] [Masters thesis]. Virginia Tech; 2013. [cited 2020 Feb 16]. Available from: http://hdl.handle.net/10919/23222.

Council of Science Editors:

Adhikari K. Verifying a Quantitative Relaxation of Linearizability via Refinement. [Masters Thesis]. Virginia Tech; 2013. Available from: http://hdl.handle.net/10919/23222

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