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You searched for +publisher:"Virginia Tech" +contributor:("Hsiao, Michael S."). Showing records 1 – 30 of 140 total matches.

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Virginia Tech

1. Hoyle, Kevin. Minutiae Triplet-based Features with Extended Ridge Information for Determining Sufficiency in Fingerprints.

Degree: MS, Electrical and Computer Engineering, 2011, Virginia Tech

 In order to deliver statistical and qualitative backing to latent fingerprint evidence, algorithms are proposed (1) to perform fingerprint matching to aid in quality assessment,… (more)

Subjects/Keywords: minutia; sufficiency; latent; quality; fingerprints; friction ridges; triangles; triplets

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APA (6th Edition):

Hoyle, K. (2011). Minutiae Triplet-based Features with Extended Ridge Information for Determining Sufficiency in Fingerprints. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/34010

Chicago Manual of Style (16th Edition):

Hoyle, Kevin. “Minutiae Triplet-based Features with Extended Ridge Information for Determining Sufficiency in Fingerprints.” 2011. Masters Thesis, Virginia Tech. Accessed March 04, 2021. http://hdl.handle.net/10919/34010.

MLA Handbook (7th Edition):

Hoyle, Kevin. “Minutiae Triplet-based Features with Extended Ridge Information for Determining Sufficiency in Fingerprints.” 2011. Web. 04 Mar 2021.

Vancouver:

Hoyle K. Minutiae Triplet-based Features with Extended Ridge Information for Determining Sufficiency in Fingerprints. [Internet] [Masters thesis]. Virginia Tech; 2011. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/10919/34010.

Council of Science Editors:

Hoyle K. Minutiae Triplet-based Features with Extended Ridge Information for Determining Sufficiency in Fingerprints. [Masters Thesis]. Virginia Tech; 2011. Available from: http://hdl.handle.net/10919/34010


Virginia Tech

2. Bakshi, Dhrumeel. Techniques for Seed Computation and Testability Enhancement for Logic Built-In Self Test.

Degree: MS, Electrical and Computer Engineering, 2012, Virginia Tech

 With the increase of device complexity and test-data volume required to guarantee adequate defect coverage, external testing is becoming increasingly difficult and expensive. Logic Built-in… (more)

Subjects/Keywords: Satisfiability Modulo Theories (SMT); LFSR Reseeding; Logic Built-In Self Test (LBIST); Integer Linear Programming (ILP); Test-point Insertion

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APA (6th Edition):

Bakshi, D. (2012). Techniques for Seed Computation and Testability Enhancement for Logic Built-In Self Test. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/35474

Chicago Manual of Style (16th Edition):

Bakshi, Dhrumeel. “Techniques for Seed Computation and Testability Enhancement for Logic Built-In Self Test.” 2012. Masters Thesis, Virginia Tech. Accessed March 04, 2021. http://hdl.handle.net/10919/35474.

MLA Handbook (7th Edition):

Bakshi, Dhrumeel. “Techniques for Seed Computation and Testability Enhancement for Logic Built-In Self Test.” 2012. Web. 04 Mar 2021.

Vancouver:

Bakshi D. Techniques for Seed Computation and Testability Enhancement for Logic Built-In Self Test. [Internet] [Masters thesis]. Virginia Tech; 2012. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/10919/35474.

Council of Science Editors:

Bakshi D. Techniques for Seed Computation and Testability Enhancement for Logic Built-In Self Test. [Masters Thesis]. Virginia Tech; 2012. Available from: http://hdl.handle.net/10919/35474


Virginia Tech

3. Kindel, David Garret. Reducing Subthreshold Leakage Power Through Hybrid MOSFET-NEMS Power Gating.

Degree: MS, Computer Engineering, 2016, Virginia Tech

 Modern devices such as smartphones and smartwatches spend a large amount of their life idle, waiting for external events. During this time, they are expending… (more)

Subjects/Keywords: NEMS; Power Gating; Low Power; Simulator; Computer Architecture

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APA (6th Edition):

Kindel, D. G. (2016). Reducing Subthreshold Leakage Power Through Hybrid MOSFET-NEMS Power Gating. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/72871

Chicago Manual of Style (16th Edition):

Kindel, David Garret. “Reducing Subthreshold Leakage Power Through Hybrid MOSFET-NEMS Power Gating.” 2016. Masters Thesis, Virginia Tech. Accessed March 04, 2021. http://hdl.handle.net/10919/72871.

MLA Handbook (7th Edition):

Kindel, David Garret. “Reducing Subthreshold Leakage Power Through Hybrid MOSFET-NEMS Power Gating.” 2016. Web. 04 Mar 2021.

Vancouver:

Kindel DG. Reducing Subthreshold Leakage Power Through Hybrid MOSFET-NEMS Power Gating. [Internet] [Masters thesis]. Virginia Tech; 2016. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/10919/72871.

Council of Science Editors:

Kindel DG. Reducing Subthreshold Leakage Power Through Hybrid MOSFET-NEMS Power Gating. [Masters Thesis]. Virginia Tech; 2016. Available from: http://hdl.handle.net/10919/72871


Virginia Tech

4. Nguyen, Huy. Sequential Equivalence Checking with Efficient Filtering Strategies for Inductive Invariants.

Degree: MS, Electrical and Computer Engineering, 2011, Virginia Tech

 Powerful sequential optimization techniques can drastically change the Integrated Circuit (IC) design paradigm. Due to the limited capability of sequential verification tools, aggressive sequential optimization… (more)

Subjects/Keywords: Boolean Satisfiability(SAT); Sequential Equivalence Checking(SEC); Formal Verification; Dynamic Invariant Filtering; Implications

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APA (6th Edition):

Nguyen, H. (2011). Sequential Equivalence Checking with Efficient Filtering Strategies for Inductive Invariants. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/31986

Chicago Manual of Style (16th Edition):

Nguyen, Huy. “Sequential Equivalence Checking with Efficient Filtering Strategies for Inductive Invariants.” 2011. Masters Thesis, Virginia Tech. Accessed March 04, 2021. http://hdl.handle.net/10919/31986.

MLA Handbook (7th Edition):

Nguyen, Huy. “Sequential Equivalence Checking with Efficient Filtering Strategies for Inductive Invariants.” 2011. Web. 04 Mar 2021.

Vancouver:

Nguyen H. Sequential Equivalence Checking with Efficient Filtering Strategies for Inductive Invariants. [Internet] [Masters thesis]. Virginia Tech; 2011. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/10919/31986.

Council of Science Editors:

Nguyen H. Sequential Equivalence Checking with Efficient Filtering Strategies for Inductive Invariants. [Masters Thesis]. Virginia Tech; 2011. Available from: http://hdl.handle.net/10919/31986


Virginia Tech

5. Misra, Supratik Kumar. Efficient Graph Techniques for Partial Scan Pattern Debug and Bounded Model Checkers.

Degree: MS, Electrical and Computer Engineering, 2012, Virginia Tech

 Continuous advances in VLSI technology have led to more complex digital designs and shrinking transistor sizes. Due to these developments, design verification and manufacturing test… (more)

Subjects/Keywords: Directed Acyclic Graph; Partial Scan Design; Pattern Debugger; Implication Graphs

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APA (6th Edition):

Misra, S. K. (2012). Efficient Graph Techniques for Partial Scan Pattern Debug and Bounded Model Checkers. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/31153

Chicago Manual of Style (16th Edition):

Misra, Supratik Kumar. “Efficient Graph Techniques for Partial Scan Pattern Debug and Bounded Model Checkers.” 2012. Masters Thesis, Virginia Tech. Accessed March 04, 2021. http://hdl.handle.net/10919/31153.

MLA Handbook (7th Edition):

Misra, Supratik Kumar. “Efficient Graph Techniques for Partial Scan Pattern Debug and Bounded Model Checkers.” 2012. Web. 04 Mar 2021.

Vancouver:

Misra SK. Efficient Graph Techniques for Partial Scan Pattern Debug and Bounded Model Checkers. [Internet] [Masters thesis]. Virginia Tech; 2012. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/10919/31153.

Council of Science Editors:

Misra SK. Efficient Graph Techniques for Partial Scan Pattern Debug and Bounded Model Checkers. [Masters Thesis]. Virginia Tech; 2012. Available from: http://hdl.handle.net/10919/31153


Virginia Tech

6. Shrestha, Gyanendra. Ensuring Trust Of Third-Party Hardware Design With Constrained Sequential Equivalence Checking.

Degree: MS, Electrical and Computer Engineering, 2012, Virginia Tech

 Globalization of semiconductor design and manufacturing has led to a concern of trust in the final product. The components may now be designed and manufactured… (more)

Subjects/Keywords: BMC; Miter; RTL; Hardware Trojan

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APA (6th Edition):

Shrestha, G. (2012). Ensuring Trust Of Third-Party Hardware Design With Constrained Sequential Equivalence Checking. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/44889

Chicago Manual of Style (16th Edition):

Shrestha, Gyanendra. “Ensuring Trust Of Third-Party Hardware Design With Constrained Sequential Equivalence Checking.” 2012. Masters Thesis, Virginia Tech. Accessed March 04, 2021. http://hdl.handle.net/10919/44889.

MLA Handbook (7th Edition):

Shrestha, Gyanendra. “Ensuring Trust Of Third-Party Hardware Design With Constrained Sequential Equivalence Checking.” 2012. Web. 04 Mar 2021.

Vancouver:

Shrestha G. Ensuring Trust Of Third-Party Hardware Design With Constrained Sequential Equivalence Checking. [Internet] [Masters thesis]. Virginia Tech; 2012. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/10919/44889.

Council of Science Editors:

Shrestha G. Ensuring Trust Of Third-Party Hardware Design With Constrained Sequential Equivalence Checking. [Masters Thesis]. Virginia Tech; 2012. Available from: http://hdl.handle.net/10919/44889


Virginia Tech

7. Murali, Dilip Venkateswaran. Verification of Cyber Physical Systems.

Degree: MS, Computer Engineering, 2013, Virginia Tech

 Due to the increasing complexity of today\'s cyber-physical systems, defects become inevitable and harder to detect. The complexity of such software is generally huge, with… (more)

Subjects/Keywords: Invariants detection; Symbolic Execution; KLEE; Cloud9; VCC

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APA (6th Edition):

Murali, D. V. (2013). Verification of Cyber Physical Systems. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/23824

Chicago Manual of Style (16th Edition):

Murali, Dilip Venkateswaran. “Verification of Cyber Physical Systems.” 2013. Masters Thesis, Virginia Tech. Accessed March 04, 2021. http://hdl.handle.net/10919/23824.

MLA Handbook (7th Edition):

Murali, Dilip Venkateswaran. “Verification of Cyber Physical Systems.” 2013. Web. 04 Mar 2021.

Vancouver:

Murali DV. Verification of Cyber Physical Systems. [Internet] [Masters thesis]. Virginia Tech; 2013. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/10919/23824.

Council of Science Editors:

Murali DV. Verification of Cyber Physical Systems. [Masters Thesis]. Virginia Tech; 2013. Available from: http://hdl.handle.net/10919/23824


Virginia Tech

8. Bhal, Siddharth. Fog computing for robotics system with adaptive task allocation.

Degree: MS, Computer Engineering, 2017, Virginia Tech

 The evolution of cloud computing has finally started to affect robotics. Indeed, there have been several real-time cloud applications making their way into robotics as… (more)

Subjects/Keywords: cloud robotics; fog computing; task allocation; multi-robot systems

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APA (6th Edition):

Bhal, S. (2017). Fog computing for robotics system with adaptive task allocation. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/78723

Chicago Manual of Style (16th Edition):

Bhal, Siddharth. “Fog computing for robotics system with adaptive task allocation.” 2017. Masters Thesis, Virginia Tech. Accessed March 04, 2021. http://hdl.handle.net/10919/78723.

MLA Handbook (7th Edition):

Bhal, Siddharth. “Fog computing for robotics system with adaptive task allocation.” 2017. Web. 04 Mar 2021.

Vancouver:

Bhal S. Fog computing for robotics system with adaptive task allocation. [Internet] [Masters thesis]. Virginia Tech; 2017. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/10919/78723.

Council of Science Editors:

Bhal S. Fog computing for robotics system with adaptive task allocation. [Masters Thesis]. Virginia Tech; 2017. Available from: http://hdl.handle.net/10919/78723


Virginia Tech

9. Gabriel, Matthew Frederick. An Expanded Speedup Model for the Early Phases of High Performance Computing Cluster (HPCC) Design.

Degree: MS, Computer Engineering, 2013, Virginia Tech

 The size and complexity of many scientific and enterprise-level applications require a high degree of parallelization in order to produce outputs within an acceptable period… (more)

Subjects/Keywords: High Performance Computing; Speedup; Amdahl; Gustafson

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APA (6th Edition):

Gabriel, M. F. (2013). An Expanded Speedup Model for the Early Phases of High Performance Computing Cluster (HPCC) Design. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/22053

Chicago Manual of Style (16th Edition):

Gabriel, Matthew Frederick. “An Expanded Speedup Model for the Early Phases of High Performance Computing Cluster (HPCC) Design.” 2013. Masters Thesis, Virginia Tech. Accessed March 04, 2021. http://hdl.handle.net/10919/22053.

MLA Handbook (7th Edition):

Gabriel, Matthew Frederick. “An Expanded Speedup Model for the Early Phases of High Performance Computing Cluster (HPCC) Design.” 2013. Web. 04 Mar 2021.

Vancouver:

Gabriel MF. An Expanded Speedup Model for the Early Phases of High Performance Computing Cluster (HPCC) Design. [Internet] [Masters thesis]. Virginia Tech; 2013. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/10919/22053.

Council of Science Editors:

Gabriel MF. An Expanded Speedup Model for the Early Phases of High Performance Computing Cluster (HPCC) Design. [Masters Thesis]. Virginia Tech; 2013. Available from: http://hdl.handle.net/10919/22053


Virginia Tech

10. Adhikari, Kiran. Verifying a Quantitative Relaxation of Linearizability via Refinement.

Degree: MS, Computer Engineering, 2013, Virginia Tech

 Concurrent data structures have found increasingly widespread use in both multicore and distributed computing environments, thereby escalating the priority for verifying their correctness. The thread… (more)

Subjects/Keywords: Quasi Linearizability; Refinement; Model Checking

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APA (6th Edition):

Adhikari, K. (2013). Verifying a Quantitative Relaxation of Linearizability via Refinement. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/23222

Chicago Manual of Style (16th Edition):

Adhikari, Kiran. “Verifying a Quantitative Relaxation of Linearizability via Refinement.” 2013. Masters Thesis, Virginia Tech. Accessed March 04, 2021. http://hdl.handle.net/10919/23222.

MLA Handbook (7th Edition):

Adhikari, Kiran. “Verifying a Quantitative Relaxation of Linearizability via Refinement.” 2013. Web. 04 Mar 2021.

Vancouver:

Adhikari K. Verifying a Quantitative Relaxation of Linearizability via Refinement. [Internet] [Masters thesis]. Virginia Tech; 2013. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/10919/23222.

Council of Science Editors:

Adhikari K. Verifying a Quantitative Relaxation of Linearizability via Refinement. [Masters Thesis]. Virginia Tech; 2013. Available from: http://hdl.handle.net/10919/23222


Virginia Tech

11. Theyyar Maalolan, Lakshman. Trusted Unmanned Aerial System Operations.

Degree: MS, Computer Engineering, 2020, Virginia Tech

 Software code in autonomous systems, like cars, drones, and robots, keeps growing not just in length, but also in complexity. The use of machine learning… (more)

Subjects/Keywords: Runtime verification; Safety monitors; FPGA; UAS; Formal methods

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APA (6th Edition):

Theyyar Maalolan, L. (2020). Trusted Unmanned Aerial System Operations. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/98735

Chicago Manual of Style (16th Edition):

Theyyar Maalolan, Lakshman. “Trusted Unmanned Aerial System Operations.” 2020. Masters Thesis, Virginia Tech. Accessed March 04, 2021. http://hdl.handle.net/10919/98735.

MLA Handbook (7th Edition):

Theyyar Maalolan, Lakshman. “Trusted Unmanned Aerial System Operations.” 2020. Web. 04 Mar 2021.

Vancouver:

Theyyar Maalolan L. Trusted Unmanned Aerial System Operations. [Internet] [Masters thesis]. Virginia Tech; 2020. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/10919/98735.

Council of Science Editors:

Theyyar Maalolan L. Trusted Unmanned Aerial System Operations. [Masters Thesis]. Virginia Tech; 2020. Available from: http://hdl.handle.net/10919/98735


Virginia Tech

12. Limaye, Chinmay Avinash. Formal Verification Techniques for Reversible Circuits.

Degree: MS, Electrical and Computer Engineering, 2011, Virginia Tech

 As the number of transistors per unit chip area increases, the power dissipation of the chip becomes a bottleneck. New nano-technology materials have been proposed… (more)

Subjects/Keywords: Binary Decision Diagram (BDD); Reversible Circuits; Redundancy; Equivalence Checking

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APA (6th Edition):

Limaye, C. A. (2011). Formal Verification Techniques for Reversible Circuits. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/33406

Chicago Manual of Style (16th Edition):

Limaye, Chinmay Avinash. “Formal Verification Techniques for Reversible Circuits.” 2011. Masters Thesis, Virginia Tech. Accessed March 04, 2021. http://hdl.handle.net/10919/33406.

MLA Handbook (7th Edition):

Limaye, Chinmay Avinash. “Formal Verification Techniques for Reversible Circuits.” 2011. Web. 04 Mar 2021.

Vancouver:

Limaye CA. Formal Verification Techniques for Reversible Circuits. [Internet] [Masters thesis]. Virginia Tech; 2011. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/10919/33406.

Council of Science Editors:

Limaye CA. Formal Verification Techniques for Reversible Circuits. [Masters Thesis]. Virginia Tech; 2011. Available from: http://hdl.handle.net/10919/33406


Virginia Tech

13. Messaoud, Safa. Translating Discrete Time SIMULINK to SIGNAL.

Degree: MS, Computer Engineering, 2014, Virginia Tech

 As Cyber Physical Systems (CPS) are getting more complex and safety critical, Model Based Design (MBD), which consists of building formal models of a system… (more)

Subjects/Keywords: SIMULINK; SIGNAL; Embedded Software; Code Generation

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APA (6th Edition):

Messaoud, S. (2014). Translating Discrete Time SIMULINK to SIGNAL. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/49299

Chicago Manual of Style (16th Edition):

Messaoud, Safa. “Translating Discrete Time SIMULINK to SIGNAL.” 2014. Masters Thesis, Virginia Tech. Accessed March 04, 2021. http://hdl.handle.net/10919/49299.

MLA Handbook (7th Edition):

Messaoud, Safa. “Translating Discrete Time SIMULINK to SIGNAL.” 2014. Web. 04 Mar 2021.

Vancouver:

Messaoud S. Translating Discrete Time SIMULINK to SIGNAL. [Internet] [Masters thesis]. Virginia Tech; 2014. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/10919/49299.

Council of Science Editors:

Messaoud S. Translating Discrete Time SIMULINK to SIGNAL. [Masters Thesis]. Virginia Tech; 2014. Available from: http://hdl.handle.net/10919/49299


Virginia Tech

14. Hu, Wei. Sufficiency-based Filtering of Invariants for Sequential Equivalence Checking.

Degree: MS, Electrical and Computer Engineering, 2011, Virginia Tech

 Verification, as opposed to Testing and Post-Silicon Validation, is a critical step for Integrated Circuits (IC) Design, answering the question â Are we designing the… (more)

Subjects/Keywords: Invariant filtering; Assume and Verify; Boolean Satisfiability(SAT); Sequential Equivalence Checking(SEC)

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APA (6th Edition):

Hu, W. (2011). Sufficiency-based Filtering of Invariants for Sequential Equivalence Checking. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/31121

Chicago Manual of Style (16th Edition):

Hu, Wei. “Sufficiency-based Filtering of Invariants for Sequential Equivalence Checking.” 2011. Masters Thesis, Virginia Tech. Accessed March 04, 2021. http://hdl.handle.net/10919/31121.

MLA Handbook (7th Edition):

Hu, Wei. “Sufficiency-based Filtering of Invariants for Sequential Equivalence Checking.” 2011. Web. 04 Mar 2021.

Vancouver:

Hu W. Sufficiency-based Filtering of Invariants for Sequential Equivalence Checking. [Internet] [Masters thesis]. Virginia Tech; 2011. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/10919/31121.

Council of Science Editors:

Hu W. Sufficiency-based Filtering of Invariants for Sequential Equivalence Checking. [Masters Thesis]. Virginia Tech; 2011. Available from: http://hdl.handle.net/10919/31121


Virginia Tech

15. Hanle, Donald. Fast Discovery of Illegal State Cubes for Sequential Equivalence Checking.

Degree: MS, Electrical and Computer Engineering, 2011, Virginia Tech

 Sequential Equivalence checking has been and still is a challenging problem. Verifying two circuits that are structurally different but logically the same is very important… (more)

Subjects/Keywords: BDD; Illegal States; SEC

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APA (6th Edition):

Hanle, D. (2011). Fast Discovery of Illegal State Cubes for Sequential Equivalence Checking. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/32461

Chicago Manual of Style (16th Edition):

Hanle, Donald. “Fast Discovery of Illegal State Cubes for Sequential Equivalence Checking.” 2011. Masters Thesis, Virginia Tech. Accessed March 04, 2021. http://hdl.handle.net/10919/32461.

MLA Handbook (7th Edition):

Hanle, Donald. “Fast Discovery of Illegal State Cubes for Sequential Equivalence Checking.” 2011. Web. 04 Mar 2021.

Vancouver:

Hanle D. Fast Discovery of Illegal State Cubes for Sequential Equivalence Checking. [Internet] [Masters thesis]. Virginia Tech; 2011. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/10919/32461.

Council of Science Editors:

Hanle D. Fast Discovery of Illegal State Cubes for Sequential Equivalence Checking. [Masters Thesis]. Virginia Tech; 2011. Available from: http://hdl.handle.net/10919/32461


Virginia Tech

16. Pandit, Shuchi. Novel Architectures for Trace Buffer Design to facilitate Post-Silicon Validation and Test.

Degree: MS, Computer Engineering, 2014, Virginia Tech

 Post-Silicon validation is playing an increasingly important role as more chips are failing in the functional mode due to either manufacturing defects escaped during scan-based… (more)

Subjects/Keywords: Trace Buffer Architecture; Signal Restoration; Invariants

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APA (6th Edition):

Pandit, S. (2014). Novel Architectures for Trace Buffer Design to facilitate Post-Silicon Validation and Test. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/49151

Chicago Manual of Style (16th Edition):

Pandit, Shuchi. “Novel Architectures for Trace Buffer Design to facilitate Post-Silicon Validation and Test.” 2014. Masters Thesis, Virginia Tech. Accessed March 04, 2021. http://hdl.handle.net/10919/49151.

MLA Handbook (7th Edition):

Pandit, Shuchi. “Novel Architectures for Trace Buffer Design to facilitate Post-Silicon Validation and Test.” 2014. Web. 04 Mar 2021.

Vancouver:

Pandit S. Novel Architectures for Trace Buffer Design to facilitate Post-Silicon Validation and Test. [Internet] [Masters thesis]. Virginia Tech; 2014. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/10919/49151.

Council of Science Editors:

Pandit S. Novel Architectures for Trace Buffer Design to facilitate Post-Silicon Validation and Test. [Masters Thesis]. Virginia Tech; 2014. Available from: http://hdl.handle.net/10919/49151


Virginia Tech

17. Gulcan, Ege. Flexible and Lightweight Cryptographic Engines for Constrained Systems.

Degree: MS, Computer Engineering, 2015, Virginia Tech

 There is a significant effort in building lightweight cryptographic operations, yet the proposed solutions are typically single purpose modules that can only provide a fixed… (more)

Subjects/Keywords: Lightweight Cryptography; Block Ciphers; Flexible Architectures; SIMON; FPGA

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APA (6th Edition):

Gulcan, E. (2015). Flexible and Lightweight Cryptographic Engines for Constrained Systems. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/52913

Chicago Manual of Style (16th Edition):

Gulcan, Ege. “Flexible and Lightweight Cryptographic Engines for Constrained Systems.” 2015. Masters Thesis, Virginia Tech. Accessed March 04, 2021. http://hdl.handle.net/10919/52913.

MLA Handbook (7th Edition):

Gulcan, Ege. “Flexible and Lightweight Cryptographic Engines for Constrained Systems.” 2015. Web. 04 Mar 2021.

Vancouver:

Gulcan E. Flexible and Lightweight Cryptographic Engines for Constrained Systems. [Internet] [Masters thesis]. Virginia Tech; 2015. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/10919/52913.

Council of Science Editors:

Gulcan E. Flexible and Lightweight Cryptographic Engines for Constrained Systems. [Masters Thesis]. Virginia Tech; 2015. Available from: http://hdl.handle.net/10919/52913


Virginia Tech

18. Pabbuleti, Krishna Chaitanya. Performance Optimization of Public Key Cryptography on Embedded Platforms.

Degree: MS, Computer Engineering, 2014, Virginia Tech

 Embedded systems are so ubiquitous that they account for almost 90% of all the computing devices. They range from very small scale devices with an… (more)

Subjects/Keywords: Elliptic Curve Cryptography; Modular Arithmetic; SIMD; Hash-based Signatures; MSP430; Wireless Sensor Node

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APA (6th Edition):

Pabbuleti, K. C. (2014). Performance Optimization of Public Key Cryptography on Embedded Platforms. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/48120

Chicago Manual of Style (16th Edition):

Pabbuleti, Krishna Chaitanya. “Performance Optimization of Public Key Cryptography on Embedded Platforms.” 2014. Masters Thesis, Virginia Tech. Accessed March 04, 2021. http://hdl.handle.net/10919/48120.

MLA Handbook (7th Edition):

Pabbuleti, Krishna Chaitanya. “Performance Optimization of Public Key Cryptography on Embedded Platforms.” 2014. Web. 04 Mar 2021.

Vancouver:

Pabbuleti KC. Performance Optimization of Public Key Cryptography on Embedded Platforms. [Internet] [Masters thesis]. Virginia Tech; 2014. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/10919/48120.

Council of Science Editors:

Pabbuleti KC. Performance Optimization of Public Key Cryptography on Embedded Platforms. [Masters Thesis]. Virginia Tech; 2014. Available from: http://hdl.handle.net/10919/48120


Virginia Tech

19. Duong, Khanh Viet. On Enhancing Deterministic Sequential ATPG.

Degree: MS, Electrical and Computer Engineering, 2011, Virginia Tech

 This thesis presents four different techniques for improving the average-case performance of deterministic sequential circuit Automatic Test Patterns Generators (ATPG). Three techniques make use of… (more)

Subjects/Keywords: Automatic Test Pattern Generation; Logic Testing; Sequential Circuits

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APA (6th Edition):

Duong, K. V. (2011). On Enhancing Deterministic Sequential ATPG. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/31283

Chicago Manual of Style (16th Edition):

Duong, Khanh Viet. “On Enhancing Deterministic Sequential ATPG.” 2011. Masters Thesis, Virginia Tech. Accessed March 04, 2021. http://hdl.handle.net/10919/31283.

MLA Handbook (7th Edition):

Duong, Khanh Viet. “On Enhancing Deterministic Sequential ATPG.” 2011. Web. 04 Mar 2021.

Vancouver:

Duong KV. On Enhancing Deterministic Sequential ATPG. [Internet] [Masters thesis]. Virginia Tech; 2011. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/10919/31283.

Council of Science Editors:

Duong KV. On Enhancing Deterministic Sequential ATPG. [Masters Thesis]. Virginia Tech; 2011. Available from: http://hdl.handle.net/10919/31283


Virginia Tech

20. Sinha, Ambuj Sudhir. Design Techniques for Side-channel Resistant Embedded Software.

Degree: MS, Electrical and Computer Engineering, 2011, Virginia Tech

 Side Channel Attacks (SCA) are a class of passive attacks on cryptosystems that exploit implementation characteristics of the system. Currently, a lot of research is… (more)

Subjects/Keywords: Bitslice Cryptography; Side Channel Attacks; Virtual Secure Circuit; Secure Embedded Systems; Side-channel Countermeasures

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APA (6th Edition):

Sinha, A. S. (2011). Design Techniques for Side-channel Resistant Embedded Software. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/34465

Chicago Manual of Style (16th Edition):

Sinha, Ambuj Sudhir. “Design Techniques for Side-channel Resistant Embedded Software.” 2011. Masters Thesis, Virginia Tech. Accessed March 04, 2021. http://hdl.handle.net/10919/34465.

MLA Handbook (7th Edition):

Sinha, Ambuj Sudhir. “Design Techniques for Side-channel Resistant Embedded Software.” 2011. Web. 04 Mar 2021.

Vancouver:

Sinha AS. Design Techniques for Side-channel Resistant Embedded Software. [Internet] [Masters thesis]. Virginia Tech; 2011. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/10919/34465.

Council of Science Editors:

Sinha AS. Design Techniques for Side-channel Resistant Embedded Software. [Masters Thesis]. Virginia Tech; 2011. Available from: http://hdl.handle.net/10919/34465


Virginia Tech

21. Prabhu, Sarvesh P. An Efficient 2-Phase Strategy to Achieve High Branch Coverage.

Degree: MS, Electrical and Computer Engineering, 2012, Virginia Tech

 Symbolic execution-based test generation is gaining popularity for software test generation. The increasing complexity of the software program is posing new challenges in software execution-based… (more)

Subjects/Keywords: Branch Coverage; Conflict-driven Learning; Symbolic Execution; Software Testing

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APA (6th Edition):

Prabhu, S. P. (2012). An Efficient 2-Phase Strategy to Achieve High Branch Coverage. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/40931

Chicago Manual of Style (16th Edition):

Prabhu, Sarvesh P. “An Efficient 2-Phase Strategy to Achieve High Branch Coverage.” 2012. Masters Thesis, Virginia Tech. Accessed March 04, 2021. http://hdl.handle.net/10919/40931.

MLA Handbook (7th Edition):

Prabhu, Sarvesh P. “An Efficient 2-Phase Strategy to Achieve High Branch Coverage.” 2012. Web. 04 Mar 2021.

Vancouver:

Prabhu SP. An Efficient 2-Phase Strategy to Achieve High Branch Coverage. [Internet] [Masters thesis]. Virginia Tech; 2012. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/10919/40931.

Council of Science Editors:

Prabhu SP. An Efficient 2-Phase Strategy to Achieve High Branch Coverage. [Masters Thesis]. Virginia Tech; 2012. Available from: http://hdl.handle.net/10919/40931


Virginia Tech

22. Moudgil, Rashmi. A Statistical and Circuit Based Technique for Counterfeit Detection in Existing ICs.

Degree: MS, Computer Engineering, 2013, Virginia Tech

 Counterfeit Integrated Circuits (ICs) are previously used ICs that are resold as new. They have become a serious problem in modern electronic devices. They cause… (more)

Subjects/Keywords: Counterfeits; Aging; Process Variation

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APA (6th Edition):

Moudgil, R. (2013). A Statistical and Circuit Based Technique for Counterfeit Detection in Existing ICs. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/23177

Chicago Manual of Style (16th Edition):

Moudgil, Rashmi. “A Statistical and Circuit Based Technique for Counterfeit Detection in Existing ICs.” 2013. Masters Thesis, Virginia Tech. Accessed March 04, 2021. http://hdl.handle.net/10919/23177.

MLA Handbook (7th Edition):

Moudgil, Rashmi. “A Statistical and Circuit Based Technique for Counterfeit Detection in Existing ICs.” 2013. Web. 04 Mar 2021.

Vancouver:

Moudgil R. A Statistical and Circuit Based Technique for Counterfeit Detection in Existing ICs. [Internet] [Masters thesis]. Virginia Tech; 2013. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/10919/23177.

Council of Science Editors:

Moudgil R. A Statistical and Circuit Based Technique for Counterfeit Detection in Existing ICs. [Masters Thesis]. Virginia Tech; 2013. Available from: http://hdl.handle.net/10919/23177


Virginia Tech

23. Munagani, Indira Priya Darshini. Mining Rare Features in Fingerprints using Core points and Triplet-based Features.

Degree: MS, Computer Engineering, 2014, Virginia Tech

 A fingerprint matching algorithm with a novel set of matching parameters based on core points and triangular descriptors is proposed to discover rarity in fingerprints.… (more)

Subjects/Keywords: Fingerprints; Rare Features; Rarity; Latent; Core Points; Triplets; GPU

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APA (6th Edition):

Munagani, I. P. D. (2014). Mining Rare Features in Fingerprints using Core points and Triplet-based Features. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/24784

Chicago Manual of Style (16th Edition):

Munagani, Indira Priya Darshini. “Mining Rare Features in Fingerprints using Core points and Triplet-based Features.” 2014. Masters Thesis, Virginia Tech. Accessed March 04, 2021. http://hdl.handle.net/10919/24784.

MLA Handbook (7th Edition):

Munagani, Indira Priya Darshini. “Mining Rare Features in Fingerprints using Core points and Triplet-based Features.” 2014. Web. 04 Mar 2021.

Vancouver:

Munagani IPD. Mining Rare Features in Fingerprints using Core points and Triplet-based Features. [Internet] [Masters thesis]. Virginia Tech; 2014. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/10919/24784.

Council of Science Editors:

Munagani IPD. Mining Rare Features in Fingerprints using Core points and Triplet-based Features. [Masters Thesis]. Virginia Tech; 2014. Available from: http://hdl.handle.net/10919/24784


Virginia Tech

24. Xu, Hao. Safety of Self-driving Cars: A Case Study on Lane Keeping Systems.

Degree: MS, Computer Engineering, 2020, Virginia Tech

 Self-driving cars is a hot topic nowadays. Machine learning is a popular method to achieve self-driving cars. Machine learning constructs a neural network, which imitates… (more)

Subjects/Keywords: Self-driving; Neural Network; Lane Detection; Specification; Enforcement; Delay; Prediction.

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APA (6th Edition):

Xu, H. (2020). Safety of Self-driving Cars: A Case Study on Lane Keeping Systems. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/99292

Chicago Manual of Style (16th Edition):

Xu, Hao. “Safety of Self-driving Cars: A Case Study on Lane Keeping Systems.” 2020. Masters Thesis, Virginia Tech. Accessed March 04, 2021. http://hdl.handle.net/10919/99292.

MLA Handbook (7th Edition):

Xu, Hao. “Safety of Self-driving Cars: A Case Study on Lane Keeping Systems.” 2020. Web. 04 Mar 2021.

Vancouver:

Xu H. Safety of Self-driving Cars: A Case Study on Lane Keeping Systems. [Internet] [Masters thesis]. Virginia Tech; 2020. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/10919/99292.

Council of Science Editors:

Xu H. Safety of Self-driving Cars: A Case Study on Lane Keeping Systems. [Masters Thesis]. Virginia Tech; 2020. Available from: http://hdl.handle.net/10919/99292


Virginia Tech

25. Kakusa, Takondwa Lisungu. Use of Assembly Inspired Instructions in the Allowance of Natural Language Processing in ROS.

Degree: MS, Computer Engineering, 2018, Virginia Tech

 Natural Language processing is a growing field and widely used in both industrial and and commercial cases. Though it is difficult to create a natural… (more)

Subjects/Keywords: Natural Language Processing; Robotics; ROS

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APA (6th Edition):

Kakusa, T. L. (2018). Use of Assembly Inspired Instructions in the Allowance of Natural Language Processing in ROS. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/84521

Chicago Manual of Style (16th Edition):

Kakusa, Takondwa Lisungu. “Use of Assembly Inspired Instructions in the Allowance of Natural Language Processing in ROS.” 2018. Masters Thesis, Virginia Tech. Accessed March 04, 2021. http://hdl.handle.net/10919/84521.

MLA Handbook (7th Edition):

Kakusa, Takondwa Lisungu. “Use of Assembly Inspired Instructions in the Allowance of Natural Language Processing in ROS.” 2018. Web. 04 Mar 2021.

Vancouver:

Kakusa TL. Use of Assembly Inspired Instructions in the Allowance of Natural Language Processing in ROS. [Internet] [Masters thesis]. Virginia Tech; 2018. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/10919/84521.

Council of Science Editors:

Kakusa TL. Use of Assembly Inspired Instructions in the Allowance of Natural Language Processing in ROS. [Masters Thesis]. Virginia Tech; 2018. Available from: http://hdl.handle.net/10919/84521


Virginia Tech

26. Khoshnood, Sepideh. Constraint Solving for Diagnosing Concurrency Bugs.

Degree: MS, Computer Engineering, 2015, Virginia Tech

 Programmers often have to spend a significant amount of time inspecting the software code and execution traces to identify the root cause of a software… (more)

Subjects/Keywords: Concurrency; Bug Localization; Bounded Model Checking; MAX-SAT

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APA (6th Edition):

Khoshnood, S. (2015). Constraint Solving for Diagnosing Concurrency Bugs. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/52784

Chicago Manual of Style (16th Edition):

Khoshnood, Sepideh. “Constraint Solving for Diagnosing Concurrency Bugs.” 2015. Masters Thesis, Virginia Tech. Accessed March 04, 2021. http://hdl.handle.net/10919/52784.

MLA Handbook (7th Edition):

Khoshnood, Sepideh. “Constraint Solving for Diagnosing Concurrency Bugs.” 2015. Web. 04 Mar 2021.

Vancouver:

Khoshnood S. Constraint Solving for Diagnosing Concurrency Bugs. [Internet] [Masters thesis]. Virginia Tech; 2015. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/10919/52784.

Council of Science Editors:

Khoshnood S. Constraint Solving for Diagnosing Concurrency Bugs. [Masters Thesis]. Virginia Tech; 2015. Available from: http://hdl.handle.net/10919/52784


Virginia Tech

27. Varadarajan, Aravind Krishnan. Improving Bio-Inspired Frameworks.

Degree: MS, Computer Engineering, 2018, Virginia Tech

 In this thesis, we provide solutions to two different bio-inspired algorithms. The first is enhancing the performance of bio-inspired test generation for circuits described in… (more)

Subjects/Keywords: RTL; GPU; Neural Nets; Relaibility; Performance; Branch Coverage; Test Generation; Genetic Algorithm; CUDA

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APA (6th Edition):

Varadarajan, A. K. (2018). Improving Bio-Inspired Frameworks. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/97506

Chicago Manual of Style (16th Edition):

Varadarajan, Aravind Krishnan. “Improving Bio-Inspired Frameworks.” 2018. Masters Thesis, Virginia Tech. Accessed March 04, 2021. http://hdl.handle.net/10919/97506.

MLA Handbook (7th Edition):

Varadarajan, Aravind Krishnan. “Improving Bio-Inspired Frameworks.” 2018. Web. 04 Mar 2021.

Vancouver:

Varadarajan AK. Improving Bio-Inspired Frameworks. [Internet] [Masters thesis]. Virginia Tech; 2018. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/10919/97506.

Council of Science Editors:

Varadarajan AK. Improving Bio-Inspired Frameworks. [Masters Thesis]. Virginia Tech; 2018. Available from: http://hdl.handle.net/10919/97506


Virginia Tech

28. Bansal, Kunal. Increasing Branch Coverage with Dual Metric RTL Test Generation.

Degree: MS, Computer Engineering, 2018, Virginia Tech

 In this thesis, we present a new register-transfer level (RTL) test generation method that makes use of two coverage metrics, Branch Coverage, and Mutation Coverage… (more)

Subjects/Keywords: Branch; Mutation; Coverage; Metric; RTL

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APA (6th Edition):

Bansal, K. (2018). Increasing Branch Coverage with Dual Metric RTL Test Generation. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/96581

Chicago Manual of Style (16th Edition):

Bansal, Kunal. “Increasing Branch Coverage with Dual Metric RTL Test Generation.” 2018. Masters Thesis, Virginia Tech. Accessed March 04, 2021. http://hdl.handle.net/10919/96581.

MLA Handbook (7th Edition):

Bansal, Kunal. “Increasing Branch Coverage with Dual Metric RTL Test Generation.” 2018. Web. 04 Mar 2021.

Vancouver:

Bansal K. Increasing Branch Coverage with Dual Metric RTL Test Generation. [Internet] [Masters thesis]. Virginia Tech; 2018. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/10919/96581.

Council of Science Editors:

Bansal K. Increasing Branch Coverage with Dual Metric RTL Test Generation. [Masters Thesis]. Virginia Tech; 2018. Available from: http://hdl.handle.net/10919/96581


Virginia Tech

29. Kiaei, Pantea. Architecture Support for Countermeasures against Side-Channel Analysis and Fault Attack.

Degree: MS, Computer Engineering, 2019, Virginia Tech

 Ciphers are algorithms designed by mathematicians. They protect data by encrypting them. In one of the main categories of these ciphers, called symmetric-key ciphers, a… (more)

Subjects/Keywords: Side-channel attacks; Fault attacks; Custom-instruction extensions; Bitslicing; Software countermeasures

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APA (6th Edition):

Kiaei, P. (2019). Architecture Support for Countermeasures against Side-Channel Analysis and Fault Attack. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/93537

Chicago Manual of Style (16th Edition):

Kiaei, Pantea. “Architecture Support for Countermeasures against Side-Channel Analysis and Fault Attack.” 2019. Masters Thesis, Virginia Tech. Accessed March 04, 2021. http://hdl.handle.net/10919/93537.

MLA Handbook (7th Edition):

Kiaei, Pantea. “Architecture Support for Countermeasures against Side-Channel Analysis and Fault Attack.” 2019. Web. 04 Mar 2021.

Vancouver:

Kiaei P. Architecture Support for Countermeasures against Side-Channel Analysis and Fault Attack. [Internet] [Masters thesis]. Virginia Tech; 2019. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/10919/93537.

Council of Science Editors:

Kiaei P. Architecture Support for Countermeasures against Side-Channel Analysis and Fault Attack. [Masters Thesis]. Virginia Tech; 2019. Available from: http://hdl.handle.net/10919/93537


Virginia Tech

30. Quesenberry, Joshua Daniel. Communication Synthesis for MIMO Decoder Matrices.

Degree: MS, Electrical and Computer Engineering, 2011, Virginia Tech

 The design in this work provides an easy and cost-efficient way of performing an FPGA implementation of a specific algorithm through use of a custom… (more)

Subjects/Keywords: Communication Synthesis; MIMO; FPGA; Xilinx

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APA (6th Edition):

Quesenberry, J. D. (2011). Communication Synthesis for MIMO Decoder Matrices. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/51149

Chicago Manual of Style (16th Edition):

Quesenberry, Joshua Daniel. “Communication Synthesis for MIMO Decoder Matrices.” 2011. Masters Thesis, Virginia Tech. Accessed March 04, 2021. http://hdl.handle.net/10919/51149.

MLA Handbook (7th Edition):

Quesenberry, Joshua Daniel. “Communication Synthesis for MIMO Decoder Matrices.” 2011. Web. 04 Mar 2021.

Vancouver:

Quesenberry JD. Communication Synthesis for MIMO Decoder Matrices. [Internet] [Masters thesis]. Virginia Tech; 2011. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/10919/51149.

Council of Science Editors:

Quesenberry JD. Communication Synthesis for MIMO Decoder Matrices. [Masters Thesis]. Virginia Tech; 2011. Available from: http://hdl.handle.net/10919/51149

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