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You searched for +publisher:"Virginia Tech" +contributor:("Athanas, Peter M."). Showing records 1 – 30 of 162 total matches.

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Virginia Tech

1. Irick, Charles Robert. Enhancing GNU Radio for Hardware Accelerated Radio Design.

Degree: MS, Electrical and Computer Engineering, 2010, Virginia Tech

 As technology evolves and new methods for designing radios arise, it becomes necessary to continue the search for fast and flexible development environments. Some of… (more)

Subjects/Keywords: Virtex-5; FPGA; GNU Radio; SDR

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APA (6th Edition):

Irick, C. R. (2010). Enhancing GNU Radio for Hardware Accelerated Radio Design. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/33474

Chicago Manual of Style (16th Edition):

Irick, Charles Robert. “Enhancing GNU Radio for Hardware Accelerated Radio Design.” 2010. Masters Thesis, Virginia Tech. Accessed July 07, 2020. http://hdl.handle.net/10919/33474.

MLA Handbook (7th Edition):

Irick, Charles Robert. “Enhancing GNU Radio for Hardware Accelerated Radio Design.” 2010. Web. 07 Jul 2020.

Vancouver:

Irick CR. Enhancing GNU Radio for Hardware Accelerated Radio Design. [Internet] [Masters thesis]. Virginia Tech; 2010. [cited 2020 Jul 07]. Available from: http://hdl.handle.net/10919/33474.

Council of Science Editors:

Irick CR. Enhancing GNU Radio for Hardware Accelerated Radio Design. [Masters Thesis]. Virginia Tech; 2010. Available from: http://hdl.handle.net/10919/33474


Virginia Tech

2. Tavaragiri, Abhay. A Management Paradigm for FPGA Design Flow Acceleration.

Degree: MS, Electrical and Computer Engineering, 2011, Virginia Tech

 Advances in FPGA density and complexity have not been matched by a corresponding improvement in the performance of the implementation tools. Knowledge of incremental changes… (more)

Subjects/Keywords: FPGA Management Technique; XML; Productivity; TORC

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APA (6th Edition):

Tavaragiri, A. (2011). A Management Paradigm for FPGA Design Flow Acceleration. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/33923

Chicago Manual of Style (16th Edition):

Tavaragiri, Abhay. “A Management Paradigm for FPGA Design Flow Acceleration.” 2011. Masters Thesis, Virginia Tech. Accessed July 07, 2020. http://hdl.handle.net/10919/33923.

MLA Handbook (7th Edition):

Tavaragiri, Abhay. “A Management Paradigm for FPGA Design Flow Acceleration.” 2011. Web. 07 Jul 2020.

Vancouver:

Tavaragiri A. A Management Paradigm for FPGA Design Flow Acceleration. [Internet] [Masters thesis]. Virginia Tech; 2011. [cited 2020 Jul 07]. Available from: http://hdl.handle.net/10919/33923.

Council of Science Editors:

Tavaragiri A. A Management Paradigm for FPGA Design Flow Acceleration. [Masters Thesis]. Virginia Tech; 2011. Available from: http://hdl.handle.net/10919/33923


Virginia Tech

3. Jeong, Jeong-O. Hybrid FPGA and GPP Implementation of IEEE 802.15.4 Physical Layer.

Degree: MS, Electrical and Computer Engineering, 2012, Virginia Tech

 In this thesis, two different cases of hybrid IEEE 802.15.4 PHY (Physical Layer) implementation are explored. The first case is an FPGA implementation of IEEE… (more)

Subjects/Keywords: Software Defined Radio; FPGA; ZigBee; IEEE 802.15.4; USRP N210

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APA (6th Edition):

Jeong, J. (2012). Hybrid FPGA and GPP Implementation of IEEE 802.15.4 Physical Layer. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/34425

Chicago Manual of Style (16th Edition):

Jeong, Jeong-O. “Hybrid FPGA and GPP Implementation of IEEE 802.15.4 Physical Layer.” 2012. Masters Thesis, Virginia Tech. Accessed July 07, 2020. http://hdl.handle.net/10919/34425.

MLA Handbook (7th Edition):

Jeong, Jeong-O. “Hybrid FPGA and GPP Implementation of IEEE 802.15.4 Physical Layer.” 2012. Web. 07 Jul 2020.

Vancouver:

Jeong J. Hybrid FPGA and GPP Implementation of IEEE 802.15.4 Physical Layer. [Internet] [Masters thesis]. Virginia Tech; 2012. [cited 2020 Jul 07]. Available from: http://hdl.handle.net/10919/34425.

Council of Science Editors:

Jeong J. Hybrid FPGA and GPP Implementation of IEEE 802.15.4 Physical Layer. [Masters Thesis]. Virginia Tech; 2012. Available from: http://hdl.handle.net/10919/34425


Virginia Tech

4. Stroop, Richard Henry Lee. Enhancing GNU Radio for Run-Time Assembly of FPGA-Based Accelerators.

Degree: MS, Electrical and Computer Engineering, 2012, Virginia Tech

 Software defined radios (SDRs) have changed the paradigm of slowly designing custom ra- dios, instead allowing designers to quickly iterate designs with a large range… (more)

Subjects/Keywords: FPGA; SDR; qFlow; GNU Radio

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APA (6th Edition):

Stroop, R. H. L. (2012). Enhancing GNU Radio for Run-Time Assembly of FPGA-Based Accelerators. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/34426

Chicago Manual of Style (16th Edition):

Stroop, Richard Henry Lee. “Enhancing GNU Radio for Run-Time Assembly of FPGA-Based Accelerators.” 2012. Masters Thesis, Virginia Tech. Accessed July 07, 2020. http://hdl.handle.net/10919/34426.

MLA Handbook (7th Edition):

Stroop, Richard Henry Lee. “Enhancing GNU Radio for Run-Time Assembly of FPGA-Based Accelerators.” 2012. Web. 07 Jul 2020.

Vancouver:

Stroop RHL. Enhancing GNU Radio for Run-Time Assembly of FPGA-Based Accelerators. [Internet] [Masters thesis]. Virginia Tech; 2012. [cited 2020 Jul 07]. Available from: http://hdl.handle.net/10919/34426.

Council of Science Editors:

Stroop RHL. Enhancing GNU Radio for Run-Time Assembly of FPGA-Based Accelerators. [Masters Thesis]. Virginia Tech; 2012. Available from: http://hdl.handle.net/10919/34426


Virginia Tech

5. Pimenta Pereira, Karl Savio. Characterization of FPGA-based High Performance Computers.

Degree: MS, Electrical and Computer Engineering, 2011, Virginia Tech

 As CPU clock frequencies plateau and the doubling of CPU cores per processor exacerbate the memory wall, hybrid core computing, utilizing CPUs augmented with FPGAs… (more)

Subjects/Keywords: FFT; molecular dynamics; integer-point; floating-point; GPU; HPC; FPGA

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APA (6th Edition):

Pimenta Pereira, K. S. (2011). Characterization of FPGA-based High Performance Computers. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/34483

Chicago Manual of Style (16th Edition):

Pimenta Pereira, Karl Savio. “Characterization of FPGA-based High Performance Computers.” 2011. Masters Thesis, Virginia Tech. Accessed July 07, 2020. http://hdl.handle.net/10919/34483.

MLA Handbook (7th Edition):

Pimenta Pereira, Karl Savio. “Characterization of FPGA-based High Performance Computers.” 2011. Web. 07 Jul 2020.

Vancouver:

Pimenta Pereira KS. Characterization of FPGA-based High Performance Computers. [Internet] [Masters thesis]. Virginia Tech; 2011. [cited 2020 Jul 07]. Available from: http://hdl.handle.net/10919/34483.

Council of Science Editors:

Pimenta Pereira KS. Characterization of FPGA-based High Performance Computers. [Masters Thesis]. Virginia Tech; 2011. Available from: http://hdl.handle.net/10919/34483


Virginia Tech

6. Chandrasekharan, Athira. Accelerating Incremental Floorplanning of Partially Reconfigurable Designs to Improve FPGA Productivity.

Degree: MS, Electrical and Computer Engineering, 2010, Virginia Tech

 FPGA implementation tool turnaround time has unfortunately not kept pace with FPGA density advances. It is difficult to parallelize place-and-route algorithms without sacrificing determinism or… (more)

Subjects/Keywords: Reconfigurable Computing; Incremental Floorplanning; FPGAs

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APA (6th Edition):

Chandrasekharan, A. (2010). Accelerating Incremental Floorplanning of Partially Reconfigurable Designs to Improve FPGA Productivity. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/34499

Chicago Manual of Style (16th Edition):

Chandrasekharan, Athira. “Accelerating Incremental Floorplanning of Partially Reconfigurable Designs to Improve FPGA Productivity.” 2010. Masters Thesis, Virginia Tech. Accessed July 07, 2020. http://hdl.handle.net/10919/34499.

MLA Handbook (7th Edition):

Chandrasekharan, Athira. “Accelerating Incremental Floorplanning of Partially Reconfigurable Designs to Improve FPGA Productivity.” 2010. Web. 07 Jul 2020.

Vancouver:

Chandrasekharan A. Accelerating Incremental Floorplanning of Partially Reconfigurable Designs to Improve FPGA Productivity. [Internet] [Masters thesis]. Virginia Tech; 2010. [cited 2020 Jul 07]. Available from: http://hdl.handle.net/10919/34499.

Council of Science Editors:

Chandrasekharan A. Accelerating Incremental Floorplanning of Partially Reconfigurable Designs to Improve FPGA Productivity. [Masters Thesis]. Virginia Tech; 2010. Available from: http://hdl.handle.net/10919/34499


Virginia Tech

7. Couch, Jacob Donald. Applications of TORC: An Open Toolkit for Reconfigurable Computing.

Degree: MS, Electrical and Computer Engineering, 2011, Virginia Tech

 Two research projects are proposed that rely on Tools for open Reconfigurable Computing (TORC) and the openness of the Xilinx tool chain. The first project,… (more)

Subjects/Keywords: Xilinx; TORC; qFlow; tFlow; Unconventional Transmitters; FPGA

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APA (6th Edition):

Couch, J. D. (2011). Applications of TORC: An Open Toolkit for Reconfigurable Computing. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/34624

Chicago Manual of Style (16th Edition):

Couch, Jacob Donald. “Applications of TORC: An Open Toolkit for Reconfigurable Computing.” 2011. Masters Thesis, Virginia Tech. Accessed July 07, 2020. http://hdl.handle.net/10919/34624.

MLA Handbook (7th Edition):

Couch, Jacob Donald. “Applications of TORC: An Open Toolkit for Reconfigurable Computing.” 2011. Web. 07 Jul 2020.

Vancouver:

Couch JD. Applications of TORC: An Open Toolkit for Reconfigurable Computing. [Internet] [Masters thesis]. Virginia Tech; 2011. [cited 2020 Jul 07]. Available from: http://hdl.handle.net/10919/34624.

Council of Science Editors:

Couch JD. Applications of TORC: An Open Toolkit for Reconfigurable Computing. [Masters Thesis]. Virginia Tech; 2011. Available from: http://hdl.handle.net/10919/34624


Virginia Tech

8. Shagrithaya, Kavya Subraya. Enabling Development of OpenCL Applications on FPGA platforms.

Degree: MS, Electrical and Computer Engineering, 2012, Virginia Tech

 FPGAs can potentially deliver tremendous acceleration in high-performance server and em- bedded computing applications. Whether used to augment a processor or as a stand-alone device,… (more)

Subjects/Keywords: FPGA; AutoESL; OpenCL; Convey; HPC

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APA (6th Edition):

Shagrithaya, K. S. (2012). Enabling Development of OpenCL Applications on FPGA platforms. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/34669

Chicago Manual of Style (16th Edition):

Shagrithaya, Kavya Subraya. “Enabling Development of OpenCL Applications on FPGA platforms.” 2012. Masters Thesis, Virginia Tech. Accessed July 07, 2020. http://hdl.handle.net/10919/34669.

MLA Handbook (7th Edition):

Shagrithaya, Kavya Subraya. “Enabling Development of OpenCL Applications on FPGA platforms.” 2012. Web. 07 Jul 2020.

Vancouver:

Shagrithaya KS. Enabling Development of OpenCL Applications on FPGA platforms. [Internet] [Masters thesis]. Virginia Tech; 2012. [cited 2020 Jul 07]. Available from: http://hdl.handle.net/10919/34669.

Council of Science Editors:

Shagrithaya KS. Enabling Development of OpenCL Applications on FPGA platforms. [Masters Thesis]. Virginia Tech; 2012. Available from: http://hdl.handle.net/10919/34669


Virginia Tech

9. Simmons, Jacob Ross. A self-contained motion capture platform for e-textiles.

Degree: MS, Electrical and Computer Engineering, 2010, Virginia Tech

 Wearable computers and e-textiles are increasingly prevalent in todayâ s society. Motion capture is one of many potential applications for on-body electronic systems. Self-contained motion… (more)

Subjects/Keywords: inertial measurement units; wearable computing; e-textiles

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APA (6th Edition):

Simmons, J. R. (2010). A self-contained motion capture platform for e-textiles. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/34772

Chicago Manual of Style (16th Edition):

Simmons, Jacob Ross. “A self-contained motion capture platform for e-textiles.” 2010. Masters Thesis, Virginia Tech. Accessed July 07, 2020. http://hdl.handle.net/10919/34772.

MLA Handbook (7th Edition):

Simmons, Jacob Ross. “A self-contained motion capture platform for e-textiles.” 2010. Web. 07 Jul 2020.

Vancouver:

Simmons JR. A self-contained motion capture platform for e-textiles. [Internet] [Masters thesis]. Virginia Tech; 2010. [cited 2020 Jul 07]. Available from: http://hdl.handle.net/10919/34772.

Council of Science Editors:

Simmons JR. A self-contained motion capture platform for e-textiles. [Masters Thesis]. Virginia Tech; 2010. Available from: http://hdl.handle.net/10919/34772


Virginia Tech

10. Morozov, Sergey Victorovich. Elliptic Curve Cryptography on Heterogeneous Multicore Platform.

Degree: MS, Electrical and Computer Engineering, 2010, Virginia Tech

 Elliptic curve cryptography (ECC) is becoming the algorithm of choice for digital signature generation and authentication in embedded context. However, performance of ECC and the… (more)

Subjects/Keywords: Binary Field; DSP; ARM; Cryptography; Elliptic Curve; Prime Field; Multiprocessor; Point Multiplication; Multicore

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APA (6th Edition):

Morozov, S. V. (2010). Elliptic Curve Cryptography on Heterogeneous Multicore Platform. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/34872

Chicago Manual of Style (16th Edition):

Morozov, Sergey Victorovich. “Elliptic Curve Cryptography on Heterogeneous Multicore Platform.” 2010. Masters Thesis, Virginia Tech. Accessed July 07, 2020. http://hdl.handle.net/10919/34872.

MLA Handbook (7th Edition):

Morozov, Sergey Victorovich. “Elliptic Curve Cryptography on Heterogeneous Multicore Platform.” 2010. Web. 07 Jul 2020.

Vancouver:

Morozov SV. Elliptic Curve Cryptography on Heterogeneous Multicore Platform. [Internet] [Masters thesis]. Virginia Tech; 2010. [cited 2020 Jul 07]. Available from: http://hdl.handle.net/10919/34872.

Council of Science Editors:

Morozov SV. Elliptic Curve Cryptography on Heterogeneous Multicore Platform. [Masters Thesis]. Virginia Tech; 2010. Available from: http://hdl.handle.net/10919/34872


Virginia Tech

11. Parekh, Umang Kumar. A Toolkit for Rapid FPGA System Deployment.

Degree: MS, Electrical and Computer Engineering, 2010, Virginia Tech

 FPGA implementation tools have not kept pace with growing FPGA density. It is common for non-trivial designs to take multiple hours to go through the… (more)

Subjects/Keywords: Router; Virtex-4; Toolkit; Autonomous; FPGA

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APA (6th Edition):

Parekh, U. K. (2010). A Toolkit for Rapid FPGA System Deployment. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/35703

Chicago Manual of Style (16th Edition):

Parekh, Umang Kumar. “A Toolkit for Rapid FPGA System Deployment.” 2010. Masters Thesis, Virginia Tech. Accessed July 07, 2020. http://hdl.handle.net/10919/35703.

MLA Handbook (7th Edition):

Parekh, Umang Kumar. “A Toolkit for Rapid FPGA System Deployment.” 2010. Web. 07 Jul 2020.

Vancouver:

Parekh UK. A Toolkit for Rapid FPGA System Deployment. [Internet] [Masters thesis]. Virginia Tech; 2010. [cited 2020 Jul 07]. Available from: http://hdl.handle.net/10919/35703.

Council of Science Editors:

Parekh UK. A Toolkit for Rapid FPGA System Deployment. [Masters Thesis]. Virginia Tech; 2010. Available from: http://hdl.handle.net/10919/35703


Virginia Tech

12. Shalf, John Marshall. Advanced System-Scale and Chip-Scale Interconnection Networks for Ultrascale Systems.

Degree: MS, Electrical and Computer Engineering, 2010, Virginia Tech

 The path towards realizing next-generation petascale and exascale computing is increasingly dependent on building supercomputers with unprecedented numbers of processors. Given the rise of multicore… (more)

Subjects/Keywords: energy efficiency; manycore; exascale; interconnects; NoC; photonics

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APA (6th Edition):

Shalf, J. M. (2010). Advanced System-Scale and Chip-Scale Interconnection Networks for Ultrascale Systems. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/36134

Chicago Manual of Style (16th Edition):

Shalf, John Marshall. “Advanced System-Scale and Chip-Scale Interconnection Networks for Ultrascale Systems.” 2010. Masters Thesis, Virginia Tech. Accessed July 07, 2020. http://hdl.handle.net/10919/36134.

MLA Handbook (7th Edition):

Shalf, John Marshall. “Advanced System-Scale and Chip-Scale Interconnection Networks for Ultrascale Systems.” 2010. Web. 07 Jul 2020.

Vancouver:

Shalf JM. Advanced System-Scale and Chip-Scale Interconnection Networks for Ultrascale Systems. [Internet] [Masters thesis]. Virginia Tech; 2010. [cited 2020 Jul 07]. Available from: http://hdl.handle.net/10919/36134.

Council of Science Editors:

Shalf JM. Advanced System-Scale and Chip-Scale Interconnection Networks for Ultrascale Systems. [Masters Thesis]. Virginia Tech; 2010. Available from: http://hdl.handle.net/10919/36134


Virginia Tech

13. Bhardwaj, Prabhaav. Framework for Hardware Agility on FPGAs.

Degree: MS, Electrical and Computer Engineering, 2010, Virginia Tech

 As hardware applications become increasingly complex, the supporting technology needs to evolve and adapt to the demands. Field Programmable Gate Array (FPGA), Application Specific Integrated… (more)

Subjects/Keywords: Virtex 5; Dynamic Routing; FPGA; Reconfigurable Computing

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APA (6th Edition):

Bhardwaj, P. (2010). Framework for Hardware Agility on FPGAs. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/36347

Chicago Manual of Style (16th Edition):

Bhardwaj, Prabhaav. “Framework for Hardware Agility on FPGAs.” 2010. Masters Thesis, Virginia Tech. Accessed July 07, 2020. http://hdl.handle.net/10919/36347.

MLA Handbook (7th Edition):

Bhardwaj, Prabhaav. “Framework for Hardware Agility on FPGAs.” 2010. Web. 07 Jul 2020.

Vancouver:

Bhardwaj P. Framework for Hardware Agility on FPGAs. [Internet] [Masters thesis]. Virginia Tech; 2010. [cited 2020 Jul 07]. Available from: http://hdl.handle.net/10919/36347.

Council of Science Editors:

Bhardwaj P. Framework for Hardware Agility on FPGAs. [Masters Thesis]. Virginia Tech; 2010. Available from: http://hdl.handle.net/10919/36347


Virginia Tech

14. Sohanghpurwala, Ali Asgar Ali Akbar. OpenPR: An Open-Source Partial Reconfiguration Tool-Kit for Xilinx FPGAs.

Degree: MS, Electrical and Computer Engineering, 2010, Virginia Tech

 The Xilinx Partial Reconfiguration tool kits have been instrumental for performing a wide variety of research on Xilinx FPGAs. These tool kits provide a methodology… (more)

Subjects/Keywords: open-source; FPGA; partial-reconfiguration

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APA (6th Edition):

Sohanghpurwala, A. A. A. A. (2010). OpenPR: An Open-Source Partial Reconfiguration Tool-Kit for Xilinx FPGAs. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/36348

Chicago Manual of Style (16th Edition):

Sohanghpurwala, Ali Asgar Ali Akbar. “OpenPR: An Open-Source Partial Reconfiguration Tool-Kit for Xilinx FPGAs.” 2010. Masters Thesis, Virginia Tech. Accessed July 07, 2020. http://hdl.handle.net/10919/36348.

MLA Handbook (7th Edition):

Sohanghpurwala, Ali Asgar Ali Akbar. “OpenPR: An Open-Source Partial Reconfiguration Tool-Kit for Xilinx FPGAs.” 2010. Web. 07 Jul 2020.

Vancouver:

Sohanghpurwala AAAA. OpenPR: An Open-Source Partial Reconfiguration Tool-Kit for Xilinx FPGAs. [Internet] [Masters thesis]. Virginia Tech; 2010. [cited 2020 Jul 07]. Available from: http://hdl.handle.net/10919/36348.

Council of Science Editors:

Sohanghpurwala AAAA. OpenPR: An Open-Source Partial Reconfiguration Tool-Kit for Xilinx FPGAs. [Masters Thesis]. Virginia Tech; 2010. Available from: http://hdl.handle.net/10919/36348


Virginia Tech

15. Asthana, Rohit Mohan. High-Level CSP Model Compiler for FPGAs.

Degree: MS, Electrical and Computer Engineering, 2010, Virginia Tech

 The ever-growing competition in current electronics industry has resulted in stringent time-to-market goals and reduced design time available to engineers. Lesser design time has subsequently… (more)

Subjects/Keywords: High-Level Synthesis; FPGAs; Models of Computation (MoC); Communicating Sequential Processes (CSP); Autocode Generation

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APA (6th Edition):

Asthana, R. M. (2010). High-Level CSP Model Compiler for FPGAs. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/36428

Chicago Manual of Style (16th Edition):

Asthana, Rohit Mohan. “High-Level CSP Model Compiler for FPGAs.” 2010. Masters Thesis, Virginia Tech. Accessed July 07, 2020. http://hdl.handle.net/10919/36428.

MLA Handbook (7th Edition):

Asthana, Rohit Mohan. “High-Level CSP Model Compiler for FPGAs.” 2010. Web. 07 Jul 2020.

Vancouver:

Asthana RM. High-Level CSP Model Compiler for FPGAs. [Internet] [Masters thesis]. Virginia Tech; 2010. [cited 2020 Jul 07]. Available from: http://hdl.handle.net/10919/36428.

Council of Science Editors:

Asthana RM. High-Level CSP Model Compiler for FPGAs. [Masters Thesis]. Virginia Tech; 2010. Available from: http://hdl.handle.net/10919/36428


Virginia Tech

16. Demma, James Daniel. A Hardware Generator for Factor Graph Applications.

Degree: MS, Electrical and Computer Engineering, 2014, Virginia Tech

 A Factor Graph (FG  – http://en.wikipedia.org/wiki/Factor_graph) is a structure used to find solutions to problems that can be represented as a Probabilistic Graphical Model (PGM).… (more)

Subjects/Keywords: Factor Graph; Probabilistic Graphical Model; Digital Design; Sum-Product; Min-Sum; Belief Propagation; Hardware Generator

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APA (6th Edition):

Demma, J. D. (2014). A Hardware Generator for Factor Graph Applications. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/48599

Chicago Manual of Style (16th Edition):

Demma, James Daniel. “A Hardware Generator for Factor Graph Applications.” 2014. Masters Thesis, Virginia Tech. Accessed July 07, 2020. http://hdl.handle.net/10919/48599.

MLA Handbook (7th Edition):

Demma, James Daniel. “A Hardware Generator for Factor Graph Applications.” 2014. Web. 07 Jul 2020.

Vancouver:

Demma JD. A Hardware Generator for Factor Graph Applications. [Internet] [Masters thesis]. Virginia Tech; 2014. [cited 2020 Jul 07]. Available from: http://hdl.handle.net/10919/48599.

Council of Science Editors:

Demma JD. A Hardware Generator for Factor Graph Applications. [Masters Thesis]. Virginia Tech; 2014. Available from: http://hdl.handle.net/10919/48599


Virginia Tech

17. Rooks, Kurtis M. A Zynq-based Cluster Cognitive Radio.

Degree: MS, Electrical and Computer Engineering, 2014, Virginia Tech

 Traditional hardware radios provide very rigid solutions to radio problems. Intelligent software defined radios, also known as cognitive radios, provide flexibility and agility compared to… (more)

Subjects/Keywords: cogntive radio; Xilinx Zynq; tFlow; FPGA; GNU Radio; cluster

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APA (6th Edition):

Rooks, K. M. (2014). A Zynq-based Cluster Cognitive Radio. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/49682

Chicago Manual of Style (16th Edition):

Rooks, Kurtis M. “A Zynq-based Cluster Cognitive Radio.” 2014. Masters Thesis, Virginia Tech. Accessed July 07, 2020. http://hdl.handle.net/10919/49682.

MLA Handbook (7th Edition):

Rooks, Kurtis M. “A Zynq-based Cluster Cognitive Radio.” 2014. Web. 07 Jul 2020.

Vancouver:

Rooks KM. A Zynq-based Cluster Cognitive Radio. [Internet] [Masters thesis]. Virginia Tech; 2014. [cited 2020 Jul 07]. Available from: http://hdl.handle.net/10919/49682.

Council of Science Editors:

Rooks KM. A Zynq-based Cluster Cognitive Radio. [Masters Thesis]. Virginia Tech; 2014. Available from: http://hdl.handle.net/10919/49682


Virginia Tech

18. Judge, Lyndon Virginia. Design Methods for Cryptanalysis.

Degree: MS, Electrical and Computer Engineering, 2012, Virginia Tech

 Security of cryptographic algorithms relies on the computational difficulty of deriving the secret key using public information. Cryptanalysis, including logical and implementation attacks, plays an… (more)

Subjects/Keywords: Design method; Bluespec; Hardware software co-design; FPGA; Elliptic curve cryptography (ECC); Pollard rho; Prime field arithmetic

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APA (6th Edition):

Judge, L. V. (2012). Design Methods for Cryptanalysis. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/52639

Chicago Manual of Style (16th Edition):

Judge, Lyndon Virginia. “Design Methods for Cryptanalysis.” 2012. Masters Thesis, Virginia Tech. Accessed July 07, 2020. http://hdl.handle.net/10919/52639.

MLA Handbook (7th Edition):

Judge, Lyndon Virginia. “Design Methods for Cryptanalysis.” 2012. Web. 07 Jul 2020.

Vancouver:

Judge LV. Design Methods for Cryptanalysis. [Internet] [Masters thesis]. Virginia Tech; 2012. [cited 2020 Jul 07]. Available from: http://hdl.handle.net/10919/52639.

Council of Science Editors:

Judge LV. Design Methods for Cryptanalysis. [Masters Thesis]. Virginia Tech; 2012. Available from: http://hdl.handle.net/10919/52639


Virginia Tech

19. Lee, Kevin. Module Shaping and Exploration in Rapid FPGA Design and Assembly Workflows.

Degree: MS, Electrical and Computer Engineering, 2015, Virginia Tech

 The modular design methodology has been widely adopted to harness the complexity of large FPGA-based systems. As a result, a number of commercial and academic… (more)

Subjects/Keywords: FPGA; Productivity; Rapid Compilation; Modular Workflow

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APA (6th Edition):

Lee, K. (2015). Module Shaping and Exploration in Rapid FPGA Design and Assembly Workflows. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/53705

Chicago Manual of Style (16th Edition):

Lee, Kevin. “Module Shaping and Exploration in Rapid FPGA Design and Assembly Workflows.” 2015. Masters Thesis, Virginia Tech. Accessed July 07, 2020. http://hdl.handle.net/10919/53705.

MLA Handbook (7th Edition):

Lee, Kevin. “Module Shaping and Exploration in Rapid FPGA Design and Assembly Workflows.” 2015. Web. 07 Jul 2020.

Vancouver:

Lee K. Module Shaping and Exploration in Rapid FPGA Design and Assembly Workflows. [Internet] [Masters thesis]. Virginia Tech; 2015. [cited 2020 Jul 07]. Available from: http://hdl.handle.net/10919/53705.

Council of Science Editors:

Lee K. Module Shaping and Exploration in Rapid FPGA Design and Assembly Workflows. [Masters Thesis]. Virginia Tech; 2015. Available from: http://hdl.handle.net/10919/53705


Virginia Tech

20. Shi, Zhun. Rapid Prototyping of an FPGA-Based Video Processing System.

Degree: MS, Electrical and Computer Engineering, 2016, Virginia Tech

 Computer vision technology can be seen in a variety of applications ranging from mobile phones to autonomous vehicles. Many computer vision applications such as drones… (more)

Subjects/Keywords: FPGA; Computer Vision; Video Processing; Rapid Prototyping; High-Level Synthesis

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APA (6th Edition):

Shi, Z. (2016). Rapid Prototyping of an FPGA-Based Video Processing System. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/71389

Chicago Manual of Style (16th Edition):

Shi, Zhun. “Rapid Prototyping of an FPGA-Based Video Processing System.” 2016. Masters Thesis, Virginia Tech. Accessed July 07, 2020. http://hdl.handle.net/10919/71389.

MLA Handbook (7th Edition):

Shi, Zhun. “Rapid Prototyping of an FPGA-Based Video Processing System.” 2016. Web. 07 Jul 2020.

Vancouver:

Shi Z. Rapid Prototyping of an FPGA-Based Video Processing System. [Internet] [Masters thesis]. Virginia Tech; 2016. [cited 2020 Jul 07]. Available from: http://hdl.handle.net/10919/71389.

Council of Science Editors:

Shi Z. Rapid Prototyping of an FPGA-Based Video Processing System. [Masters Thesis]. Virginia Tech; 2016. Available from: http://hdl.handle.net/10919/71389


Virginia Tech

21. Bieberly, Frank. Heterogeneous Processing in Software Defined Radio: Flexible Implementation and Optimal Resource Mapping.

Degree: MS, Electrical and Computer Engineering, 2012, Virginia Tech

 The advantages provided by Software Defined Radios (SDRs) have made them useful tools for communication engineers and academics alike. The ability to support a wide… (more)

Subjects/Keywords: oftware Defined Radio; Heterogeneous Processing; Resource Mapping

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APA (6th Edition):

Bieberly, F. (2012). Heterogeneous Processing in Software Defined Radio: Flexible Implementation and Optimal Resource Mapping. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/31380

Chicago Manual of Style (16th Edition):

Bieberly, Frank. “Heterogeneous Processing in Software Defined Radio: Flexible Implementation and Optimal Resource Mapping.” 2012. Masters Thesis, Virginia Tech. Accessed July 07, 2020. http://hdl.handle.net/10919/31380.

MLA Handbook (7th Edition):

Bieberly, Frank. “Heterogeneous Processing in Software Defined Radio: Flexible Implementation and Optimal Resource Mapping.” 2012. Web. 07 Jul 2020.

Vancouver:

Bieberly F. Heterogeneous Processing in Software Defined Radio: Flexible Implementation and Optimal Resource Mapping. [Internet] [Masters thesis]. Virginia Tech; 2012. [cited 2020 Jul 07]. Available from: http://hdl.handle.net/10919/31380.

Council of Science Editors:

Bieberly F. Heterogeneous Processing in Software Defined Radio: Flexible Implementation and Optimal Resource Mapping. [Masters Thesis]. Virginia Tech; 2012. Available from: http://hdl.handle.net/10919/31380


Virginia Tech

22. Arora, Samiksha. Firmware Development of the LAICE Instrument Interface Board (LIIB).

Degree: MS, Electrical and Computer Engineering, 2017, Virginia Tech

 The Lower Atmosphere/Ionosphere Coupling Experiment (LAICE) CubeSat mission includes the payload instruments that generate scientific data by interacting with the flight computer. The LAICE Instrument… (more)

Subjects/Keywords: FPGA Design; Interface Mechanism; LAICE Instrument Interface Board; Spacecraft

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APA (6th Edition):

Arora, S. (2017). Firmware Development of the LAICE Instrument Interface Board (LIIB). (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/78242

Chicago Manual of Style (16th Edition):

Arora, Samiksha. “Firmware Development of the LAICE Instrument Interface Board (LIIB).” 2017. Masters Thesis, Virginia Tech. Accessed July 07, 2020. http://hdl.handle.net/10919/78242.

MLA Handbook (7th Edition):

Arora, Samiksha. “Firmware Development of the LAICE Instrument Interface Board (LIIB).” 2017. Web. 07 Jul 2020.

Vancouver:

Arora S. Firmware Development of the LAICE Instrument Interface Board (LIIB). [Internet] [Masters thesis]. Virginia Tech; 2017. [cited 2020 Jul 07]. Available from: http://hdl.handle.net/10919/78242.

Council of Science Editors:

Arora S. Firmware Development of the LAICE Instrument Interface Board (LIIB). [Masters Thesis]. Virginia Tech; 2017. Available from: http://hdl.handle.net/10919/78242


Virginia Tech

23. Zeng, Kevin. Enhancing Productivity with Back-End Similarity Matching of Digital Circuits for IP Reuse.

Degree: MS, Electrical and Computer Engineering, 2013, Virginia Tech

 Productivity for digital circuit design is being outpaced currently by the rate at which silicon is growing such as FPGAs. Complex designs take a large… (more)

Subjects/Keywords: FPGA; Productivity; Digital Circuits; Graph Matching; Similarity; IP Reuse

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APA (6th Edition):

Zeng, K. (2013). Enhancing Productivity with Back-End Similarity Matching of Digital Circuits for IP Reuse. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/23144

Chicago Manual of Style (16th Edition):

Zeng, Kevin. “Enhancing Productivity with Back-End Similarity Matching of Digital Circuits for IP Reuse.” 2013. Masters Thesis, Virginia Tech. Accessed July 07, 2020. http://hdl.handle.net/10919/23144.

MLA Handbook (7th Edition):

Zeng, Kevin. “Enhancing Productivity with Back-End Similarity Matching of Digital Circuits for IP Reuse.” 2013. Web. 07 Jul 2020.

Vancouver:

Zeng K. Enhancing Productivity with Back-End Similarity Matching of Digital Circuits for IP Reuse. [Internet] [Masters thesis]. Virginia Tech; 2013. [cited 2020 Jul 07]. Available from: http://hdl.handle.net/10919/23144.

Council of Science Editors:

Zeng K. Enhancing Productivity with Back-End Similarity Matching of Digital Circuits for IP Reuse. [Masters Thesis]. Virginia Tech; 2013. Available from: http://hdl.handle.net/10919/23144


Virginia Tech

24. Xin, Xin. A Filtered Multitone (FMT) Implementation with Custom Instructions on an Altera FPGA.

Degree: MS, Electrical and Computer Engineering, 2013, Virginia Tech

 There is a belief that radio frequencies  are running out. However, according to a report from the Federal Communications Commission (FCC) in 2002, a different… (more)

Subjects/Keywords: Multicarrier Communication; FMT; Overlay; Cognitive Radio; Altera FPGA

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APA (6th Edition):

Xin, X. (2013). A Filtered Multitone (FMT) Implementation with Custom Instructions on an Altera FPGA. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/23193

Chicago Manual of Style (16th Edition):

Xin, Xin. “A Filtered Multitone (FMT) Implementation with Custom Instructions on an Altera FPGA.” 2013. Masters Thesis, Virginia Tech. Accessed July 07, 2020. http://hdl.handle.net/10919/23193.

MLA Handbook (7th Edition):

Xin, Xin. “A Filtered Multitone (FMT) Implementation with Custom Instructions on an Altera FPGA.” 2013. Web. 07 Jul 2020.

Vancouver:

Xin X. A Filtered Multitone (FMT) Implementation with Custom Instructions on an Altera FPGA. [Internet] [Masters thesis]. Virginia Tech; 2013. [cited 2020 Jul 07]. Available from: http://hdl.handle.net/10919/23193.

Council of Science Editors:

Xin X. A Filtered Multitone (FMT) Implementation with Custom Instructions on an Altera FPGA. [Masters Thesis]. Virginia Tech; 2013. Available from: http://hdl.handle.net/10919/23193


Virginia Tech

25. Lewis, Robert Alan. Analysis of a self-contained motion capture garment for e-textiles.

Degree: MS, Electrical and Computer Engineering, 2011, Virginia Tech

 Wearable computers and e-textiles are becoming increasingly widespread in todayâ s society. Motion capture is one of the many potential applications for on-body electronic systems.… (more)

Subjects/Keywords: Optical Motion Capture; Inertial Measurement Units; E-textiles; Wearable Computing

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APA (6th Edition):

Lewis, R. A. (2011). Analysis of a self-contained motion capture garment for e-textiles. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/32529

Chicago Manual of Style (16th Edition):

Lewis, Robert Alan. “Analysis of a self-contained motion capture garment for e-textiles.” 2011. Masters Thesis, Virginia Tech. Accessed July 07, 2020. http://hdl.handle.net/10919/32529.

MLA Handbook (7th Edition):

Lewis, Robert Alan. “Analysis of a self-contained motion capture garment for e-textiles.” 2011. Web. 07 Jul 2020.

Vancouver:

Lewis RA. Analysis of a self-contained motion capture garment for e-textiles. [Internet] [Masters thesis]. Virginia Tech; 2011. [cited 2020 Jul 07]. Available from: http://hdl.handle.net/10919/32529.

Council of Science Editors:

Lewis RA. Analysis of a self-contained motion capture garment for e-textiles. [Masters Thesis]. Virginia Tech; 2011. Available from: http://hdl.handle.net/10919/32529


Virginia Tech

26. Said, Karim AbdelFattah. PicoRF: A PC-based SDR Platform using a High Performance PCIe Plug-in Card Extension.

Degree: MS, Electrical and Computer Engineering, 2012, Virginia Tech

 Wireless communication serves as the foundation for a wide range of services that have become an integral part of human life in this day and… (more)

Subjects/Keywords: PCI Express; Partial Reconfiguration; GNU Radio; RFIC; SDR

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APA (6th Edition):

Said, K. A. (2012). PicoRF: A PC-based SDR Platform using a High Performance PCIe Plug-in Card Extension. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/34443

Chicago Manual of Style (16th Edition):

Said, Karim AbdelFattah. “PicoRF: A PC-based SDR Platform using a High Performance PCIe Plug-in Card Extension.” 2012. Masters Thesis, Virginia Tech. Accessed July 07, 2020. http://hdl.handle.net/10919/34443.

MLA Handbook (7th Edition):

Said, Karim AbdelFattah. “PicoRF: A PC-based SDR Platform using a High Performance PCIe Plug-in Card Extension.” 2012. Web. 07 Jul 2020.

Vancouver:

Said KA. PicoRF: A PC-based SDR Platform using a High Performance PCIe Plug-in Card Extension. [Internet] [Masters thesis]. Virginia Tech; 2012. [cited 2020 Jul 07]. Available from: http://hdl.handle.net/10919/34443.

Council of Science Editors:

Said KA. PicoRF: A PC-based SDR Platform using a High Performance PCIe Plug-in Card Extension. [Masters Thesis]. Virginia Tech; 2012. Available from: http://hdl.handle.net/10919/34443


Virginia Tech

27. Mandadi, Harsha. Remote Integrity Checking using Multiple PUF based Component Identifiers.

Degree: MS, Computer Engineering, 2017, Virginia Tech

 Modern Printed Circuit Boards (PCB) contain sophisticated and valuable electronic components, and this makes them a prime target for counterfeiting. In this thesis, we consider… (more)

Subjects/Keywords: Physical Unclonable Functions; Fuzzy Extractors; Authentic Protocol

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APA (6th Edition):

Mandadi, H. (2017). Remote Integrity Checking using Multiple PUF based Component Identifiers. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/78200

Chicago Manual of Style (16th Edition):

Mandadi, Harsha. “Remote Integrity Checking using Multiple PUF based Component Identifiers.” 2017. Masters Thesis, Virginia Tech. Accessed July 07, 2020. http://hdl.handle.net/10919/78200.

MLA Handbook (7th Edition):

Mandadi, Harsha. “Remote Integrity Checking using Multiple PUF based Component Identifiers.” 2017. Web. 07 Jul 2020.

Vancouver:

Mandadi H. Remote Integrity Checking using Multiple PUF based Component Identifiers. [Internet] [Masters thesis]. Virginia Tech; 2017. [cited 2020 Jul 07]. Available from: http://hdl.handle.net/10919/78200.

Council of Science Editors:

Mandadi H. Remote Integrity Checking using Multiple PUF based Component Identifiers. [Masters Thesis]. Virginia Tech; 2017. Available from: http://hdl.handle.net/10919/78200

28. Modi, Harmish Rajeshkumar. In-System Testing of Configurable Logic Blocks in Xilinx 7-Series FPGAs.

Degree: MS, Electrical and Computer Engineering, 2015, Virginia Tech

 FPGA fault recovery techniques, such as bitstream scrubbing, are only limited to detecting and correcting soft errors that corrupt the configuration memory. Scrubbing and related… (more)

Subjects/Keywords: FPGA; Built-In Self-Test; Iterative Logic Array

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APA (6th Edition):

Modi, H. R. (2015). In-System Testing of Configurable Logic Blocks in Xilinx 7-Series FPGAs. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/55123

Chicago Manual of Style (16th Edition):

Modi, Harmish Rajeshkumar. “In-System Testing of Configurable Logic Blocks in Xilinx 7-Series FPGAs.” 2015. Masters Thesis, Virginia Tech. Accessed July 07, 2020. http://hdl.handle.net/10919/55123.

MLA Handbook (7th Edition):

Modi, Harmish Rajeshkumar. “In-System Testing of Configurable Logic Blocks in Xilinx 7-Series FPGAs.” 2015. Web. 07 Jul 2020.

Vancouver:

Modi HR. In-System Testing of Configurable Logic Blocks in Xilinx 7-Series FPGAs. [Internet] [Masters thesis]. Virginia Tech; 2015. [cited 2020 Jul 07]. Available from: http://hdl.handle.net/10919/55123.

Council of Science Editors:

Modi HR. In-System Testing of Configurable Logic Blocks in Xilinx 7-Series FPGAs. [Masters Thesis]. Virginia Tech; 2015. Available from: http://hdl.handle.net/10919/55123

29. Soni, Ritesh K. Open-Source Bitstream Generation for FPGAs.

Degree: MS, Electrical and Computer Engineering, 2013, Virginia Tech

 Bitstream generation has traditionally been the single part of the FPGA design flow that has not been openly reproduced. This work enables bitstream generation for… (more)

Subjects/Keywords: FPGA; bitstream; low-level assembly; open-source

…falls in this category. It was developed by Xilinx and Virginia Tech with the aim of providing… 

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APA (6th Edition):

Soni, R. K. (2013). Open-Source Bitstream Generation for FPGAs. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/51836

Chicago Manual of Style (16th Edition):

Soni, Ritesh K. “Open-Source Bitstream Generation for FPGAs.” 2013. Masters Thesis, Virginia Tech. Accessed July 07, 2020. http://hdl.handle.net/10919/51836.

MLA Handbook (7th Edition):

Soni, Ritesh K. “Open-Source Bitstream Generation for FPGAs.” 2013. Web. 07 Jul 2020.

Vancouver:

Soni RK. Open-Source Bitstream Generation for FPGAs. [Internet] [Masters thesis]. Virginia Tech; 2013. [cited 2020 Jul 07]. Available from: http://hdl.handle.net/10919/51836.

Council of Science Editors:

Soni RK. Open-Source Bitstream Generation for FPGAs. [Masters Thesis]. Virginia Tech; 2013. Available from: http://hdl.handle.net/10919/51836

30. Dobson, Christopher Vaness. An Architecture Study on a Xilinx Zynq Cluster with Software Defined Radio Applications.

Degree: MS, Electrical and Computer Engineering, 2014, Virginia Tech

 The rapid rise in computational performance offered by computer systems has greatly increased the number of practical software defined radio applications. The addition of FPGAs… (more)

Subjects/Keywords: Zynq; tFlow; Software Defined Radio; Cognitive Radio

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APA (6th Edition):

Dobson, C. V. (2014). An Architecture Study on a Xilinx Zynq Cluster with Software Defined Radio Applications. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/49579

Chicago Manual of Style (16th Edition):

Dobson, Christopher Vaness. “An Architecture Study on a Xilinx Zynq Cluster with Software Defined Radio Applications.” 2014. Masters Thesis, Virginia Tech. Accessed July 07, 2020. http://hdl.handle.net/10919/49579.

MLA Handbook (7th Edition):

Dobson, Christopher Vaness. “An Architecture Study on a Xilinx Zynq Cluster with Software Defined Radio Applications.” 2014. Web. 07 Jul 2020.

Vancouver:

Dobson CV. An Architecture Study on a Xilinx Zynq Cluster with Software Defined Radio Applications. [Internet] [Masters thesis]. Virginia Tech; 2014. [cited 2020 Jul 07]. Available from: http://hdl.handle.net/10919/49579.

Council of Science Editors:

Dobson CV. An Architecture Study on a Xilinx Zynq Cluster with Software Defined Radio Applications. [Masters Thesis]. Virginia Tech; 2014. Available from: http://hdl.handle.net/10919/49579

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