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You searched for +publisher:"Vanderbilt University" +contributor:("Bharat L. Bhuva"). Showing records 1 – 30 of 45 total matches.

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Vanderbilt University

1. Chetia, Jugantor. An efficient AVF estimation technique using circuit partitioning.

Degree: MS, Electrical Engineering, 2012, Vanderbilt University

 Soft errors induced by radiation particles are increasingly becoming a source of concern for reliable design of VLSI systems. An important parameter to quantify the… (more)

Subjects/Keywords: AVF; statistical fault injection; circuit partitioning

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APA (6th Edition):

Chetia, J. (2012). An efficient AVF estimation technique using circuit partitioning. (Masters Thesis). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-01252012-174557/ ;

Chicago Manual of Style (16th Edition):

Chetia, Jugantor. “An efficient AVF estimation technique using circuit partitioning.” 2012. Masters Thesis, Vanderbilt University. Accessed October 23, 2019. http://etd.library.vanderbilt.edu/available/etd-01252012-174557/ ;.

MLA Handbook (7th Edition):

Chetia, Jugantor. “An efficient AVF estimation technique using circuit partitioning.” 2012. Web. 23 Oct 2019.

Vancouver:

Chetia J. An efficient AVF estimation technique using circuit partitioning. [Internet] [Masters thesis]. Vanderbilt University; 2012. [cited 2019 Oct 23]. Available from: http://etd.library.vanderbilt.edu/available/etd-01252012-174557/ ;.

Council of Science Editors:

Chetia J. An efficient AVF estimation technique using circuit partitioning. [Masters Thesis]. Vanderbilt University; 2012. Available from: http://etd.library.vanderbilt.edu/available/etd-01252012-174557/ ;


Vanderbilt University

2. Kou, Lingbo. Impact of process variations on soft error sensitivity of 32-nm VLSI circuits in near-threshold region.

Degree: MS, Electrical Engineering, 2014, Vanderbilt University

 Power consumption has become a major concern of integrated circuit (IC) design. Reducing the supply voltage to the near-threshold region is one method to reduce… (more)

Subjects/Keywords: flip-flop; radiation-induced soft errors; sram; near-threshold voltage; critical charge; process variations; reliability

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APA (6th Edition):

Kou, L. (2014). Impact of process variations on soft error sensitivity of 32-nm VLSI circuits in near-threshold region. (Masters Thesis). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-04082014-141041/ ;

Chicago Manual of Style (16th Edition):

Kou, Lingbo. “Impact of process variations on soft error sensitivity of 32-nm VLSI circuits in near-threshold region.” 2014. Masters Thesis, Vanderbilt University. Accessed October 23, 2019. http://etd.library.vanderbilt.edu/available/etd-04082014-141041/ ;.

MLA Handbook (7th Edition):

Kou, Lingbo. “Impact of process variations on soft error sensitivity of 32-nm VLSI circuits in near-threshold region.” 2014. Web. 23 Oct 2019.

Vancouver:

Kou L. Impact of process variations on soft error sensitivity of 32-nm VLSI circuits in near-threshold region. [Internet] [Masters thesis]. Vanderbilt University; 2014. [cited 2019 Oct 23]. Available from: http://etd.library.vanderbilt.edu/available/etd-04082014-141041/ ;.

Council of Science Editors:

Kou L. Impact of process variations on soft error sensitivity of 32-nm VLSI circuits in near-threshold region. [Masters Thesis]. Vanderbilt University; 2014. Available from: http://etd.library.vanderbilt.edu/available/etd-04082014-141041/ ;


Vanderbilt University

3. Kay, William Hunter. Single-Event Upset Characterization of Flip-Flops Across Temperature and Supply Voltage for a 20-nm Bulk, Planar, CMOS Technology.

Degree: MS, Electrical Engineering, 2015, Vanderbilt University

 The scaling of CMOS technology has brought about the increased susceptibility of circuits to single-event (SE) effects. Electronic systems operating in space often face extreme… (more)

Subjects/Keywords: flip flop; 20 nm; single event; SET; SEE; SEU

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APA (6th Edition):

Kay, W. H. (2015). Single-Event Upset Characterization of Flip-Flops Across Temperature and Supply Voltage for a 20-nm Bulk, Planar, CMOS Technology. (Masters Thesis). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-03302015-133003/ ;

Chicago Manual of Style (16th Edition):

Kay, William Hunter. “Single-Event Upset Characterization of Flip-Flops Across Temperature and Supply Voltage for a 20-nm Bulk, Planar, CMOS Technology.” 2015. Masters Thesis, Vanderbilt University. Accessed October 23, 2019. http://etd.library.vanderbilt.edu/available/etd-03302015-133003/ ;.

MLA Handbook (7th Edition):

Kay, William Hunter. “Single-Event Upset Characterization of Flip-Flops Across Temperature and Supply Voltage for a 20-nm Bulk, Planar, CMOS Technology.” 2015. Web. 23 Oct 2019.

Vancouver:

Kay WH. Single-Event Upset Characterization of Flip-Flops Across Temperature and Supply Voltage for a 20-nm Bulk, Planar, CMOS Technology. [Internet] [Masters thesis]. Vanderbilt University; 2015. [cited 2019 Oct 23]. Available from: http://etd.library.vanderbilt.edu/available/etd-03302015-133003/ ;.

Council of Science Editors:

Kay WH. Single-Event Upset Characterization of Flip-Flops Across Temperature and Supply Voltage for a 20-nm Bulk, Planar, CMOS Technology. [Masters Thesis]. Vanderbilt University; 2015. Available from: http://etd.library.vanderbilt.edu/available/etd-03302015-133003/ ;


Vanderbilt University

4. Gadlage, Matthew John. Impact of Temperature on Single-Event Transients in Deep Submicrometer Bulk and Silicon-On-Insulator Digital CMOS Technologies.

Degree: PhD, Electrical Engineering, 2010, Vanderbilt University

 Single-event transients (SETs) are a significant reliability issue for space-based electronic systems. A single-event transient is a radiation-induced glitch in an electronic circuit caused by… (more)

Subjects/Keywords: radiation effects; space environment; soft errors; heavy ions; single event effects; single event transients; silicon-on-insulator; temperature

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APA (6th Edition):

Gadlage, M. J. (2010). Impact of Temperature on Single-Event Transients in Deep Submicrometer Bulk and Silicon-On-Insulator Digital CMOS Technologies. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-03262010-102121/ ;

Chicago Manual of Style (16th Edition):

Gadlage, Matthew John. “Impact of Temperature on Single-Event Transients in Deep Submicrometer Bulk and Silicon-On-Insulator Digital CMOS Technologies.” 2010. Doctoral Dissertation, Vanderbilt University. Accessed October 23, 2019. http://etd.library.vanderbilt.edu/available/etd-03262010-102121/ ;.

MLA Handbook (7th Edition):

Gadlage, Matthew John. “Impact of Temperature on Single-Event Transients in Deep Submicrometer Bulk and Silicon-On-Insulator Digital CMOS Technologies.” 2010. Web. 23 Oct 2019.

Vancouver:

Gadlage MJ. Impact of Temperature on Single-Event Transients in Deep Submicrometer Bulk and Silicon-On-Insulator Digital CMOS Technologies. [Internet] [Doctoral dissertation]. Vanderbilt University; 2010. [cited 2019 Oct 23]. Available from: http://etd.library.vanderbilt.edu/available/etd-03262010-102121/ ;.

Council of Science Editors:

Gadlage MJ. Impact of Temperature on Single-Event Transients in Deep Submicrometer Bulk and Silicon-On-Insulator Digital CMOS Technologies. [Doctoral Dissertation]. Vanderbilt University; 2010. Available from: http://etd.library.vanderbilt.edu/available/etd-03262010-102121/ ;


Vanderbilt University

5. Olson, Brian David. Single-Event Effect Mitigation in Pipelined Analog-to-Digital Converters.

Degree: PhD, Electrical Engineering, 2010, Vanderbilt University

 Analog-to-digital converters (ADCs) are necessary circuits in many space, military, and medical circuit applications. Intelligence, surveillance, reconnaissance, and communication missions all require high performance ADCs.… (more)

Subjects/Keywords: single-events; SEU; SEE; RHBD; radiation hardened by design; ADC; single-event effects; analog-to-digital converters

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APA (6th Edition):

Olson, B. D. (2010). Single-Event Effect Mitigation in Pipelined Analog-to-Digital Converters. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-12102010-152348/ ;

Chicago Manual of Style (16th Edition):

Olson, Brian David. “Single-Event Effect Mitigation in Pipelined Analog-to-Digital Converters.” 2010. Doctoral Dissertation, Vanderbilt University. Accessed October 23, 2019. http://etd.library.vanderbilt.edu/available/etd-12102010-152348/ ;.

MLA Handbook (7th Edition):

Olson, Brian David. “Single-Event Effect Mitigation in Pipelined Analog-to-Digital Converters.” 2010. Web. 23 Oct 2019.

Vancouver:

Olson BD. Single-Event Effect Mitigation in Pipelined Analog-to-Digital Converters. [Internet] [Doctoral dissertation]. Vanderbilt University; 2010. [cited 2019 Oct 23]. Available from: http://etd.library.vanderbilt.edu/available/etd-12102010-152348/ ;.

Council of Science Editors:

Olson BD. Single-Event Effect Mitigation in Pipelined Analog-to-Digital Converters. [Doctoral Dissertation]. Vanderbilt University; 2010. Available from: http://etd.library.vanderbilt.edu/available/etd-12102010-152348/ ;


Vanderbilt University

6. Hsu, Shao-Hua. Development of Vertical Nanodiamond Vacuum Field Emission Microelectronic Integrated Devices.

Degree: PhD, Electrical Engineering, 2014, Vanderbilt University

 Recent development of nanocrystalline diamonds has demonstrated the potential use of diamond material for vacuum microelectronics. Apart from the advantages of conventional microcrystalline diamond, nanodiamond… (more)

Subjects/Keywords: Microelectronic Devices; Nanodiamond; Vacuum Field Emission; Integrated Circuits; Signal Amplifiers

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APA (6th Edition):

Hsu, S. (2014). Development of Vertical Nanodiamond Vacuum Field Emission Microelectronic Integrated Devices. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-02272014-153712/ ;

Chicago Manual of Style (16th Edition):

Hsu, Shao-Hua. “Development of Vertical Nanodiamond Vacuum Field Emission Microelectronic Integrated Devices.” 2014. Doctoral Dissertation, Vanderbilt University. Accessed October 23, 2019. http://etd.library.vanderbilt.edu/available/etd-02272014-153712/ ;.

MLA Handbook (7th Edition):

Hsu, Shao-Hua. “Development of Vertical Nanodiamond Vacuum Field Emission Microelectronic Integrated Devices.” 2014. Web. 23 Oct 2019.

Vancouver:

Hsu S. Development of Vertical Nanodiamond Vacuum Field Emission Microelectronic Integrated Devices. [Internet] [Doctoral dissertation]. Vanderbilt University; 2014. [cited 2019 Oct 23]. Available from: http://etd.library.vanderbilt.edu/available/etd-02272014-153712/ ;.

Council of Science Editors:

Hsu S. Development of Vertical Nanodiamond Vacuum Field Emission Microelectronic Integrated Devices. [Doctoral Dissertation]. Vanderbilt University; 2014. Available from: http://etd.library.vanderbilt.edu/available/etd-02272014-153712/ ;


Vanderbilt University

7. Kiddie, Bradley Thomas. Single-Event Multiple-Transient Characterization and Mitigation via Standard Cell Placement Methods.

Degree: PhD, Electrical Engineering, 2016, Vanderbilt University

 The effects of radiation on the operation of integrated circuits (IC) continue to take a more important role as technology feature sizes scale down, critical… (more)

Subjects/Keywords: reliability; radiation; eda; single-event transient; single-event multiple-transient; placement; algorithm

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APA (6th Edition):

Kiddie, B. T. (2016). Single-Event Multiple-Transient Characterization and Mitigation via Standard Cell Placement Methods. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-09282016-101105/ ;

Chicago Manual of Style (16th Edition):

Kiddie, Bradley Thomas. “Single-Event Multiple-Transient Characterization and Mitigation via Standard Cell Placement Methods.” 2016. Doctoral Dissertation, Vanderbilt University. Accessed October 23, 2019. http://etd.library.vanderbilt.edu/available/etd-09282016-101105/ ;.

MLA Handbook (7th Edition):

Kiddie, Bradley Thomas. “Single-Event Multiple-Transient Characterization and Mitigation via Standard Cell Placement Methods.” 2016. Web. 23 Oct 2019.

Vancouver:

Kiddie BT. Single-Event Multiple-Transient Characterization and Mitigation via Standard Cell Placement Methods. [Internet] [Doctoral dissertation]. Vanderbilt University; 2016. [cited 2019 Oct 23]. Available from: http://etd.library.vanderbilt.edu/available/etd-09282016-101105/ ;.

Council of Science Editors:

Kiddie BT. Single-Event Multiple-Transient Characterization and Mitigation via Standard Cell Placement Methods. [Doctoral Dissertation]. Vanderbilt University; 2016. Available from: http://etd.library.vanderbilt.edu/available/etd-09282016-101105/ ;


Vanderbilt University

8. Jiang, Hui. Design of soft-error-aware sequential circuits with power and speed optimization.

Degree: PhD, Electrical Engineering, 2018, Vanderbilt University

 A single-event effect (SEE) of circuits is strongly dependent on the supply voltage and the physical capacitance. Reduction in supply voltage as well as technology… (more)

Subjects/Keywords: power optimization; sequential circuit; soft error rate; Single event effects; empirical model

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APA (6th Edition):

Jiang, H. (2018). Design of soft-error-aware sequential circuits with power and speed optimization. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-03192018-153616/ ;

Chicago Manual of Style (16th Edition):

Jiang, Hui. “Design of soft-error-aware sequential circuits with power and speed optimization.” 2018. Doctoral Dissertation, Vanderbilt University. Accessed October 23, 2019. http://etd.library.vanderbilt.edu/available/etd-03192018-153616/ ;.

MLA Handbook (7th Edition):

Jiang, Hui. “Design of soft-error-aware sequential circuits with power and speed optimization.” 2018. Web. 23 Oct 2019.

Vancouver:

Jiang H. Design of soft-error-aware sequential circuits with power and speed optimization. [Internet] [Doctoral dissertation]. Vanderbilt University; 2018. [cited 2019 Oct 23]. Available from: http://etd.library.vanderbilt.edu/available/etd-03192018-153616/ ;.

Council of Science Editors:

Jiang H. Design of soft-error-aware sequential circuits with power and speed optimization. [Doctoral Dissertation]. Vanderbilt University; 2018. Available from: http://etd.library.vanderbilt.edu/available/etd-03192018-153616/ ;


Vanderbilt University

9. Zhang, Hangfang. Impact of Designer-Controlled Parameters on Single-Event Responses for Flip-Flop Designs in Advanced Technologies.

Degree: PhD, Electrical Engineering, 2018, Vanderbilt University

 Modern ICs need to be designed with proper designer-controllable factors to meet power, speed and single-event (SE) performance requirements in different applications. Commercial fabrication houses… (more)

Subjects/Keywords: Single Event; Threshold Voltage; FinFET; Design Parameter; Temperature; Angular Incidence; Flip-Flop; Well Structure

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APA (6th Edition):

Zhang, H. (2018). Impact of Designer-Controlled Parameters on Single-Event Responses for Flip-Flop Designs in Advanced Technologies. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-04072018-123506/ ;

Chicago Manual of Style (16th Edition):

Zhang, Hangfang. “Impact of Designer-Controlled Parameters on Single-Event Responses for Flip-Flop Designs in Advanced Technologies.” 2018. Doctoral Dissertation, Vanderbilt University. Accessed October 23, 2019. http://etd.library.vanderbilt.edu/available/etd-04072018-123506/ ;.

MLA Handbook (7th Edition):

Zhang, Hangfang. “Impact of Designer-Controlled Parameters on Single-Event Responses for Flip-Flop Designs in Advanced Technologies.” 2018. Web. 23 Oct 2019.

Vancouver:

Zhang H. Impact of Designer-Controlled Parameters on Single-Event Responses for Flip-Flop Designs in Advanced Technologies. [Internet] [Doctoral dissertation]. Vanderbilt University; 2018. [cited 2019 Oct 23]. Available from: http://etd.library.vanderbilt.edu/available/etd-04072018-123506/ ;.

Council of Science Editors:

Zhang H. Impact of Designer-Controlled Parameters on Single-Event Responses for Flip-Flop Designs in Advanced Technologies. [Doctoral Dissertation]. Vanderbilt University; 2018. Available from: http://etd.library.vanderbilt.edu/available/etd-04072018-123506/ ;


Vanderbilt University

10. Megat Hamari, Puteri Saidatul A. Electrothermal Behavior of Attached and Freestanding Diamond Resistors.

Degree: PhD, Electrical Engineering, 2010, Vanderbilt University

 Passive devices are micro circuit elements that play a critical role in electronic products. The extraordinary physical properties of diamond such as high thermal conductivity,… (more)

Subjects/Keywords: diamond resistors; diamond thin films; chemical vapor deposition; freestanding resistor

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APA (6th Edition):

Megat Hamari, P. S. A. (2010). Electrothermal Behavior of Attached and Freestanding Diamond Resistors. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-12022010-134653/ ;

Chicago Manual of Style (16th Edition):

Megat Hamari, Puteri Saidatul A. “Electrothermal Behavior of Attached and Freestanding Diamond Resistors.” 2010. Doctoral Dissertation, Vanderbilt University. Accessed October 23, 2019. http://etd.library.vanderbilt.edu/available/etd-12022010-134653/ ;.

MLA Handbook (7th Edition):

Megat Hamari, Puteri Saidatul A. “Electrothermal Behavior of Attached and Freestanding Diamond Resistors.” 2010. Web. 23 Oct 2019.

Vancouver:

Megat Hamari PSA. Electrothermal Behavior of Attached and Freestanding Diamond Resistors. [Internet] [Doctoral dissertation]. Vanderbilt University; 2010. [cited 2019 Oct 23]. Available from: http://etd.library.vanderbilt.edu/available/etd-12022010-134653/ ;.

Council of Science Editors:

Megat Hamari PSA. Electrothermal Behavior of Attached and Freestanding Diamond Resistors. [Doctoral Dissertation]. Vanderbilt University; 2010. Available from: http://etd.library.vanderbilt.edu/available/etd-12022010-134653/ ;


Vanderbilt University

11. Kauppila, Amy Vaughn. Analysis of parameter variation impact on the single event response in sub-100nm CMOS storage cells.

Degree: PhD, Electrical Engineering, 2012, Vanderbilt University

 Current deep sub-micron technologies are particularly susceptible to single events. The challenge derives from a conglomeration of effects that affect circuitsâ radiation response. For instance,… (more)

Subjects/Keywords: single event upset; parameter variation

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APA (6th Edition):

Kauppila, A. V. (2012). Analysis of parameter variation impact on the single event response in sub-100nm CMOS storage cells. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-04092012-111410/ ;

Chicago Manual of Style (16th Edition):

Kauppila, Amy Vaughn. “Analysis of parameter variation impact on the single event response in sub-100nm CMOS storage cells.” 2012. Doctoral Dissertation, Vanderbilt University. Accessed October 23, 2019. http://etd.library.vanderbilt.edu/available/etd-04092012-111410/ ;.

MLA Handbook (7th Edition):

Kauppila, Amy Vaughn. “Analysis of parameter variation impact on the single event response in sub-100nm CMOS storage cells.” 2012. Web. 23 Oct 2019.

Vancouver:

Kauppila AV. Analysis of parameter variation impact on the single event response in sub-100nm CMOS storage cells. [Internet] [Doctoral dissertation]. Vanderbilt University; 2012. [cited 2019 Oct 23]. Available from: http://etd.library.vanderbilt.edu/available/etd-04092012-111410/ ;.

Council of Science Editors:

Kauppila AV. Analysis of parameter variation impact on the single event response in sub-100nm CMOS storage cells. [Doctoral Dissertation]. Vanderbilt University; 2012. Available from: http://etd.library.vanderbilt.edu/available/etd-04092012-111410/ ;


Vanderbilt University

12. Assis, Thiago Rocha de. Soft error aware physical synthesis.

Degree: PhD, Electrical Engineering, 2015, Vanderbilt University

 To allow accurate analysis of Soft Errors by Electronic Design Automation (EDA) tools, analytical models were developed to estimate electrical characteristics of the single event.… (more)

Subjects/Keywords: single event transient; set pulse width; collected charge; radiation effects; electronic design automation; physical synthesis; soft error; reliability

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APA (6th Edition):

Assis, T. R. d. (2015). Soft error aware physical synthesis. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-11242015-013303/ ;

Chicago Manual of Style (16th Edition):

Assis, Thiago Rocha de. “Soft error aware physical synthesis.” 2015. Doctoral Dissertation, Vanderbilt University. Accessed October 23, 2019. http://etd.library.vanderbilt.edu/available/etd-11242015-013303/ ;.

MLA Handbook (7th Edition):

Assis, Thiago Rocha de. “Soft error aware physical synthesis.” 2015. Web. 23 Oct 2019.

Vancouver:

Assis TRd. Soft error aware physical synthesis. [Internet] [Doctoral dissertation]. Vanderbilt University; 2015. [cited 2019 Oct 23]. Available from: http://etd.library.vanderbilt.edu/available/etd-11242015-013303/ ;.

Council of Science Editors:

Assis TRd. Soft error aware physical synthesis. [Doctoral Dissertation]. Vanderbilt University; 2015. Available from: http://etd.library.vanderbilt.edu/available/etd-11242015-013303/ ;


Vanderbilt University

13. Chen, Yanran. Analysis and hardening of all-digital phase-locked loops (ADPLLs) to single-event radiation effects.

Degree: PhD, Electrical Engineering, 2017, Vanderbilt University

 In deep sub-micron CMOS technologies, all-digital phase-locked loops (ADPLLs) are favored over conventional analog or mixed-signal phase-locked loops (A/MS) PLLs for providing the clock signals… (more)

Subjects/Keywords: Single-Event Upsets (SEU); All-digital Phase-locked Loops (ADPLLs); Single-Event Effects (SEE)

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APA (6th Edition):

Chen, Y. (2017). Analysis and hardening of all-digital phase-locked loops (ADPLLs) to single-event radiation effects. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu//available/etd-09222017-180229/ ;

Chicago Manual of Style (16th Edition):

Chen, Yanran. “Analysis and hardening of all-digital phase-locked loops (ADPLLs) to single-event radiation effects.” 2017. Doctoral Dissertation, Vanderbilt University. Accessed October 23, 2019. http://etd.library.vanderbilt.edu//available/etd-09222017-180229/ ;.

MLA Handbook (7th Edition):

Chen, Yanran. “Analysis and hardening of all-digital phase-locked loops (ADPLLs) to single-event radiation effects.” 2017. Web. 23 Oct 2019.

Vancouver:

Chen Y. Analysis and hardening of all-digital phase-locked loops (ADPLLs) to single-event radiation effects. [Internet] [Doctoral dissertation]. Vanderbilt University; 2017. [cited 2019 Oct 23]. Available from: http://etd.library.vanderbilt.edu//available/etd-09222017-180229/ ;.

Council of Science Editors:

Chen Y. Analysis and hardening of all-digital phase-locked loops (ADPLLs) to single-event radiation effects. [Doctoral Dissertation]. Vanderbilt University; 2017. Available from: http://etd.library.vanderbilt.edu//available/etd-09222017-180229/ ;

14. Benakanakere Sheshadri, Vijay. Upset trends in flip-flop designs at deep submicron technologies.

Degree: MS, Electrical Engineering, 2010, Vanderbilt University

 Advances in fabrication technologies for semiconductor integrated circuits (ICs) have resulted in sub-100 nm feature sizes. Along with this desired reduction in dimension has come… (more)

Subjects/Keywords: Critical Charge; DICE; Q8FF; Charge threshold plot; MRED

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APA (6th Edition):

Benakanakere Sheshadri, V. (2010). Upset trends in flip-flop designs at deep submicron technologies. (Masters Thesis). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-09062010-120803/ ;

Chicago Manual of Style (16th Edition):

Benakanakere Sheshadri, Vijay. “Upset trends in flip-flop designs at deep submicron technologies.” 2010. Masters Thesis, Vanderbilt University. Accessed October 23, 2019. http://etd.library.vanderbilt.edu/available/etd-09062010-120803/ ;.

MLA Handbook (7th Edition):

Benakanakere Sheshadri, Vijay. “Upset trends in flip-flop designs at deep submicron technologies.” 2010. Web. 23 Oct 2019.

Vancouver:

Benakanakere Sheshadri V. Upset trends in flip-flop designs at deep submicron technologies. [Internet] [Masters thesis]. Vanderbilt University; 2010. [cited 2019 Oct 23]. Available from: http://etd.library.vanderbilt.edu/available/etd-09062010-120803/ ;.

Council of Science Editors:

Benakanakere Sheshadri V. Upset trends in flip-flop designs at deep submicron technologies. [Masters Thesis]. Vanderbilt University; 2010. Available from: http://etd.library.vanderbilt.edu/available/etd-09062010-120803/ ;

15. Bickham, Ryan Christopher. An analysis of error detection techniques for arithmetic logic units.

Degree: ME, Electrical Engineering, 2010, Vanderbilt University

 Scaling in VLSI systems leads to higher packing densities for transistors. As a result, they are more likely to be hit by an incident particle,… (more)

Subjects/Keywords: Arithmetic codes; Error Detection; Redundancy; Berger codes; Parity codes

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APA (6th Edition):

Bickham, R. C. (2010). An analysis of error detection techniques for arithmetic logic units. (Masters Thesis). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-03292010-160012/ ;

Chicago Manual of Style (16th Edition):

Bickham, Ryan Christopher. “An analysis of error detection techniques for arithmetic logic units.” 2010. Masters Thesis, Vanderbilt University. Accessed October 23, 2019. http://etd.library.vanderbilt.edu/available/etd-03292010-160012/ ;.

MLA Handbook (7th Edition):

Bickham, Ryan Christopher. “An analysis of error detection techniques for arithmetic logic units.” 2010. Web. 23 Oct 2019.

Vancouver:

Bickham RC. An analysis of error detection techniques for arithmetic logic units. [Internet] [Masters thesis]. Vanderbilt University; 2010. [cited 2019 Oct 23]. Available from: http://etd.library.vanderbilt.edu/available/etd-03292010-160012/ ;.

Council of Science Editors:

Bickham RC. An analysis of error detection techniques for arithmetic logic units. [Masters Thesis]. Vanderbilt University; 2010. Available from: http://etd.library.vanderbilt.edu/available/etd-03292010-160012/ ;

16. Tekumala, Lakshmi Deepika. On-chip characterization of single-event charge-collection.

Degree: MS, Electrical Engineering, 2012, Vanderbilt University

 Particle strikes on microelectronic circuits lead to undesirable current transients on the circuit node due to charge generation and charge collection processes. Typically, TCAD tools… (more)

Subjects/Keywords: single-events; charge collection; autonomous circuit technique; on-chip characterization; UMC 40nm

…August, 2012 Nashville, Tennessee Approved: Professor Bharat L . Bhuva Professor Lloyd W… …Thesis Submitted to the Faculty of the Graduate School of Vanderbilt University in partial… 

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APA (6th Edition):

Tekumala, L. D. (2012). On-chip characterization of single-event charge-collection. (Masters Thesis). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-08052012-215357/ ;

Chicago Manual of Style (16th Edition):

Tekumala, Lakshmi Deepika. “On-chip characterization of single-event charge-collection.” 2012. Masters Thesis, Vanderbilt University. Accessed October 23, 2019. http://etd.library.vanderbilt.edu/available/etd-08052012-215357/ ;.

MLA Handbook (7th Edition):

Tekumala, Lakshmi Deepika. “On-chip characterization of single-event charge-collection.” 2012. Web. 23 Oct 2019.

Vancouver:

Tekumala LD. On-chip characterization of single-event charge-collection. [Internet] [Masters thesis]. Vanderbilt University; 2012. [cited 2019 Oct 23]. Available from: http://etd.library.vanderbilt.edu/available/etd-08052012-215357/ ;.

Council of Science Editors:

Tekumala LD. On-chip characterization of single-event charge-collection. [Masters Thesis]. Vanderbilt University; 2012. Available from: http://etd.library.vanderbilt.edu/available/etd-08052012-215357/ ;

17. Ossi, Edward John. Soft-error mitigation at the architecture-level using Berger codes for error detection.

Degree: ME, Electrical Engineering, 2011, Vanderbilt University

 Soft-error mitigation using design techniques at the architecture-level can overcome the limitations of process and circuit-level mitigation techniques in advanced technologies. This thesis presents two… (more)

Subjects/Keywords: berger code; architecture; soft error

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APA (6th Edition):

Ossi, E. J. (2011). Soft-error mitigation at the architecture-level using Berger codes for error detection. (Masters Thesis). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-12022011-121416/ ;

Chicago Manual of Style (16th Edition):

Ossi, Edward John. “Soft-error mitigation at the architecture-level using Berger codes for error detection.” 2011. Masters Thesis, Vanderbilt University. Accessed October 23, 2019. http://etd.library.vanderbilt.edu/available/etd-12022011-121416/ ;.

MLA Handbook (7th Edition):

Ossi, Edward John. “Soft-error mitigation at the architecture-level using Berger codes for error detection.” 2011. Web. 23 Oct 2019.

Vancouver:

Ossi EJ. Soft-error mitigation at the architecture-level using Berger codes for error detection. [Internet] [Masters thesis]. Vanderbilt University; 2011. [cited 2019 Oct 23]. Available from: http://etd.library.vanderbilt.edu/available/etd-12022011-121416/ ;.

Council of Science Editors:

Ossi EJ. Soft-error mitigation at the architecture-level using Berger codes for error detection. [Masters Thesis]. Vanderbilt University; 2011. Available from: http://etd.library.vanderbilt.edu/available/etd-12022011-121416/ ;

18. Adeleke, Adeola. Logic repair and soft error rate reduction using approximate logic functions.

Degree: MS, Electrical Engineering, 2012, Vanderbilt University

 Continuing CMOS devices scaling causes an increase in the vulnerability of integrated circuits to radiation-induced soft errors. Furthermore, as transistor density increases, the probability of… (more)

Subjects/Keywords: functions; logic; approximate; logic; repair

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APA (6th Edition):

Adeleke, A. (2012). Logic repair and soft error rate reduction using approximate logic functions. (Masters Thesis). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-03122012-095419/ ;

Chicago Manual of Style (16th Edition):

Adeleke, Adeola. “Logic repair and soft error rate reduction using approximate logic functions.” 2012. Masters Thesis, Vanderbilt University. Accessed October 23, 2019. http://etd.library.vanderbilt.edu/available/etd-03122012-095419/ ;.

MLA Handbook (7th Edition):

Adeleke, Adeola. “Logic repair and soft error rate reduction using approximate logic functions.” 2012. Web. 23 Oct 2019.

Vancouver:

Adeleke A. Logic repair and soft error rate reduction using approximate logic functions. [Internet] [Masters thesis]. Vanderbilt University; 2012. [cited 2019 Oct 23]. Available from: http://etd.library.vanderbilt.edu/available/etd-03122012-095419/ ;.

Council of Science Editors:

Adeleke A. Logic repair and soft error rate reduction using approximate logic functions. [Masters Thesis]. Vanderbilt University; 2012. Available from: http://etd.library.vanderbilt.edu/available/etd-03122012-095419/ ;

19. Chatterjee, Indranil. Single-event charge collection and upset in 65-nm and 40-nm dual- and triple-well bulk CMOS SRAMS.

Degree: MS, Electrical Engineering, 2012, Vanderbilt University

 CMOS technologies can be either dual-well or triple-well. Triple-well technology has several advantages compared to dual-well technology in terms of electrical performance. Differences in the… (more)

Subjects/Keywords: Soft-errors; Single-Event Upset Reversal; Heavy Ion Irradiation; Triple-well; Dual-well; Single-Event Effects

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APA (6th Edition):

Chatterjee, I. (2012). Single-event charge collection and upset in 65-nm and 40-nm dual- and triple-well bulk CMOS SRAMS. (Masters Thesis). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-03252012-195135/ ;

Chicago Manual of Style (16th Edition):

Chatterjee, Indranil. “Single-event charge collection and upset in 65-nm and 40-nm dual- and triple-well bulk CMOS SRAMS.” 2012. Masters Thesis, Vanderbilt University. Accessed October 23, 2019. http://etd.library.vanderbilt.edu/available/etd-03252012-195135/ ;.

MLA Handbook (7th Edition):

Chatterjee, Indranil. “Single-event charge collection and upset in 65-nm and 40-nm dual- and triple-well bulk CMOS SRAMS.” 2012. Web. 23 Oct 2019.

Vancouver:

Chatterjee I. Single-event charge collection and upset in 65-nm and 40-nm dual- and triple-well bulk CMOS SRAMS. [Internet] [Masters thesis]. Vanderbilt University; 2012. [cited 2019 Oct 23]. Available from: http://etd.library.vanderbilt.edu/available/etd-03252012-195135/ ;.

Council of Science Editors:

Chatterjee I. Single-event charge collection and upset in 65-nm and 40-nm dual- and triple-well bulk CMOS SRAMS. [Masters Thesis]. Vanderbilt University; 2012. Available from: http://etd.library.vanderbilt.edu/available/etd-03252012-195135/ ;

20. Kiddie, Bradley Thomas. Layout-Based Fault Injection for Combinational Logic in Nanometer Technologies.

Degree: MS, Electrical Engineering, 2012, Vanderbilt University

 As feature sizes and operating voltages decrease, single-event transients from particle strikes in logic circuits become more probable. Much literature is available on the effects… (more)

Subjects/Keywords: reliability; radiation-induced faults; single-event transient; multiple transient faults; soft errors; combinational logic; layout

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APA (6th Edition):

Kiddie, B. T. (2012). Layout-Based Fault Injection for Combinational Logic in Nanometer Technologies. (Masters Thesis). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-03262012-131128/ ;

Chicago Manual of Style (16th Edition):

Kiddie, Bradley Thomas. “Layout-Based Fault Injection for Combinational Logic in Nanometer Technologies.” 2012. Masters Thesis, Vanderbilt University. Accessed October 23, 2019. http://etd.library.vanderbilt.edu/available/etd-03262012-131128/ ;.

MLA Handbook (7th Edition):

Kiddie, Bradley Thomas. “Layout-Based Fault Injection for Combinational Logic in Nanometer Technologies.” 2012. Web. 23 Oct 2019.

Vancouver:

Kiddie BT. Layout-Based Fault Injection for Combinational Logic in Nanometer Technologies. [Internet] [Masters thesis]. Vanderbilt University; 2012. [cited 2019 Oct 23]. Available from: http://etd.library.vanderbilt.edu/available/etd-03262012-131128/ ;.

Council of Science Editors:

Kiddie BT. Layout-Based Fault Injection for Combinational Logic in Nanometer Technologies. [Masters Thesis]. Vanderbilt University; 2012. Available from: http://etd.library.vanderbilt.edu/available/etd-03262012-131128/ ;

21. Jiang, Hui. Drosophila Automated Olfactory Training and Testing System for Associative Learning.

Degree: MS, Electrical Engineering, 2015, Vanderbilt University

 This thesis demonstrates the feasibility of designing and building a Drosophila automated training and testing system for Pavlovian classical associative learning/memory analyses using inexpensive hardware… (more)

Subjects/Keywords: Pavlovian classical conditioning; automation; learning; Drosophila; memory

…This system was developed at Broadie Laboratory of Vanderbilt University. In the second part… …developed at the Broadie Laboratory of Vanderbilt University. The automated system was designed… 

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APA (6th Edition):

Jiang, H. (2015). Drosophila Automated Olfactory Training and Testing System for Associative Learning. (Masters Thesis). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu//available/etd-01122015-133013/ ;

Chicago Manual of Style (16th Edition):

Jiang, Hui. “Drosophila Automated Olfactory Training and Testing System for Associative Learning.” 2015. Masters Thesis, Vanderbilt University. Accessed October 23, 2019. http://etd.library.vanderbilt.edu//available/etd-01122015-133013/ ;.

MLA Handbook (7th Edition):

Jiang, Hui. “Drosophila Automated Olfactory Training and Testing System for Associative Learning.” 2015. Web. 23 Oct 2019.

Vancouver:

Jiang H. Drosophila Automated Olfactory Training and Testing System for Associative Learning. [Internet] [Masters thesis]. Vanderbilt University; 2015. [cited 2019 Oct 23]. Available from: http://etd.library.vanderbilt.edu//available/etd-01122015-133013/ ;.

Council of Science Editors:

Jiang H. Drosophila Automated Olfactory Training and Testing System for Associative Learning. [Masters Thesis]. Vanderbilt University; 2015. Available from: http://etd.library.vanderbilt.edu//available/etd-01122015-133013/ ;

22. Reece, Trey. Assessing and Detecting Malicious Hardware in Integrated Circuits.

Degree: PhD, Electrical Engineering, 2014, Vanderbilt University

 System security often focuses on the software, causing hardware security to be overlooked. Such oversight allows for attacks that can completely undermine the use of… (more)

Subjects/Keywords: integrated circuit design; vlsi; hardware trojan; hardware security; verification

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APA (6th Edition):

Reece, T. (2014). Assessing and Detecting Malicious Hardware in Integrated Circuits. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-12052014-031031/ ;

Chicago Manual of Style (16th Edition):

Reece, Trey. “Assessing and Detecting Malicious Hardware in Integrated Circuits.” 2014. Doctoral Dissertation, Vanderbilt University. Accessed October 23, 2019. http://etd.library.vanderbilt.edu/available/etd-12052014-031031/ ;.

MLA Handbook (7th Edition):

Reece, Trey. “Assessing and Detecting Malicious Hardware in Integrated Circuits.” 2014. Web. 23 Oct 2019.

Vancouver:

Reece T. Assessing and Detecting Malicious Hardware in Integrated Circuits. [Internet] [Doctoral dissertation]. Vanderbilt University; 2014. [cited 2019 Oct 23]. Available from: http://etd.library.vanderbilt.edu/available/etd-12052014-031031/ ;.

Council of Science Editors:

Reece T. Assessing and Detecting Malicious Hardware in Integrated Circuits. [Doctoral Dissertation]. Vanderbilt University; 2014. Available from: http://etd.library.vanderbilt.edu/available/etd-12052014-031031/ ;

23. Rong, Guoguang. Label-free Nanoscale Biosensing using a Porous Silicon Waveguide.

Degree: PhD, Electrical Engineering, 2008, Vanderbilt University

 The need to develop highly sensitive, selective, and cost-effective biosensors spans the areas of medicine, the environment, food safety, and homeland security. Accurate and reliable… (more)

Subjects/Keywords: Biosensors  – Design and construction; nanoscale; high sensitivity; label-free; optical; Porous silicon; Wave guides  – Design and construction

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APA (6th Edition):

Rong, G. (2008). Label-free Nanoscale Biosensing using a Porous Silicon Waveguide. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-08222008-141939/ ;

Chicago Manual of Style (16th Edition):

Rong, Guoguang. “Label-free Nanoscale Biosensing using a Porous Silicon Waveguide.” 2008. Doctoral Dissertation, Vanderbilt University. Accessed October 23, 2019. http://etd.library.vanderbilt.edu/available/etd-08222008-141939/ ;.

MLA Handbook (7th Edition):

Rong, Guoguang. “Label-free Nanoscale Biosensing using a Porous Silicon Waveguide.” 2008. Web. 23 Oct 2019.

Vancouver:

Rong G. Label-free Nanoscale Biosensing using a Porous Silicon Waveguide. [Internet] [Doctoral dissertation]. Vanderbilt University; 2008. [cited 2019 Oct 23]. Available from: http://etd.library.vanderbilt.edu/available/etd-08222008-141939/ ;.

Council of Science Editors:

Rong G. Label-free Nanoscale Biosensing using a Porous Silicon Waveguide. [Doctoral Dissertation]. Vanderbilt University; 2008. Available from: http://etd.library.vanderbilt.edu/available/etd-08222008-141939/ ;

24. Wei, Xing. Porous silicon waveguide biosensors with a grating coupler.

Degree: PhD, Electrical Engineering, 2012, Vanderbilt University

 Sensitive label-free optical biosensors based on grating-coupled porous silicon (PSi) waveguides are demonstrated for biosensing applications. This is the first time that the benefits of… (more)

Subjects/Keywords: gratings; optical biosensor; Porous silicon; waveguide

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APA (6th Edition):

Wei, X. (2012). Porous silicon waveguide biosensors with a grating coupler. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-03262012-231223/ ;

Chicago Manual of Style (16th Edition):

Wei, Xing. “Porous silicon waveguide biosensors with a grating coupler.” 2012. Doctoral Dissertation, Vanderbilt University. Accessed October 23, 2019. http://etd.library.vanderbilt.edu/available/etd-03262012-231223/ ;.

MLA Handbook (7th Edition):

Wei, Xing. “Porous silicon waveguide biosensors with a grating coupler.” 2012. Web. 23 Oct 2019.

Vancouver:

Wei X. Porous silicon waveguide biosensors with a grating coupler. [Internet] [Doctoral dissertation]. Vanderbilt University; 2012. [cited 2019 Oct 23]. Available from: http://etd.library.vanderbilt.edu/available/etd-03262012-231223/ ;.

Council of Science Editors:

Wei X. Porous silicon waveguide biosensors with a grating coupler. [Doctoral Dissertation]. Vanderbilt University; 2012. Available from: http://etd.library.vanderbilt.edu/available/etd-03262012-231223/ ;

25. Raina, Supil. Nanodiamond macroelectrodes and ultramicroelectrode arrays for bio-analyte detection.

Degree: PhD, Interdisciplinary Materials Science, 2011, Vanderbilt University

 Properties such as high electrical conductivity; chemical and electrochemical stability over a wide range of conditions; rapid electron transfer kinetics for different redox systems; and… (more)

Subjects/Keywords: fast scan cyclic voltammetry; diffusion; electrochemistry; dopamine; nanodiamond

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APA (6th Edition):

Raina, S. (2011). Nanodiamond macroelectrodes and ultramicroelectrode arrays for bio-analyte detection. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu//available/etd-11012011-163309/ ;

Chicago Manual of Style (16th Edition):

Raina, Supil. “Nanodiamond macroelectrodes and ultramicroelectrode arrays for bio-analyte detection.” 2011. Doctoral Dissertation, Vanderbilt University. Accessed October 23, 2019. http://etd.library.vanderbilt.edu//available/etd-11012011-163309/ ;.

MLA Handbook (7th Edition):

Raina, Supil. “Nanodiamond macroelectrodes and ultramicroelectrode arrays for bio-analyte detection.” 2011. Web. 23 Oct 2019.

Vancouver:

Raina S. Nanodiamond macroelectrodes and ultramicroelectrode arrays for bio-analyte detection. [Internet] [Doctoral dissertation]. Vanderbilt University; 2011. [cited 2019 Oct 23]. Available from: http://etd.library.vanderbilt.edu//available/etd-11012011-163309/ ;.

Council of Science Editors:

Raina S. Nanodiamond macroelectrodes and ultramicroelectrode arrays for bio-analyte detection. [Doctoral Dissertation]. Vanderbilt University; 2011. Available from: http://etd.library.vanderbilt.edu//available/etd-11012011-163309/ ;

26. Kauppila, Jeffrey Scott. Layout-Aware Modeling and Analysis Methodologies for Transient Radiation Effects on Integrated Circuit Electronics.

Degree: PhD, Electrical Engineering, 2015, Vanderbilt University

 The development of integrated circuits intended for use in transient radiation environments must account for the impact of the environment on the operation of the… (more)

Subjects/Keywords: CAD Tools; Semiconductor Device Modeling; Process Design Kit; Gummel Poon; BSIMSOI; MEXTRAM; Radiation Modeling; TCAD; BSIM4; Bias-Dependent Modeling; Dose Rate Effects; Compact Models; Single Event Effects; Compact Model; BJT; MOSFET; Layout-Aware Modeling; Layout-Aware Analysis; SPICE; Layout; Radiation Effects; Circuit Simulation; Radiation-Enabled Model; Single-Event Transient; Single-Event Upset; Charge Sharing; Computational Modeling

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APA (6th Edition):

Kauppila, J. S. (2015). Layout-Aware Modeling and Analysis Methodologies for Transient Radiation Effects on Integrated Circuit Electronics. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-03152015-142439/ ;

Chicago Manual of Style (16th Edition):

Kauppila, Jeffrey Scott. “Layout-Aware Modeling and Analysis Methodologies for Transient Radiation Effects on Integrated Circuit Electronics.” 2015. Doctoral Dissertation, Vanderbilt University. Accessed October 23, 2019. http://etd.library.vanderbilt.edu/available/etd-03152015-142439/ ;.

MLA Handbook (7th Edition):

Kauppila, Jeffrey Scott. “Layout-Aware Modeling and Analysis Methodologies for Transient Radiation Effects on Integrated Circuit Electronics.” 2015. Web. 23 Oct 2019.

Vancouver:

Kauppila JS. Layout-Aware Modeling and Analysis Methodologies for Transient Radiation Effects on Integrated Circuit Electronics. [Internet] [Doctoral dissertation]. Vanderbilt University; 2015. [cited 2019 Oct 23]. Available from: http://etd.library.vanderbilt.edu/available/etd-03152015-142439/ ;.

Council of Science Editors:

Kauppila JS. Layout-Aware Modeling and Analysis Methodologies for Transient Radiation Effects on Integrated Circuit Electronics. [Doctoral Dissertation]. Vanderbilt University; 2015. Available from: http://etd.library.vanderbilt.edu/available/etd-03152015-142439/ ;

27. Chatterjee, Indranil. Geometric Dependence of the Total Ionizing Dose Response of FinFETs.

Degree: PhD, Electrical Engineering, 2014, Vanderbilt University

 The total ionizing dose induced degradation in advanced deep-submicron CMOS technologies has been significantly reduced by scaling. Damage to isolating field oxides remains a significant… (more)

Subjects/Keywords: Total dose effects; Isolation oxides; Bulk FinFET; SOI FinFET; Parasitic transistor; Oxide traps; Charge trapping

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APA (6th Edition):

Chatterjee, I. (2014). Geometric Dependence of the Total Ionizing Dose Response of FinFETs. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-07312014-201221/ ;

Chicago Manual of Style (16th Edition):

Chatterjee, Indranil. “Geometric Dependence of the Total Ionizing Dose Response of FinFETs.” 2014. Doctoral Dissertation, Vanderbilt University. Accessed October 23, 2019. http://etd.library.vanderbilt.edu/available/etd-07312014-201221/ ;.

MLA Handbook (7th Edition):

Chatterjee, Indranil. “Geometric Dependence of the Total Ionizing Dose Response of FinFETs.” 2014. Web. 23 Oct 2019.

Vancouver:

Chatterjee I. Geometric Dependence of the Total Ionizing Dose Response of FinFETs. [Internet] [Doctoral dissertation]. Vanderbilt University; 2014. [cited 2019 Oct 23]. Available from: http://etd.library.vanderbilt.edu/available/etd-07312014-201221/ ;.

Council of Science Editors:

Chatterjee I. Geometric Dependence of the Total Ionizing Dose Response of FinFETs. [Doctoral Dissertation]. Vanderbilt University; 2014. Available from: http://etd.library.vanderbilt.edu/available/etd-07312014-201221/ ;

28. Jagannathan, Srikanth. TID characterization of high frequency RF circuits in NANO-CMOS technologies.

Degree: PhD, Electrical Engineering, 2013, Vanderbilt University

 Rapid downscaling of CMOS technology has resulted in significant improvement in the RF performance of Silicon MOSFETs. As a result, standard CMOS technology has become… (more)

Subjects/Keywords: RF; TID

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APA (6th Edition):

Jagannathan, S. (2013). TID characterization of high frequency RF circuits in NANO-CMOS technologies. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu//available/etd-11152013-150900/ ;

Chicago Manual of Style (16th Edition):

Jagannathan, Srikanth. “TID characterization of high frequency RF circuits in NANO-CMOS technologies.” 2013. Doctoral Dissertation, Vanderbilt University. Accessed October 23, 2019. http://etd.library.vanderbilt.edu//available/etd-11152013-150900/ ;.

MLA Handbook (7th Edition):

Jagannathan, Srikanth. “TID characterization of high frequency RF circuits in NANO-CMOS technologies.” 2013. Web. 23 Oct 2019.

Vancouver:

Jagannathan S. TID characterization of high frequency RF circuits in NANO-CMOS technologies. [Internet] [Doctoral dissertation]. Vanderbilt University; 2013. [cited 2019 Oct 23]. Available from: http://etd.library.vanderbilt.edu//available/etd-11152013-150900/ ;.

Council of Science Editors:

Jagannathan S. TID characterization of high frequency RF circuits in NANO-CMOS technologies. [Doctoral Dissertation]. Vanderbilt University; 2013. Available from: http://etd.library.vanderbilt.edu//available/etd-11152013-150900/ ;

29. Amusan, Oluwole Ayodele. Effects of single-event-induced charge sharing in sub-100 nm bulk CMOS technologies.

Degree: PhD, Electrical Engineering, 2009, Vanderbilt University

 Sub-100 nm technologies are more vulnerable than older technologies to single event effects (SEE) due to Moore's Law scaling trend. The increased SEE vulnerability has… (more)

Subjects/Keywords: nodal spacing; single event circuit characterization; soft error cross-section; pulse-widths; guard-bands; Dual Interlocked Cell (DICE) latch; Radiation hardening; Space environment; charge sharing mitigation; heavy-ion; guard-rings; Metal oxide semiconductors Complementary  – Effect of radiation on

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APA (6th Edition):

Amusan, O. A. (2009). Effects of single-event-induced charge sharing in sub-100 nm bulk CMOS technologies. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-02162009-141344/ ;

Chicago Manual of Style (16th Edition):

Amusan, Oluwole Ayodele. “Effects of single-event-induced charge sharing in sub-100 nm bulk CMOS technologies.” 2009. Doctoral Dissertation, Vanderbilt University. Accessed October 23, 2019. http://etd.library.vanderbilt.edu/available/etd-02162009-141344/ ;.

MLA Handbook (7th Edition):

Amusan, Oluwole Ayodele. “Effects of single-event-induced charge sharing in sub-100 nm bulk CMOS technologies.” 2009. Web. 23 Oct 2019.

Vancouver:

Amusan OA. Effects of single-event-induced charge sharing in sub-100 nm bulk CMOS technologies. [Internet] [Doctoral dissertation]. Vanderbilt University; 2009. [cited 2019 Oct 23]. Available from: http://etd.library.vanderbilt.edu/available/etd-02162009-141344/ ;.

Council of Science Editors:

Amusan OA. Effects of single-event-induced charge sharing in sub-100 nm bulk CMOS technologies. [Doctoral Dissertation]. Vanderbilt University; 2009. Available from: http://etd.library.vanderbilt.edu/available/etd-02162009-141344/ ;

30. Balasubramanian, Anupama. Measurement and analysis of single event induced crosstalk in nanoscale cmos technologies.

Degree: PhD, Electrical Engineering, 2008, Vanderbilt University

 The constant race for increasing the chip density in semiconductor integrated circuits has not only decreased the minimum device feature size but also the minimum… (more)

Subjects/Keywords: INTERCONNECT; RADIATION; CROSSTALK; SINGLE EVENT; CMOS; SIMULATION; 3D TCAD

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APA (6th Edition):

Balasubramanian, A. (2008). Measurement and analysis of single event induced crosstalk in nanoscale cmos technologies. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-08202008-122228/ ;

Chicago Manual of Style (16th Edition):

Balasubramanian, Anupama. “Measurement and analysis of single event induced crosstalk in nanoscale cmos technologies.” 2008. Doctoral Dissertation, Vanderbilt University. Accessed October 23, 2019. http://etd.library.vanderbilt.edu/available/etd-08202008-122228/ ;.

MLA Handbook (7th Edition):

Balasubramanian, Anupama. “Measurement and analysis of single event induced crosstalk in nanoscale cmos technologies.” 2008. Web. 23 Oct 2019.

Vancouver:

Balasubramanian A. Measurement and analysis of single event induced crosstalk in nanoscale cmos technologies. [Internet] [Doctoral dissertation]. Vanderbilt University; 2008. [cited 2019 Oct 23]. Available from: http://etd.library.vanderbilt.edu/available/etd-08202008-122228/ ;.

Council of Science Editors:

Balasubramanian A. Measurement and analysis of single event induced crosstalk in nanoscale cmos technologies. [Doctoral Dissertation]. Vanderbilt University; 2008. Available from: http://etd.library.vanderbilt.edu/available/etd-08202008-122228/ ;

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