You searched for +publisher:"Vanderbilt University" +contributor:("Bharat L. Bhuva").
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Vanderbilt University
1.
Chetia, Jugantor.
An efficient AVF estimation technique using circuit partitioning.
Degree: MS, Electrical Engineering, 2012, Vanderbilt University
URL: http://etd.library.vanderbilt.edu/available/etd-01252012-174557/ 
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► Soft errors induced by radiation particles are increasingly becoming a source of concern for reliable design of VLSI systems. An important parameter to quantify the…
(more)
▼ Soft errors induced by radiation particles are increasingly becoming a source of concern for
reliable design of VLSI systems. An important parameter to quantify the soft error response of a
system is Architectural Vulnerability Factor (AVF), which is the probability that a fault in a part
of the system will result in an error. One of the most common techniques to estimate AVF of a
system is by using statistical fault injection (SFI). Traditional SFI techniques can be
computationally inefficient with increasing design complexity. In this work, a novel technique
has been developed to enable computationally efficient AVF estimation using enhanced node
observability. Possible target applications for this technique have been identified with results
showing orders of magnitude improvement over traditional SFI techniques.
Advisors/Committee Members: Lloyd W. Massengill (chair), Bharat L. Bhuva (chair).
Subjects/Keywords: AVF; statistical fault injection; circuit partitioning
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APA (6th Edition):
Chetia, J. (2012). An efficient AVF estimation technique using circuit partitioning. (Masters Thesis). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-01252012-174557/ ;
Chicago Manual of Style (16th Edition):
Chetia, Jugantor. “An efficient AVF estimation technique using circuit partitioning.” 2012. Masters Thesis, Vanderbilt University. Accessed October 23, 2019.
http://etd.library.vanderbilt.edu/available/etd-01252012-174557/ ;.
MLA Handbook (7th Edition):
Chetia, Jugantor. “An efficient AVF estimation technique using circuit partitioning.” 2012. Web. 23 Oct 2019.
Vancouver:
Chetia J. An efficient AVF estimation technique using circuit partitioning. [Internet] [Masters thesis]. Vanderbilt University; 2012. [cited 2019 Oct 23].
Available from: http://etd.library.vanderbilt.edu/available/etd-01252012-174557/ ;.
Council of Science Editors:
Chetia J. An efficient AVF estimation technique using circuit partitioning. [Masters Thesis]. Vanderbilt University; 2012. Available from: http://etd.library.vanderbilt.edu/available/etd-01252012-174557/ ;
Vanderbilt University
2.
Kou, Lingbo.
Impact of process variations on soft error sensitivity of 32-nm VLSI circuits in near-threshold region.
Degree: MS, Electrical Engineering, 2014, Vanderbilt University
URL: http://etd.library.vanderbilt.edu/available/etd-04082014-141041/
;
► Power consumption has become a major concern of integrated circuit (IC) design. Reducing the supply voltage to the near-threshold region is one method to reduce…
(more)
▼ Power consumption has become a major concern of integrated circuit (IC) design. Reducing the supply voltage to the near-threshold region is one method to reduce the power consumption. However, operating in this region makes the circuit more sensitive to process variations. In the thesis, the impact of process variations on a 32-nm 6T SRAM cell and two kinds of flip-flops (transmission gate flip-flop and clocked CMOS flip-flop) under near-threshold voltage is studied. Monte Carlo method is used to evaluate the potential of the circuits for soft errors. The double exponential current source is used to simulate the strike of an ionizing particle. For the SRAM cell, the results show that threshold voltage variability is a more significant parameter affecting the critical charge distribution of the circuit under both the near-threshold voltage and the nominal supply voltage. For the flip-flops, the reduced supply voltage has little impact on the critical charge variation induced by process variations. Moreover, the near-threshold operation has much smaller leakage power than the nominal supply voltage. However, the delay time of the circuits is also greatly increased in near-threshold region.
Advisors/Committee Members: William H. Robinson (chair), Bharat L. Bhuva (chair).
Subjects/Keywords: flip-flop; radiation-induced soft errors; sram; near-threshold voltage; critical charge; process variations; reliability
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APA (6th Edition):
Kou, L. (2014). Impact of process variations on soft error sensitivity of 32-nm VLSI circuits in near-threshold region. (Masters Thesis). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-04082014-141041/ ;
Chicago Manual of Style (16th Edition):
Kou, Lingbo. “Impact of process variations on soft error sensitivity of 32-nm VLSI circuits in near-threshold region.” 2014. Masters Thesis, Vanderbilt University. Accessed October 23, 2019.
http://etd.library.vanderbilt.edu/available/etd-04082014-141041/ ;.
MLA Handbook (7th Edition):
Kou, Lingbo. “Impact of process variations on soft error sensitivity of 32-nm VLSI circuits in near-threshold region.” 2014. Web. 23 Oct 2019.
Vancouver:
Kou L. Impact of process variations on soft error sensitivity of 32-nm VLSI circuits in near-threshold region. [Internet] [Masters thesis]. Vanderbilt University; 2014. [cited 2019 Oct 23].
Available from: http://etd.library.vanderbilt.edu/available/etd-04082014-141041/ ;.
Council of Science Editors:
Kou L. Impact of process variations on soft error sensitivity of 32-nm VLSI circuits in near-threshold region. [Masters Thesis]. Vanderbilt University; 2014. Available from: http://etd.library.vanderbilt.edu/available/etd-04082014-141041/ ;
Vanderbilt University
3.
Kay, William Hunter.
Single-Event Upset Characterization of Flip-Flops Across Temperature and Supply Voltage for a 20-nm Bulk, Planar, CMOS Technology.
Degree: MS, Electrical Engineering, 2015, Vanderbilt University
URL: http://etd.library.vanderbilt.edu/available/etd-03302015-133003/
;
► The scaling of CMOS technology has brought about the increased susceptibility of circuits to single-event (SE) effects. Electronic systems operating in space often face extreme…
(more)
▼ The scaling of CMOS technology has brought about the increased susceptibility of circuits to single-event (SE) effects. Electronic systems operating in space often face extreme temperature conditions and high levels of radioactivity. Additionally, power management for space systems may require electronic circuits to operate at a lower than nominal supply voltage. Lowering the supply voltage results in decreased critical charge for storage cells, ultimately increasing SE failure rates. The combined effects of radiation, reduced voltage, and temperature may reduce the operating margin for circuit-level parameters, causing unexpected failures. This warrants further investigation into the SE effects of over a range of temperatures and reduced bias. Previous studies investigating the relationship between temperature and single-event transient (SET) pulse width have concluded that the SE response is dominated by parasitic bipolar effects. However, these bipolar effects are only triggered by high linear energy transfer (LET) particles which are relatively uncommon compared to the number of low LET particles typically encountered in space and terrestrial environments. In the absence of parasitic bipolar effects, other mechanisms such as modulation of carrier mobilities will dominate the SE response of circuits in high temperature environments. Therefore, this work addresses temperature effects on SE cross-sections for flip flops at the 20-nm technology node using low LET alpha particles. Experimental results indicate that cross-sections vary by up to 700% due to the temperature dependence of carrier mobilities. This trend holds true for a number of different flip flop designs with a range of radiation hardness.
Advisors/Committee Members: Dr. Bharat L. Bhuva (committee member), Dr. W. Timothy Holman (committee member).
Subjects/Keywords: flip flop; 20 nm; single event; SET; SEE; SEU
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APA (6th Edition):
Kay, W. H. (2015). Single-Event Upset Characterization of Flip-Flops Across Temperature and Supply Voltage for a 20-nm Bulk, Planar, CMOS Technology. (Masters Thesis). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-03302015-133003/ ;
Chicago Manual of Style (16th Edition):
Kay, William Hunter. “Single-Event Upset Characterization of Flip-Flops Across Temperature and Supply Voltage for a 20-nm Bulk, Planar, CMOS Technology.” 2015. Masters Thesis, Vanderbilt University. Accessed October 23, 2019.
http://etd.library.vanderbilt.edu/available/etd-03302015-133003/ ;.
MLA Handbook (7th Edition):
Kay, William Hunter. “Single-Event Upset Characterization of Flip-Flops Across Temperature and Supply Voltage for a 20-nm Bulk, Planar, CMOS Technology.” 2015. Web. 23 Oct 2019.
Vancouver:
Kay WH. Single-Event Upset Characterization of Flip-Flops Across Temperature and Supply Voltage for a 20-nm Bulk, Planar, CMOS Technology. [Internet] [Masters thesis]. Vanderbilt University; 2015. [cited 2019 Oct 23].
Available from: http://etd.library.vanderbilt.edu/available/etd-03302015-133003/ ;.
Council of Science Editors:
Kay WH. Single-Event Upset Characterization of Flip-Flops Across Temperature and Supply Voltage for a 20-nm Bulk, Planar, CMOS Technology. [Masters Thesis]. Vanderbilt University; 2015. Available from: http://etd.library.vanderbilt.edu/available/etd-03302015-133003/ ;
Vanderbilt University
4.
Gadlage, Matthew John.
Impact of Temperature on Single-Event Transients in Deep Submicrometer Bulk and Silicon-On-Insulator Digital CMOS Technologies.
Degree: PhD, Electrical Engineering, 2010, Vanderbilt University
URL: http://etd.library.vanderbilt.edu/available/etd-03262010-102121/
;
► Single-event transients (SETs) are a significant reliability issue for space-based electronic systems. A single-event transient is a radiation-induced glitch in an electronic circuit caused by…
(more)
▼ Single-event transients (SETs) are a significant reliability issue for space-based electronic systems. A single-event transient is a radiation-induced glitch in an electronic circuit caused by an ionizing particle. While there has been a large amount of research published on SETs, one key aspect that has been mostly ignored has been the impact of temperature on the time duration of these transients. Since the temperature ranges over which some space missions need to operate can be extreme, the role of temperature for all radiation effects is of vital importance for space systems. However, to understand fully how temperature will impact SETs, a complete understanding of SETs at room temperature is first needed. In this dissertation, heavy-ion data on ten SET test structures fabricated in a myriad of semiconductor technologies are presented. The data from these test structures give valuable insight into how the SET problem is changing with each technology node and how temperature affects the time duration of SETs.
Advisors/Committee Members: Ronald D. Schrimpf (chair), Bharat L. Bhuva (chair), Robert A. Reed (committee member), W. Timothy Holman (committee member), Senta V. Greene (committee member).
Subjects/Keywords: radiation effects; space environment; soft errors; heavy ions; single event effects; single event transients; silicon-on-insulator; temperature
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APA (6th Edition):
Gadlage, M. J. (2010). Impact of Temperature on Single-Event Transients in Deep Submicrometer Bulk and Silicon-On-Insulator Digital CMOS Technologies. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-03262010-102121/ ;
Chicago Manual of Style (16th Edition):
Gadlage, Matthew John. “Impact of Temperature on Single-Event Transients in Deep Submicrometer Bulk and Silicon-On-Insulator Digital CMOS Technologies.” 2010. Doctoral Dissertation, Vanderbilt University. Accessed October 23, 2019.
http://etd.library.vanderbilt.edu/available/etd-03262010-102121/ ;.
MLA Handbook (7th Edition):
Gadlage, Matthew John. “Impact of Temperature on Single-Event Transients in Deep Submicrometer Bulk and Silicon-On-Insulator Digital CMOS Technologies.” 2010. Web. 23 Oct 2019.
Vancouver:
Gadlage MJ. Impact of Temperature on Single-Event Transients in Deep Submicrometer Bulk and Silicon-On-Insulator Digital CMOS Technologies. [Internet] [Doctoral dissertation]. Vanderbilt University; 2010. [cited 2019 Oct 23].
Available from: http://etd.library.vanderbilt.edu/available/etd-03262010-102121/ ;.
Council of Science Editors:
Gadlage MJ. Impact of Temperature on Single-Event Transients in Deep Submicrometer Bulk and Silicon-On-Insulator Digital CMOS Technologies. [Doctoral Dissertation]. Vanderbilt University; 2010. Available from: http://etd.library.vanderbilt.edu/available/etd-03262010-102121/ ;
Vanderbilt University
5.
Olson, Brian David.
Single-Event Effect Mitigation in Pipelined Analog-to-Digital Converters.
Degree: PhD, Electrical Engineering, 2010, Vanderbilt University
URL: http://etd.library.vanderbilt.edu/available/etd-12102010-152348/
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► Analog-to-digital converters (ADCs) are necessary circuits in many space, military, and medical circuit applications. Intelligence, surveillance, reconnaissance, and communication missions all require high performance ADCs.…
(more)
▼ Analog-to-digital converters (ADCs) are necessary circuits in many space, military, and medical circuit applications. Intelligence, surveillance, reconnaissance, and communication missions all require high performance ADCs. Speed, resolution, and power are concerns in high performance designs. Unlike commercial applications, space, military, and some medical electronics must also be able to function in a radiation environment. This additional complexity provides an interesting and needed area of research.
The goal of this work is to understand single event effects (SEEs) in high-speed ADCs, so the impact of design topologies and mitigation techniques can be evaluated for Department of Defense (DOD) or commercial space deployment. This goal is broken into two parts. The first part characterizes and explains the single event effect response, and presents a novel method of evaluating SEEs in ADCs through the use of frequency domain analysis. The second part provides additional circuit design alternatives for hardening pipelined ADCs: the use of comparator triple modular redundancy or robust encoder logic in the front pipeline stages, dual-path hardening in switched-capacitor sub-circuits, and applying analog layout techniques to all transistors-pairs along the fully-differential signal path. The conclusion of this work helps designers achieve ADCs for the next generation applications, influence experimental testing methodologies, and applies to other high-speed mixed signal applications.
Advisors/Committee Members: Dale McMorrow (committee member), Lloyd W. Massengill (chair), W. Timothy Holman (committee member), Bharat L. Bhuva (committee member), Arthur F. Witulski (committee member).
Subjects/Keywords: single-events; SEU; SEE; RHBD; radiation hardened by design; ADC; single-event effects; analog-to-digital converters
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APA (6th Edition):
Olson, B. D. (2010). Single-Event Effect Mitigation in Pipelined Analog-to-Digital Converters. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-12102010-152348/ ;
Chicago Manual of Style (16th Edition):
Olson, Brian David. “Single-Event Effect Mitigation in Pipelined Analog-to-Digital Converters.” 2010. Doctoral Dissertation, Vanderbilt University. Accessed October 23, 2019.
http://etd.library.vanderbilt.edu/available/etd-12102010-152348/ ;.
MLA Handbook (7th Edition):
Olson, Brian David. “Single-Event Effect Mitigation in Pipelined Analog-to-Digital Converters.” 2010. Web. 23 Oct 2019.
Vancouver:
Olson BD. Single-Event Effect Mitigation in Pipelined Analog-to-Digital Converters. [Internet] [Doctoral dissertation]. Vanderbilt University; 2010. [cited 2019 Oct 23].
Available from: http://etd.library.vanderbilt.edu/available/etd-12102010-152348/ ;.
Council of Science Editors:
Olson BD. Single-Event Effect Mitigation in Pipelined Analog-to-Digital Converters. [Doctoral Dissertation]. Vanderbilt University; 2010. Available from: http://etd.library.vanderbilt.edu/available/etd-12102010-152348/ ;
Vanderbilt University
6.
Hsu, Shao-Hua.
Development of Vertical Nanodiamond Vacuum Field Emission Microelectronic Integrated Devices.
Degree: PhD, Electrical Engineering, 2014, Vanderbilt University
URL: http://etd.library.vanderbilt.edu/available/etd-02272014-153712/
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► Recent development of nanocrystalline diamonds has demonstrated the potential use of diamond material for vacuum microelectronics. Apart from the advantages of conventional microcrystalline diamond, nanodiamond…
(more)
▼ Recent development of nanocrystalline diamonds has demonstrated the potential use of diamond material for vacuum microelectronics. Apart from the advantages of conventional microcrystalline diamond, nanodiamond with smaller grain size and smoother surface morphology possesses unique properties including the insertion of deliberate amounts of sp2-carbon into the sp3-diamond matrix and controlled electrical conductivity, expanding its utility for practical applications. This research is focused on the design, fabrication, and characterization of nitrogen-incorporated nanodiamond vacuum field emission (VFE) functional devices and integrated circuits, specifically on vertically configured VFE transistors, triodes, and differential amplifiers (diff-amps).
A well-controlled and IC-compatible fabrication process has been developed to achieve three-terminal nanodiamond VFE integrated devices for vacuum micro/nanoelectronics. The nanodiamond pyramidal sharpened nanotips built with self-aligned silicon gate and anode electrodes were fabricated by employing a dual-mask microfabrication process which involved a silicon-on-insulator (SOI) mold transfer technique in collaboration with chemical vapor deposition (CVD) of nanodiamond and silicon gate partitioning. With proper design of the electrodes placement, the fabricated VFE functional devices have achieved transistor and triode characteristics, and they have been further implemented into vacuum integrated circuit building block â differential amplifiers.
The nanodiamond VFE transistors and triodes demonstrate efficient gate-modulated electron field emission behavior with low operating voltages, high emission current, and negligible gate intercepted current. The dc characteristics of the transistor demonstrate distinct linear, saturation and cutoff regions with low turn-on gate voltage and high amplification factor. The triode demonstrates high emission current with efficient current modulation by low gate voltages. The ac signal amplification performance has been evaluated, indicating the applicability of nanodiamond VFE transistors and triodes as signal amplifiers and buffer amplifiers, respectively. An identical pair of nanodiamond VFE transistors with well-matched field emission characteristics was constructed and employed to accomplish a nanodiamond VFE diff-amp for the first time. A large common-mode-rejection ratio (~ 60 dB) was realized, demonstrating a viable approach to vacuum-based IC technology. These achievements signify the fundamental step for further development of vacuum integrated micro/nanoelectronics for practical applications, including high-speed, high-power and extreme-environment electronics.
Advisors/Committee Members: Prof. Ralph W. Bruce (committee member), Prof. Weng P. Kang (chair), Prof. Bharat L. Bhuva (committee member), Prof. Yaqiong Xu (committee member), Prof. Deyu Li (committee member).
Subjects/Keywords: Microelectronic Devices; Nanodiamond; Vacuum Field Emission; Integrated Circuits; Signal Amplifiers
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APA (6th Edition):
Hsu, S. (2014). Development of Vertical Nanodiamond Vacuum Field Emission Microelectronic Integrated Devices. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-02272014-153712/ ;
Chicago Manual of Style (16th Edition):
Hsu, Shao-Hua. “Development of Vertical Nanodiamond Vacuum Field Emission Microelectronic Integrated Devices.” 2014. Doctoral Dissertation, Vanderbilt University. Accessed October 23, 2019.
http://etd.library.vanderbilt.edu/available/etd-02272014-153712/ ;.
MLA Handbook (7th Edition):
Hsu, Shao-Hua. “Development of Vertical Nanodiamond Vacuum Field Emission Microelectronic Integrated Devices.” 2014. Web. 23 Oct 2019.
Vancouver:
Hsu S. Development of Vertical Nanodiamond Vacuum Field Emission Microelectronic Integrated Devices. [Internet] [Doctoral dissertation]. Vanderbilt University; 2014. [cited 2019 Oct 23].
Available from: http://etd.library.vanderbilt.edu/available/etd-02272014-153712/ ;.
Council of Science Editors:
Hsu S. Development of Vertical Nanodiamond Vacuum Field Emission Microelectronic Integrated Devices. [Doctoral Dissertation]. Vanderbilt University; 2014. Available from: http://etd.library.vanderbilt.edu/available/etd-02272014-153712/ ;
Vanderbilt University
7.
Kiddie, Bradley Thomas.
Single-Event Multiple-Transient Characterization and Mitigation via Standard Cell Placement Methods.
Degree: PhD, Electrical Engineering, 2016, Vanderbilt University
URL: http://etd.library.vanderbilt.edu/available/etd-09282016-101105/
;
► The effects of radiation on the operation of integrated circuits (IC) continue to take a more important role as technology feature sizes scale down, critical…
(more)
▼ The effects of radiation on the operation of integrated circuits (IC) continue to take a more important role as technology feature sizes scale down, critical charge decreases, and operating frequencies increase. In space and other harsh environments, single ion strikes are more likely to affect multiple, physically-adjacent devices on a modern IC, thereby introducing formidable research problems for (1) modeling these effects and (2) designing circuits to mitigate them. While single-event transient (SET) behavior traditionally has been well characterized, single-event multiple-transients (SEMT) require a more complex and novel approach to capture reliability characteristics with tenable simulation times prior to chip manufacturing.
This dissertation presents an automated method to quickly characterize modern combinational logic blocks for radiation-induced SEMT vulnerability. Radiation events are modeled based on physically-observed effects, and then integrated into an electronic design automation (EDA) functional verification flow for ease of implementation. When considering the placement of standard logic cells, SEMT modeling reveals the impact on charge sharing and diffusion, and consequently reliability of logic circuits in the presence of multiple transients. Modifications to standard cell placement are investigated, and a new EDA placement algorithm is developed and implemented to achieve reductions in SEMT-induced errors with zero cost to circuit area and minimal effects on other circuit performance characteristics.
Advisors/Committee Members: William H. Robinson (chair), Bharat L. Bhuva (committee member), Ronald D. Schrimpf (committee member), Gabor Karsai (committee member), Mark N. Ellingham (committee member).
Subjects/Keywords: reliability; radiation; eda; single-event transient; single-event multiple-transient; placement; algorithm
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APA (6th Edition):
Kiddie, B. T. (2016). Single-Event Multiple-Transient Characterization and Mitigation via Standard Cell Placement Methods. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-09282016-101105/ ;
Chicago Manual of Style (16th Edition):
Kiddie, Bradley Thomas. “Single-Event Multiple-Transient Characterization and Mitigation via Standard Cell Placement Methods.” 2016. Doctoral Dissertation, Vanderbilt University. Accessed October 23, 2019.
http://etd.library.vanderbilt.edu/available/etd-09282016-101105/ ;.
MLA Handbook (7th Edition):
Kiddie, Bradley Thomas. “Single-Event Multiple-Transient Characterization and Mitigation via Standard Cell Placement Methods.” 2016. Web. 23 Oct 2019.
Vancouver:
Kiddie BT. Single-Event Multiple-Transient Characterization and Mitigation via Standard Cell Placement Methods. [Internet] [Doctoral dissertation]. Vanderbilt University; 2016. [cited 2019 Oct 23].
Available from: http://etd.library.vanderbilt.edu/available/etd-09282016-101105/ ;.
Council of Science Editors:
Kiddie BT. Single-Event Multiple-Transient Characterization and Mitigation via Standard Cell Placement Methods. [Doctoral Dissertation]. Vanderbilt University; 2016. Available from: http://etd.library.vanderbilt.edu/available/etd-09282016-101105/ ;
Vanderbilt University
8.
Jiang, Hui.
Design of soft-error-aware sequential circuits with power and speed optimization.
Degree: PhD, Electrical Engineering, 2018, Vanderbilt University
URL: http://etd.library.vanderbilt.edu/available/etd-03192018-153616/
;
► A single-event effect (SEE) of circuits is strongly dependent on the supply voltage and the physical capacitance. Reduction in supply voltage as well as technology…
(more)
▼ A single-event effect (SEE) of circuits is strongly dependent on the supply voltage and the physical capacitance. Reduction in supply voltage as well as technology scaling trends (smaller nodal capacitances) may result in dramatically increased sensitivity of the circuits to radiation. For this reason, SEE are especially considered challenges for low-power and high performance circuits. Hence, it is imperative to consider the SEE induced errors of the low power and high performance design when designing circuits for applications requiring high reliability.
In this proposed research, a methodology to bridge the gap between experimental results and predictive models for SEE performance of sequential logic circuits have been developed. A study of the relationship between circuit SEE tolerance and power consumption is performed using this methodology. The purpose is to build a framework of designing soft-error-aware sequential circuits with power and speed optimization. A figure-of-merit (FOM) is provided for designers to make informed decisions on meeting power, speed, and SE specifications after the proposed framework. To comprehensively comment on the design parameters of different sequential logic circuits, a FOM is defined as the inverse of the product of power and SE cross-section (PCSP-1). Since minimization of power and SE cross-section is desirable, a lower PCSP value and thus a higher FOM value can be considered to be an indicator of an optimized design. This work focuses on the study of both power consumption and SEE tolerance at device and circuit-level. Sequential circuits are used as circuit examples in this proposed research. The ultimate goal of the work is to provide designers with capabilities and FOM to choose the suitable low power and SEE tolerance design for different targeted design specifications and operating environment.
Advisors/Committee Members: Robinson H. William (committee member), Aniruddha Gokhale (committee member), Ronald D. Schrimpf (committee member), Lloyd Massengill (committee member), Bharat L. Bhuva (chair).
Subjects/Keywords: power optimization; sequential circuit; soft error rate; Single event effects; empirical model
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APA (6th Edition):
Jiang, H. (2018). Design of soft-error-aware sequential circuits with power and speed optimization. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-03192018-153616/ ;
Chicago Manual of Style (16th Edition):
Jiang, Hui. “Design of soft-error-aware sequential circuits with power and speed optimization.” 2018. Doctoral Dissertation, Vanderbilt University. Accessed October 23, 2019.
http://etd.library.vanderbilt.edu/available/etd-03192018-153616/ ;.
MLA Handbook (7th Edition):
Jiang, Hui. “Design of soft-error-aware sequential circuits with power and speed optimization.” 2018. Web. 23 Oct 2019.
Vancouver:
Jiang H. Design of soft-error-aware sequential circuits with power and speed optimization. [Internet] [Doctoral dissertation]. Vanderbilt University; 2018. [cited 2019 Oct 23].
Available from: http://etd.library.vanderbilt.edu/available/etd-03192018-153616/ ;.
Council of Science Editors:
Jiang H. Design of soft-error-aware sequential circuits with power and speed optimization. [Doctoral Dissertation]. Vanderbilt University; 2018. Available from: http://etd.library.vanderbilt.edu/available/etd-03192018-153616/ ;
Vanderbilt University
9.
Zhang, Hangfang.
Impact of Designer-Controlled Parameters on Single-Event Responses for Flip-Flop Designs in Advanced Technologies.
Degree: PhD, Electrical Engineering, 2018, Vanderbilt University
URL: http://etd.library.vanderbilt.edu/available/etd-04072018-123506/
;
► Modern ICs need to be designed with proper designer-controllable factors to meet power, speed and single-event (SE) performance requirements in different applications. Commercial fabrication houses…
(more)
▼ Modern ICs need to be designed with proper designer-controllable factors to meet power, speed and single-event (SE) performance requirements in different applications. Commercial fabrication houses have successfully transitioned to FinFET structure for advanced semiconductor processes. For FinFET technologies, since the physical structure changes significantly compared to planar technologies, the underlying charge collection mechanism at a circuit node evolves that most single-event effects need to be reevaluated for FinFET technologies. This work characterizes SE performance for flip-flop (FF) designs in a commercial 14/16-nm bulk FinFET technology from a designerâs perspective. For the first time, effects of designer-controlled parameters related to fabrication process, such as threshold voltage, dual- and triple-well processes, on SE performance and power consumption have been investigated in FinFET technologies. Theoretic analysis, simulation and experimental results are used to understand the effects of threshold voltage and well structure on SE upset responses. By comparing with former planar technologies, this work provides designers with better understanding of how SE mechanism evolves from planar to FinFET technologies, better idea of overall SE performance for FF designs and provide design guidelines for choosing proper designer-controlled parameters for specific applications in FinFET technologies.
Advisors/Committee Members: Marcelo M. Disconzi (committee member), Daniel M. Fleetwood (committee member), Bharat L. Bhuva (chair), Lloyd W. Massengill (committee member), Ronald D. Schrimpf (committee member).
Subjects/Keywords: Single Event; Threshold Voltage; FinFET; Design Parameter; Temperature; Angular Incidence; Flip-Flop; Well Structure
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APA (6th Edition):
Zhang, H. (2018). Impact of Designer-Controlled Parameters on Single-Event Responses for Flip-Flop Designs in Advanced Technologies. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-04072018-123506/ ;
Chicago Manual of Style (16th Edition):
Zhang, Hangfang. “Impact of Designer-Controlled Parameters on Single-Event Responses for Flip-Flop Designs in Advanced Technologies.” 2018. Doctoral Dissertation, Vanderbilt University. Accessed October 23, 2019.
http://etd.library.vanderbilt.edu/available/etd-04072018-123506/ ;.
MLA Handbook (7th Edition):
Zhang, Hangfang. “Impact of Designer-Controlled Parameters on Single-Event Responses for Flip-Flop Designs in Advanced Technologies.” 2018. Web. 23 Oct 2019.
Vancouver:
Zhang H. Impact of Designer-Controlled Parameters on Single-Event Responses for Flip-Flop Designs in Advanced Technologies. [Internet] [Doctoral dissertation]. Vanderbilt University; 2018. [cited 2019 Oct 23].
Available from: http://etd.library.vanderbilt.edu/available/etd-04072018-123506/ ;.
Council of Science Editors:
Zhang H. Impact of Designer-Controlled Parameters on Single-Event Responses for Flip-Flop Designs in Advanced Technologies. [Doctoral Dissertation]. Vanderbilt University; 2018. Available from: http://etd.library.vanderbilt.edu/available/etd-04072018-123506/ ;
Vanderbilt University
10.
Megat Hamari, Puteri Saidatul A.
Electrothermal Behavior of Attached and Freestanding Diamond Resistors.
Degree: PhD, Electrical Engineering, 2010, Vanderbilt University
URL: http://etd.library.vanderbilt.edu/available/etd-12022010-134653/
;
► Passive devices are micro circuit elements that play a critical role in electronic products. The extraordinary physical properties of diamond such as high thermal conductivity,…
(more)
▼ Passive devices are micro circuit elements that play a critical role in electronic products. The extraordinary physical properties of diamond such as high thermal conductivity, small thermal coefficient of expansion and hardness present intriguing possibilities for the fabrication of microstructures which benefit from an extended dynamic range, faster response, or reduced degradation. We have successfully fabricated miniature powered freestanding diamond resistors that demonstrated an ability to "glow" under power pulse loading and handle very high power density. These resistors are isolated from the substrate by a cavity. The freestanding diamond resistors were heated with voltage pulses such that the diamond resistors experienced thermal emission from Joule heating. They were examined for their electrothermal behavior including measurements of their infrared emission under power pulse loading and their dynamic thermal response. The freestanding resistors were found to withstand higher power than equivalent attached diamond resistors and could operate at power density levels well over 3x that of conventional passive power resistors.
Advisors/Committee Members: Professor Jim L. Davidson (chair), Professor Weng P. Kang (committee member), Professor Bharat L. Bhuva (committee member), Professor Norman H. Tolk (committee member), Professor Alvin M. Strauss (committee member).
Subjects/Keywords: diamond resistors; diamond thin films; chemical vapor deposition; freestanding resistor
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APA (6th Edition):
Megat Hamari, P. S. A. (2010). Electrothermal Behavior of Attached and Freestanding Diamond Resistors. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-12022010-134653/ ;
Chicago Manual of Style (16th Edition):
Megat Hamari, Puteri Saidatul A. “Electrothermal Behavior of Attached and Freestanding Diamond Resistors.” 2010. Doctoral Dissertation, Vanderbilt University. Accessed October 23, 2019.
http://etd.library.vanderbilt.edu/available/etd-12022010-134653/ ;.
MLA Handbook (7th Edition):
Megat Hamari, Puteri Saidatul A. “Electrothermal Behavior of Attached and Freestanding Diamond Resistors.” 2010. Web. 23 Oct 2019.
Vancouver:
Megat Hamari PSA. Electrothermal Behavior of Attached and Freestanding Diamond Resistors. [Internet] [Doctoral dissertation]. Vanderbilt University; 2010. [cited 2019 Oct 23].
Available from: http://etd.library.vanderbilt.edu/available/etd-12022010-134653/ ;.
Council of Science Editors:
Megat Hamari PSA. Electrothermal Behavior of Attached and Freestanding Diamond Resistors. [Doctoral Dissertation]. Vanderbilt University; 2010. Available from: http://etd.library.vanderbilt.edu/available/etd-12022010-134653/ ;
Vanderbilt University
11.
Kauppila, Amy Vaughn.
Analysis of parameter variation impact on the single event response in sub-100nm CMOS storage cells.
Degree: PhD, Electrical Engineering, 2012, Vanderbilt University
URL: http://etd.library.vanderbilt.edu/available/etd-04092012-111410/
;
► Current deep sub-micron technologies are particularly susceptible to single events. The challenge derives from a conglomeration of effects that affect circuitsâ radiation response. For instance,…
(more)
▼ Current deep sub-micron technologies are particularly susceptible to single events. The challenge derives from a conglomeration of effects
that affect circuitsâ radiation response. For instance, decreasing device size has led to decreased storage charge and increased operating
speeds. Decreased storage charge contributes to single event sensitivity since the charge deposited by the ionized particle is now more on
par with the storage node charge. The increased operating speeds increase circuit sensitivity since they are now comparable to the speed
of a single event transient. Single events are expected to dominate other reliability concerns in deep sub-micrometer devices due to
decreased transistor currents and nodal capacitances. Thus, it is vital to understand and quantify the impact of contributing mechanisms.
In addition to the challenges presented by radiation, transistor and chip design also faces a challenge from the variations that are inherent
to the manufacturing process. During chip fabrication, extreme measures are taken to ensure precision. However, variations in lithography,
random dopant fluctuations, gate depletion, surface state charge, and line-edge roughness cause changes in individual transistor behavior
and therefore, changes in the behavior-describing transistor parameters. The non-standard behavior then affects circuit performance and
therefore impacts single event response. It is anticipated that process variations will substantially increase with shrinking device sizes.
Consequently, the potential impact of process variations on SE circuit response is significant.
In order to accurately predict the single-event response of any circuit, it is necessary to identify and quantify the impact of the specific
process variations. This work correlates the shifts in radiation response to specific device and process-parameter variations by quantifying
the impact of process variability on the range of single-event upset (SEU) critical charge. Monte-Carlo simulations are leveraged to assess
the impact of process variations on SEU response. This dissertation analyzes the impact of process variations on the single-event upset
response of sub-100nm CMOS memory storage circuits.
Advisors/Committee Members: Dr. Shi-Jie [email protected] (committee member), Dr. W. Timothy Holman (committee member), Dr. Lloyd W. Massengill (committee member), Dr. Ronald D. Schrimpf (committee member), Dr. Bharat L. Bhuva (chair).
Subjects/Keywords: single event upset; parameter variation
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APA (6th Edition):
Kauppila, A. V. (2012). Analysis of parameter variation impact on the single event response in sub-100nm CMOS storage cells. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-04092012-111410/ ;
Chicago Manual of Style (16th Edition):
Kauppila, Amy Vaughn. “Analysis of parameter variation impact on the single event response in sub-100nm CMOS storage cells.” 2012. Doctoral Dissertation, Vanderbilt University. Accessed October 23, 2019.
http://etd.library.vanderbilt.edu/available/etd-04092012-111410/ ;.
MLA Handbook (7th Edition):
Kauppila, Amy Vaughn. “Analysis of parameter variation impact on the single event response in sub-100nm CMOS storage cells.” 2012. Web. 23 Oct 2019.
Vancouver:
Kauppila AV. Analysis of parameter variation impact on the single event response in sub-100nm CMOS storage cells. [Internet] [Doctoral dissertation]. Vanderbilt University; 2012. [cited 2019 Oct 23].
Available from: http://etd.library.vanderbilt.edu/available/etd-04092012-111410/ ;.
Council of Science Editors:
Kauppila AV. Analysis of parameter variation impact on the single event response in sub-100nm CMOS storage cells. [Doctoral Dissertation]. Vanderbilt University; 2012. Available from: http://etd.library.vanderbilt.edu/available/etd-04092012-111410/ ;
Vanderbilt University
12.
Assis, Thiago Rocha de.
Soft error aware physical synthesis.
Degree: PhD, Electrical Engineering, 2015, Vanderbilt University
URL: http://etd.library.vanderbilt.edu/available/etd-11242015-013303/
;
► To allow accurate analysis of Soft Errors by Electronic Design Automation (EDA) tools, analytical models were developed to estimate electrical characteristics of the single event.…
(more)
▼ To allow accurate analysis of Soft Errors by Electronic Design Automation (EDA) tools, analytical models were developed to estimate electrical characteristics of the single event. The Ambipolar-Diffusion-With-Cutoff (ADC) model was extended in this work to model charge sharing, thus allowing accurate charge estimation by EDA tools An Single Event Transient (SET) pulse width estimation methodology was developed to model the Standard Cells response to the soft error. Combining these models along with circuit masking probabilities, the circuit soft-error cross-section is estimated. These soft error models are then integrated into an automatic standard cell placement tool based on Quadratic Optimization. Results show the impact of Physical Synthesis electrical correction techniques, such as Buffering, Gate Cloning and Gate Sizing, to the circuit soft error cross-section. Furthermore, an algorithm to reduce the circuit soft error cross-section by optimizing the Tap Cell placement was also developed and demonstrated. Results from this thesis provide key insights to control the circuit soft error cross-section during the Physical Synthesis design flow for integrated circuits at the most advanced technology nodes.
Advisors/Committee Members: Dr. Bharat L. Bhuva (chair), Dr. Aniruddha S. Gokhale (committee member), Dr. Shi-Jie Wen (committee member), Dr. William H. Robinson (committee member), Dr. Ronald D. Schrimpf (committee member).
Subjects/Keywords: single event transient; set pulse width; collected charge; radiation effects; electronic design automation; physical synthesis; soft error; reliability
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APA (6th Edition):
Assis, T. R. d. (2015). Soft error aware physical synthesis. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-11242015-013303/ ;
Chicago Manual of Style (16th Edition):
Assis, Thiago Rocha de. “Soft error aware physical synthesis.” 2015. Doctoral Dissertation, Vanderbilt University. Accessed October 23, 2019.
http://etd.library.vanderbilt.edu/available/etd-11242015-013303/ ;.
MLA Handbook (7th Edition):
Assis, Thiago Rocha de. “Soft error aware physical synthesis.” 2015. Web. 23 Oct 2019.
Vancouver:
Assis TRd. Soft error aware physical synthesis. [Internet] [Doctoral dissertation]. Vanderbilt University; 2015. [cited 2019 Oct 23].
Available from: http://etd.library.vanderbilt.edu/available/etd-11242015-013303/ ;.
Council of Science Editors:
Assis TRd. Soft error aware physical synthesis. [Doctoral Dissertation]. Vanderbilt University; 2015. Available from: http://etd.library.vanderbilt.edu/available/etd-11242015-013303/ ;
Vanderbilt University
13.
Chen, Yanran.
Analysis and hardening of all-digital phase-locked loops (ADPLLs) to single-event radiation effects.
Degree: PhD, Electrical Engineering, 2017, Vanderbilt University
URL: http://etd.library.vanderbilt.edu//available/etd-09222017-180229/
;
► In deep sub-micron CMOS technologies, all-digital phase-locked loops (ADPLLs) are favored over conventional analog or mixed-signal phase-locked loops (A/MS) PLLs for providing the clock signals…
(more)
▼ In deep sub-micron CMOS technologies, all-digital phase-locked loops (ADPLLs) are favored over conventional analog or mixed-signal phase-locked loops (A/MS) PLLs for providing the clock signals for modern integrated circuits (ICs). Since an accurate clock signal is an important guarantee of the correct functionality of a system on chip (SOC), single-event effects (SEEs), as a type of reliability issues, have been extensively studied in A/MS PLLs, which are mostly based on a charge-pump PLL (CPPLL) architecture. However, little is known about the single-event vulnerability and hardening of ADPLLs.
In this dissertation, three major single-event error signatures were identified and perturbation time error metric was proposed to quantify the error signatures in ADPLLs. Circuit-level simulation and experimental testing were conducted to characterize the subcircuits of different types ADPLLs to distinguish and analyze their individual contribution to the overall ADPLL SE vulnerability. High-order pole registers in the DLF were identified to be the most sensitive module in ADPLLs. In addition, different ADPLLs with complex system architectures were also characterized and analyzed for SE vulnerability.
Additionally, a novel time-domain model for SEU-induced errors in ADPLLs was proposed and verified with experimental results. The model successfully predicts the output time-domain response and perturbation time of the ADPLLs for any SEUs in any sub-circuits, which allows designers to distinguish the most SE sensitive modules in the ADPLL topology and apply selective hardening solutions before tapeout.
RHBD hardening guidelines for different types of ADPLLs for different operating environment and targeted design specifications were proposed based on SE characterization and modeling of the ADPLL designs. Last but not least, the proposed model and hardening techniques are compared with existing work on A/MS PLLs to provide conventional PLL designers with insights on RHBD ADPLL designs.
Advisors/Committee Members: Prof. Lloyd W. Massengill (chair), Prof. Bharat L. Bhuva (committee member), Prof. W. Timothy Holman (committee member), Prof. Michael L. Alles (committee member), Prof. T. Daniel Loveless (committee member), Prof. Mark N. Ellingham (committee member).
Subjects/Keywords: Single-Event Upsets (SEU); All-digital Phase-locked Loops (ADPLLs); Single-Event Effects (SEE)
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APA ·
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MLA ·
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CSE |
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APA (6th Edition):
Chen, Y. (2017). Analysis and hardening of all-digital phase-locked loops (ADPLLs) to single-event radiation effects. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu//available/etd-09222017-180229/ ;
Chicago Manual of Style (16th Edition):
Chen, Yanran. “Analysis and hardening of all-digital phase-locked loops (ADPLLs) to single-event radiation effects.” 2017. Doctoral Dissertation, Vanderbilt University. Accessed October 23, 2019.
http://etd.library.vanderbilt.edu//available/etd-09222017-180229/ ;.
MLA Handbook (7th Edition):
Chen, Yanran. “Analysis and hardening of all-digital phase-locked loops (ADPLLs) to single-event radiation effects.” 2017. Web. 23 Oct 2019.
Vancouver:
Chen Y. Analysis and hardening of all-digital phase-locked loops (ADPLLs) to single-event radiation effects. [Internet] [Doctoral dissertation]. Vanderbilt University; 2017. [cited 2019 Oct 23].
Available from: http://etd.library.vanderbilt.edu//available/etd-09222017-180229/ ;.
Council of Science Editors:
Chen Y. Analysis and hardening of all-digital phase-locked loops (ADPLLs) to single-event radiation effects. [Doctoral Dissertation]. Vanderbilt University; 2017. Available from: http://etd.library.vanderbilt.edu//available/etd-09222017-180229/ ;
14.
Benakanakere Sheshadri, Vijay.
Upset trends in flip-flop designs at deep submicron technologies.
Degree: MS, Electrical Engineering, 2010, Vanderbilt University
URL: http://etd.library.vanderbilt.edu/available/etd-09062010-120803/
;
► Advances in fabrication technologies for semiconductor integrated circuits (ICs) have resulted in sub-100 nm feature sizes. Along with this desired reduction in dimension has come…
(more)
▼ Advances in fabrication technologies for semiconductor integrated circuits (ICs) have resulted in sub-100 nm feature sizes. Along with this desired reduction in dimension has come an undesired increase in vulnerability of flip-flops to soft errors, which are caused by energetic particles that either directly or indirectly deposit energy, and create electron-hole pairs in the semiconductor material. These charges, when collected at a circuit node, perturb the associated node voltage, creating a transient pulse, which may alter the data stored in the flip-flop, causing a single- event upset (SEU). Decreasing technology feature size has resulted in higher packing densities, as a result of which, single-event related charge might be collected at multiple nodes in a circuit. Circuit-level simulations predict increased vulnerability of flip-flop designs and increased occurrence of single-event upsets in advanced technologies due to multi-node charge collection from single-ion strikes. This trend is examined by simulating 3D models of the flip-flops in a terrestrial neutron environment using Monte-Carlo Radiative Energy Deposition (MRED) simulations for charge deposition in several technology generations.
Advisors/Committee Members: Dr. Robert A Reed (committee member), Dr. Bharat L Bhuva (committee member).
Subjects/Keywords: Critical Charge; DICE; Q8FF; Charge threshold plot; MRED
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APA (6th Edition):
Benakanakere Sheshadri, V. (2010). Upset trends in flip-flop designs at deep submicron technologies. (Masters Thesis). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-09062010-120803/ ;
Chicago Manual of Style (16th Edition):
Benakanakere Sheshadri, Vijay. “Upset trends in flip-flop designs at deep submicron technologies.” 2010. Masters Thesis, Vanderbilt University. Accessed October 23, 2019.
http://etd.library.vanderbilt.edu/available/etd-09062010-120803/ ;.
MLA Handbook (7th Edition):
Benakanakere Sheshadri, Vijay. “Upset trends in flip-flop designs at deep submicron technologies.” 2010. Web. 23 Oct 2019.
Vancouver:
Benakanakere Sheshadri V. Upset trends in flip-flop designs at deep submicron technologies. [Internet] [Masters thesis]. Vanderbilt University; 2010. [cited 2019 Oct 23].
Available from: http://etd.library.vanderbilt.edu/available/etd-09062010-120803/ ;.
Council of Science Editors:
Benakanakere Sheshadri V. Upset trends in flip-flop designs at deep submicron technologies. [Masters Thesis]. Vanderbilt University; 2010. Available from: http://etd.library.vanderbilt.edu/available/etd-09062010-120803/ ;
15.
Bickham, Ryan Christopher.
An analysis of error detection techniques for arithmetic logic units.
Degree: ME, Electrical Engineering, 2010, Vanderbilt University
URL: http://etd.library.vanderbilt.edu/available/etd-03292010-160012/
;
► Scaling in VLSI systems leads to higher packing densities for transistors. As a result, they are more likely to be hit by an incident particle,…
(more)
▼ Scaling in VLSI systems leads to higher packing densities for transistors. As a result, they are more likely to be hit by an incident particle, such as neutrons or alpha particles. The interaction of neutron and alpha particles with semiconductor devices may lead to permanent, intermittent, or transient faults that result in an error. Thus, error detection becomes a greater concern for system reliability as transistor size decreases. To achieve the desired reliability, computer architects investigate new techniques to detect and correct soft errors caused by transient faults. Usually, a tradeoff is made between the performance of a processor and the area and power required for error detection. This thesis uses a 45-nm cell library to synthesize hardware description language (HDL) models for selected error detection techniques when used with Arithmetic Logic Units (ALUs). Key results include a drastic increase in power consumption for some techniques as the bit-width of the ALU increases. Results are also compared to the baseline of dual modular redundancy (DMR).
Advisors/Committee Members: Dr. Bharat L. Bhuva (chair), Dr. William H. Robinson (chair).
Subjects/Keywords: Arithmetic codes; Error Detection; Redundancy; Berger codes; Parity codes
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APA (6th Edition):
Bickham, R. C. (2010). An analysis of error detection techniques for arithmetic logic units. (Masters Thesis). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-03292010-160012/ ;
Chicago Manual of Style (16th Edition):
Bickham, Ryan Christopher. “An analysis of error detection techniques for arithmetic logic units.” 2010. Masters Thesis, Vanderbilt University. Accessed October 23, 2019.
http://etd.library.vanderbilt.edu/available/etd-03292010-160012/ ;.
MLA Handbook (7th Edition):
Bickham, Ryan Christopher. “An analysis of error detection techniques for arithmetic logic units.” 2010. Web. 23 Oct 2019.
Vancouver:
Bickham RC. An analysis of error detection techniques for arithmetic logic units. [Internet] [Masters thesis]. Vanderbilt University; 2010. [cited 2019 Oct 23].
Available from: http://etd.library.vanderbilt.edu/available/etd-03292010-160012/ ;.
Council of Science Editors:
Bickham RC. An analysis of error detection techniques for arithmetic logic units. [Masters Thesis]. Vanderbilt University; 2010. Available from: http://etd.library.vanderbilt.edu/available/etd-03292010-160012/ ;
16.
Tekumala, Lakshmi Deepika.
On-chip characterization of single-event charge-collection.
Degree: MS, Electrical Engineering, 2012, Vanderbilt University
URL: http://etd.library.vanderbilt.edu/available/etd-08052012-215357/
;
► Particle strikes on microelectronic circuits lead to undesirable current transients on the circuit node due to charge generation and charge collection processes. Typically, TCAD tools…
(more)
▼ Particle strikes on microelectronic circuits lead to undesirable current transients on the circuit node due to charge generation and charge collection processes. Typically, TCAD tools are used to examine charge collection process after particle strikes and provide an insight into the various charge collection mechanisms. Since the charge collected on a circuit node is also affected by its circuit and layout parameters, and the presence of multiple transistors within a certain distance, on-chip characterization of charge collection becomes desirable for advanced technologies. The focus of this thesis is on the design of an on-chip self-triggered charge collection measurement circuit technique to experimentally quantify single-event charge collection process for deep sub-micron technologies. Simulation results on UMC 40nm technology show a maximum measurement resolution of ~5 fC for the circuit.
Advisors/Committee Members: Dr. Bharat L Bhuva (committee member), Dr. Lloyd Massengill (committee member).
Subjects/Keywords: single-events; charge collection; autonomous circuit technique; on-chip characterization; UMC 40nm
…August, 2012
Nashville, Tennessee
Approved:
Professor Bharat L . Bhuva
Professor Lloyd W… …Thesis
Submitted to the Faculty of the
Graduate School of Vanderbilt University
in partial…
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APA (6th Edition):
Tekumala, L. D. (2012). On-chip characterization of single-event charge-collection. (Masters Thesis). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-08052012-215357/ ;
Chicago Manual of Style (16th Edition):
Tekumala, Lakshmi Deepika. “On-chip characterization of single-event charge-collection.” 2012. Masters Thesis, Vanderbilt University. Accessed October 23, 2019.
http://etd.library.vanderbilt.edu/available/etd-08052012-215357/ ;.
MLA Handbook (7th Edition):
Tekumala, Lakshmi Deepika. “On-chip characterization of single-event charge-collection.” 2012. Web. 23 Oct 2019.
Vancouver:
Tekumala LD. On-chip characterization of single-event charge-collection. [Internet] [Masters thesis]. Vanderbilt University; 2012. [cited 2019 Oct 23].
Available from: http://etd.library.vanderbilt.edu/available/etd-08052012-215357/ ;.
Council of Science Editors:
Tekumala LD. On-chip characterization of single-event charge-collection. [Masters Thesis]. Vanderbilt University; 2012. Available from: http://etd.library.vanderbilt.edu/available/etd-08052012-215357/ ;
17.
Ossi, Edward John.
Soft-error mitigation at the architecture-level using Berger codes for error detection.
Degree: ME, Electrical Engineering, 2011, Vanderbilt University
URL: http://etd.library.vanderbilt.edu/available/etd-12022011-121416/
;
► Soft-error mitigation using design techniques at the architecture-level can overcome the limitations of process and circuit-level mitigation techniques in advanced technologies. This thesis presents two…
(more)
▼ Soft-error mitigation using design techniques at the architecture-level can overcome the limitations of process and circuit-level mitigation techniques in advanced technologies. This thesis presents two architecture-level error detection and correction strategies that target the Arithmetic Logic Units (ALU) within a microprocessor. The ALU was chosen because it is the heart of a microprocessor and the errors that affect it are unlike those that affect the rest of the microprocessor. The error detection code used for encoding the data is Berger code. A Register-Transfer Level (RTL) model of the circuits was built using VHDL code and then simulated. The designs were then synthesized using the FreePDK library for area, speed, and power calculations. The merits and simulation results of the two implementations are discussed. Both strategies show an effective means to detect and recover from radiation-induced soft errors; however, the area cost and speed penalties of these strategies are too severe for practical use.
Advisors/Committee Members: Bharat L. Bhuva (chair), William H. Robinson (committee member).
Subjects/Keywords: berger code; architecture; soft error
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APA (6th Edition):
Ossi, E. J. (2011). Soft-error mitigation at the architecture-level using Berger codes for error detection. (Masters Thesis). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-12022011-121416/ ;
Chicago Manual of Style (16th Edition):
Ossi, Edward John. “Soft-error mitigation at the architecture-level using Berger codes for error detection.” 2011. Masters Thesis, Vanderbilt University. Accessed October 23, 2019.
http://etd.library.vanderbilt.edu/available/etd-12022011-121416/ ;.
MLA Handbook (7th Edition):
Ossi, Edward John. “Soft-error mitigation at the architecture-level using Berger codes for error detection.” 2011. Web. 23 Oct 2019.
Vancouver:
Ossi EJ. Soft-error mitigation at the architecture-level using Berger codes for error detection. [Internet] [Masters thesis]. Vanderbilt University; 2011. [cited 2019 Oct 23].
Available from: http://etd.library.vanderbilt.edu/available/etd-12022011-121416/ ;.
Council of Science Editors:
Ossi EJ. Soft-error mitigation at the architecture-level using Berger codes for error detection. [Masters Thesis]. Vanderbilt University; 2011. Available from: http://etd.library.vanderbilt.edu/available/etd-12022011-121416/ ;
18.
Adeleke, Adeola.
Logic repair and soft error rate reduction using approximate logic functions.
Degree: MS, Electrical Engineering, 2012, Vanderbilt University
URL: http://etd.library.vanderbilt.edu/available/etd-03122012-095419/
;
► Continuing CMOS devices scaling causes an increase in the vulnerability of integrated circuits to radiation-induced soft errors. Furthermore, as transistor density increases, the probability of…
(more)
▼ Continuing CMOS devices scaling causes an increase in the vulnerability of integrated circuits to radiation-induced soft errors. Furthermore, as transistor density increases, the probability of transistors failing increases accordingly. Consequently, design approaches that address these threats to architectural reliability are required. Existing techniques for providing hardware robustness often require incurring significant area, power, speed, and weight penalties. Moreover, many of the existing techniques are only applicable to memory elements. In this project, a new technique for soft error rate reduction and logic repair using approximate logic functions has been developed. By utilizing this technique, designers can flexibly select the protection level of logic circuits while balancing out design trade-offs
Advisors/Committee Members: Bharat L. Bhuva (chair), Lloyd W. Massengill (committee member).
Subjects/Keywords: functions; logic; approximate; logic; repair
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APA (6th Edition):
Adeleke, A. (2012). Logic repair and soft error rate reduction using approximate logic functions. (Masters Thesis). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-03122012-095419/ ;
Chicago Manual of Style (16th Edition):
Adeleke, Adeola. “Logic repair and soft error rate reduction using approximate logic functions.” 2012. Masters Thesis, Vanderbilt University. Accessed October 23, 2019.
http://etd.library.vanderbilt.edu/available/etd-03122012-095419/ ;.
MLA Handbook (7th Edition):
Adeleke, Adeola. “Logic repair and soft error rate reduction using approximate logic functions.” 2012. Web. 23 Oct 2019.
Vancouver:
Adeleke A. Logic repair and soft error rate reduction using approximate logic functions. [Internet] [Masters thesis]. Vanderbilt University; 2012. [cited 2019 Oct 23].
Available from: http://etd.library.vanderbilt.edu/available/etd-03122012-095419/ ;.
Council of Science Editors:
Adeleke A. Logic repair and soft error rate reduction using approximate logic functions. [Masters Thesis]. Vanderbilt University; 2012. Available from: http://etd.library.vanderbilt.edu/available/etd-03122012-095419/ ;
19.
Chatterjee, Indranil.
Single-event charge collection and upset in 65-nm and 40-nm dual- and triple-well bulk CMOS SRAMS.
Degree: MS, Electrical Engineering, 2012, Vanderbilt University
URL: http://etd.library.vanderbilt.edu/available/etd-03252012-195135/
;
► CMOS technologies can be either dual-well or triple-well. Triple-well technology has several advantages compared to dual-well technology in terms of electrical performance. Differences in the…
(more)
▼ CMOS technologies can be either dual-well or triple-well. Triple-well technology has several advantages compared to dual-well technology in terms of electrical performance. Differences in the ion-induced single-event response between these two technology options, however, are not well understood. This work presents a comparative analysis of heavy ion-induced upsets in dual-well and triple-well 40-nm CMOS SRAMs. Primary factors affecting the charge-collection mechanisms for a wide range of particle energies are investigated, showing that triple-well technologies are more vulnerable to low-LET particles, while dual-well technologies are more vulnerable to high-LET particles. For the triple-well technology, charge confinement and multiple-transistor charge collection triggers the âSingle Event Upset Reversalâ mechanism that reduces sensitivity at high LETs.
Advisors/Committee Members: Ronald D. Schrimpf (committee member), Bharat L. Bhuva (chair).
Subjects/Keywords: Soft-errors; Single-Event Upset Reversal; Heavy Ion Irradiation; Triple-well; Dual-well; Single-Event Effects
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APA (6th Edition):
Chatterjee, I. (2012). Single-event charge collection and upset in 65-nm and 40-nm dual- and triple-well bulk CMOS SRAMS. (Masters Thesis). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-03252012-195135/ ;
Chicago Manual of Style (16th Edition):
Chatterjee, Indranil. “Single-event charge collection and upset in 65-nm and 40-nm dual- and triple-well bulk CMOS SRAMS.” 2012. Masters Thesis, Vanderbilt University. Accessed October 23, 2019.
http://etd.library.vanderbilt.edu/available/etd-03252012-195135/ ;.
MLA Handbook (7th Edition):
Chatterjee, Indranil. “Single-event charge collection and upset in 65-nm and 40-nm dual- and triple-well bulk CMOS SRAMS.” 2012. Web. 23 Oct 2019.
Vancouver:
Chatterjee I. Single-event charge collection and upset in 65-nm and 40-nm dual- and triple-well bulk CMOS SRAMS. [Internet] [Masters thesis]. Vanderbilt University; 2012. [cited 2019 Oct 23].
Available from: http://etd.library.vanderbilt.edu/available/etd-03252012-195135/ ;.
Council of Science Editors:
Chatterjee I. Single-event charge collection and upset in 65-nm and 40-nm dual- and triple-well bulk CMOS SRAMS. [Masters Thesis]. Vanderbilt University; 2012. Available from: http://etd.library.vanderbilt.edu/available/etd-03252012-195135/ ;
20.
Kiddie, Bradley Thomas.
Layout-Based Fault Injection for Combinational Logic in Nanometer Technologies.
Degree: MS, Electrical Engineering, 2012, Vanderbilt University
URL: http://etd.library.vanderbilt.edu/available/etd-03262012-131128/
;
► As feature sizes and operating voltages decrease, single-event transients from particle strikes in logic circuits become more probable. Much literature is available on the effects…
(more)
▼ As feature sizes and operating voltages decrease, single-event transients from particle strikes in logic circuits become more probable. Much literature is available on the effects of these events in memory, but with increasing clock speeds, combinational logic has also been shown to be at risk. In this work, several combinational circuits are selected and simulated, taking into account gate library and layout information, in order to characterize the effects of particle strikes which upset single nodes as well as multiple, physically adjacent nodes. It is shown that traditional reliability tests which simulate a single fault are not sufficient â multiple faults stemming from a single strike occur and are more complex. However, multiple faults do not always translate to additional errors in the output â logical reconvergence limits the effect of faults within a circuit. In order to properly understand reliability in circuit design, analysis of multiple faults should be taken into account.
Advisors/Committee Members: William H. Robinson (chair), Bharat L. Bhuva (committee member).
Subjects/Keywords: reliability; radiation-induced faults; single-event transient; multiple transient faults; soft errors; combinational logic; layout
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APA (6th Edition):
Kiddie, B. T. (2012). Layout-Based Fault Injection for Combinational Logic in Nanometer Technologies. (Masters Thesis). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-03262012-131128/ ;
Chicago Manual of Style (16th Edition):
Kiddie, Bradley Thomas. “Layout-Based Fault Injection for Combinational Logic in Nanometer Technologies.” 2012. Masters Thesis, Vanderbilt University. Accessed October 23, 2019.
http://etd.library.vanderbilt.edu/available/etd-03262012-131128/ ;.
MLA Handbook (7th Edition):
Kiddie, Bradley Thomas. “Layout-Based Fault Injection for Combinational Logic in Nanometer Technologies.” 2012. Web. 23 Oct 2019.
Vancouver:
Kiddie BT. Layout-Based Fault Injection for Combinational Logic in Nanometer Technologies. [Internet] [Masters thesis]. Vanderbilt University; 2012. [cited 2019 Oct 23].
Available from: http://etd.library.vanderbilt.edu/available/etd-03262012-131128/ ;.
Council of Science Editors:
Kiddie BT. Layout-Based Fault Injection for Combinational Logic in Nanometer Technologies. [Masters Thesis]. Vanderbilt University; 2012. Available from: http://etd.library.vanderbilt.edu/available/etd-03262012-131128/ ;
21.
Jiang, Hui.
Drosophila Automated Olfactory Training and Testing System for Associative Learning.
Degree: MS, Electrical Engineering, 2015, Vanderbilt University
URL: http://etd.library.vanderbilt.edu//available/etd-01122015-133013/
;
► This thesis demonstrates the feasibility of designing and building a Drosophila automated training and testing system for Pavlovian classical associative learning/memory analyses using inexpensive hardware…
(more)
▼ This thesis demonstrates the feasibility of designing and building a Drosophila automated training and testing system for Pavlovian classical associative learning/memory analyses using inexpensive hardware and software (total design under $700US). There were two platforms designed using inexpensive electronic devices, 3D printed parts, and different configurations. Both were controlled by an open source Arduino microcontroller, eight solenoid valves, and a square pulse stimulator. The two platform data were logged by an odor sensor and three air flow sensors. This thesis presents the system design and the results of biological testing. The results show that controlling and data logging electronic devices work well for this application.
Advisors/Committee Members: Kendal S. Broadie (committee member), Bharat L. Bhuva (committee member).
Subjects/Keywords: Pavlovian classical conditioning; automation; learning; Drosophila; memory
…This
system was developed at Broadie Laboratory of Vanderbilt University. In the second part… …developed at the Broadie Laboratory of Vanderbilt University.
The automated system was designed…
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APA (6th Edition):
Jiang, H. (2015). Drosophila Automated Olfactory Training and Testing System for Associative Learning. (Masters Thesis). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu//available/etd-01122015-133013/ ;
Chicago Manual of Style (16th Edition):
Jiang, Hui. “Drosophila Automated Olfactory Training and Testing System for Associative Learning.” 2015. Masters Thesis, Vanderbilt University. Accessed October 23, 2019.
http://etd.library.vanderbilt.edu//available/etd-01122015-133013/ ;.
MLA Handbook (7th Edition):
Jiang, Hui. “Drosophila Automated Olfactory Training and Testing System for Associative Learning.” 2015. Web. 23 Oct 2019.
Vancouver:
Jiang H. Drosophila Automated Olfactory Training and Testing System for Associative Learning. [Internet] [Masters thesis]. Vanderbilt University; 2015. [cited 2019 Oct 23].
Available from: http://etd.library.vanderbilt.edu//available/etd-01122015-133013/ ;.
Council of Science Editors:
Jiang H. Drosophila Automated Olfactory Training and Testing System for Associative Learning. [Masters Thesis]. Vanderbilt University; 2015. Available from: http://etd.library.vanderbilt.edu//available/etd-01122015-133013/ ;
22.
Reece, Trey.
Assessing and Detecting Malicious Hardware in Integrated Circuits.
Degree: PhD, Electrical Engineering, 2014, Vanderbilt University
URL: http://etd.library.vanderbilt.edu/available/etd-12052014-031031/
;
► System security often focuses on the software, causing hardware security to be overlooked. Such oversight allows for attacks that can completely undermine the use of…
(more)
▼ System security often focuses on the software, causing hardware security to be overlooked. Such oversight allows for attacks that can completely undermine the use of hardware as the root of trust. During the design of an integrated circuit, there are several opportunities for adversaries to make malicious modifications or insertions to a design. These attacks, known as hardware Trojans, can have catastrophic effects on a circuit if left undetected. This dissertation addresses Trojan impact, and proposes two low-cost detection methods for hardware Trojans inserted at different points in the production pipeline, namely: (1) Trojans hidden within third-party intellectual property (IP) licensed from a vendor, and (2) Trojans inserted during the fabrication steps taking place at external fabrication plants.
Determining whether third-party IP does only its intended function and nothing else is a major challenge. Through comparison of two similar but untrusted designs using design unrolling and Boolean satisfiability, functional differences can be identified for all possible input combinations within a window of time. This technique was tested on multiple Trojan benchmarks and demonstrated effective and accurate detectability.
Process variation poses the greatest obstacle to detecting Trojans in chips. In order to detect Trojans inserted during fabrication, a digital model is created. This model can then be trained using the fabricated chip to account for different parameters, such as process variation. The parameters of the trained model can be used to identify suspicious areas of the chip. Furthermore, this process does not require expensive test equipment, nor does it require a costly golden, trusted chip for comparison.
Advisors/Committee Members: Thomas Daniel Loveless (committee member), Bradley A. Malin (committee member), Bharat L. Bhuva (committee member), Gabor Karsai (committee member), William H. Robinson (chair).
Subjects/Keywords: integrated circuit design; vlsi; hardware trojan; hardware security; verification
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APA (6th Edition):
Reece, T. (2014). Assessing and Detecting Malicious Hardware in Integrated Circuits. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-12052014-031031/ ;
Chicago Manual of Style (16th Edition):
Reece, Trey. “Assessing and Detecting Malicious Hardware in Integrated Circuits.” 2014. Doctoral Dissertation, Vanderbilt University. Accessed October 23, 2019.
http://etd.library.vanderbilt.edu/available/etd-12052014-031031/ ;.
MLA Handbook (7th Edition):
Reece, Trey. “Assessing and Detecting Malicious Hardware in Integrated Circuits.” 2014. Web. 23 Oct 2019.
Vancouver:
Reece T. Assessing and Detecting Malicious Hardware in Integrated Circuits. [Internet] [Doctoral dissertation]. Vanderbilt University; 2014. [cited 2019 Oct 23].
Available from: http://etd.library.vanderbilt.edu/available/etd-12052014-031031/ ;.
Council of Science Editors:
Reece T. Assessing and Detecting Malicious Hardware in Integrated Circuits. [Doctoral Dissertation]. Vanderbilt University; 2014. Available from: http://etd.library.vanderbilt.edu/available/etd-12052014-031031/ ;
23.
Rong, Guoguang.
Label-free Nanoscale Biosensing using a Porous Silicon Waveguide.
Degree: PhD, Electrical Engineering, 2008, Vanderbilt University
URL: http://etd.library.vanderbilt.edu/available/etd-08222008-141939/
;
► The need to develop highly sensitive, selective, and cost-effective biosensors spans the areas of medicine, the environment, food safety, and homeland security. Accurate and reliable…
(more)
▼ The need to develop highly sensitive, selective, and cost-effective biosensors spans the areas of medicine, the environment, food safety, and homeland security. Accurate and reliable detection of trace quantities of small molecules is particularly challenging for existing sensor technology. Porous silicon is an excellent material for small molecule biosensing due to its large surface area and its capability of size selective sensing. In this work, a label-free porous silicon optical waveguide is demonstrated for the detection of short DNA oligonucleotides. The waveguide design enables the optical field to be localized exactly where biomolecules are attached to the sensor, leading to enhanced detection sensitivity. A prism is used to couple light into the waveguide at a particular angle where a sharp resonance dip is observed. The resonance angle is very sensitive to small changes in the porous silicon waveguide refractive index that occur, for example, when biomolecules bind inside the pores of the waveguide. Two different porous silicon waveguide structures are presented and compared: a p-type porous silicon waveguide with 20-30 nm pores in the Otto configuration and an n-type porous silicon waveguide with 100 nm pores in the Kretschmann configuration. Field profiles of the porous silicon waveguides are analyzed and their sensitivity enhancement over traditional sensor technology is shown for small molecule detection. In addition to experimental demonstration of quantitative and selective detection of DNA molecules using the porous silicon waveguide biosensor, the effects of biomolecular size on the sensitivity of porous silicon waveguide biosensors is discussed. With smaller pores, p-type porous silicon waveguides are more sensitive detecting shorter DNA molecules, while larger pore n-type porous silicon waveguides are capable of detecting longer DNA molecules that cannot easily infiltrate into p-type waveguides. Finally, further research is suggested to improve the sensor performance through modified design, alternate biomolecules to detect, and systems integration.
Advisors/Committee Members: Raymond L. Mernaugh (committee member), Robert A. Weller (committee member), Weng Poo Kang (committee member), Bharat L. Bhuva (committee member), Sharon M. Weiss (chair).
Subjects/Keywords: Biosensors – Design and construction; nanoscale; high sensitivity; label-free; optical; Porous silicon; Wave guides – Design and construction
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APA (6th Edition):
Rong, G. (2008). Label-free Nanoscale Biosensing using a Porous Silicon Waveguide. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-08222008-141939/ ;
Chicago Manual of Style (16th Edition):
Rong, Guoguang. “Label-free Nanoscale Biosensing using a Porous Silicon Waveguide.” 2008. Doctoral Dissertation, Vanderbilt University. Accessed October 23, 2019.
http://etd.library.vanderbilt.edu/available/etd-08222008-141939/ ;.
MLA Handbook (7th Edition):
Rong, Guoguang. “Label-free Nanoscale Biosensing using a Porous Silicon Waveguide.” 2008. Web. 23 Oct 2019.
Vancouver:
Rong G. Label-free Nanoscale Biosensing using a Porous Silicon Waveguide. [Internet] [Doctoral dissertation]. Vanderbilt University; 2008. [cited 2019 Oct 23].
Available from: http://etd.library.vanderbilt.edu/available/etd-08222008-141939/ ;.
Council of Science Editors:
Rong G. Label-free Nanoscale Biosensing using a Porous Silicon Waveguide. [Doctoral Dissertation]. Vanderbilt University; 2008. Available from: http://etd.library.vanderbilt.edu/available/etd-08222008-141939/ ;
24.
Wei, Xing.
Porous silicon waveguide biosensors with a grating coupler.
Degree: PhD, Electrical Engineering, 2012, Vanderbilt University
URL: http://etd.library.vanderbilt.edu/available/etd-03262012-231223/
;
► Sensitive label-free optical biosensors based on grating-coupled porous silicon (PSi) waveguides are demonstrated for biosensing applications. This is the first time that the benefits of…
(more)
▼ Sensitive label-free optical biosensors based on grating-coupled porous silicon (PSi) waveguides are demonstrated for biosensing applications. This is the first time that the benefits of both PSi and diffraction gratings have been combined for the detection of small molecules. The large surface area and strong field confinement in the waveguide region where biomolecules are immobilized make it possible to detect biomolecule interactions with high sensitivity. Diffraction gratings provide a simple, convenient, and effective means of coupling light into the waveguide for DNA hybridization experiments. Through both experiments and theoretical calculations, it was shown that an all-PSi grating-coupled waveguide biosensor exhibits a more than 30-fold larger signal response for small molecule detection compared to planar waveguide sensors. Kinetics parameters of different sized molecules in nanoscale pores were also determined for the first time using PDMS flow cell integrated PSi grating-coupled waveguides.
Advisors/Committee Members: Sharon M. Weiss (chair), Bharat L. Bhuva (committee member), Deyu Li (committee member), Ronald D. Schrimpf (committee member), Yaqiong Xu (committee member).
Subjects/Keywords: gratings; optical biosensor; Porous silicon; waveguide
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APA (6th Edition):
Wei, X. (2012). Porous silicon waveguide biosensors with a grating coupler. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-03262012-231223/ ;
Chicago Manual of Style (16th Edition):
Wei, Xing. “Porous silicon waveguide biosensors with a grating coupler.” 2012. Doctoral Dissertation, Vanderbilt University. Accessed October 23, 2019.
http://etd.library.vanderbilt.edu/available/etd-03262012-231223/ ;.
MLA Handbook (7th Edition):
Wei, Xing. “Porous silicon waveguide biosensors with a grating coupler.” 2012. Web. 23 Oct 2019.
Vancouver:
Wei X. Porous silicon waveguide biosensors with a grating coupler. [Internet] [Doctoral dissertation]. Vanderbilt University; 2012. [cited 2019 Oct 23].
Available from: http://etd.library.vanderbilt.edu/available/etd-03262012-231223/ ;.
Council of Science Editors:
Wei X. Porous silicon waveguide biosensors with a grating coupler. [Doctoral Dissertation]. Vanderbilt University; 2012. Available from: http://etd.library.vanderbilt.edu/available/etd-03262012-231223/ ;
25.
Raina, Supil.
Nanodiamond macroelectrodes and ultramicroelectrode arrays for bio-analyte detection.
Degree: PhD, Interdisciplinary Materials Science, 2011, Vanderbilt University
URL: http://etd.library.vanderbilt.edu//available/etd-11012011-163309/
;
► Properties such as high electrical conductivity; chemical and electrochemical stability over a wide range of conditions; rapid electron transfer kinetics for different redox systems; and…
(more)
▼ Properties such as high electrical conductivity; chemical and electrochemical stability over a wide range of conditions; rapid electron transfer kinetics for different redox systems; and reproducible electrical, microstructural and chemical properties are essential pre-requisites for electrochemical electrodes. Nanodiamond is one such electrode material which has been shown to be suitable for electroanalytical applications. In this dissertation, MPECVD (Microwave Plasma Enhanced Chemical Vapor Deposition) process and conventional silicon microfabrication technology has been used for synthesis and fabrication of nanodiamond thin-film macroelectrodes and ultramicroelectrode arrays (UMEAs) with different geometries- pyramidal, planar and columnar. This work combines the excellent material properties of nanodiamond with the benefits of using UMEAs- higher analyte flux density, reduced ohmic losses and higher temporal resolution.
Scanning electron microscopy, X-ray photoelectron spectroscopy and Raman spectroscopy were used for material characterization. Electrochemical performance was analyzed using ferri/ferrocyanide redox couple and essential bio-analytes such as Dopamine, Ascorbic Acid (AA) and Uric Acid (UA) in phosphate buffered saline (PBS). To simulate true physiological conditions, detection and quantification of dopamine in presence of interferants such as AA and UA was also examined, in-vitro. In addition, effects of the input gas mixture, i.e., hydrogen, methane and nitrogen, on nanodiamond macroelectrode properties were evaluated and optimized. Increase in nitrogen gas flow produced distinct changes in the nanodiamond microstructure and electrochemical response. The fabrication processes and electroanalytical performance, under steady state conditions, of the UMEAs with different geometries were compared to identify their respective drawbacks and new fabrication processes were developed to overcome them in order to consistently produce more reliable bio-sensors. The sensitivity of the UMEAs varied inversely with their dimensions. Neurotransmitter concentrations vary at sub-second time-scale and can only be monitored and quantified by using an electrode with high temporal resolution and fast electron transfer kinetics. Hence, âbackground subtracted fast scan cyclic voltammetryâ for Dopamine detection using planar nanodiamond UMEA was implemented. All the results from electrochemical characterization were achieved without any surface functionalization and/or modification.
Advisors/Committee Members: Weng P. Kang (chair), Jimmy L. Davidson (committee member), Sharon M. Weiss (committee member), Bharat L. Bhuva (committee member), Deyu Li (committee member).
Subjects/Keywords: fast scan cyclic voltammetry; diffusion; electrochemistry; dopamine; nanodiamond
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APA (6th Edition):
Raina, S. (2011). Nanodiamond macroelectrodes and ultramicroelectrode arrays for bio-analyte detection. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu//available/etd-11012011-163309/ ;
Chicago Manual of Style (16th Edition):
Raina, Supil. “Nanodiamond macroelectrodes and ultramicroelectrode arrays for bio-analyte detection.” 2011. Doctoral Dissertation, Vanderbilt University. Accessed October 23, 2019.
http://etd.library.vanderbilt.edu//available/etd-11012011-163309/ ;.
MLA Handbook (7th Edition):
Raina, Supil. “Nanodiamond macroelectrodes and ultramicroelectrode arrays for bio-analyte detection.” 2011. Web. 23 Oct 2019.
Vancouver:
Raina S. Nanodiamond macroelectrodes and ultramicroelectrode arrays for bio-analyte detection. [Internet] [Doctoral dissertation]. Vanderbilt University; 2011. [cited 2019 Oct 23].
Available from: http://etd.library.vanderbilt.edu//available/etd-11012011-163309/ ;.
Council of Science Editors:
Raina S. Nanodiamond macroelectrodes and ultramicroelectrode arrays for bio-analyte detection. [Doctoral Dissertation]. Vanderbilt University; 2011. Available from: http://etd.library.vanderbilt.edu//available/etd-11012011-163309/ ;
26.
Kauppila, Jeffrey Scott.
Layout-Aware Modeling and Analysis Methodologies for Transient Radiation Effects on Integrated Circuit Electronics.
Degree: PhD, Electrical Engineering, 2015, Vanderbilt University
URL: http://etd.library.vanderbilt.edu/available/etd-03152015-142439/
;
► The development of integrated circuits intended for use in transient radiation environments must account for the impact of the environment on the operation of the…
(more)
▼ The development of integrated circuits intended for use in transient radiation environments must account for the impact of the environment on the operation of the circuit. The design of integrated circuits is increasingly simulation driven, and increased costs to fabricate designs require engineers to consider radiation effects in the simulation and design phase to limit fabrication and test cycles required to produce a radiation hardened part. This work advances the historical modeling approaches with bias-dependent and layout-aware methods for modeling the dose-rate and single-event effects in advanced technologies.
This research develops a bias-dependent modeling method that accounts for circuit induced shaping of the device-level transient current. Behavioral modeling languages are utilized to eliminate independent current sources and lumped SPICE element models. Dose rate models are developed for multiple dielectrically-isolated processes across technology types, accounting for real-time bias-dependence and layout geometries in modern integrated circuit processes. Single-event modeling methods are developed to capture the bias-dependent current response observed in recent TCAD simulations. Bulk CMOS and SiGe HBT technology model parameterization for multiple-device charge collection is demonstrated. A new geometry-aware single-event model for sub-50nm partially-depleted SOI CMOS with an integrated parasitic BJT parameterized by technology and design parameters is developed. Dose-rate and single-event model simulations compare well to TCAD and test data.
A novel layout-aware analysis method is developed, utilizing a hybrid of compact models (for efficiency) and spatially-aware layout objects (for geometric charge collection accuracy), in an industry standard integrated circuit design tool flow. The layout-aware analysis provides designers with visual feedback about the sensitivity of a design directly referenced to the circuit layout.
The methods developed in this research are being actively utilized in radiation-effects research at universities, aerospace and defense corporations, and commercial integrated circuit design and manufacturing facilities. Layout-aware radiation-enabled models using the methodologies developed in this work have been integrated with process design kits and deployed to the radiation-hardened-by-design community. This research develops capabilities that provide a path forward to model transient radiation effects in advanced integrated circuit technologies.
Advisors/Committee Members: Lloyd W. Massengill, Ph.D. (chair), Ronald D. Schrimpf, Ph.D. (committee member), W. Timothy Holman, Ph.D. (committee member), Bharat L. Bhuva, Ph.D. (committee member), Mark N. Ellingham, Ph.D. (committee member).
Subjects/Keywords: CAD Tools; Semiconductor Device Modeling; Process Design Kit; Gummel Poon; BSIMSOI; MEXTRAM; Radiation Modeling; TCAD; BSIM4; Bias-Dependent Modeling; Dose Rate Effects; Compact Models; Single Event Effects; Compact Model; BJT; MOSFET; Layout-Aware Modeling; Layout-Aware Analysis; SPICE; Layout; Radiation Effects; Circuit Simulation; Radiation-Enabled Model; Single-Event Transient; Single-Event Upset; Charge Sharing; Computational Modeling
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APA (6th Edition):
Kauppila, J. S. (2015). Layout-Aware Modeling and Analysis Methodologies for Transient Radiation Effects on Integrated Circuit Electronics. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-03152015-142439/ ;
Chicago Manual of Style (16th Edition):
Kauppila, Jeffrey Scott. “Layout-Aware Modeling and Analysis Methodologies for Transient Radiation Effects on Integrated Circuit Electronics.” 2015. Doctoral Dissertation, Vanderbilt University. Accessed October 23, 2019.
http://etd.library.vanderbilt.edu/available/etd-03152015-142439/ ;.
MLA Handbook (7th Edition):
Kauppila, Jeffrey Scott. “Layout-Aware Modeling and Analysis Methodologies for Transient Radiation Effects on Integrated Circuit Electronics.” 2015. Web. 23 Oct 2019.
Vancouver:
Kauppila JS. Layout-Aware Modeling and Analysis Methodologies for Transient Radiation Effects on Integrated Circuit Electronics. [Internet] [Doctoral dissertation]. Vanderbilt University; 2015. [cited 2019 Oct 23].
Available from: http://etd.library.vanderbilt.edu/available/etd-03152015-142439/ ;.
Council of Science Editors:
Kauppila JS. Layout-Aware Modeling and Analysis Methodologies for Transient Radiation Effects on Integrated Circuit Electronics. [Doctoral Dissertation]. Vanderbilt University; 2015. Available from: http://etd.library.vanderbilt.edu/available/etd-03152015-142439/ ;
27.
Chatterjee, Indranil.
Geometric Dependence of the Total Ionizing Dose Response of FinFETs.
Degree: PhD, Electrical Engineering, 2014, Vanderbilt University
URL: http://etd.library.vanderbilt.edu/available/etd-07312014-201221/
;
► The total ionizing dose induced degradation in advanced deep-submicron CMOS technologies has been significantly reduced by scaling. Damage to isolating field oxides remains a significant…
(more)
▼ The total ionizing dose induced degradation in advanced deep-submicron CMOS technologies has been significantly reduced by scaling. Damage to isolating field oxides remains a significant threat for integrated circuits fabricated in these technologies that must operate in harsh radiation environments. This work investigates the effects of geometry on the total ionizing dose response of bulk and Silicon-on-Insulator (SOI) FinFETs. Experimental and TCAD simulations show that the post-irradiation response of bulk FinFETs is dominated by buildup of charge in the shallow trench isolation oxide which induces a parasitic leakage current path, whereas in SOI FinFETs, charge trapping in Buried Oxide (BOX) usually is the primary contributing factor to device degradation in a radiation environment. For bulk FinFETs, the radiation-induced degradation increases with decreasing fin-width, increases with decreasing channel length, and increases with increasing fin-to-fin separation.
Advisors/Committee Members: ShiJie Wen (committee member), Aniruddha S. Gokhale (committee member), Balaji Narasimham (committee member), Michael L. Alles (committee member), Bharat L. Bhuva (chair), Daniel M. Fleetwood (chair), Ronald D. Schrimpf (committee member).
Subjects/Keywords: Total dose effects; Isolation oxides; Bulk FinFET; SOI FinFET; Parasitic transistor; Oxide traps; Charge trapping
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APA (6th Edition):
Chatterjee, I. (2014). Geometric Dependence of the Total Ionizing Dose Response of FinFETs. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-07312014-201221/ ;
Chicago Manual of Style (16th Edition):
Chatterjee, Indranil. “Geometric Dependence of the Total Ionizing Dose Response of FinFETs.” 2014. Doctoral Dissertation, Vanderbilt University. Accessed October 23, 2019.
http://etd.library.vanderbilt.edu/available/etd-07312014-201221/ ;.
MLA Handbook (7th Edition):
Chatterjee, Indranil. “Geometric Dependence of the Total Ionizing Dose Response of FinFETs.” 2014. Web. 23 Oct 2019.
Vancouver:
Chatterjee I. Geometric Dependence of the Total Ionizing Dose Response of FinFETs. [Internet] [Doctoral dissertation]. Vanderbilt University; 2014. [cited 2019 Oct 23].
Available from: http://etd.library.vanderbilt.edu/available/etd-07312014-201221/ ;.
Council of Science Editors:
Chatterjee I. Geometric Dependence of the Total Ionizing Dose Response of FinFETs. [Doctoral Dissertation]. Vanderbilt University; 2014. Available from: http://etd.library.vanderbilt.edu/available/etd-07312014-201221/ ;
28.
Jagannathan, Srikanth.
TID characterization of high frequency RF circuits in NANO-CMOS technologies.
Degree: PhD, Electrical Engineering, 2013, Vanderbilt University
URL: http://etd.library.vanderbilt.edu//available/etd-11152013-150900/
;
► Rapid downscaling of CMOS technology has resulted in significant improvement in the RF performance of Silicon MOSFETs. As a result, standard CMOS technology has become…
(more)
▼ Rapid downscaling of CMOS technology has resulted in significant improvement in the RF performance of Silicon MOSFETs. As a result, standard CMOS technology has become a popular choice for implementing RF applications. Nano-scale CMOS device characteristics can be highly sensitive to variations in process (P), supply voltage (V) and operating temperature (T). This makes the design of RF circuits using nano-scale CMOS devices increasingly challenging to satisfy the performance specifications across all PVT corners. Another parameter that needs to be considered in the design space for RF circuits used in aerospace and military applications is total ionizing dose (TID) irradiation. Even a relatively small amount of TID-induced degradation that may not be significant for typical digital CMOS applications can be quite important for analog RF applications, especially when compounded by PVT variations.
Radiation experiments show degradation in the performance of a 20.4 GHz voltage controlled oscillator (VCO) designed and fabricated in the IBM 32 nm CMOS SOI technology. At elevated temperature, the TID-induced degradation in the VCO performance is further enhanced causing failure to meet required design specifications. Measured TID-induced DC and RF parametric degradation of NMOS and PMOS transistors in the IBM 45 nm CMOS SOI technology were used to develop compact models. These models were used in example K-band RF circuits, such as the VCO and a low noise amplifier (LNA), to predict TID-induced degradation in the circuit performance.
The circuit simulations show consistent results, predicting specification failures in these RF circuits due to the combined effects of PVT corners and TID. The failure to meet design specifications of a circuit can in turn cause the failure of the entire RF system. The TID-aware compact models are further used to suggest radiation hardened by design (RHBD) alternatives along with tradeoff study of RF circuit performance and its radiation response. This study provides valuable design and reliability insights for RFIC designers targeting military and aerospace applications.
Advisors/Committee Members: Lloyd. W. Massengill (chair), Daniel T. Loveless (committee member), Ronald D. Schrimpf (committee member), William T. Holman (committee member), Bharat L. Bhuva (committee member), Mark N. Ellingham (committee member).
Subjects/Keywords: RF; TID
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APA ·
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Export
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APA (6th Edition):
Jagannathan, S. (2013). TID characterization of high frequency RF circuits in NANO-CMOS technologies. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu//available/etd-11152013-150900/ ;
Chicago Manual of Style (16th Edition):
Jagannathan, Srikanth. “TID characterization of high frequency RF circuits in NANO-CMOS technologies.” 2013. Doctoral Dissertation, Vanderbilt University. Accessed October 23, 2019.
http://etd.library.vanderbilt.edu//available/etd-11152013-150900/ ;.
MLA Handbook (7th Edition):
Jagannathan, Srikanth. “TID characterization of high frequency RF circuits in NANO-CMOS technologies.” 2013. Web. 23 Oct 2019.
Vancouver:
Jagannathan S. TID characterization of high frequency RF circuits in NANO-CMOS technologies. [Internet] [Doctoral dissertation]. Vanderbilt University; 2013. [cited 2019 Oct 23].
Available from: http://etd.library.vanderbilt.edu//available/etd-11152013-150900/ ;.
Council of Science Editors:
Jagannathan S. TID characterization of high frequency RF circuits in NANO-CMOS technologies. [Doctoral Dissertation]. Vanderbilt University; 2013. Available from: http://etd.library.vanderbilt.edu//available/etd-11152013-150900/ ;
29.
Amusan, Oluwole Ayodele.
Effects of single-event-induced charge sharing in sub-100 nm bulk CMOS technologies.
Degree: PhD, Electrical Engineering, 2009, Vanderbilt University
URL: http://etd.library.vanderbilt.edu/available/etd-02162009-141344/
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► Sub-100 nm technologies are more vulnerable than older technologies to single event effects (SEE) due to Moore's Law scaling trend. The increased SEE vulnerability has…
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▼ Sub-100 nm technologies are more vulnerable than older technologies to single event effects (SEE) due to Moore's Law scaling trend. The increased SEE vulnerability has been attributed to the decrease in nodal charge for information storage, reduced nodal separation, and increased switching frequency. The effect of the reduced nodal separation is the increased probability of simultaneous charge collection at several nodes from a single ion-strike (called charge sharing).
Charge sharing is a significant SEE issue because it can render circuit-level hardening techniques ineffective. Conventional SEE radiation-hardened by design (RHBD) approaches provide excellent protection against single event upsets (SEU) resulting from charge collection occurs on a single node. However, for sub-100 nm technologies, the probability of multiple node charge collection is significant, thwarting RHBD protection. As CMOS processes continue to scale, there is a continued decrease in nodal pitch, but virtually no change in the charge generation radius of the heavy-ion strike. Hence, charge sharing is a troubling reliability roadblock for advanced technologies.
This dissertation introduces and details the charge sharing effect. It examines â through finite element simulations, focused laser testing, and broadbeam heavy ion experiments â the effects of charge sharing at the 130 nm and 90 nm CMOS technology nodes. Results include quantification of the all-important angle of incidence on device and circuit response. Further, this dissertation examines the effectiveness of several charge sharing mitigation techniques.
The work presented in this dissertation directly impacts the SEE qualification techniques used by the radiation community for sub-100 nm technologies. The mitigation techniques proposed and verified are useful for improving the radiation hardness of advanced technologies, and provide designers with design guidelines applicable to space-deployed applications.
Advisors/Committee Members: Dr. Mark N. Ellingham (committee member), Dr. Michael L. Alles (committee member), Dr. Arthur F. Witulski (committee member), Dr. Bharat L. Bhuva (committee member), Dr. Lloyd W. Massengill (chair).
Subjects/Keywords: nodal spacing; single event circuit characterization; soft error cross-section; pulse-widths; guard-bands; Dual Interlocked Cell (DICE) latch; Radiation hardening; Space environment; charge sharing mitigation; heavy-ion; guard-rings; Metal oxide semiconductors Complementary – Effect of radiation on
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APA ·
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APA (6th Edition):
Amusan, O. A. (2009). Effects of single-event-induced charge sharing in sub-100 nm bulk CMOS technologies. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-02162009-141344/ ;
Chicago Manual of Style (16th Edition):
Amusan, Oluwole Ayodele. “Effects of single-event-induced charge sharing in sub-100 nm bulk CMOS technologies.” 2009. Doctoral Dissertation, Vanderbilt University. Accessed October 23, 2019.
http://etd.library.vanderbilt.edu/available/etd-02162009-141344/ ;.
MLA Handbook (7th Edition):
Amusan, Oluwole Ayodele. “Effects of single-event-induced charge sharing in sub-100 nm bulk CMOS technologies.” 2009. Web. 23 Oct 2019.
Vancouver:
Amusan OA. Effects of single-event-induced charge sharing in sub-100 nm bulk CMOS technologies. [Internet] [Doctoral dissertation]. Vanderbilt University; 2009. [cited 2019 Oct 23].
Available from: http://etd.library.vanderbilt.edu/available/etd-02162009-141344/ ;.
Council of Science Editors:
Amusan OA. Effects of single-event-induced charge sharing in sub-100 nm bulk CMOS technologies. [Doctoral Dissertation]. Vanderbilt University; 2009. Available from: http://etd.library.vanderbilt.edu/available/etd-02162009-141344/ ;
30.
Balasubramanian, Anupama.
Measurement and analysis of single event induced crosstalk in nanoscale cmos technologies.
Degree: PhD, Electrical Engineering, 2008, Vanderbilt University
URL: http://etd.library.vanderbilt.edu/available/etd-08202008-122228/
;
► The constant race for increasing the chip density in semiconductor integrated circuits has not only decreased the minimum device feature size but also the minimum…
(more)
▼ The constant race for increasing the chip density in semiconductor integrated circuits has not only decreased the minimum device feature size but also the minimum amount of charge required to represent a HIGH node voltage. In the radiation domain, this translates into reduced charge requirements for generating a Single-Event Transient (SET) and the resulting Single-Event Upset (SEU). Most of the hardening techniques to combat these effects have focused on the propagation of SET pulses through logic gates, without regard to interconnects between them.
In these nanoscale technologies, scaling and closely packed interconnects magnify crosstalk effects causing a SET pulse to affect multiple logic paths instead of the single hit path. Such events increase the vulnerable area and the SET susceptibility of complementary metal-oxide-semiconductor (CMOS) circuits. This research analyses factors affecting the crosstalk pulse due to a SE in digital logic circuits for sub-100 nm technologies.
Specifically, the threefold objective of this research has been achieved: (i) the factors that exacerbate SE induced coupling identified using simulations and modeling (ii) a sample circuit designed, fabricated and tested to provide the first ever experimental measurement of SE induced interconnect crosstalk; and (iii) design margins and mitigation techniques to contain this effect provided. Simulation and Laser absorption experimental results obtained substantiate that the effects of Single Event (SE) induced crosstalk depend greatly on (i) the dV/dt of the aggressor pulse voltage, (ii) the interconnect length (coupling capacitance) and (iii) the driving strengths of devices connected to the aggressor and victim lines. This work has presented to the radiation effects community a new phenomenon that is gaining significance with scaling technologies and the use of commercial foundries to fabricate parts for space. As the semiconductor industry keeps up with the scaling trend of increased chip density and interconnect routing complexity, SE induced crosstalk effects are inevitable. Judicious design and layout planning using analyses performed in this dissertation can help mitigate or contain this effect.
Advisors/Committee Members: Dr. Raymond L. Mernaugh (committee member), Dr. Weng Poo Kang (committee member), Dr. Lloyd W. Massengill (committee member), Dr. Robert A. Reed (committee member), Dr. Bharat L. Bhuva (chair).
Subjects/Keywords: INTERCONNECT; RADIATION; CROSSTALK; SINGLE EVENT; CMOS; SIMULATION; 3D TCAD
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APA ·
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APA (6th Edition):
Balasubramanian, A. (2008). Measurement and analysis of single event induced crosstalk in nanoscale cmos technologies. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-08202008-122228/ ;
Chicago Manual of Style (16th Edition):
Balasubramanian, Anupama. “Measurement and analysis of single event induced crosstalk in nanoscale cmos technologies.” 2008. Doctoral Dissertation, Vanderbilt University. Accessed October 23, 2019.
http://etd.library.vanderbilt.edu/available/etd-08202008-122228/ ;.
MLA Handbook (7th Edition):
Balasubramanian, Anupama. “Measurement and analysis of single event induced crosstalk in nanoscale cmos technologies.” 2008. Web. 23 Oct 2019.
Vancouver:
Balasubramanian A. Measurement and analysis of single event induced crosstalk in nanoscale cmos technologies. [Internet] [Doctoral dissertation]. Vanderbilt University; 2008. [cited 2019 Oct 23].
Available from: http://etd.library.vanderbilt.edu/available/etd-08202008-122228/ ;.
Council of Science Editors:
Balasubramanian A. Measurement and analysis of single event induced crosstalk in nanoscale cmos technologies. [Doctoral Dissertation]. Vanderbilt University; 2008. Available from: http://etd.library.vanderbilt.edu/available/etd-08202008-122228/ ;
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Open Access Theses and Dissertations
