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You searched for +publisher:"Vanderbilt University" +contributor:("Bharat L. Bhuva"). Showing records 1 – 30 of 45 total matches.

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Vanderbilt University

1. Kou, Lingbo. Impact of process variations on soft error sensitivity of 32-nm VLSI circuits in near-threshold region.

Degree: MS, Electrical Engineering, 2014, Vanderbilt University

 Power consumption has become a major concern of integrated circuit (IC) design. Reducing the supply voltage to the near-threshold region is one method to reduce… (more)

Subjects/Keywords: flip-flop; radiation-induced soft errors; sram; near-threshold voltage; critical charge; process variations; reliability

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APA (6th Edition):

Kou, L. (2014). Impact of process variations on soft error sensitivity of 32-nm VLSI circuits in near-threshold region. (Thesis). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/12068

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kou, Lingbo. “Impact of process variations on soft error sensitivity of 32-nm VLSI circuits in near-threshold region.” 2014. Thesis, Vanderbilt University. Accessed March 01, 2021. http://hdl.handle.net/1803/12068.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kou, Lingbo. “Impact of process variations on soft error sensitivity of 32-nm VLSI circuits in near-threshold region.” 2014. Web. 01 Mar 2021.

Vancouver:

Kou L. Impact of process variations on soft error sensitivity of 32-nm VLSI circuits in near-threshold region. [Internet] [Thesis]. Vanderbilt University; 2014. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1803/12068.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kou L. Impact of process variations on soft error sensitivity of 32-nm VLSI circuits in near-threshold region. [Thesis]. Vanderbilt University; 2014. Available from: http://hdl.handle.net/1803/12068

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Vanderbilt University

2. Ossi, Edward John. Soft-error mitigation at the architecture-level using Berger codes for error detection.

Degree: ME, Electrical Engineering, 2011, Vanderbilt University

 Soft-error mitigation using design techniques at the architecture-level can overcome the limitations of process and circuit-level mitigation techniques in advanced technologies. This thesis presents two… (more)

Subjects/Keywords: berger code; architecture; soft error

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APA (6th Edition):

Ossi, E. J. (2011). Soft-error mitigation at the architecture-level using Berger codes for error detection. (Thesis). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/15019

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ossi, Edward John. “Soft-error mitigation at the architecture-level using Berger codes for error detection.” 2011. Thesis, Vanderbilt University. Accessed March 01, 2021. http://hdl.handle.net/1803/15019.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ossi, Edward John. “Soft-error mitigation at the architecture-level using Berger codes for error detection.” 2011. Web. 01 Mar 2021.

Vancouver:

Ossi EJ. Soft-error mitigation at the architecture-level using Berger codes for error detection. [Internet] [Thesis]. Vanderbilt University; 2011. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1803/15019.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ossi EJ. Soft-error mitigation at the architecture-level using Berger codes for error detection. [Thesis]. Vanderbilt University; 2011. Available from: http://hdl.handle.net/1803/15019

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Vanderbilt University

3. Tekumala, Lakshmi Deepika. On-chip characterization of single-event charge-collection.

Degree: MS, Electrical Engineering, 2012, Vanderbilt University

 Particle strikes on microelectronic circuits lead to undesirable current transients on the circuit node due to charge generation and charge collection processes. Typically, TCAD tools… (more)

Subjects/Keywords: single-events; charge collection; autonomous circuit technique; on-chip characterization; UMC 40nm

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APA (6th Edition):

Tekumala, L. D. (2012). On-chip characterization of single-event charge-collection. (Thesis). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/13828

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Tekumala, Lakshmi Deepika. “On-chip characterization of single-event charge-collection.” 2012. Thesis, Vanderbilt University. Accessed March 01, 2021. http://hdl.handle.net/1803/13828.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Tekumala, Lakshmi Deepika. “On-chip characterization of single-event charge-collection.” 2012. Web. 01 Mar 2021.

Vancouver:

Tekumala LD. On-chip characterization of single-event charge-collection. [Internet] [Thesis]. Vanderbilt University; 2012. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1803/13828.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tekumala LD. On-chip characterization of single-event charge-collection. [Thesis]. Vanderbilt University; 2012. Available from: http://hdl.handle.net/1803/13828

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Vanderbilt University

4. Adeleke, Adeola. Logic repair and soft error rate reduction using approximate logic functions.

Degree: MS, Electrical Engineering, 2012, Vanderbilt University

 Continuing CMOS devices scaling causes an increase in the vulnerability of integrated circuits to radiation-induced soft errors. Furthermore, as transistor density increases, the probability of… (more)

Subjects/Keywords: functions; logic; approximate; logic; repair

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APA (6th Edition):

Adeleke, A. (2012). Logic repair and soft error rate reduction using approximate logic functions. (Thesis). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/10736

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Adeleke, Adeola. “Logic repair and soft error rate reduction using approximate logic functions.” 2012. Thesis, Vanderbilt University. Accessed March 01, 2021. http://hdl.handle.net/1803/10736.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Adeleke, Adeola. “Logic repair and soft error rate reduction using approximate logic functions.” 2012. Web. 01 Mar 2021.

Vancouver:

Adeleke A. Logic repair and soft error rate reduction using approximate logic functions. [Internet] [Thesis]. Vanderbilt University; 2012. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1803/10736.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Adeleke A. Logic repair and soft error rate reduction using approximate logic functions. [Thesis]. Vanderbilt University; 2012. Available from: http://hdl.handle.net/1803/10736

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Vanderbilt University

5. Chatterjee, Indranil. Single-event charge collection and upset in 65-nm and 40-nm dual- and triple-well bulk CMOS SRAMS.

Degree: MS, Electrical Engineering, 2012, Vanderbilt University

 CMOS technologies can be either dual-well or triple-well. Triple-well technology has several advantages compared to dual-well technology in terms of electrical performance. Differences in the… (more)

Subjects/Keywords: Soft-errors; Single-Event Upset Reversal; Heavy Ion Irradiation; Triple-well; Dual-well; Single-Event Effects

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APA (6th Edition):

Chatterjee, I. (2012). Single-event charge collection and upset in 65-nm and 40-nm dual- and triple-well bulk CMOS SRAMS. (Thesis). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/11296

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chatterjee, Indranil. “Single-event charge collection and upset in 65-nm and 40-nm dual- and triple-well bulk CMOS SRAMS.” 2012. Thesis, Vanderbilt University. Accessed March 01, 2021. http://hdl.handle.net/1803/11296.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chatterjee, Indranil. “Single-event charge collection and upset in 65-nm and 40-nm dual- and triple-well bulk CMOS SRAMS.” 2012. Web. 01 Mar 2021.

Vancouver:

Chatterjee I. Single-event charge collection and upset in 65-nm and 40-nm dual- and triple-well bulk CMOS SRAMS. [Internet] [Thesis]. Vanderbilt University; 2012. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1803/11296.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chatterjee I. Single-event charge collection and upset in 65-nm and 40-nm dual- and triple-well bulk CMOS SRAMS. [Thesis]. Vanderbilt University; 2012. Available from: http://hdl.handle.net/1803/11296

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Vanderbilt University

6. Jiang, Hui. Drosophila Automated Olfactory Training and Testing System for Associative Learning.

Degree: MS, Electrical Engineering, 2015, Vanderbilt University

 This thesis demonstrates the feasibility of designing and building a Drosophila automated training and testing system for Pavlovian classical associative learning/memory analyses using inexpensive hardware… (more)

Subjects/Keywords: Pavlovian classical conditioning; automation; learning; Drosophila; memory

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APA (6th Edition):

Jiang, H. (2015). Drosophila Automated Olfactory Training and Testing System for Associative Learning. (Thesis). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/10420

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Jiang, Hui. “Drosophila Automated Olfactory Training and Testing System for Associative Learning.” 2015. Thesis, Vanderbilt University. Accessed March 01, 2021. http://hdl.handle.net/1803/10420.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Jiang, Hui. “Drosophila Automated Olfactory Training and Testing System for Associative Learning.” 2015. Web. 01 Mar 2021.

Vancouver:

Jiang H. Drosophila Automated Olfactory Training and Testing System for Associative Learning. [Internet] [Thesis]. Vanderbilt University; 2015. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1803/10420.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Jiang H. Drosophila Automated Olfactory Training and Testing System for Associative Learning. [Thesis]. Vanderbilt University; 2015. Available from: http://hdl.handle.net/1803/10420

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Vanderbilt University

7. Kiddie, Bradley Thomas. Layout-Based Fault Injection for Combinational Logic in Nanometer Technologies.

Degree: MS, Electrical Engineering, 2012, Vanderbilt University

 As feature sizes and operating voltages decrease, single-event transients from particle strikes in logic circuits become more probable. Much literature is available on the effects… (more)

Subjects/Keywords: reliability; radiation-induced faults; single-event transient; multiple transient faults; soft errors; combinational logic; layout

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APA (6th Edition):

Kiddie, B. T. (2012). Layout-Based Fault Injection for Combinational Logic in Nanometer Technologies. (Thesis). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/11408

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kiddie, Bradley Thomas. “Layout-Based Fault Injection for Combinational Logic in Nanometer Technologies.” 2012. Thesis, Vanderbilt University. Accessed March 01, 2021. http://hdl.handle.net/1803/11408.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kiddie, Bradley Thomas. “Layout-Based Fault Injection for Combinational Logic in Nanometer Technologies.” 2012. Web. 01 Mar 2021.

Vancouver:

Kiddie BT. Layout-Based Fault Injection for Combinational Logic in Nanometer Technologies. [Internet] [Thesis]. Vanderbilt University; 2012. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1803/11408.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kiddie BT. Layout-Based Fault Injection for Combinational Logic in Nanometer Technologies. [Thesis]. Vanderbilt University; 2012. Available from: http://hdl.handle.net/1803/11408

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Vanderbilt University

8. Chetia, Jugantor. An efficient AVF estimation technique using circuit partitioning.

Degree: MS, Electrical Engineering, 2012, Vanderbilt University

 Soft errors induced by radiation particles are increasingly becoming a source of concern for reliable design of VLSI systems. An important parameter to quantify the… (more)

Subjects/Keywords: AVF; statistical fault injection; circuit partitioning

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APA (6th Edition):

Chetia, J. (2012). An efficient AVF estimation technique using circuit partitioning. (Thesis). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/10484

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chetia, Jugantor. “An efficient AVF estimation technique using circuit partitioning.” 2012. Thesis, Vanderbilt University. Accessed March 01, 2021. http://hdl.handle.net/1803/10484.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chetia, Jugantor. “An efficient AVF estimation technique using circuit partitioning.” 2012. Web. 01 Mar 2021.

Vancouver:

Chetia J. An efficient AVF estimation technique using circuit partitioning. [Internet] [Thesis]. Vanderbilt University; 2012. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1803/10484.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chetia J. An efficient AVF estimation technique using circuit partitioning. [Thesis]. Vanderbilt University; 2012. Available from: http://hdl.handle.net/1803/10484

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Vanderbilt University

9. Kay, William Hunter. Single-Event Upset Characterization of Flip-Flops Across Temperature and Supply Voltage for a 20-nm Bulk, Planar, CMOS Technology.

Degree: MS, Electrical Engineering, 2015, Vanderbilt University

 The scaling of CMOS technology has brought about the increased susceptibility of circuits to single-event (SE) effects. Electronic systems operating in space often face extreme… (more)

Subjects/Keywords: flip flop; 20 nm; single event; SET; SEE; SEU

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APA (6th Edition):

Kay, W. H. (2015). Single-Event Upset Characterization of Flip-Flops Across Temperature and Supply Voltage for a 20-nm Bulk, Planar, CMOS Technology. (Thesis). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/11784

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kay, William Hunter. “Single-Event Upset Characterization of Flip-Flops Across Temperature and Supply Voltage for a 20-nm Bulk, Planar, CMOS Technology.” 2015. Thesis, Vanderbilt University. Accessed March 01, 2021. http://hdl.handle.net/1803/11784.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kay, William Hunter. “Single-Event Upset Characterization of Flip-Flops Across Temperature and Supply Voltage for a 20-nm Bulk, Planar, CMOS Technology.” 2015. Web. 01 Mar 2021.

Vancouver:

Kay WH. Single-Event Upset Characterization of Flip-Flops Across Temperature and Supply Voltage for a 20-nm Bulk, Planar, CMOS Technology. [Internet] [Thesis]. Vanderbilt University; 2015. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1803/11784.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kay WH. Single-Event Upset Characterization of Flip-Flops Across Temperature and Supply Voltage for a 20-nm Bulk, Planar, CMOS Technology. [Thesis]. Vanderbilt University; 2015. Available from: http://hdl.handle.net/1803/11784

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Vanderbilt University

10. Wei, Xing. Porous silicon waveguide biosensors with a grating coupler.

Degree: PhD, Electrical Engineering, 2012, Vanderbilt University

 Sensitive label-free optical biosensors based on grating-coupled porous silicon (PSi) waveguides are demonstrated for biosensing applications. This is the first time that the benefits of… (more)

Subjects/Keywords: gratings; optical biosensor; Porous silicon; waveguide

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APA (6th Edition):

Wei, X. (2012). Porous silicon waveguide biosensors with a grating coupler. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/11427

Chicago Manual of Style (16th Edition):

Wei, Xing. “Porous silicon waveguide biosensors with a grating coupler.” 2012. Doctoral Dissertation, Vanderbilt University. Accessed March 01, 2021. http://hdl.handle.net/1803/11427.

MLA Handbook (7th Edition):

Wei, Xing. “Porous silicon waveguide biosensors with a grating coupler.” 2012. Web. 01 Mar 2021.

Vancouver:

Wei X. Porous silicon waveguide biosensors with a grating coupler. [Internet] [Doctoral dissertation]. Vanderbilt University; 2012. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1803/11427.

Council of Science Editors:

Wei X. Porous silicon waveguide biosensors with a grating coupler. [Doctoral Dissertation]. Vanderbilt University; 2012. Available from: http://hdl.handle.net/1803/11427


Vanderbilt University

11. Jiang, Hui. Design of soft-error-aware sequential circuits with power and speed optimization.

Degree: PhD, Electrical Engineering, 2018, Vanderbilt University

 A single-event effect (SEE) of circuits is strongly dependent on the supply voltage and the physical capacitance. Reduction in supply voltage as well as technology… (more)

Subjects/Keywords: power optimization; sequential circuit; soft error rate; Single event effects; empirical model

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APA (6th Edition):

Jiang, H. (2018). Design of soft-error-aware sequential circuits with power and speed optimization. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/10911

Chicago Manual of Style (16th Edition):

Jiang, Hui. “Design of soft-error-aware sequential circuits with power and speed optimization.” 2018. Doctoral Dissertation, Vanderbilt University. Accessed March 01, 2021. http://hdl.handle.net/1803/10911.

MLA Handbook (7th Edition):

Jiang, Hui. “Design of soft-error-aware sequential circuits with power and speed optimization.” 2018. Web. 01 Mar 2021.

Vancouver:

Jiang H. Design of soft-error-aware sequential circuits with power and speed optimization. [Internet] [Doctoral dissertation]. Vanderbilt University; 2018. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1803/10911.

Council of Science Editors:

Jiang H. Design of soft-error-aware sequential circuits with power and speed optimization. [Doctoral Dissertation]. Vanderbilt University; 2018. Available from: http://hdl.handle.net/1803/10911


Vanderbilt University

12. Chatterjee, Indranil. Geometric Dependence of the Total Ionizing Dose Response of FinFETs.

Degree: PhD, Electrical Engineering, 2014, Vanderbilt University

 The total ionizing dose induced degradation in advanced deep-submicron CMOS technologies has been significantly reduced by scaling. Damage to isolating field oxides remains a significant… (more)

Subjects/Keywords: Total dose effects; Isolation oxides; Bulk FinFET; SOI FinFET; Parasitic transistor; Oxide traps; Charge trapping

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chatterjee, I. (2014). Geometric Dependence of the Total Ionizing Dose Response of FinFETs. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/13758

Chicago Manual of Style (16th Edition):

Chatterjee, Indranil. “Geometric Dependence of the Total Ionizing Dose Response of FinFETs.” 2014. Doctoral Dissertation, Vanderbilt University. Accessed March 01, 2021. http://hdl.handle.net/1803/13758.

MLA Handbook (7th Edition):

Chatterjee, Indranil. “Geometric Dependence of the Total Ionizing Dose Response of FinFETs.” 2014. Web. 01 Mar 2021.

Vancouver:

Chatterjee I. Geometric Dependence of the Total Ionizing Dose Response of FinFETs. [Internet] [Doctoral dissertation]. Vanderbilt University; 2014. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1803/13758.

Council of Science Editors:

Chatterjee I. Geometric Dependence of the Total Ionizing Dose Response of FinFETs. [Doctoral Dissertation]. Vanderbilt University; 2014. Available from: http://hdl.handle.net/1803/13758


Vanderbilt University

13. Jagannathan, Srikanth. TID characterization of high frequency RF circuits in NANO-CMOS technologies.

Degree: PhD, Electrical Engineering, 2013, Vanderbilt University

 Rapid downscaling of CMOS technology has resulted in significant improvement in the RF performance of Silicon MOSFETs. As a result, standard CMOS technology has become… (more)

Subjects/Keywords: RF; TID

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APA (6th Edition):

Jagannathan, S. (2013). TID characterization of high frequency RF circuits in NANO-CMOS technologies. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/14535

Chicago Manual of Style (16th Edition):

Jagannathan, Srikanth. “TID characterization of high frequency RF circuits in NANO-CMOS technologies.” 2013. Doctoral Dissertation, Vanderbilt University. Accessed March 01, 2021. http://hdl.handle.net/1803/14535.

MLA Handbook (7th Edition):

Jagannathan, Srikanth. “TID characterization of high frequency RF circuits in NANO-CMOS technologies.” 2013. Web. 01 Mar 2021.

Vancouver:

Jagannathan S. TID characterization of high frequency RF circuits in NANO-CMOS technologies. [Internet] [Doctoral dissertation]. Vanderbilt University; 2013. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1803/14535.

Council of Science Editors:

Jagannathan S. TID characterization of high frequency RF circuits in NANO-CMOS technologies. [Doctoral Dissertation]. Vanderbilt University; 2013. Available from: http://hdl.handle.net/1803/14535


Vanderbilt University

14. Kauppila, Amy Vaughn. Analysis of parameter variation impact on the single event response in sub-100nm CMOS storage cells.

Degree: PhD, Electrical Engineering, 2012, Vanderbilt University

 Current deep sub-micron technologies are particularly susceptible to single events. The challenge derives from a conglomeration of effects that affect circuits’ radiation response. For instance,… (more)

Subjects/Keywords: single event upset; parameter variation

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APA (6th Edition):

Kauppila, A. V. (2012). Analysis of parameter variation impact on the single event response in sub-100nm CMOS storage cells. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/12080

Chicago Manual of Style (16th Edition):

Kauppila, Amy Vaughn. “Analysis of parameter variation impact on the single event response in sub-100nm CMOS storage cells.” 2012. Doctoral Dissertation, Vanderbilt University. Accessed March 01, 2021. http://hdl.handle.net/1803/12080.

MLA Handbook (7th Edition):

Kauppila, Amy Vaughn. “Analysis of parameter variation impact on the single event response in sub-100nm CMOS storage cells.” 2012. Web. 01 Mar 2021.

Vancouver:

Kauppila AV. Analysis of parameter variation impact on the single event response in sub-100nm CMOS storage cells. [Internet] [Doctoral dissertation]. Vanderbilt University; 2012. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1803/12080.

Council of Science Editors:

Kauppila AV. Analysis of parameter variation impact on the single event response in sub-100nm CMOS storage cells. [Doctoral Dissertation]. Vanderbilt University; 2012. Available from: http://hdl.handle.net/1803/12080


Vanderbilt University

15. Saxena, Tripti. A Generic Framework for Design Space Exploration.

Degree: PhD, Computer Science, 2012, Vanderbilt University

 As the complexity of software systems rises, designers are often faced with the challenge of identifying potential design solutions from a large space of possible… (more)

Subjects/Keywords: Design Space Exploration; Model-driven development; Constraint Programming

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APA (6th Edition):

Saxena, T. (2012). A Generic Framework for Design Space Exploration. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/13790

Chicago Manual of Style (16th Edition):

Saxena, Tripti. “A Generic Framework for Design Space Exploration.” 2012. Doctoral Dissertation, Vanderbilt University. Accessed March 01, 2021. http://hdl.handle.net/1803/13790.

MLA Handbook (7th Edition):

Saxena, Tripti. “A Generic Framework for Design Space Exploration.” 2012. Web. 01 Mar 2021.

Vancouver:

Saxena T. A Generic Framework for Design Space Exploration. [Internet] [Doctoral dissertation]. Vanderbilt University; 2012. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1803/13790.

Council of Science Editors:

Saxena T. A Generic Framework for Design Space Exploration. [Doctoral Dissertation]. Vanderbilt University; 2012. Available from: http://hdl.handle.net/1803/13790


Vanderbilt University

16. Hsu, Shao-Hua. Development of Vertical Nanodiamond Vacuum Field Emission Microelectronic Integrated Devices.

Degree: PhD, Electrical Engineering, 2014, Vanderbilt University

 Recent development of nanocrystalline diamonds has demonstrated the potential use of diamond material for vacuum microelectronics. Apart from the advantages of conventional microcrystalline diamond, nanodiamond… (more)

Subjects/Keywords: Microelectronic Devices; Nanodiamond; Vacuum Field Emission; Integrated Circuits; Signal Amplifiers

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APA (6th Edition):

Hsu, S. (2014). Development of Vertical Nanodiamond Vacuum Field Emission Microelectronic Integrated Devices. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/10632

Chicago Manual of Style (16th Edition):

Hsu, Shao-Hua. “Development of Vertical Nanodiamond Vacuum Field Emission Microelectronic Integrated Devices.” 2014. Doctoral Dissertation, Vanderbilt University. Accessed March 01, 2021. http://hdl.handle.net/1803/10632.

MLA Handbook (7th Edition):

Hsu, Shao-Hua. “Development of Vertical Nanodiamond Vacuum Field Emission Microelectronic Integrated Devices.” 2014. Web. 01 Mar 2021.

Vancouver:

Hsu S. Development of Vertical Nanodiamond Vacuum Field Emission Microelectronic Integrated Devices. [Internet] [Doctoral dissertation]. Vanderbilt University; 2014. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1803/10632.

Council of Science Editors:

Hsu S. Development of Vertical Nanodiamond Vacuum Field Emission Microelectronic Integrated Devices. [Doctoral Dissertation]. Vanderbilt University; 2014. Available from: http://hdl.handle.net/1803/10632


Vanderbilt University

17. Gaspard, Nelson Joseph III. Single-Event Upset Technology Scaling Trends of Unhardened and Hardened Flip-Flops in Bulk CMOS.

Degree: PhD, Electrical Engineering, 2017, Vanderbilt University

 Alpha, heavy-ion, neutron, and proton experimental results from 130-nm to 28-nm technology nodes are establish single-event upset cross section trends in soft and hardened flip-flop… (more)

Subjects/Keywords: single event upset; CMOS; flip-flop; soft error

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APA (6th Edition):

Gaspard, N. J. I. (2017). Single-Event Upset Technology Scaling Trends of Unhardened and Hardened Flip-Flops in Bulk CMOS. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/10824

Chicago Manual of Style (16th Edition):

Gaspard, Nelson Joseph III. “Single-Event Upset Technology Scaling Trends of Unhardened and Hardened Flip-Flops in Bulk CMOS.” 2017. Doctoral Dissertation, Vanderbilt University. Accessed March 01, 2021. http://hdl.handle.net/1803/10824.

MLA Handbook (7th Edition):

Gaspard, Nelson Joseph III. “Single-Event Upset Technology Scaling Trends of Unhardened and Hardened Flip-Flops in Bulk CMOS.” 2017. Web. 01 Mar 2021.

Vancouver:

Gaspard NJI. Single-Event Upset Technology Scaling Trends of Unhardened and Hardened Flip-Flops in Bulk CMOS. [Internet] [Doctoral dissertation]. Vanderbilt University; 2017. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1803/10824.

Council of Science Editors:

Gaspard NJI. Single-Event Upset Technology Scaling Trends of Unhardened and Hardened Flip-Flops in Bulk CMOS. [Doctoral Dissertation]. Vanderbilt University; 2017. Available from: http://hdl.handle.net/1803/10824


Vanderbilt University

18. Kiddie, Bradley Thomas. Single-Event Multiple-Transient Characterization and Mitigation via Standard Cell Placement Methods.

Degree: PhD, Electrical Engineering, 2016, Vanderbilt University

 The effects of radiation on the operation of integrated circuits (IC) continue to take a more important role as technology feature sizes scale down, critical… (more)

Subjects/Keywords: reliability; radiation; eda; single-event transient; single-event multiple-transient; placement; algorithm

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APA (6th Edition):

Kiddie, B. T. (2016). Single-Event Multiple-Transient Characterization and Mitigation via Standard Cell Placement Methods. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/14250

Chicago Manual of Style (16th Edition):

Kiddie, Bradley Thomas. “Single-Event Multiple-Transient Characterization and Mitigation via Standard Cell Placement Methods.” 2016. Doctoral Dissertation, Vanderbilt University. Accessed March 01, 2021. http://hdl.handle.net/1803/14250.

MLA Handbook (7th Edition):

Kiddie, Bradley Thomas. “Single-Event Multiple-Transient Characterization and Mitigation via Standard Cell Placement Methods.” 2016. Web. 01 Mar 2021.

Vancouver:

Kiddie BT. Single-Event Multiple-Transient Characterization and Mitigation via Standard Cell Placement Methods. [Internet] [Doctoral dissertation]. Vanderbilt University; 2016. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1803/14250.

Council of Science Editors:

Kiddie BT. Single-Event Multiple-Transient Characterization and Mitigation via Standard Cell Placement Methods. [Doctoral Dissertation]. Vanderbilt University; 2016. Available from: http://hdl.handle.net/1803/14250


Vanderbilt University

19. Reece, Trey. Assessing and Detecting Malicious Hardware in Integrated Circuits.

Degree: PhD, Electrical Engineering, 2014, Vanderbilt University

 System security often focuses on the software, causing hardware security to be overlooked. Such oversight allows for attacks that can completely undermine the use of… (more)

Subjects/Keywords: integrated circuit design; vlsi; hardware trojan; hardware security; verification

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APA (6th Edition):

Reece, T. (2014). Assessing and Detecting Malicious Hardware in Integrated Circuits. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/15155

Chicago Manual of Style (16th Edition):

Reece, Trey. “Assessing and Detecting Malicious Hardware in Integrated Circuits.” 2014. Doctoral Dissertation, Vanderbilt University. Accessed March 01, 2021. http://hdl.handle.net/1803/15155.

MLA Handbook (7th Edition):

Reece, Trey. “Assessing and Detecting Malicious Hardware in Integrated Circuits.” 2014. Web. 01 Mar 2021.

Vancouver:

Reece T. Assessing and Detecting Malicious Hardware in Integrated Circuits. [Internet] [Doctoral dissertation]. Vanderbilt University; 2014. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1803/15155.

Council of Science Editors:

Reece T. Assessing and Detecting Malicious Hardware in Integrated Circuits. [Doctoral Dissertation]. Vanderbilt University; 2014. Available from: http://hdl.handle.net/1803/15155


Vanderbilt University

20. Ghosh, Nikkon. Monolithic multifinger lateral nanodiamond electron emission devices.

Degree: PhD, Electrical Engineering, 2012, Vanderbilt University

 Chemical-vapor-deposited (CVD) diamond is an excellent electron emission material due to its low electron affinity, robust mechanical and chemical properties, high thermal conductivity, and ability… (more)

Subjects/Keywords: ELECTRON-EMISSION; NANO-GAP; LATERAL; MONOLITHIC; NANODIAMOND

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APA (6th Edition):

Ghosh, N. (2012). Monolithic multifinger lateral nanodiamond electron emission devices. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/14363

Chicago Manual of Style (16th Edition):

Ghosh, Nikkon. “Monolithic multifinger lateral nanodiamond electron emission devices.” 2012. Doctoral Dissertation, Vanderbilt University. Accessed March 01, 2021. http://hdl.handle.net/1803/14363.

MLA Handbook (7th Edition):

Ghosh, Nikkon. “Monolithic multifinger lateral nanodiamond electron emission devices.” 2012. Web. 01 Mar 2021.

Vancouver:

Ghosh N. Monolithic multifinger lateral nanodiamond electron emission devices. [Internet] [Doctoral dissertation]. Vanderbilt University; 2012. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1803/14363.

Council of Science Editors:

Ghosh N. Monolithic multifinger lateral nanodiamond electron emission devices. [Doctoral Dissertation]. Vanderbilt University; 2012. Available from: http://hdl.handle.net/1803/14363


Vanderbilt University

21. Chen, Yanran. Analysis and hardening of all-digital phase-locked loops (ADPLLs) to single-event radiation effects.

Degree: PhD, Electrical Engineering, 2017, Vanderbilt University

 In deep sub-micron CMOS technologies, all-digital phase-locked loops (ADPLLs) are favored over conventional analog or mixed-signal phase-locked loops (A/MS) PLLs for providing the clock signals… (more)

Subjects/Keywords: Single-Event Upsets (SEU); All-digital Phase-locked Loops (ADPLLs); Single-Event Effects (SEE)

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APA (6th Edition):

Chen, Y. (2017). Analysis and hardening of all-digital phase-locked loops (ADPLLs) to single-event radiation effects. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/14206

Chicago Manual of Style (16th Edition):

Chen, Yanran. “Analysis and hardening of all-digital phase-locked loops (ADPLLs) to single-event radiation effects.” 2017. Doctoral Dissertation, Vanderbilt University. Accessed March 01, 2021. http://hdl.handle.net/1803/14206.

MLA Handbook (7th Edition):

Chen, Yanran. “Analysis and hardening of all-digital phase-locked loops (ADPLLs) to single-event radiation effects.” 2017. Web. 01 Mar 2021.

Vancouver:

Chen Y. Analysis and hardening of all-digital phase-locked loops (ADPLLs) to single-event radiation effects. [Internet] [Doctoral dissertation]. Vanderbilt University; 2017. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1803/14206.

Council of Science Editors:

Chen Y. Analysis and hardening of all-digital phase-locked loops (ADPLLs) to single-event radiation effects. [Doctoral Dissertation]. Vanderbilt University; 2017. Available from: http://hdl.handle.net/1803/14206


Vanderbilt University

22. Zhang, Hangfang. Impact of Designer-Controlled Parameters on Single-Event Responses for Flip-Flop Designs in Advanced Technologies.

Degree: PhD, Electrical Engineering, 2018, Vanderbilt University

 Modern ICs need to be designed with proper designer-controllable factors to meet power, speed and single-event (SE) performance requirements in different applications. Commercial fabrication houses… (more)

Subjects/Keywords: Single Event; Threshold Voltage; FinFET; Design Parameter; Temperature; Angular Incidence; Flip-Flop; Well Structure

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APA (6th Edition):

Zhang, H. (2018). Impact of Designer-Controlled Parameters on Single-Event Responses for Flip-Flop Designs in Advanced Technologies. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/12055

Chicago Manual of Style (16th Edition):

Zhang, Hangfang. “Impact of Designer-Controlled Parameters on Single-Event Responses for Flip-Flop Designs in Advanced Technologies.” 2018. Doctoral Dissertation, Vanderbilt University. Accessed March 01, 2021. http://hdl.handle.net/1803/12055.

MLA Handbook (7th Edition):

Zhang, Hangfang. “Impact of Designer-Controlled Parameters on Single-Event Responses for Flip-Flop Designs in Advanced Technologies.” 2018. Web. 01 Mar 2021.

Vancouver:

Zhang H. Impact of Designer-Controlled Parameters on Single-Event Responses for Flip-Flop Designs in Advanced Technologies. [Internet] [Doctoral dissertation]. Vanderbilt University; 2018. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1803/12055.

Council of Science Editors:

Zhang H. Impact of Designer-Controlled Parameters on Single-Event Responses for Flip-Flop Designs in Advanced Technologies. [Doctoral Dissertation]. Vanderbilt University; 2018. Available from: http://hdl.handle.net/1803/12055


Vanderbilt University

23. Assis, Thiago Rocha de. Soft error aware physical synthesis.

Degree: PhD, Electrical Engineering, 2015, Vanderbilt University

 To allow accurate analysis of Soft Errors by Electronic Design Automation (EDA) tools, analytical models were developed to estimate electrical characteristics of the single event.… (more)

Subjects/Keywords: single event transient; set pulse width; collected charge; radiation effects; electronic design automation; physical synthesis; soft error; reliability

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APA (6th Edition):

Assis, T. R. d. (2015). Soft error aware physical synthesis. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/14789

Chicago Manual of Style (16th Edition):

Assis, Thiago Rocha de. “Soft error aware physical synthesis.” 2015. Doctoral Dissertation, Vanderbilt University. Accessed March 01, 2021. http://hdl.handle.net/1803/14789.

MLA Handbook (7th Edition):

Assis, Thiago Rocha de. “Soft error aware physical synthesis.” 2015. Web. 01 Mar 2021.

Vancouver:

Assis TRd. Soft error aware physical synthesis. [Internet] [Doctoral dissertation]. Vanderbilt University; 2015. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1803/14789.

Council of Science Editors:

Assis TRd. Soft error aware physical synthesis. [Doctoral Dissertation]. Vanderbilt University; 2015. Available from: http://hdl.handle.net/1803/14789


Vanderbilt University

24. Raina, Supil. Nanodiamond macroelectrodes and ultramicroelectrode arrays for bio-analyte detection.

Degree: PhD, Interdisciplinary Materials Science, 2011, Vanderbilt University

 Properties such as high electrical conductivity; chemical and electrochemical stability over a wide range of conditions; rapid electron transfer kinetics for different redox systems; and… (more)

Subjects/Keywords: fast scan cyclic voltammetry; diffusion; electrochemistry; dopamine; nanodiamond

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APA (6th Edition):

Raina, S. (2011). Nanodiamond macroelectrodes and ultramicroelectrode arrays for bio-analyte detection. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/14408

Chicago Manual of Style (16th Edition):

Raina, Supil. “Nanodiamond macroelectrodes and ultramicroelectrode arrays for bio-analyte detection.” 2011. Doctoral Dissertation, Vanderbilt University. Accessed March 01, 2021. http://hdl.handle.net/1803/14408.

MLA Handbook (7th Edition):

Raina, Supil. “Nanodiamond macroelectrodes and ultramicroelectrode arrays for bio-analyte detection.” 2011. Web. 01 Mar 2021.

Vancouver:

Raina S. Nanodiamond macroelectrodes and ultramicroelectrode arrays for bio-analyte detection. [Internet] [Doctoral dissertation]. Vanderbilt University; 2011. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1803/14408.

Council of Science Editors:

Raina S. Nanodiamond macroelectrodes and ultramicroelectrode arrays for bio-analyte detection. [Doctoral Dissertation]. Vanderbilt University; 2011. Available from: http://hdl.handle.net/1803/14408


Vanderbilt University

25. Kauppila, Jeffrey Scott. Layout-Aware Modeling and Analysis Methodologies for Transient Radiation Effects on Integrated Circuit Electronics.

Degree: PhD, Electrical Engineering, 2015, Vanderbilt University

 The development of integrated circuits intended for use in transient radiation environments must account for the impact of the environment on the operation of the… (more)

Subjects/Keywords: CAD Tools; Semiconductor Device Modeling; Process Design Kit; Gummel Poon; BSIMSOI; MEXTRAM; Radiation Modeling; TCAD; BSIM4; Bias-Dependent Modeling; Dose Rate Effects; Compact Models; Single Event Effects; Compact Model; BJT; MOSFET; Layout-Aware Modeling; Layout-Aware Analysis; SPICE; Layout; Radiation Effects; Circuit Simulation; Radiation-Enabled Model; Single-Event Transient; Single-Event Upset; Charge Sharing; Computational Modeling

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APA (6th Edition):

Kauppila, J. S. (2015). Layout-Aware Modeling and Analysis Methodologies for Transient Radiation Effects on Integrated Circuit Electronics. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/10793

Chicago Manual of Style (16th Edition):

Kauppila, Jeffrey Scott. “Layout-Aware Modeling and Analysis Methodologies for Transient Radiation Effects on Integrated Circuit Electronics.” 2015. Doctoral Dissertation, Vanderbilt University. Accessed March 01, 2021. http://hdl.handle.net/1803/10793.

MLA Handbook (7th Edition):

Kauppila, Jeffrey Scott. “Layout-Aware Modeling and Analysis Methodologies for Transient Radiation Effects on Integrated Circuit Electronics.” 2015. Web. 01 Mar 2021.

Vancouver:

Kauppila JS. Layout-Aware Modeling and Analysis Methodologies for Transient Radiation Effects on Integrated Circuit Electronics. [Internet] [Doctoral dissertation]. Vanderbilt University; 2015. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1803/10793.

Council of Science Editors:

Kauppila JS. Layout-Aware Modeling and Analysis Methodologies for Transient Radiation Effects on Integrated Circuit Electronics. [Doctoral Dissertation]. Vanderbilt University; 2015. Available from: http://hdl.handle.net/1803/10793


Vanderbilt University

26. Narasimham, Balaji. On Chip Characterization of Single Event Transient Pulse Widths.

Degree: MS, Electrical Engineering, 2005, Vanderbilt University

 It is now well known to the radiation effects community that single event effects caused by energetic particles, particularly single event transients, will be among… (more)

Subjects/Keywords: transient pulse width; SET; SEU; single event; CMOS; RHBD; Radiation hardening; Integrated circuits  – Effect of radiation on  – Computer simulation

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APA (6th Edition):

Narasimham, B. (2005). On Chip Characterization of Single Event Transient Pulse Widths. (Thesis). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/14887

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Narasimham, Balaji. “On Chip Characterization of Single Event Transient Pulse Widths.” 2005. Thesis, Vanderbilt University. Accessed March 01, 2021. http://hdl.handle.net/1803/14887.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Narasimham, Balaji. “On Chip Characterization of Single Event Transient Pulse Widths.” 2005. Web. 01 Mar 2021.

Vancouver:

Narasimham B. On Chip Characterization of Single Event Transient Pulse Widths. [Internet] [Thesis]. Vanderbilt University; 2005. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1803/14887.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Narasimham B. On Chip Characterization of Single Event Transient Pulse Widths. [Thesis]. Vanderbilt University; 2005. Available from: http://hdl.handle.net/1803/14887

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Vanderbilt University

27. Reece, Trey. Detection of Malicious Hardware in ASICs and FPGAs.

Degree: MS, Electrical Engineering, 2009, Vanderbilt University

 Detecting malicious modifications to a circuit is a daunting task, regardless of the medium. In a fabricated circuit, most methods of detecting hardware Trojans rely… (more)

Subjects/Keywords: Malicious Hardware; Process variation; hardware trojan

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APA (6th Edition):

Reece, T. (2009). Detection of Malicious Hardware in ASICs and FPGAs. (Thesis). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/15004

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Reece, Trey. “Detection of Malicious Hardware in ASICs and FPGAs.” 2009. Thesis, Vanderbilt University. Accessed March 01, 2021. http://hdl.handle.net/1803/15004.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Reece, Trey. “Detection of Malicious Hardware in ASICs and FPGAs.” 2009. Web. 01 Mar 2021.

Vancouver:

Reece T. Detection of Malicious Hardware in ASICs and FPGAs. [Internet] [Thesis]. Vanderbilt University; 2009. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1803/15004.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Reece T. Detection of Malicious Hardware in ASICs and FPGAs. [Thesis]. Vanderbilt University; 2009. Available from: http://hdl.handle.net/1803/15004

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Vanderbilt University

28. Holt, Christopher. Analysis of single event transients in dynamic logic circuitry.

Degree: MS, Electrical Engineering, 2008, Vanderbilt University

 Dynamic logic circuitry is generally faster and smaller than equivalent static logic circuits. The use of these circuits in space is desirable, but not much… (more)

Subjects/Keywords: Logic circuits  – Testing; SETs; Dynamic logic; single event transients; Integrated circuits  – Effect of radiation on

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APA (6th Edition):

Holt, C. (2008). Analysis of single event transients in dynamic logic circuitry. (Thesis). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/11928

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Holt, Christopher. “Analysis of single event transients in dynamic logic circuitry.” 2008. Thesis, Vanderbilt University. Accessed March 01, 2021. http://hdl.handle.net/1803/11928.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Holt, Christopher. “Analysis of single event transients in dynamic logic circuitry.” 2008. Web. 01 Mar 2021.

Vancouver:

Holt C. Analysis of single event transients in dynamic logic circuitry. [Internet] [Thesis]. Vanderbilt University; 2008. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1803/11928.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Holt C. Analysis of single event transients in dynamic logic circuitry. [Thesis]. Vanderbilt University; 2008. Available from: http://hdl.handle.net/1803/11928

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Vanderbilt University

29. Limbrick, Daniel Brian. Mitigation of Radiation-induced Soft Errors Using Temporal Embedded Signature Monitoring.

Degree: MS, Electrical Engineering, 2009, Vanderbilt University

 Soft errors can alter the correct execution of code within a microprocessor, particularly if control logic is compromised. This thesis addresses the vulnerability of a… (more)

Subjects/Keywords: signature monitoring; control flow; architectural reliability; soft errors

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APA (6th Edition):

Limbrick, D. B. (2009). Mitigation of Radiation-induced Soft Errors Using Temporal Embedded Signature Monitoring. (Thesis). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/15101

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Limbrick, Daniel Brian. “Mitigation of Radiation-induced Soft Errors Using Temporal Embedded Signature Monitoring.” 2009. Thesis, Vanderbilt University. Accessed March 01, 2021. http://hdl.handle.net/1803/15101.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Limbrick, Daniel Brian. “Mitigation of Radiation-induced Soft Errors Using Temporal Embedded Signature Monitoring.” 2009. Web. 01 Mar 2021.

Vancouver:

Limbrick DB. Mitigation of Radiation-induced Soft Errors Using Temporal Embedded Signature Monitoring. [Internet] [Thesis]. Vanderbilt University; 2009. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1803/15101.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Limbrick DB. Mitigation of Radiation-induced Soft Errors Using Temporal Embedded Signature Monitoring. [Thesis]. Vanderbilt University; 2009. Available from: http://hdl.handle.net/1803/15101

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Vanderbilt University

30. Pagey, Manish Prabhakar. Characterization and modeling of hot-carrier degradation in sub-micron NMOSFETS.

Degree: MS, Electrical Engineering, 2003, Vanderbilt University

 The continuous demand for higher packing density and faster operating speeds in modern digital CMOS circuits has driven the scaling of the metal-oxide-silicon field effect… (more)

Subjects/Keywords: mosfet; oxide; degradation; reliability; hot-carrier

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APA (6th Edition):

Pagey, M. P. (2003). Characterization and modeling of hot-carrier degradation in sub-micron NMOSFETS. (Thesis). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/12629

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Pagey, Manish Prabhakar. “Characterization and modeling of hot-carrier degradation in sub-micron NMOSFETS.” 2003. Thesis, Vanderbilt University. Accessed March 01, 2021. http://hdl.handle.net/1803/12629.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Pagey, Manish Prabhakar. “Characterization and modeling of hot-carrier degradation in sub-micron NMOSFETS.” 2003. Web. 01 Mar 2021.

Vancouver:

Pagey MP. Characterization and modeling of hot-carrier degradation in sub-micron NMOSFETS. [Internet] [Thesis]. Vanderbilt University; 2003. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1803/12629.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Pagey MP. Characterization and modeling of hot-carrier degradation in sub-micron NMOSFETS. [Thesis]. Vanderbilt University; 2003. Available from: http://hdl.handle.net/1803/12629

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

[1] [2]

.