+publisher:"Vanderbilt University" +contributor:("Bharat L. Bhuva")

Vanderbilt University

1. Kou, Lingbo. Impact of process variations on soft error sensitivity of 32-nm VLSI circuits in near-threshold region.

Degree: MS, Electrical Engineering, 2014, Vanderbilt University

URL: http://hdl.handle.net/1803/12068

► Power consumption has become a major concern of integrated circuit (IC) design. Reducing the supply voltage to the near-threshold region is one method to reduce… (more)

Subjects/Keywords: flip-flop; radiation-induced soft errors; sram; near-threshold voltage; critical charge; process variations; reliability

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Kou, L. (2014). Impact of process variations on soft error sensitivity of 32-nm VLSI circuits in near-threshold region. (Thesis). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/12068

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Kou, Lingbo. “Impact of process variations on soft error sensitivity of 32-nm VLSI circuits in near-threshold region.” 2014. Thesis, Vanderbilt University. Accessed March 01, 2021. http://hdl.handle.net/1803/12068.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Kou, Lingbo. “Impact of process variations on soft error sensitivity of 32-nm VLSI circuits in near-threshold region.” 2014. Web. 01 Mar 2021.

Vancouver:

Kou L. Impact of process variations on soft error sensitivity of 32-nm VLSI circuits in near-threshold region. [Internet] [Thesis]. Vanderbilt University; 2014. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1803/12068.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kou L. Impact of process variations on soft error sensitivity of 32-nm VLSI circuits in near-threshold region. [Thesis]. Vanderbilt University; 2014. Available from: http://hdl.handle.net/1803/12068

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Vanderbilt University

2. Ossi, Edward John. Soft-error mitigation at the architecture-level using Berger codes for error detection.

Degree: ME, Electrical Engineering, 2011, Vanderbilt University

URL: http://hdl.handle.net/1803/15019

► Soft-error mitigation using design techniques at the architecture-level can overcome the limitations of process and circuit-level mitigation techniques in advanced technologies. This thesis presents two… (more)

Subjects/Keywords: berger code; architecture; soft error

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Ossi, E. J. (2011). Soft-error mitigation at the architecture-level using Berger codes for error detection. (Thesis). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/15019

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Ossi, Edward John. “Soft-error mitigation at the architecture-level using Berger codes for error detection.” 2011. Thesis, Vanderbilt University. Accessed March 01, 2021. http://hdl.handle.net/1803/15019.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Ossi, Edward John. “Soft-error mitigation at the architecture-level using Berger codes for error detection.” 2011. Web. 01 Mar 2021.

Vancouver:

Ossi EJ. Soft-error mitigation at the architecture-level using Berger codes for error detection. [Internet] [Thesis]. Vanderbilt University; 2011. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1803/15019.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ossi EJ. Soft-error mitigation at the architecture-level using Berger codes for error detection. [Thesis]. Vanderbilt University; 2011. Available from: http://hdl.handle.net/1803/15019

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Vanderbilt University

3. Tekumala, Lakshmi Deepika. On-chip characterization of single-event charge-collection.

Degree: MS, Electrical Engineering, 2012, Vanderbilt University

URL: http://hdl.handle.net/1803/13828

► Particle strikes on microelectronic circuits lead to undesirable current transients on the circuit node due to charge generation and charge collection processes. Typically, TCAD tools… (more)

Subjects/Keywords: single-events; charge collection; autonomous circuit technique; on-chip characterization; UMC 40nm

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Tekumala, L. D. (2012). On-chip characterization of single-event charge-collection. (Thesis). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/13828

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Tekumala, Lakshmi Deepika. “On-chip characterization of single-event charge-collection.” 2012. Thesis, Vanderbilt University. Accessed March 01, 2021. http://hdl.handle.net/1803/13828.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Tekumala, Lakshmi Deepika. “On-chip characterization of single-event charge-collection.” 2012. Web. 01 Mar 2021.

Vancouver:

Tekumala LD. On-chip characterization of single-event charge-collection. [Internet] [Thesis]. Vanderbilt University; 2012. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1803/13828.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tekumala LD. On-chip characterization of single-event charge-collection. [Thesis]. Vanderbilt University; 2012. Available from: http://hdl.handle.net/1803/13828

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Vanderbilt University

4. Adeleke, Adeola. Logic repair and soft error rate reduction using approximate logic functions.

Degree: MS, Electrical Engineering, 2012, Vanderbilt University

URL: http://hdl.handle.net/1803/10736

► Continuing CMOS devices scaling causes an increase in the vulnerability of integrated circuits to radiation-induced soft errors. Furthermore, as transistor density increases, the probability of… (more)

Subjects/Keywords: functions; logic; approximate; logic; repair

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Adeleke, A. (2012). Logic repair and soft error rate reduction using approximate logic functions. (Thesis). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/10736

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Adeleke, Adeola. “Logic repair and soft error rate reduction using approximate logic functions.” 2012. Thesis, Vanderbilt University. Accessed March 01, 2021. http://hdl.handle.net/1803/10736.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Adeleke, Adeola. “Logic repair and soft error rate reduction using approximate logic functions.” 2012. Web. 01 Mar 2021.

Vancouver:

Adeleke A. Logic repair and soft error rate reduction using approximate logic functions. [Internet] [Thesis]. Vanderbilt University; 2012. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1803/10736.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Adeleke A. Logic repair and soft error rate reduction using approximate logic functions. [Thesis]. Vanderbilt University; 2012. Available from: http://hdl.handle.net/1803/10736

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Vanderbilt University

5. Chatterjee, Indranil. Single-event charge collection and upset in 65-nm and 40-nm dual- and triple-well bulk CMOS SRAMS.

Degree: MS, Electrical Engineering, 2012, Vanderbilt University

URL: http://hdl.handle.net/1803/11296

► CMOS technologies can be either dual-well or triple-well. Triple-well technology has several advantages compared to dual-well technology in terms of electrical performance. Differences in the… (more)

Subjects/Keywords: Soft-errors; Single-Event Upset Reversal; Heavy Ion Irradiation; Triple-well; Dual-well; Single-Event Effects

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Chatterjee, I. (2012). Single-event charge collection and upset in 65-nm and 40-nm dual- and triple-well bulk CMOS SRAMS. (Thesis). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/11296

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Chatterjee, Indranil. “Single-event charge collection and upset in 65-nm and 40-nm dual- and triple-well bulk CMOS SRAMS.” 2012. Thesis, Vanderbilt University. Accessed March 01, 2021. http://hdl.handle.net/1803/11296.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Chatterjee, Indranil. “Single-event charge collection and upset in 65-nm and 40-nm dual- and triple-well bulk CMOS SRAMS.” 2012. Web. 01 Mar 2021.

Vancouver:

Chatterjee I. Single-event charge collection and upset in 65-nm and 40-nm dual- and triple-well bulk CMOS SRAMS. [Internet] [Thesis]. Vanderbilt University; 2012. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1803/11296.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chatterjee I. Single-event charge collection and upset in 65-nm and 40-nm dual- and triple-well bulk CMOS SRAMS. [Thesis]. Vanderbilt University; 2012. Available from: http://hdl.handle.net/1803/11296

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Vanderbilt University

6. Jiang, Hui. Drosophila Automated Olfactory Training and Testing System for Associative Learning.

Degree: MS, Electrical Engineering, 2015, Vanderbilt University

URL: http://hdl.handle.net/1803/10420

► This thesis demonstrates the feasibility of designing and building a Drosophila automated training and testing system for Pavlovian classical associative learning/memory analyses using inexpensive hardware… (more)

Subjects/Keywords: Pavlovian classical conditioning; automation; learning; Drosophila; memory

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Jiang, H. (2015). Drosophila Automated Olfactory Training and Testing System for Associative Learning. (Thesis). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/10420

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Jiang, Hui. “Drosophila Automated Olfactory Training and Testing System for Associative Learning.” 2015. Thesis, Vanderbilt University. Accessed March 01, 2021. http://hdl.handle.net/1803/10420.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Jiang, Hui. “Drosophila Automated Olfactory Training and Testing System for Associative Learning.” 2015. Web. 01 Mar 2021.

Vancouver:

Jiang H. Drosophila Automated Olfactory Training and Testing System for Associative Learning. [Internet] [Thesis]. Vanderbilt University; 2015. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1803/10420.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Jiang H. Drosophila Automated Olfactory Training and Testing System for Associative Learning. [Thesis]. Vanderbilt University; 2015. Available from: http://hdl.handle.net/1803/10420

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Vanderbilt University

7. Kiddie, Bradley Thomas. Layout-Based Fault Injection for Combinational Logic in Nanometer Technologies.

Degree: MS, Electrical Engineering, 2012, Vanderbilt University

URL: http://hdl.handle.net/1803/11408

► As feature sizes and operating voltages decrease, single-event transients from particle strikes in logic circuits become more probable. Much literature is available on the effects… (more)

Subjects/Keywords: reliability; radiation-induced faults; single-event transient; multiple transient faults; soft errors; combinational logic; layout

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Kiddie, B. T. (2012). Layout-Based Fault Injection for Combinational Logic in Nanometer Technologies. (Thesis). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/11408

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Kiddie, Bradley Thomas. “Layout-Based Fault Injection for Combinational Logic in Nanometer Technologies.” 2012. Thesis, Vanderbilt University. Accessed March 01, 2021. http://hdl.handle.net/1803/11408.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Kiddie, Bradley Thomas. “Layout-Based Fault Injection for Combinational Logic in Nanometer Technologies.” 2012. Web. 01 Mar 2021.

Vancouver:

Kiddie BT. Layout-Based Fault Injection for Combinational Logic in Nanometer Technologies. [Internet] [Thesis]. Vanderbilt University; 2012. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1803/11408.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kiddie BT. Layout-Based Fault Injection for Combinational Logic in Nanometer Technologies. [Thesis]. Vanderbilt University; 2012. Available from: http://hdl.handle.net/1803/11408

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Vanderbilt University

8. Chetia, Jugantor. An efficient AVF estimation technique using circuit partitioning.

Degree: MS, Electrical Engineering, 2012, Vanderbilt University

URL: http://hdl.handle.net/1803/10484

► Soft errors induced by radiation particles are increasingly becoming a source of concern for reliable design of VLSI systems. An important parameter to quantify the… (more)

Subjects/Keywords: AVF; statistical fault injection; circuit partitioning

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Chetia, J. (2012). An efficient AVF estimation technique using circuit partitioning. (Thesis). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/10484

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Chetia, Jugantor. “An efficient AVF estimation technique using circuit partitioning.” 2012. Thesis, Vanderbilt University. Accessed March 01, 2021. http://hdl.handle.net/1803/10484.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Chetia, Jugantor. “An efficient AVF estimation technique using circuit partitioning.” 2012. Web. 01 Mar 2021.

Vancouver:

Chetia J. An efficient AVF estimation technique using circuit partitioning. [Internet] [Thesis]. Vanderbilt University; 2012. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1803/10484.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chetia J. An efficient AVF estimation technique using circuit partitioning. [Thesis]. Vanderbilt University; 2012. Available from: http://hdl.handle.net/1803/10484

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Vanderbilt University

9. Kay, William Hunter. Single-Event Upset Characterization of Flip-Flops Across Temperature and Supply Voltage for a 20-nm Bulk, Planar, CMOS Technology.

Degree: MS, Electrical Engineering, 2015, Vanderbilt University

URL: http://hdl.handle.net/1803/11784

► The scaling of CMOS technology has brought about the increased susceptibility of circuits to single-event (SE) effects. Electronic systems operating in space often face extreme… (more)

Subjects/Keywords: flip flop; 20 nm; single event; SET; SEE; SEU

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Kay, W. H. (2015). Single-Event Upset Characterization of Flip-Flops Across Temperature and Supply Voltage for a 20-nm Bulk, Planar, CMOS Technology. (Thesis). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/11784

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Kay, William Hunter. “Single-Event Upset Characterization of Flip-Flops Across Temperature and Supply Voltage for a 20-nm Bulk, Planar, CMOS Technology.” 2015. Thesis, Vanderbilt University. Accessed March 01, 2021. http://hdl.handle.net/1803/11784.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Kay, William Hunter. “Single-Event Upset Characterization of Flip-Flops Across Temperature and Supply Voltage for a 20-nm Bulk, Planar, CMOS Technology.” 2015. Web. 01 Mar 2021.

Vancouver:

Kay WH. Single-Event Upset Characterization of Flip-Flops Across Temperature and Supply Voltage for a 20-nm Bulk, Planar, CMOS Technology. [Internet] [Thesis]. Vanderbilt University; 2015. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1803/11784.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kay WH. Single-Event Upset Characterization of Flip-Flops Across Temperature and Supply Voltage for a 20-nm Bulk, Planar, CMOS Technology. [Thesis]. Vanderbilt University; 2015. Available from: http://hdl.handle.net/1803/11784

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Vanderbilt University

10. Wei, Xing. Porous silicon waveguide biosensors with a grating coupler.

Degree: PhD, Electrical Engineering, 2012, Vanderbilt University

URL: http://hdl.handle.net/1803/11427

► Sensitive label-free optical biosensors based on grating-coupled porous silicon (PSi) waveguides are demonstrated for biosensing applications. This is the first time that the benefits of… (more)

Subjects/Keywords: gratings; optical biosensor; Porous silicon; waveguide

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Wei, X. (2012). Porous silicon waveguide biosensors with a grating coupler. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/11427

Chicago Manual of Style (16^th Edition):

Wei, Xing. “Porous silicon waveguide biosensors with a grating coupler.” 2012. Doctoral Dissertation, Vanderbilt University. Accessed March 01, 2021. http://hdl.handle.net/1803/11427.

MLA Handbook (7^th Edition):

Wei, Xing. “Porous silicon waveguide biosensors with a grating coupler.” 2012. Web. 01 Mar 2021.

Vancouver:

Wei X. Porous silicon waveguide biosensors with a grating coupler. [Internet] [Doctoral dissertation]. Vanderbilt University; 2012. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1803/11427.

Council of Science Editors:

Wei X. Porous silicon waveguide biosensors with a grating coupler. [Doctoral Dissertation]. Vanderbilt University; 2012. Available from: http://hdl.handle.net/1803/11427

Vanderbilt University

11. Jiang, Hui. Design of soft-error-aware sequential circuits with power and speed optimization.

Degree: PhD, Electrical Engineering, 2018, Vanderbilt University

URL: http://hdl.handle.net/1803/10911

► A single-event effect (SEE) of circuits is strongly dependent on the supply voltage and the physical capacitance. Reduction in supply voltage as well as technology… (more)

▼ A single-event effect (SEE) of circuits is strongly dependent on the supply voltage and the physical capacitance. Reduction in supply voltage as well as technology scaling trends (smaller nodal capacitances) may result in dramatically increased sensitivity of the circuits to radiation. For this reason, SEE are especially considered challenges for low-power and high performance circuits. Hence, it is imperative to consider the SEE induced errors of the low power and high performance design when designing circuits for applications requiring high reliability. In this proposed research, a methodology to bridge the gap between experimental results and predictive models for SEE performance of sequential logic circuits have been developed. A study of the relationship between circuit SEE tolerance and power consumption is performed using this methodology. The purpose is to build a framework of designing soft-error-aware sequential circuits with power and speed optimization. A figure-of-merit (FOM) is provided for designers to make informed decisions on meeting power, speed, and SE specifications after the proposed framework. To comprehensively comment on the design parameters of different sequential logic circuits, a FOM is defined as the inverse of the product of power and SE cross-section (PCSP-1). Since minimization of power and SE cross-section is desirable, a lower PCSP value and thus a higher FOM value can be considered to be an indicator of an optimized design. This work focuses on the study of both power consumption and SEE tolerance at device and circuit-level. Sequential circuits are used as circuit examples in this proposed research. The ultimate goal of the work is to provide designers with capabilities and FOM to choose the suitable low power and SEE tolerance design for different targeted design specifications and operating environment. Advisors/Committee Members: Robinson H. William (committee member), Aniruddha Gokhale (committee member), Ronald D. Schrimpf (committee member), Lloyd Massengill (committee member), Bharat L. Bhuva (Committee Chair).

Subjects/Keywords: power optimization; sequential circuit; soft error rate; Single event effects; empirical model

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Jiang, H. (2018). Design of soft-error-aware sequential circuits with power and speed optimization. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/10911

Chicago Manual of Style (16^th Edition):

Jiang, Hui. “Design of soft-error-aware sequential circuits with power and speed optimization.” 2018. Doctoral Dissertation, Vanderbilt University. Accessed March 01, 2021. http://hdl.handle.net/1803/10911.

MLA Handbook (7^th Edition):

Jiang, Hui. “Design of soft-error-aware sequential circuits with power and speed optimization.” 2018. Web. 01 Mar 2021.

Vancouver:

Jiang H. Design of soft-error-aware sequential circuits with power and speed optimization. [Internet] [Doctoral dissertation]. Vanderbilt University; 2018. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1803/10911.

Council of Science Editors:

Jiang H. Design of soft-error-aware sequential circuits with power and speed optimization. [Doctoral Dissertation]. Vanderbilt University; 2018. Available from: http://hdl.handle.net/1803/10911

Vanderbilt University

12. Chatterjee, Indranil. Geometric Dependence of the Total Ionizing Dose Response of FinFETs.

Degree: PhD, Electrical Engineering, 2014, Vanderbilt University

URL: http://hdl.handle.net/1803/13758

► The total ionizing dose induced degradation in advanced deep-submicron CMOS technologies has been significantly reduced by scaling. Damage to isolating field oxides remains a significant… (more)

Subjects/Keywords: Total dose effects; Isolation oxides; Bulk FinFET; SOI FinFET; Parasitic transistor; Oxide traps; Charge trapping

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Chatterjee, I. (2014). Geometric Dependence of the Total Ionizing Dose Response of FinFETs. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/13758

Chicago Manual of Style (16^th Edition):

Chatterjee, Indranil. “Geometric Dependence of the Total Ionizing Dose Response of FinFETs.” 2014. Doctoral Dissertation, Vanderbilt University. Accessed March 01, 2021. http://hdl.handle.net/1803/13758.

MLA Handbook (7^th Edition):

Chatterjee, Indranil. “Geometric Dependence of the Total Ionizing Dose Response of FinFETs.” 2014. Web. 01 Mar 2021.

Vancouver:

Chatterjee I. Geometric Dependence of the Total Ionizing Dose Response of FinFETs. [Internet] [Doctoral dissertation]. Vanderbilt University; 2014. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1803/13758.

Council of Science Editors:

Chatterjee I. Geometric Dependence of the Total Ionizing Dose Response of FinFETs. [Doctoral Dissertation]. Vanderbilt University; 2014. Available from: http://hdl.handle.net/1803/13758

Vanderbilt University

13. Jagannathan, Srikanth. TID characterization of high frequency RF circuits in NANO-CMOS technologies.

Degree: PhD, Electrical Engineering, 2013, Vanderbilt University

URL: http://hdl.handle.net/1803/14535

► Rapid downscaling of CMOS technology has resulted in significant improvement in the RF performance of Silicon MOSFETs. As a result, standard CMOS technology has become… (more)

▼ Rapid downscaling of CMOS technology has resulted in significant improvement in the RF performance of Silicon MOSFETs. As a result, standard CMOS technology has become a popular choice for implementing RF applications. Nano-scale CMOS device characteristics can be highly sensitive to variations in process (P), supply voltage (V) and operating temperature (T). This makes the design of RF circuits using nano-scale CMOS devices increasingly challenging to satisfy the performance specifications across all PVT corners. Another parameter that needs to be considered in the design space for RF circuits used in aerospace and military applications is total ionizing dose (TID) irradiation. Even a relatively small amount of TID-induced degradation that may not be significant for typical digital CMOS applications can be quite important for analog RF applications, especially when compounded by PVT variations. Radiation experiments show degradation in the performance of a 20.4 GHz voltage controlled oscillator (VCO) designed and fabricated in the IBM 32 nm CMOS SOI technology. At elevated temperature, the TID-induced degradation in the VCO performance is further enhanced causing failure to meet required design specifications. Measured TID-induced DC and RF parametric degradation of NMOS and PMOS transistors in the IBM 45 nm CMOS SOI technology were used to develop compact models. These models were used in example K-band RF circuits, such as the VCO and a low noise amplifier (LNA), to predict TID-induced degradation in the circuit performance. The circuit simulations show consistent results, predicting specification failures in these RF circuits due to the combined effects of PVT corners and TID. The failure to meet design specifications of a circuit can in turn cause the failure of the entire RF system. The TID-aware compact models are further used to suggest radiation hardened by design (RHBD) alternatives along with tradeoff study of RF circuit performance and its radiation response. This study provides valuable design and reliability insights for RFIC designers targeting military and aerospace applications. Advisors/Committee Members: Daniel T. Loveless (committee member), Ronald D. Schrimpf (committee member), William T. Holman (committee member), Bharat L. Bhuva (committee member), Mark N. Ellingham (committee member), Lloyd. W. Massengill (Committee Chair).

Subjects/Keywords: RF; TID

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Jagannathan, S. (2013). TID characterization of high frequency RF circuits in NANO-CMOS technologies. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/14535

Chicago Manual of Style (16^th Edition):

Jagannathan, Srikanth. “TID characterization of high frequency RF circuits in NANO-CMOS technologies.” 2013. Doctoral Dissertation, Vanderbilt University. Accessed March 01, 2021. http://hdl.handle.net/1803/14535.

MLA Handbook (7^th Edition):

Jagannathan, Srikanth. “TID characterization of high frequency RF circuits in NANO-CMOS technologies.” 2013. Web. 01 Mar 2021.

Vancouver:

Jagannathan S. TID characterization of high frequency RF circuits in NANO-CMOS technologies. [Internet] [Doctoral dissertation]. Vanderbilt University; 2013. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1803/14535.

Council of Science Editors:

Jagannathan S. TID characterization of high frequency RF circuits in NANO-CMOS technologies. [Doctoral Dissertation]. Vanderbilt University; 2013. Available from: http://hdl.handle.net/1803/14535

Vanderbilt University

14. Kauppila, Amy Vaughn. Analysis of parameter variation impact on the single event response in sub-100nm CMOS storage cells.

Degree: PhD, Electrical Engineering, 2012, Vanderbilt University

URL: http://hdl.handle.net/1803/12080

► Current deep sub-micron technologies are particularly susceptible to single events. The challenge derives from a conglomeration of effects that affect circuits’ radiation response. For instance,… (more)

▼ Current deep sub-micron technologies are particularly susceptible to single events. The challenge derives from a conglomeration of effects that affect circuits’ radiation response. For instance, decreasing device size has led to decreased storage charge and increased operating speeds. Decreased storage charge contributes to single event sensitivity since the charge deposited by the ionized particle is now more on par with the storage node charge. The increased operating speeds increase circuit sensitivity since they are now comparable to the speed of a single event transient. Single events are expected to dominate other reliability concerns in deep sub-micrometer devices due to decreased transistor currents and nodal capacitances. Thus, it is vital to understand and quantify the impact of contributing mechanisms. In addition to the challenges presented by radiation, transistor and chip design also faces a challenge from the variations that are inherent to the manufacturing process. During chip fabrication, extreme measures are taken to ensure precision. However, variations in lithography, random dopant fluctuations, gate depletion, surface state charge, and line-edge roughness cause changes in individual transistor behavior and therefore, changes in the behavior-describing transistor parameters. The non-standard behavior then affects circuit performance and therefore impacts single event response. It is anticipated that process variations will substantially increase with shrinking device sizes. Consequently, the potential impact of process variations on SE circuit response is significant. In order to accurately predict the single-event response of any circuit, it is necessary to identify and quantify the impact of the specific process variations. This work correlates the shifts in radiation response to specific device and process-parameter variations by quantifying the impact of process variability on the range of single-event upset (SEU) critical charge. Monte-Carlo simulations are leveraged to assess the impact of process variations on SEU response. This dissertation analyzes the impact of process variations on the single-event upset response of sub-100nm CMOS memory storage circuits. Advisors/Committee Members: Dr. Shi-Jie [email protected] (committee member), Dr. W. Timothy Holman (committee member), Dr. Lloyd W. Massengill (committee member), Dr. Ronald D. Schrimpf (committee member), Dr. Bharat L. Bhuva (Committee Chair).

Subjects/Keywords: single event upset; parameter variation

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Kauppila, A. V. (2012). Analysis of parameter variation impact on the single event response in sub-100nm CMOS storage cells. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/12080

Chicago Manual of Style (16^th Edition):

Kauppila, Amy Vaughn. “Analysis of parameter variation impact on the single event response in sub-100nm CMOS storage cells.” 2012. Doctoral Dissertation, Vanderbilt University. Accessed March 01, 2021. http://hdl.handle.net/1803/12080.

MLA Handbook (7^th Edition):

Kauppila, Amy Vaughn. “Analysis of parameter variation impact on the single event response in sub-100nm CMOS storage cells.” 2012. Web. 01 Mar 2021.

Vancouver:

Kauppila AV. Analysis of parameter variation impact on the single event response in sub-100nm CMOS storage cells. [Internet] [Doctoral dissertation]. Vanderbilt University; 2012. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1803/12080.

Council of Science Editors:

Kauppila AV. Analysis of parameter variation impact on the single event response in sub-100nm CMOS storage cells. [Doctoral Dissertation]. Vanderbilt University; 2012. Available from: http://hdl.handle.net/1803/12080

Vanderbilt University

15. Saxena, Tripti. A Generic Framework for Design Space Exploration.

Degree: PhD, Computer Science, 2012, Vanderbilt University

URL: http://hdl.handle.net/1803/13790

► As the complexity of software systems rises, designers are often faced with the challenge of identifying potential design solutions from a large space of possible… (more)

Subjects/Keywords: Design Space Exploration; Model-driven development; Constraint Programming

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Saxena, T. (2012). A Generic Framework for Design Space Exploration. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/13790

Chicago Manual of Style (16^th Edition):

Saxena, Tripti. “A Generic Framework for Design Space Exploration.” 2012. Doctoral Dissertation, Vanderbilt University. Accessed March 01, 2021. http://hdl.handle.net/1803/13790.

MLA Handbook (7^th Edition):

Saxena, Tripti. “A Generic Framework for Design Space Exploration.” 2012. Web. 01 Mar 2021.

Vancouver:

Saxena T. A Generic Framework for Design Space Exploration. [Internet] [Doctoral dissertation]. Vanderbilt University; 2012. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1803/13790.

Council of Science Editors:

Saxena T. A Generic Framework for Design Space Exploration. [Doctoral Dissertation]. Vanderbilt University; 2012. Available from: http://hdl.handle.net/1803/13790

Vanderbilt University

16. Hsu, Shao-Hua. Development of Vertical Nanodiamond Vacuum Field Emission Microelectronic Integrated Devices.

Degree: PhD, Electrical Engineering, 2014, Vanderbilt University

URL: http://hdl.handle.net/1803/10632

► Recent development of nanocrystalline diamonds has demonstrated the potential use of diamond material for vacuum microelectronics. Apart from the advantages of conventional microcrystalline diamond, nanodiamond… (more)

▼ Recent development of nanocrystalline diamonds has demonstrated the potential use of diamond material for vacuum microelectronics. Apart from the advantages of conventional microcrystalline diamond, nanodiamond with smaller grain size and smoother surface morphology possesses unique properties including the insertion of deliberate amounts of sp2-carbon into the sp3-diamond matrix and controlled electrical conductivity, expanding its utility for practical applications. This research is focused on the design, fabrication, and characterization of nitrogen-incorporated nanodiamond vacuum field emission (VFE) functional devices and integrated circuits, specifically on vertically configured VFE transistors, triodes, and differential amplifiers (diff-amps). A well-controlled and IC-compatible fabrication process has been developed to achieve three-terminal nanodiamond VFE integrated devices for vacuum micro/nanoelectronics. The nanodiamond pyramidal sharpened nanotips built with self-aligned silicon gate and anode electrodes were fabricated by employing a dual-mask microfabrication process which involved a silicon-on-insulator (SOI) mold transfer technique in collaboration with chemical vapor deposition (CVD) of nanodiamond and silicon gate partitioning. With proper design of the electrodes placement, the fabricated VFE functional devices have achieved transistor and triode characteristics, and they have been further implemented into vacuum integrated circuit building block – differential amplifiers. The nanodiamond VFE transistors and triodes demonstrate efficient gate-modulated electron field emission behavior with low operating voltages, high emission current, and negligible gate intercepted current. The dc characteristics of the transistor demonstrate distinct linear, saturation and cutoff regions with low turn-on gate voltage and high amplification factor. The triode demonstrates high emission current with efficient current modulation by low gate voltages. The ac signal amplification performance has been evaluated, indicating the applicability of nanodiamond VFE transistors and triodes as signal amplifiers and buffer amplifiers, respectively. An identical pair of nanodiamond VFE transistors with well-matched field emission characteristics was constructed and employed to accomplish a nanodiamond VFE diff-amp for the first time. A large common-mode-rejection ratio (~ 60 dB) was realized, demonstrating a viable approach to vacuum-based IC technology. These achievements signify the fundamental step for further development of vacuum integrated micro/nanoelectronics for practical applications, including high-speed, high-power and extreme-environment electronics. Advisors/Committee Members: Prof. Ralph W. Bruce (committee member), Prof. Bharat L. Bhuva (committee member), Prof. Yaqiong Xu (committee member), Prof. Deyu Li (committee member), Prof. Weng P. Kang (Committee Chair).

Subjects/Keywords: Microelectronic Devices; Nanodiamond; Vacuum Field Emission; Integrated Circuits; Signal Amplifiers

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Hsu, S. (2014). Development of Vertical Nanodiamond Vacuum Field Emission Microelectronic Integrated Devices. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/10632

Chicago Manual of Style (16^th Edition):

Hsu, Shao-Hua. “Development of Vertical Nanodiamond Vacuum Field Emission Microelectronic Integrated Devices.” 2014. Doctoral Dissertation, Vanderbilt University. Accessed March 01, 2021. http://hdl.handle.net/1803/10632.

MLA Handbook (7^th Edition):

Hsu, Shao-Hua. “Development of Vertical Nanodiamond Vacuum Field Emission Microelectronic Integrated Devices.” 2014. Web. 01 Mar 2021.

Vancouver:

Hsu S. Development of Vertical Nanodiamond Vacuum Field Emission Microelectronic Integrated Devices. [Internet] [Doctoral dissertation]. Vanderbilt University; 2014. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1803/10632.

Council of Science Editors:

Hsu S. Development of Vertical Nanodiamond Vacuum Field Emission Microelectronic Integrated Devices. [Doctoral Dissertation]. Vanderbilt University; 2014. Available from: http://hdl.handle.net/1803/10632

Vanderbilt University

17. Gaspard, Nelson Joseph III. Single-Event Upset Technology Scaling Trends of Unhardened and Hardened Flip-Flops in Bulk CMOS.

Degree: PhD, Electrical Engineering, 2017, Vanderbilt University

URL: http://hdl.handle.net/1803/10824

► Alpha, heavy-ion, neutron, and proton experimental results from 130-nm to 28-nm technology nodes are establish single-event upset cross section trends in soft and hardened flip-flop… (more)

Subjects/Keywords: single event upset; CMOS; flip-flop; soft error

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Gaspard, N. J. I. (2017). Single-Event Upset Technology Scaling Trends of Unhardened and Hardened Flip-Flops in Bulk CMOS. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/10824

Chicago Manual of Style (16^th Edition):

Gaspard, Nelson Joseph III. “Single-Event Upset Technology Scaling Trends of Unhardened and Hardened Flip-Flops in Bulk CMOS.” 2017. Doctoral Dissertation, Vanderbilt University. Accessed March 01, 2021. http://hdl.handle.net/1803/10824.

MLA Handbook (7^th Edition):

Gaspard, Nelson Joseph III. “Single-Event Upset Technology Scaling Trends of Unhardened and Hardened Flip-Flops in Bulk CMOS.” 2017. Web. 01 Mar 2021.

Vancouver:

Gaspard NJI. Single-Event Upset Technology Scaling Trends of Unhardened and Hardened Flip-Flops in Bulk CMOS. [Internet] [Doctoral dissertation]. Vanderbilt University; 2017. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1803/10824.

Council of Science Editors:

Gaspard NJI. Single-Event Upset Technology Scaling Trends of Unhardened and Hardened Flip-Flops in Bulk CMOS. [Doctoral Dissertation]. Vanderbilt University; 2017. Available from: http://hdl.handle.net/1803/10824

Vanderbilt University

18. Kiddie, Bradley Thomas. Single-Event Multiple-Transient Characterization and Mitigation via Standard Cell Placement Methods.

Degree: PhD, Electrical Engineering, 2016, Vanderbilt University

URL: http://hdl.handle.net/1803/14250

► The effects of radiation on the operation of integrated circuits (IC) continue to take a more important role as technology feature sizes scale down, critical… (more)

Subjects/Keywords: reliability; radiation; eda; single-event transient; single-event multiple-transient; placement; algorithm

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Kiddie, B. T. (2016). Single-Event Multiple-Transient Characterization and Mitigation via Standard Cell Placement Methods. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/14250

Chicago Manual of Style (16^th Edition):

Kiddie, Bradley Thomas. “Single-Event Multiple-Transient Characterization and Mitigation via Standard Cell Placement Methods.” 2016. Doctoral Dissertation, Vanderbilt University. Accessed March 01, 2021. http://hdl.handle.net/1803/14250.

MLA Handbook (7^th Edition):

Kiddie, Bradley Thomas. “Single-Event Multiple-Transient Characterization and Mitigation via Standard Cell Placement Methods.” 2016. Web. 01 Mar 2021.

Vancouver:

Kiddie BT. Single-Event Multiple-Transient Characterization and Mitigation via Standard Cell Placement Methods. [Internet] [Doctoral dissertation]. Vanderbilt University; 2016. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1803/14250.

Council of Science Editors:

Kiddie BT. Single-Event Multiple-Transient Characterization and Mitigation via Standard Cell Placement Methods. [Doctoral Dissertation]. Vanderbilt University; 2016. Available from: http://hdl.handle.net/1803/14250

Vanderbilt University

19. Reece, Trey. Assessing and Detecting Malicious Hardware in Integrated Circuits.

Degree: PhD, Electrical Engineering, 2014, Vanderbilt University

URL: http://hdl.handle.net/1803/15155

► System security often focuses on the software, causing hardware security to be overlooked. Such oversight allows for attacks that can completely undermine the use of… (more)

Subjects/Keywords: integrated circuit design; vlsi; hardware trojan; hardware security; verification

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Reece, T. (2014). Assessing and Detecting Malicious Hardware in Integrated Circuits. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/15155

Chicago Manual of Style (16^th Edition):

Reece, Trey. “Assessing and Detecting Malicious Hardware in Integrated Circuits.” 2014. Doctoral Dissertation, Vanderbilt University. Accessed March 01, 2021. http://hdl.handle.net/1803/15155.

MLA Handbook (7^th Edition):

Reece, Trey. “Assessing and Detecting Malicious Hardware in Integrated Circuits.” 2014. Web. 01 Mar 2021.

Vancouver:

Reece T. Assessing and Detecting Malicious Hardware in Integrated Circuits. [Internet] [Doctoral dissertation]. Vanderbilt University; 2014. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1803/15155.

Council of Science Editors:

Reece T. Assessing and Detecting Malicious Hardware in Integrated Circuits. [Doctoral Dissertation]. Vanderbilt University; 2014. Available from: http://hdl.handle.net/1803/15155

Vanderbilt University

20. Ghosh, Nikkon. Monolithic multifinger lateral nanodiamond electron emission devices.

Degree: PhD, Electrical Engineering, 2012, Vanderbilt University

URL: http://hdl.handle.net/1803/14363

► Chemical-vapor-deposited (CVD) diamond is an excellent electron emission material due to its low electron affinity, robust mechanical and chemical properties, high thermal conductivity, and ability… (more)

▼ Chemical-vapor-deposited (CVD) diamond is an excellent electron emission material due to its low electron affinity, robust mechanical and chemical properties, high thermal conductivity, and ability to withstand high temperature and radiation. Nanocrystalline diamond, also known as nanodiamond, is an emerging form of CVD diamond which vastly expanding its applicability in vacuum electronics. Apart from the assets of the conventional CVD diamond, it possesses certain distinct properties which include smaller grain-size, high volume density of grain-boundaries, smoother surface morphology, n-type dopant incorporation and increased sp2-carbon content. However, the utilization of nanodiamond in vacuum micro/nanoelectronics has been limited by the complexity associated with its process integration. The purpose of my research is to develop a reliable process technique to fabricate efficient nanodiamond lateral electron emission devices operable at low voltage with high emission current for applications in vacuum microelectronics and integrated-circuits. To achieve this goal, first, a well-controlled process to realize useful and potential nanodiamond electron emitter structures in array configurations using electron beam lithography (EBL) and plasma etching techniques has been developed. Detail study includes optimization of processing parameters for EBL, metal-mask deposition and nanodiamond dry etching. The main part of the research includes the application of these recently developed process techniques for the design, fabrication and characterization of micro/nanopatterned nanodiamond lateral field emission devices which include sub-micron gap two-terminal and multifinger three-terminal structures. 140-fingered nanodiamond lateral diode has been achieved for the first time with 300nm interelectrode distance. On the other hand, the three-terminal structure is composed of 140 finger-like emitters with integrated anode and gate, which also has never been reported before. The electrical characteristics of these fabricated nanodiamond vacuum lateral field emission devices demonstrated promising behavior with very low turn-on voltage with high and stable emission current. It has also been observed for the first time that three emission mechanisms dominated at different potential levels. The three-terminal structure showed anode current enhancement and suppression behavior by changing gate bias. These developments in the field of nanotechnology signify the integration of vacuum electronics with the well-established IC process techniques favorable for high-speed and high-power, IC-compatible, extreme-environment vacuum micro/nanoelectronics applications. Advisors/Committee Members: Professor Deyu Li (committee member), Professor Yaqiong Xu (committee member), Professor Bharat L. Bhuva (committee member), Professor Jim L. Davidson (committee member), Professor Weng P. Kang (Committee Chair).

Subjects/Keywords: ELECTRON-EMISSION; NANO-GAP; LATERAL; MONOLITHIC; NANODIAMOND

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Ghosh, N. (2012). Monolithic multifinger lateral nanodiamond electron emission devices. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/14363

Chicago Manual of Style (16^th Edition):

Ghosh, Nikkon. “Monolithic multifinger lateral nanodiamond electron emission devices.” 2012. Doctoral Dissertation, Vanderbilt University. Accessed March 01, 2021. http://hdl.handle.net/1803/14363.

MLA Handbook (7^th Edition):

Ghosh, Nikkon. “Monolithic multifinger lateral nanodiamond electron emission devices.” 2012. Web. 01 Mar 2021.

Vancouver:

Ghosh N. Monolithic multifinger lateral nanodiamond electron emission devices. [Internet] [Doctoral dissertation]. Vanderbilt University; 2012. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1803/14363.

Council of Science Editors:

Ghosh N. Monolithic multifinger lateral nanodiamond electron emission devices. [Doctoral Dissertation]. Vanderbilt University; 2012. Available from: http://hdl.handle.net/1803/14363

Vanderbilt University

21. Chen, Yanran. Analysis and hardening of all-digital phase-locked loops (ADPLLs) to single-event radiation effects.

Degree: PhD, Electrical Engineering, 2017, Vanderbilt University

URL: http://hdl.handle.net/1803/14206

► In deep sub-micron CMOS technologies, all-digital phase-locked loops (ADPLLs) are favored over conventional analog or mixed-signal phase-locked loops (A/MS) PLLs for providing the clock signals… (more)

▼ In deep sub-micron CMOS technologies, all-digital phase-locked loops (ADPLLs) are favored over conventional analog or mixed-signal phase-locked loops (A/MS) PLLs for providing the clock signals for modern integrated circuits (ICs). Since an accurate clock signal is an important guarantee of the correct functionality of a system on chip (SOC), single-event effects (SEEs), as a type of reliability issues, have been extensively studied in A/MS PLLs, which are mostly based on a charge-pump PLL (CPPLL) architecture. However, little is known about the single-event vulnerability and hardening of ADPLLs. In this dissertation, three major single-event error signatures were identified and perturbation time error metric was proposed to quantify the error signatures in ADPLLs. Circuit-level simulation and experimental testing were conducted to characterize the subcircuits of different types ADPLLs to distinguish and analyze their individual contribution to the overall ADPLL SE vulnerability. High-order pole registers in the DLF were identified to be the most sensitive module in ADPLLs. In addition, different ADPLLs with complex system architectures were also characterized and analyzed for SE vulnerability. Additionally, a novel time-domain model for SEU-induced errors in ADPLLs was proposed and verified with experimental results. The model successfully predicts the output time-domain response and perturbation time of the ADPLLs for any SEUs in any sub-circuits, which allows designers to distinguish the most SE sensitive modules in the ADPLL topology and apply selective hardening solutions before tapeout. RHBD hardening guidelines for different types of ADPLLs for different operating environment and targeted design specifications were proposed based on SE characterization and modeling of the ADPLL designs. Last but not least, the proposed model and hardening techniques are compared with existing work on A/MS PLLs to provide conventional PLL designers with insights on RHBD ADPLL designs. Advisors/Committee Members: Prof. Bharat L. Bhuva (committee member), Prof. W. Timothy Holman (committee member), Prof. Michael L. Alles (committee member), Prof. T. Daniel Loveless (committee member), Prof. Mark N. Ellingham (committee member), Prof. Lloyd W. Massengill (Committee Chair).

Subjects/Keywords: Single-Event Upsets (SEU); All-digital Phase-locked Loops (ADPLLs); Single-Event Effects (SEE)

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Chen, Y. (2017). Analysis and hardening of all-digital phase-locked loops (ADPLLs) to single-event radiation effects. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/14206

Chicago Manual of Style (16^th Edition):

Chen, Yanran. “Analysis and hardening of all-digital phase-locked loops (ADPLLs) to single-event radiation effects.” 2017. Doctoral Dissertation, Vanderbilt University. Accessed March 01, 2021. http://hdl.handle.net/1803/14206.

MLA Handbook (7^th Edition):

Chen, Yanran. “Analysis and hardening of all-digital phase-locked loops (ADPLLs) to single-event radiation effects.” 2017. Web. 01 Mar 2021.

Vancouver:

Chen Y. Analysis and hardening of all-digital phase-locked loops (ADPLLs) to single-event radiation effects. [Internet] [Doctoral dissertation]. Vanderbilt University; 2017. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1803/14206.

Council of Science Editors:

Chen Y. Analysis and hardening of all-digital phase-locked loops (ADPLLs) to single-event radiation effects. [Doctoral Dissertation]. Vanderbilt University; 2017. Available from: http://hdl.handle.net/1803/14206

Vanderbilt University

22. Zhang, Hangfang. Impact of Designer-Controlled Parameters on Single-Event Responses for Flip-Flop Designs in Advanced Technologies.

Degree: PhD, Electrical Engineering, 2018, Vanderbilt University

URL: http://hdl.handle.net/1803/12055

► Modern ICs need to be designed with proper designer-controllable factors to meet power, speed and single-event (SE) performance requirements in different applications. Commercial fabrication houses… (more)

Subjects/Keywords: Single Event; Threshold Voltage; FinFET; Design Parameter; Temperature; Angular Incidence; Flip-Flop; Well Structure

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Zhang, H. (2018). Impact of Designer-Controlled Parameters on Single-Event Responses for Flip-Flop Designs in Advanced Technologies. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/12055

Chicago Manual of Style (16^th Edition):

Zhang, Hangfang. “Impact of Designer-Controlled Parameters on Single-Event Responses for Flip-Flop Designs in Advanced Technologies.” 2018. Doctoral Dissertation, Vanderbilt University. Accessed March 01, 2021. http://hdl.handle.net/1803/12055.

MLA Handbook (7^th Edition):

Zhang, Hangfang. “Impact of Designer-Controlled Parameters on Single-Event Responses for Flip-Flop Designs in Advanced Technologies.” 2018. Web. 01 Mar 2021.

Vancouver:

Zhang H. Impact of Designer-Controlled Parameters on Single-Event Responses for Flip-Flop Designs in Advanced Technologies. [Internet] [Doctoral dissertation]. Vanderbilt University; 2018. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1803/12055.

Council of Science Editors:

Zhang H. Impact of Designer-Controlled Parameters on Single-Event Responses for Flip-Flop Designs in Advanced Technologies. [Doctoral Dissertation]. Vanderbilt University; 2018. Available from: http://hdl.handle.net/1803/12055

Vanderbilt University

23. Assis, Thiago Rocha de. Soft error aware physical synthesis.

Degree: PhD, Electrical Engineering, 2015, Vanderbilt University

URL: http://hdl.handle.net/1803/14789

► To allow accurate analysis of Soft Errors by Electronic Design Automation (EDA) tools, analytical models were developed to estimate electrical characteristics of the single event.… (more)

Subjects/Keywords: single event transient; set pulse width; collected charge; radiation effects; electronic design automation; physical synthesis; soft error; reliability

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Assis, T. R. d. (2015). Soft error aware physical synthesis. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/14789

Chicago Manual of Style (16^th Edition):

Assis, Thiago Rocha de. “Soft error aware physical synthesis.” 2015. Doctoral Dissertation, Vanderbilt University. Accessed March 01, 2021. http://hdl.handle.net/1803/14789.

MLA Handbook (7^th Edition):

Assis, Thiago Rocha de. “Soft error aware physical synthesis.” 2015. Web. 01 Mar 2021.

Vancouver:

Assis TRd. Soft error aware physical synthesis. [Internet] [Doctoral dissertation]. Vanderbilt University; 2015. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1803/14789.

Council of Science Editors:

Assis TRd. Soft error aware physical synthesis. [Doctoral Dissertation]. Vanderbilt University; 2015. Available from: http://hdl.handle.net/1803/14789

Vanderbilt University

24. Raina, Supil. Nanodiamond macroelectrodes and ultramicroelectrode arrays for bio-analyte detection.

Degree: PhD, Interdisciplinary Materials Science, 2011, Vanderbilt University

URL: http://hdl.handle.net/1803/14408

► Properties such as high electrical conductivity; chemical and electrochemical stability over a wide range of conditions; rapid electron transfer kinetics for different redox systems; and… (more)

▼ Properties such as high electrical conductivity; chemical and electrochemical stability over a wide range of conditions; rapid electron transfer kinetics for different redox systems; and reproducible electrical, microstructural and chemical properties are essential pre-requisites for electrochemical electrodes. Nanodiamond is one such electrode material which has been shown to be suitable for electroanalytical applications. In this dissertation, MPECVD (Microwave Plasma Enhanced Chemical Vapor Deposition) process and conventional silicon microfabrication technology has been used for synthesis and fabrication of nanodiamond thin-film macroelectrodes and ultramicroelectrode arrays (UMEAs) with different geometries- pyramidal, planar and columnar. This work combines the excellent material properties of nanodiamond with the benefits of using UMEAs- higher analyte flux density, reduced ohmic losses and higher temporal resolution. Scanning electron microscopy, X-ray photoelectron spectroscopy and Raman spectroscopy were used for material characterization. Electrochemical performance was analyzed using ferri/ferrocyanide redox couple and essential bio-analytes such as Dopamine, Ascorbic Acid (AA) and Uric Acid (UA) in phosphate buffered saline (PBS). To simulate true physiological conditions, detection and quantification of dopamine in presence of interferants such as AA and UA was also examined, in-vitro. In addition, effects of the input gas mixture, i.e., hydrogen, methane and nitrogen, on nanodiamond macroelectrode properties were evaluated and optimized. Increase in nitrogen gas flow produced distinct changes in the nanodiamond microstructure and electrochemical response. The fabrication processes and electroanalytical performance, under steady state conditions, of the UMEAs with different geometries were compared to identify their respective drawbacks and new fabrication processes were developed to overcome them in order to consistently produce more reliable bio-sensors. The sensitivity of the UMEAs varied inversely with their dimensions. Neurotransmitter concentrations vary at sub-second time-scale and can only be monitored and quantified by using an electrode with high temporal resolution and fast electron transfer kinetics. Hence, ‘background subtracted fast scan cyclic voltammetry’ for Dopamine detection using planar nanodiamond UMEA was implemented. All the results from electrochemical characterization were achieved without any surface functionalization and/or modification. Advisors/Committee Members: Jimmy L. Davidson (committee member), Sharon M. Weiss (committee member), Bharat L. Bhuva (committee member), Deyu Li (committee member), Weng P. Kang (Committee Chair).

Subjects/Keywords: fast scan cyclic voltammetry; diffusion; electrochemistry; dopamine; nanodiamond

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Raina, S. (2011). Nanodiamond macroelectrodes and ultramicroelectrode arrays for bio-analyte detection. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/14408

Chicago Manual of Style (16^th Edition):

Raina, Supil. “Nanodiamond macroelectrodes and ultramicroelectrode arrays for bio-analyte detection.” 2011. Doctoral Dissertation, Vanderbilt University. Accessed March 01, 2021. http://hdl.handle.net/1803/14408.

MLA Handbook (7^th Edition):

Raina, Supil. “Nanodiamond macroelectrodes and ultramicroelectrode arrays for bio-analyte detection.” 2011. Web. 01 Mar 2021.

Vancouver:

Raina S. Nanodiamond macroelectrodes and ultramicroelectrode arrays for bio-analyte detection. [Internet] [Doctoral dissertation]. Vanderbilt University; 2011. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1803/14408.

Council of Science Editors:

Raina S. Nanodiamond macroelectrodes and ultramicroelectrode arrays for bio-analyte detection. [Doctoral Dissertation]. Vanderbilt University; 2011. Available from: http://hdl.handle.net/1803/14408

Vanderbilt University

25. Kauppila, Jeffrey Scott. Layout-Aware Modeling and Analysis Methodologies for Transient Radiation Effects on Integrated Circuit Electronics.

Degree: PhD, Electrical Engineering, 2015, Vanderbilt University

URL: http://hdl.handle.net/1803/10793

► The development of integrated circuits intended for use in transient radiation environments must account for the impact of the environment on the operation of the… (more)

▼ The development of integrated circuits intended for use in transient radiation environments must account for the impact of the environment on the operation of the circuit. The design of integrated circuits is increasingly simulation driven, and increased costs to fabricate designs require engineers to consider radiation effects in the simulation and design phase to limit fabrication and test cycles required to produce a radiation hardened part. This work advances the historical modeling approaches with bias-dependent and layout-aware methods for modeling the dose-rate and single-event effects in advanced technologies. This research develops a bias-dependent modeling method that accounts for circuit induced shaping of the device-level transient current. Behavioral modeling languages are utilized to eliminate independent current sources and lumped SPICE element models. Dose rate models are developed for multiple dielectrically-isolated processes across technology types, accounting for real-time bias-dependence and layout geometries in modern integrated circuit processes. Single-event modeling methods are developed to capture the bias-dependent current response observed in recent TCAD simulations. Bulk CMOS and SiGe HBT technology model parameterization for multiple-device charge collection is demonstrated. A new geometry-aware single-event model for sub-50nm partially-depleted SOI CMOS with an integrated parasitic BJT parameterized by technology and design parameters is developed. Dose-rate and single-event model simulations compare well to TCAD and test data. A novel layout-aware analysis method is developed, utilizing a hybrid of compact models (for efficiency) and spatially-aware layout objects (for geometric charge collection accuracy), in an industry standard integrated circuit design tool flow. The layout-aware analysis provides designers with visual feedback about the sensitivity of a design directly referenced to the circuit layout. The methods developed in this research are being actively utilized in radiation-effects research at universities, aerospace and defense corporations, and commercial integrated circuit design and manufacturing facilities. Layout-aware radiation-enabled models using the methodologies developed in this work have been integrated with process design kits and deployed to the radiation-hardened-by-design community. This research develops capabilities that provide a path forward to model transient radiation effects in advanced integrated circuit technologies. Advisors/Committee Members: Ronald D. Schrimpf, Ph.D. (committee member), W. Timothy Holman, Ph.D. (committee member), Bharat L. Bhuva, Ph.D. (committee member), Mark N. Ellingham, Ph.D. (committee member), Lloyd W. Massengill, Ph.D. (Committee Chair).

Subjects/Keywords: CAD Tools; Semiconductor Device Modeling; Process Design Kit; Gummel Poon; BSIMSOI; MEXTRAM; Radiation Modeling; TCAD; BSIM4; Bias-Dependent Modeling; Dose Rate Effects; Compact Models; Single Event Effects; Compact Model; BJT; MOSFET; Layout-Aware Modeling; Layout-Aware Analysis; SPICE; Layout; Radiation Effects; Circuit Simulation; Radiation-Enabled Model; Single-Event Transient; Single-Event Upset; Charge Sharing; Computational Modeling

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Kauppila, J. S. (2015). Layout-Aware Modeling and Analysis Methodologies for Transient Radiation Effects on Integrated Circuit Electronics. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/10793

Chicago Manual of Style (16^th Edition):

Kauppila, Jeffrey Scott. “Layout-Aware Modeling and Analysis Methodologies for Transient Radiation Effects on Integrated Circuit Electronics.” 2015. Doctoral Dissertation, Vanderbilt University. Accessed March 01, 2021. http://hdl.handle.net/1803/10793.

MLA Handbook (7^th Edition):

Kauppila, Jeffrey Scott. “Layout-Aware Modeling and Analysis Methodologies for Transient Radiation Effects on Integrated Circuit Electronics.” 2015. Web. 01 Mar 2021.

Vancouver:

Kauppila JS. Layout-Aware Modeling and Analysis Methodologies for Transient Radiation Effects on Integrated Circuit Electronics. [Internet] [Doctoral dissertation]. Vanderbilt University; 2015. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1803/10793.

Council of Science Editors:

Kauppila JS. Layout-Aware Modeling and Analysis Methodologies for Transient Radiation Effects on Integrated Circuit Electronics. [Doctoral Dissertation]. Vanderbilt University; 2015. Available from: http://hdl.handle.net/1803/10793

Vanderbilt University

26. Narasimham, Balaji. On Chip Characterization of Single Event Transient Pulse Widths.

Degree: MS, Electrical Engineering, 2005, Vanderbilt University

URL: http://hdl.handle.net/1803/14887

► It is now well known to the radiation effects community that single event effects caused by energetic particles, particularly single event transients, will be among… (more)

Subjects/Keywords: transient pulse width; SET; SEU; single event; CMOS; RHBD; Radiation hardening; Integrated circuits – Effect of radiation on – Computer simulation

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Narasimham, B. (2005). On Chip Characterization of Single Event Transient Pulse Widths. (Thesis). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/14887

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Narasimham, Balaji. “On Chip Characterization of Single Event Transient Pulse Widths.” 2005. Thesis, Vanderbilt University. Accessed March 01, 2021. http://hdl.handle.net/1803/14887.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Narasimham, Balaji. “On Chip Characterization of Single Event Transient Pulse Widths.” 2005. Web. 01 Mar 2021.

Vancouver:

Narasimham B. On Chip Characterization of Single Event Transient Pulse Widths. [Internet] [Thesis]. Vanderbilt University; 2005. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1803/14887.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Narasimham B. On Chip Characterization of Single Event Transient Pulse Widths. [Thesis]. Vanderbilt University; 2005. Available from: http://hdl.handle.net/1803/14887

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Vanderbilt University

27. Reece, Trey. Detection of Malicious Hardware in ASICs and FPGAs.

Degree: MS, Electrical Engineering, 2009, Vanderbilt University

URL: http://hdl.handle.net/1803/15004

► Detecting malicious modifications to a circuit is a daunting task, regardless of the medium. In a fabricated circuit, most methods of detecting hardware Trojans rely… (more)

Subjects/Keywords: Malicious Hardware; Process variation; hardware trojan

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Reece, T. (2009). Detection of Malicious Hardware in ASICs and FPGAs. (Thesis). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/15004

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Reece, Trey. “Detection of Malicious Hardware in ASICs and FPGAs.” 2009. Thesis, Vanderbilt University. Accessed March 01, 2021. http://hdl.handle.net/1803/15004.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Reece, Trey. “Detection of Malicious Hardware in ASICs and FPGAs.” 2009. Web. 01 Mar 2021.

Vancouver:

Reece T. Detection of Malicious Hardware in ASICs and FPGAs. [Internet] [Thesis]. Vanderbilt University; 2009. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1803/15004.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Reece T. Detection of Malicious Hardware in ASICs and FPGAs. [Thesis]. Vanderbilt University; 2009. Available from: http://hdl.handle.net/1803/15004

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Vanderbilt University

28. Holt, Christopher. Analysis of single event transients in dynamic logic circuitry.

Degree: MS, Electrical Engineering, 2008, Vanderbilt University

URL: http://hdl.handle.net/1803/11928

► Dynamic logic circuitry is generally faster and smaller than equivalent static logic circuits. The use of these circuits in space is desirable, but not much… (more)

Subjects/Keywords: Logic circuits – Testing; SETs; Dynamic logic; single event transients; Integrated circuits – Effect of radiation on

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Holt, C. (2008). Analysis of single event transients in dynamic logic circuitry. (Thesis). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/11928

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Holt, Christopher. “Analysis of single event transients in dynamic logic circuitry.” 2008. Thesis, Vanderbilt University. Accessed March 01, 2021. http://hdl.handle.net/1803/11928.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Holt, Christopher. “Analysis of single event transients in dynamic logic circuitry.” 2008. Web. 01 Mar 2021.

Vancouver:

Holt C. Analysis of single event transients in dynamic logic circuitry. [Internet] [Thesis]. Vanderbilt University; 2008. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1803/11928.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Holt C. Analysis of single event transients in dynamic logic circuitry. [Thesis]. Vanderbilt University; 2008. Available from: http://hdl.handle.net/1803/11928

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Vanderbilt University

29. Limbrick, Daniel Brian. Mitigation of Radiation-induced Soft Errors Using Temporal Embedded Signature Monitoring.

Degree: MS, Electrical Engineering, 2009, Vanderbilt University

URL: http://hdl.handle.net/1803/15101

► Soft errors can alter the correct execution of code within a microprocessor, particularly if control logic is compromised. This thesis addresses the vulnerability of a… (more)

Subjects/Keywords: signature monitoring; control flow; architectural reliability; soft errors

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Limbrick, D. B. (2009). Mitigation of Radiation-induced Soft Errors Using Temporal Embedded Signature Monitoring. (Thesis). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/15101

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Limbrick, Daniel Brian. “Mitigation of Radiation-induced Soft Errors Using Temporal Embedded Signature Monitoring.” 2009. Thesis, Vanderbilt University. Accessed March 01, 2021. http://hdl.handle.net/1803/15101.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Limbrick, Daniel Brian. “Mitigation of Radiation-induced Soft Errors Using Temporal Embedded Signature Monitoring.” 2009. Web. 01 Mar 2021.

Vancouver:

Limbrick DB. Mitigation of Radiation-induced Soft Errors Using Temporal Embedded Signature Monitoring. [Internet] [Thesis]. Vanderbilt University; 2009. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1803/15101.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Limbrick DB. Mitigation of Radiation-induced Soft Errors Using Temporal Embedded Signature Monitoring. [Thesis]. Vanderbilt University; 2009. Available from: http://hdl.handle.net/1803/15101

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Vanderbilt University

30. Pagey, Manish Prabhakar. Characterization and modeling of hot-carrier degradation in sub-micron NMOSFETS.

Degree: MS, Electrical Engineering, 2003, Vanderbilt University

URL: http://hdl.handle.net/1803/12629

► The continuous demand for higher packing density and faster operating speeds in modern digital CMOS circuits has driven the scaling of the metal-oxide-silicon field effect… (more)

Subjects/Keywords: mosfet; oxide; degradation; reliability; hot-carrier

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Pagey, M. P. (2003). Characterization and modeling of hot-carrier degradation in sub-micron NMOSFETS. (Thesis). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/12629

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Pagey, Manish Prabhakar. “Characterization and modeling of hot-carrier degradation in sub-micron NMOSFETS.” 2003. Thesis, Vanderbilt University. Accessed March 01, 2021. http://hdl.handle.net/1803/12629.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Pagey, Manish Prabhakar. “Characterization and modeling of hot-carrier degradation in sub-micron NMOSFETS.” 2003. Web. 01 Mar 2021.

Vancouver:

Pagey MP. Characterization and modeling of hot-carrier degradation in sub-micron NMOSFETS. [Internet] [Thesis]. Vanderbilt University; 2003. [cited 2021 Mar 01]. Available from: http://hdl.handle.net/1803/12629.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Pagey MP. Characterization and modeling of hot-carrier degradation in sub-micron NMOSFETS. [Thesis]. Vanderbilt University; 2003. Available from: http://hdl.handle.net/1803/12629

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

		in
And / Or
		in
And / Or
		in
And / Or
		in

Open Access Theses and Dissertations