Advanced search options

Advanced Search Options 🞨

Browse by author name (“Author name starts with…”).

Find ETDs with:

in
/  
in
/  
in
/  
in

Written in Published in Earliest date Latest date

Sorted by

Results per page:

Sorted by: relevance · author · university · dateNew search

You searched for +publisher:"University of Washington" +contributor:("Rudell, Jacques C"). Showing records 1 – 7 of 7 total matches.

Search Limiters

Last 2 Years | English Only

No search limiters apply to these results.

▼ Search Limiters


University of Washington

1. Shin, Soonkyun. A Low-Power High-Speed High-Resolution Zero-Crossing Based Pipelined Analog to Digital Converter.

Degree: PhD, 2014, University of Washington

 In this dissertation, techniques with zero-crossing based circuits (ZCBC) to achieve high speed and high resolution in scaled technologies with very low intrinsic gain are… (more)

Subjects/Keywords: 55nm; ADC; CMOS; Pipelined; ZCBC; Electrical engineering; electrical engineering

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Shin, S. (2014). A Low-Power High-Speed High-Resolution Zero-Crossing Based Pipelined Analog to Digital Converter. (Doctoral Dissertation). University of Washington. Retrieved from http://hdl.handle.net/1773/27154

Chicago Manual of Style (16th Edition):

Shin, Soonkyun. “A Low-Power High-Speed High-Resolution Zero-Crossing Based Pipelined Analog to Digital Converter.” 2014. Doctoral Dissertation, University of Washington. Accessed November 14, 2019. http://hdl.handle.net/1773/27154.

MLA Handbook (7th Edition):

Shin, Soonkyun. “A Low-Power High-Speed High-Resolution Zero-Crossing Based Pipelined Analog to Digital Converter.” 2014. Web. 14 Nov 2019.

Vancouver:

Shin S. A Low-Power High-Speed High-Resolution Zero-Crossing Based Pipelined Analog to Digital Converter. [Internet] [Doctoral dissertation]. University of Washington; 2014. [cited 2019 Nov 14]. Available from: http://hdl.handle.net/1773/27154.

Council of Science Editors:

Shin S. A Low-Power High-Speed High-Resolution Zero-Crossing Based Pipelined Analog to Digital Converter. [Doctoral Dissertation]. University of Washington; 2014. Available from: http://hdl.handle.net/1773/27154


University of Washington

2. Bhagavatula, Venumadhav. Power and area optimization techniques for ultra-wideband millimeter-wave CMOS transceivers.

Degree: PhD, 2014, University of Washington

 Over the past decade, opportunities for utilizing the broadband spectrum available at millimeter-wave (mm-wave) frequencies has motivated research on both short and long-range, highly-integrated complementary… (more)

Subjects/Keywords: Electrical engineering; electrical engineering

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bhagavatula, V. (2014). Power and area optimization techniques for ultra-wideband millimeter-wave CMOS transceivers. (Doctoral Dissertation). University of Washington. Retrieved from http://hdl.handle.net/1773/25135

Chicago Manual of Style (16th Edition):

Bhagavatula, Venumadhav. “Power and area optimization techniques for ultra-wideband millimeter-wave CMOS transceivers.” 2014. Doctoral Dissertation, University of Washington. Accessed November 14, 2019. http://hdl.handle.net/1773/25135.

MLA Handbook (7th Edition):

Bhagavatula, Venumadhav. “Power and area optimization techniques for ultra-wideband millimeter-wave CMOS transceivers.” 2014. Web. 14 Nov 2019.

Vancouver:

Bhagavatula V. Power and area optimization techniques for ultra-wideband millimeter-wave CMOS transceivers. [Internet] [Doctoral dissertation]. University of Washington; 2014. [cited 2019 Nov 14]. Available from: http://hdl.handle.net/1773/25135.

Council of Science Editors:

Bhagavatula V. Power and area optimization techniques for ultra-wideband millimeter-wave CMOS transceivers. [Doctoral Dissertation]. University of Washington; 2014. Available from: http://hdl.handle.net/1773/25135


University of Washington

3. Zhang, Tong. Integrated Wideband Self-Interference Cancellation Techniques for FDD and Full-Duplex Wireless Communication.

Degree: PhD, 2017, University of Washington

 The continued demand for higher levels of wireless access and increased data rates for a variety of applications from mobile smart phones to back haul… (more)

Subjects/Keywords: CMOS; FDD; Full-Duplex; Integrated Circuits; RF; Self-Interference Cancellation; Electrical engineering; Electrical engineering

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zhang, T. (2017). Integrated Wideband Self-Interference Cancellation Techniques for FDD and Full-Duplex Wireless Communication. (Doctoral Dissertation). University of Washington. Retrieved from http://hdl.handle.net/1773/40047

Chicago Manual of Style (16th Edition):

Zhang, Tong. “Integrated Wideband Self-Interference Cancellation Techniques for FDD and Full-Duplex Wireless Communication.” 2017. Doctoral Dissertation, University of Washington. Accessed November 14, 2019. http://hdl.handle.net/1773/40047.

MLA Handbook (7th Edition):

Zhang, Tong. “Integrated Wideband Self-Interference Cancellation Techniques for FDD and Full-Duplex Wireless Communication.” 2017. Web. 14 Nov 2019.

Vancouver:

Zhang T. Integrated Wideband Self-Interference Cancellation Techniques for FDD and Full-Duplex Wireless Communication. [Internet] [Doctoral dissertation]. University of Washington; 2017. [cited 2019 Nov 14]. Available from: http://hdl.handle.net/1773/40047.

Council of Science Editors:

Zhang T. Integrated Wideband Self-Interference Cancellation Techniques for FDD and Full-Duplex Wireless Communication. [Doctoral Dissertation]. University of Washington; 2017. Available from: http://hdl.handle.net/1773/40047


University of Washington

4. Pepin, Eric Philip. High-Voltage Compliant, Electrode-Invariant Neural Stimulation Electronics Compatible with Low-Voltage, Bulk-CMOS Integration.

Degree: 2015, University of Washington

 This work explores the challenges of implementing practical, electrical neural stimulation interfaces using modern silicon CMOS technologies. To overcome said challenges, which stem from the… (more)

Subjects/Keywords: high-voltage; low-voltage CMOS; neural stimulation; Electrical engineering; electrical engineering

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Pepin, E. P. (2015). High-Voltage Compliant, Electrode-Invariant Neural Stimulation Electronics Compatible with Low-Voltage, Bulk-CMOS Integration. (Thesis). University of Washington. Retrieved from http://hdl.handle.net/1773/33811

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Pepin, Eric Philip. “High-Voltage Compliant, Electrode-Invariant Neural Stimulation Electronics Compatible with Low-Voltage, Bulk-CMOS Integration.” 2015. Thesis, University of Washington. Accessed November 14, 2019. http://hdl.handle.net/1773/33811.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Pepin, Eric Philip. “High-Voltage Compliant, Electrode-Invariant Neural Stimulation Electronics Compatible with Low-Voltage, Bulk-CMOS Integration.” 2015. Web. 14 Nov 2019.

Vancouver:

Pepin EP. High-Voltage Compliant, Electrode-Invariant Neural Stimulation Electronics Compatible with Low-Voltage, Bulk-CMOS Integration. [Internet] [Thesis]. University of Washington; 2015. [cited 2019 Nov 14]. Available from: http://hdl.handle.net/1773/33811.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Pepin EP. High-Voltage Compliant, Electrode-Invariant Neural Stimulation Electronics Compatible with Low-Voltage, Bulk-CMOS Integration. [Thesis]. University of Washington; 2015. Available from: http://hdl.handle.net/1773/33811

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Washington

5. Huang, Chenxi. A 40nm CMOS Single-Ended Switch-Capacitor Harmonic-Rejection Power Amplifier for ZigBee Application.

Degree: 2016, University of Washington

 This thesis describes a single-ended switch-capacitor harmonic-rejection power amplifier for the 915 MHz ISM band for ZigBee applications. A multipath feed-forward harmonic-rejection technique is employed… (more)

Subjects/Keywords: CMOS; Power amplifiers; Switched capacitor circuits; ZigBee; Electrical engineering; electrical engineering

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Huang, C. (2016). A 40nm CMOS Single-Ended Switch-Capacitor Harmonic-Rejection Power Amplifier for ZigBee Application. (Thesis). University of Washington. Retrieved from http://hdl.handle.net/1773/35570

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Huang, Chenxi. “A 40nm CMOS Single-Ended Switch-Capacitor Harmonic-Rejection Power Amplifier for ZigBee Application.” 2016. Thesis, University of Washington. Accessed November 14, 2019. http://hdl.handle.net/1773/35570.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Huang, Chenxi. “A 40nm CMOS Single-Ended Switch-Capacitor Harmonic-Rejection Power Amplifier for ZigBee Application.” 2016. Web. 14 Nov 2019.

Vancouver:

Huang C. A 40nm CMOS Single-Ended Switch-Capacitor Harmonic-Rejection Power Amplifier for ZigBee Application. [Internet] [Thesis]. University of Washington; 2016. [cited 2019 Nov 14]. Available from: http://hdl.handle.net/1773/35570.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Huang C. A 40nm CMOS Single-Ended Switch-Capacitor Harmonic-Rejection Power Amplifier for ZigBee Application. [Thesis]. University of Washington; 2016. Available from: http://hdl.handle.net/1773/35570

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

6. Micheletti, Daniel. A Prototype System and Circuits for the Development of an Implantable H-bridge Stimulator ASIC in a Bulk CMOS Process.

Degree: 2015, University of Washington

 The opportunity to introduce nanometer sized circuits and systems into the body to treat or cure mental disorders, physical injuries, and genetic disabilities has put… (more)

Subjects/Keywords: ASIC; H-bridge; Implantable; Microchip; Neural; Stimulator; Engineering; Biomedical engineering; electrical engineering

…learned so much during the course of my time at the University of Washington, whether it was in… …stimulation and recording system designed for primate testing at the Univ. of Washington; the system… …working at the University of Washington is the close proximity to the research scientists that… …for it to be used for medical research purposes by research scientists at the University of… …Washington and its collaborators; to further the field of electrical stimulation and recording and… 

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Micheletti, D. (2015). A Prototype System and Circuits for the Development of an Implantable H-bridge Stimulator ASIC in a Bulk CMOS Process. (Thesis). University of Washington. Retrieved from http://hdl.handle.net/1773/33809

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Micheletti, Daniel. “A Prototype System and Circuits for the Development of an Implantable H-bridge Stimulator ASIC in a Bulk CMOS Process.” 2015. Thesis, University of Washington. Accessed November 14, 2019. http://hdl.handle.net/1773/33809.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Micheletti, Daniel. “A Prototype System and Circuits for the Development of an Implantable H-bridge Stimulator ASIC in a Bulk CMOS Process.” 2015. Web. 14 Nov 2019.

Vancouver:

Micheletti D. A Prototype System and Circuits for the Development of an Implantable H-bridge Stimulator ASIC in a Bulk CMOS Process. [Internet] [Thesis]. University of Washington; 2015. [cited 2019 Nov 14]. Available from: http://hdl.handle.net/1773/33809.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Micheletti D. A Prototype System and Circuits for the Development of an Implantable H-bridge Stimulator ASIC in a Bulk CMOS Process. [Thesis]. University of Washington; 2015. Available from: http://hdl.handle.net/1773/33809

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

7. Ravish Suvarna, Apsara. Transformer-Based Tunable Matching Networks implemented in Silicon CMOS.

Degree: 2013, University of Washington

 The growing market for small form-factor, low power wireless communication devices has provided tremendous impetus towards research on multi-mode and multi-standard transceiver designs. A key… (more)

Subjects/Keywords: adaptive; L; Pi; matching networks; reconfigurable; Transformer; tunable; Electrical engineering; electrical engineering

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ravish Suvarna, A. (2013). Transformer-Based Tunable Matching Networks implemented in Silicon CMOS. (Thesis). University of Washington. Retrieved from http://hdl.handle.net/1773/24249

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ravish Suvarna, Apsara. “Transformer-Based Tunable Matching Networks implemented in Silicon CMOS.” 2013. Thesis, University of Washington. Accessed November 14, 2019. http://hdl.handle.net/1773/24249.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ravish Suvarna, Apsara. “Transformer-Based Tunable Matching Networks implemented in Silicon CMOS.” 2013. Web. 14 Nov 2019.

Vancouver:

Ravish Suvarna A. Transformer-Based Tunable Matching Networks implemented in Silicon CMOS. [Internet] [Thesis]. University of Washington; 2013. [cited 2019 Nov 14]. Available from: http://hdl.handle.net/1773/24249.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ravish Suvarna A. Transformer-Based Tunable Matching Networks implemented in Silicon CMOS. [Thesis]. University of Washington; 2013. Available from: http://hdl.handle.net/1773/24249

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

.