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You searched for +publisher:"University of Texas – Austin" +contributor:("Touba, Nur A."). Showing records 1 – 17 of 17 total matches.

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University of Texas – Austin

1. Lee, Kangjoo. Designing an efficient test pattern generator using input reduction with linear operations.

Degree: MSin Engineering, Electrical and Computer Engineering, 2018, University of Texas – Austin

 Advances in fabrication technology have resulted in more complicated systems, being used in ever increasing numbers of applications. The large increase in transistor counts versus… (more)

Subjects/Keywords: Test pattern generator; Pseudo-exhaustive testing; Compatibility matrix; Gauss-Jordan Elimination; Linear operations

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APA (6th Edition):

Lee, K. (2018). Designing an efficient test pattern generator using input reduction with linear operations. (Masters Thesis). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/68223

Chicago Manual of Style (16th Edition):

Lee, Kangjoo. “Designing an efficient test pattern generator using input reduction with linear operations.” 2018. Masters Thesis, University of Texas – Austin. Accessed September 19, 2019. http://hdl.handle.net/2152/68223.

MLA Handbook (7th Edition):

Lee, Kangjoo. “Designing an efficient test pattern generator using input reduction with linear operations.” 2018. Web. 19 Sep 2019.

Vancouver:

Lee K. Designing an efficient test pattern generator using input reduction with linear operations. [Internet] [Masters thesis]. University of Texas – Austin; 2018. [cited 2019 Sep 19]. Available from: http://hdl.handle.net/2152/68223.

Council of Science Editors:

Lee K. Designing an efficient test pattern generator using input reduction with linear operations. [Masters Thesis]. University of Texas – Austin; 2018. Available from: http://hdl.handle.net/2152/68223


University of Texas – Austin

2. Rab, Muhammad Tauseef. Techniques to minimize circuitry and improve efficiency for defect tolerance.

Degree: PhD, Electrical and Computer Engineering, 2013, University of Texas – Austin

 As technology continues to scale to smaller geometries and newer dimensions (3-D), with increasingly complex manufacturing processes, the ability to reliably manufacture 100% defect-free circuitry… (more)

Subjects/Keywords: Defect tolerance; 3-D ICs; Redundancy; Yield

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APA (6th Edition):

Rab, M. T. (2013). Techniques to minimize circuitry and improve efficiency for defect tolerance. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/21926

Chicago Manual of Style (16th Edition):

Rab, Muhammad Tauseef. “Techniques to minimize circuitry and improve efficiency for defect tolerance.” 2013. Doctoral Dissertation, University of Texas – Austin. Accessed September 19, 2019. http://hdl.handle.net/2152/21926.

MLA Handbook (7th Edition):

Rab, Muhammad Tauseef. “Techniques to minimize circuitry and improve efficiency for defect tolerance.” 2013. Web. 19 Sep 2019.

Vancouver:

Rab MT. Techniques to minimize circuitry and improve efficiency for defect tolerance. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2013. [cited 2019 Sep 19]. Available from: http://hdl.handle.net/2152/21926.

Council of Science Editors:

Rab MT. Techniques to minimize circuitry and improve efficiency for defect tolerance. [Doctoral Dissertation]. University of Texas – Austin; 2013. Available from: http://hdl.handle.net/2152/21926


University of Texas – Austin

3. Garcia, Juan Elias. Piezoelectric transducer built-in self-test for logging while drilling instrument sensor evaluation at rig site.

Degree: MSin Engineering, Electrical and Computer Engineering, 2014, University of Texas – Austin

 Logging While Drilling (LWD) instruments used in oil and gas exploration are subjected to extreme environmental conditions that make reliable operation a major challenge. The… (more)

Subjects/Keywords: Piezoelectric Sensor; BIST

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APA (6th Edition):

Garcia, J. E. (2014). Piezoelectric transducer built-in self-test for logging while drilling instrument sensor evaluation at rig site. (Masters Thesis). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/26344

Chicago Manual of Style (16th Edition):

Garcia, Juan Elias. “Piezoelectric transducer built-in self-test for logging while drilling instrument sensor evaluation at rig site.” 2014. Masters Thesis, University of Texas – Austin. Accessed September 19, 2019. http://hdl.handle.net/2152/26344.

MLA Handbook (7th Edition):

Garcia, Juan Elias. “Piezoelectric transducer built-in self-test for logging while drilling instrument sensor evaluation at rig site.” 2014. Web. 19 Sep 2019.

Vancouver:

Garcia JE. Piezoelectric transducer built-in self-test for logging while drilling instrument sensor evaluation at rig site. [Internet] [Masters thesis]. University of Texas – Austin; 2014. [cited 2019 Sep 19]. Available from: http://hdl.handle.net/2152/26344.

Council of Science Editors:

Garcia JE. Piezoelectric transducer built-in self-test for logging while drilling instrument sensor evaluation at rig site. [Masters Thesis]. University of Texas – Austin; 2014. Available from: http://hdl.handle.net/2152/26344


University of Texas – Austin

4. O'Donnell, William Hugh. A programmable MBIST with address and NPSF pattern generators.

Degree: MSin Engineering, Electrical and Computer Engineering, 2013, University of Texas – Austin

 The movement to smart mobile connected devices which consolidate functions of traditionally separate devices is driving innovation in System-on-chips (SoCs). One of the innovations helping… (more)

Subjects/Keywords: BIST; Memory BIST; March test; NPSF; Programmable; Background pattern generator

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APA (6th Edition):

O'Donnell, W. H. (2013). A programmable MBIST with address and NPSF pattern generators. (Masters Thesis). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/24050

Chicago Manual of Style (16th Edition):

O'Donnell, William Hugh. “A programmable MBIST with address and NPSF pattern generators.” 2013. Masters Thesis, University of Texas – Austin. Accessed September 19, 2019. http://hdl.handle.net/2152/24050.

MLA Handbook (7th Edition):

O'Donnell, William Hugh. “A programmable MBIST with address and NPSF pattern generators.” 2013. Web. 19 Sep 2019.

Vancouver:

O'Donnell WH. A programmable MBIST with address and NPSF pattern generators. [Internet] [Masters thesis]. University of Texas – Austin; 2013. [cited 2019 Sep 19]. Available from: http://hdl.handle.net/2152/24050.

Council of Science Editors:

O'Donnell WH. A programmable MBIST with address and NPSF pattern generators. [Masters Thesis]. University of Texas – Austin; 2013. Available from: http://hdl.handle.net/2152/24050

5. Mohanram, Kartik. Reliability and test of high-performance integrated circuits.

Degree: PhD, Electrical and Computer Engineering, 2003, University of Texas – Austin

 As high-density, low-cost, high-performance computing devices become more ubiquitous, there is an increased necessity to address the reliable operation of such systems. Both on-line test… (more)

Subjects/Keywords: Integrated circuits – Testing

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APA (6th Edition):

Mohanram, K. (2003). Reliability and test of high-performance integrated circuits. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/796

Chicago Manual of Style (16th Edition):

Mohanram, Kartik. “Reliability and test of high-performance integrated circuits.” 2003. Doctoral Dissertation, University of Texas – Austin. Accessed September 19, 2019. http://hdl.handle.net/2152/796.

MLA Handbook (7th Edition):

Mohanram, Kartik. “Reliability and test of high-performance integrated circuits.” 2003. Web. 19 Sep 2019.

Vancouver:

Mohanram K. Reliability and test of high-performance integrated circuits. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2003. [cited 2019 Sep 19]. Available from: http://hdl.handle.net/2152/796.

Council of Science Editors:

Mohanram K. Reliability and test of high-performance integrated circuits. [Doctoral Dissertation]. University of Texas – Austin; 2003. Available from: http://hdl.handle.net/2152/796

6. Muthyala Sudhakar, Sreenivaas. Improving encoding efficiency in test compression using sequential linear decompressors with retained free variables.

Degree: MSin Engineering, Electrical and Computer Engineering, 2013, University of Texas – Austin

 This thesis proposes an approach to improve test compression using sequential linear decompressors by using retained free variables. Sequential linear decompressors are inherently efficient and… (more)

Subjects/Keywords: Decompression; Free variables; Scan chain; Test compression; Encoding efficiency

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APA (6th Edition):

Muthyala Sudhakar, S. (2013). Improving encoding efficiency in test compression using sequential linear decompressors with retained free variables. (Masters Thesis). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/21678

Chicago Manual of Style (16th Edition):

Muthyala Sudhakar, Sreenivaas. “Improving encoding efficiency in test compression using sequential linear decompressors with retained free variables.” 2013. Masters Thesis, University of Texas – Austin. Accessed September 19, 2019. http://hdl.handle.net/2152/21678.

MLA Handbook (7th Edition):

Muthyala Sudhakar, Sreenivaas. “Improving encoding efficiency in test compression using sequential linear decompressors with retained free variables.” 2013. Web. 19 Sep 2019.

Vancouver:

Muthyala Sudhakar S. Improving encoding efficiency in test compression using sequential linear decompressors with retained free variables. [Internet] [Masters thesis]. University of Texas – Austin; 2013. [cited 2019 Sep 19]. Available from: http://hdl.handle.net/2152/21678.

Council of Science Editors:

Muthyala Sudhakar S. Improving encoding efficiency in test compression using sequential linear decompressors with retained free variables. [Masters Thesis]. University of Texas – Austin; 2013. Available from: http://hdl.handle.net/2152/21678

7. Muthyala Sudhakar, Sreenivaas. Improving encoding efficiency in test compression based on linear techniques.

Degree: PhD, Electrical and Computer Engineering, 2014, University of Texas – Austin

 Sequential linear decompressors are widely used to implement test compression. Bits stored on the tester (called free variables) are assigned values to encode the test… (more)

Subjects/Keywords: Test compression; Sequential linear decompressors; Encoding efficiency; Scan chains

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APA (6th Edition):

Muthyala Sudhakar, S. (2014). Improving encoding efficiency in test compression based on linear techniques. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/28388

Chicago Manual of Style (16th Edition):

Muthyala Sudhakar, Sreenivaas. “Improving encoding efficiency in test compression based on linear techniques.” 2014. Doctoral Dissertation, University of Texas – Austin. Accessed September 19, 2019. http://hdl.handle.net/2152/28388.

MLA Handbook (7th Edition):

Muthyala Sudhakar, Sreenivaas. “Improving encoding efficiency in test compression based on linear techniques.” 2014. Web. 19 Sep 2019.

Vancouver:

Muthyala Sudhakar S. Improving encoding efficiency in test compression based on linear techniques. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2014. [cited 2019 Sep 19]. Available from: http://hdl.handle.net/2152/28388.

Council of Science Editors:

Muthyala Sudhakar S. Improving encoding efficiency in test compression based on linear techniques. [Doctoral Dissertation]. University of Texas – Austin; 2014. Available from: http://hdl.handle.net/2152/28388


University of Texas – Austin

8. -5050-6507. Design of circuits for sub-threshold voltages : implementation of adders.

Degree: MSin Engineering, Electrical and Computer engineering, 2016, University of Texas – Austin

 The demand and the need for low-power circuits is an ever increasing trend particularly due to the added overhead of design of efficient cooling systems… (more)

Subjects/Keywords: Circuit design; Physical design

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APA (6th Edition):

-5050-6507. (2016). Design of circuits for sub-threshold voltages : implementation of adders. (Masters Thesis). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/43627

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Author name may be incomplete

Chicago Manual of Style (16th Edition):

-5050-6507. “Design of circuits for sub-threshold voltages : implementation of adders.” 2016. Masters Thesis, University of Texas – Austin. Accessed September 19, 2019. http://hdl.handle.net/2152/43627.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

MLA Handbook (7th Edition):

-5050-6507. “Design of circuits for sub-threshold voltages : implementation of adders.” 2016. Web. 19 Sep 2019.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Vancouver:

-5050-6507. Design of circuits for sub-threshold voltages : implementation of adders. [Internet] [Masters thesis]. University of Texas – Austin; 2016. [cited 2019 Sep 19]. Available from: http://hdl.handle.net/2152/43627.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Council of Science Editors:

-5050-6507. Design of circuits for sub-threshold voltages : implementation of adders. [Masters Thesis]. University of Texas – Austin; 2016. Available from: http://hdl.handle.net/2152/43627

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete


University of Texas – Austin

9. -1637-3867. Test and security in a System-on-Chip environment.

Degree: PhD, Electrical and Computer Engineering, 2019, University of Texas – Austin

 This dissertation outlines new approaches for test and security in a System-on-Chip (SoC) environment. A methodology is proposed for designing a single test access mechanism… (more)

Subjects/Keywords: DFT; Secure computing; Test compression; Data obfuscation; Logic obfuscation

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APA (6th Edition):

-1637-3867. (2019). Test and security in a System-on-Chip environment. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://dx.doi.org/10.26153/tsw/2452

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Chicago Manual of Style (16th Edition):

-1637-3867. “Test and security in a System-on-Chip environment.” 2019. Doctoral Dissertation, University of Texas – Austin. Accessed September 19, 2019. http://dx.doi.org/10.26153/tsw/2452.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

MLA Handbook (7th Edition):

-1637-3867. “Test and security in a System-on-Chip environment.” 2019. Web. 19 Sep 2019.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Vancouver:

-1637-3867. Test and security in a System-on-Chip environment. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2019. [cited 2019 Sep 19]. Available from: http://dx.doi.org/10.26153/tsw/2452.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Council of Science Editors:

-1637-3867. Test and security in a System-on-Chip environment. [Doctoral Dissertation]. University of Texas – Austin; 2019. Available from: http://dx.doi.org/10.26153/tsw/2452

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

10. -3217-4051. Fine-grained containment domains for throughput processors.

Degree: PhD, Electrical and Computer Engineering, 2015, University of Texas – Austin

 Continued scaling of semiconductor technology has made modern processors rely on large design margins to guarantee correct operation under worst case conditions. Design margins appear… (more)

Subjects/Keywords: Resilience; Containment domains; Computer architecture; Timing speculation; GPU; Design margin; Voltage droop; Checkpoint-recovery

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APA (6th Edition):

-3217-4051. (2015). Fine-grained containment domains for throughput processors. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/46990

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Chicago Manual of Style (16th Edition):

-3217-4051. “Fine-grained containment domains for throughput processors.” 2015. Doctoral Dissertation, University of Texas – Austin. Accessed September 19, 2019. http://hdl.handle.net/2152/46990.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

MLA Handbook (7th Edition):

-3217-4051. “Fine-grained containment domains for throughput processors.” 2015. Web. 19 Sep 2019.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Vancouver:

-3217-4051. Fine-grained containment domains for throughput processors. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2015. [cited 2019 Sep 19]. Available from: http://hdl.handle.net/2152/46990.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Council of Science Editors:

-3217-4051. Fine-grained containment domains for throughput processors. [Doctoral Dissertation]. University of Texas – Austin; 2015. Available from: http://hdl.handle.net/2152/46990

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete


University of Texas – Austin

11. -9100-6322. Techniques to increase compaction of output responses with unknown (X) values.

Degree: PhD, Electrical and Computer Engineering, 2018, University of Texas – Austin

 Testing requires checking whether the output response of a circuit or system is correct or has an error. Increasingly complex system-on-chip and 3-D integrated circuits… (more)

Subjects/Keywords: Compaction; Output; Unknown; Compression; DFT

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APA (6th Edition):

-9100-6322. (2018). Techniques to increase compaction of output responses with unknown (X) values. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/63368

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Chicago Manual of Style (16th Edition):

-9100-6322. “Techniques to increase compaction of output responses with unknown (X) values.” 2018. Doctoral Dissertation, University of Texas – Austin. Accessed September 19, 2019. http://hdl.handle.net/2152/63368.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

MLA Handbook (7th Edition):

-9100-6322. “Techniques to increase compaction of output responses with unknown (X) values.” 2018. Web. 19 Sep 2019.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Vancouver:

-9100-6322. Techniques to increase compaction of output responses with unknown (X) values. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2018. [cited 2019 Sep 19]. Available from: http://hdl.handle.net/2152/63368.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Council of Science Editors:

-9100-6322. Techniques to increase compaction of output responses with unknown (X) values. [Doctoral Dissertation]. University of Texas – Austin; 2018. Available from: http://hdl.handle.net/2152/63368

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete


University of Texas – Austin

12. -0784-923X. Nearly free resilient memory architectures that balance resilience, performance, and cost.

Degree: PhD, Electrical and Computer Engineering, 2017, University of Texas – Austin

 Memory reliability has been a major design constraint for mission-critical and large-scale systems for many years. Continued innovation is still necessary because the rate of… (more)

Subjects/Keywords: Memory; Resilience; Fault tolerance; DRAM; GPU; CPU; Cache; Repair; Retirement; Microarchitecture

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APA (6th Edition):

-0784-923X. (2017). Nearly free resilient memory architectures that balance resilience, performance, and cost. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/63490

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Chicago Manual of Style (16th Edition):

-0784-923X. “Nearly free resilient memory architectures that balance resilience, performance, and cost.” 2017. Doctoral Dissertation, University of Texas – Austin. Accessed September 19, 2019. http://hdl.handle.net/2152/63490.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

MLA Handbook (7th Edition):

-0784-923X. “Nearly free resilient memory architectures that balance resilience, performance, and cost.” 2017. Web. 19 Sep 2019.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Vancouver:

-0784-923X. Nearly free resilient memory architectures that balance resilience, performance, and cost. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2017. [cited 2019 Sep 19]. Available from: http://hdl.handle.net/2152/63490.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Council of Science Editors:

-0784-923X. Nearly free resilient memory architectures that balance resilience, performance, and cost. [Doctoral Dissertation]. University of Texas – Austin; 2017. Available from: http://hdl.handle.net/2152/63490

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete


University of Texas – Austin

13. -0977-2774. Bridging design and manufacturing gap through machine learning and machine-generated layout.

Degree: PhD, Electrical and Computer Engineering, 2018, University of Texas – Austin

 Very-large-scale integrated (VLSI) circuits have entered the era of 1x nm technology node and beyond. Emerging manufacturing processes such as multiple patterning lithography, E-beam lithography… (more)

Subjects/Keywords: VLSI design automation; Design for manufacturability; Machine learning; Physical design; Post-layout optimization; Mask synthesis

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APA (6th Edition):

-0977-2774. (2018). Bridging design and manufacturing gap through machine learning and machine-generated layout. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/65900

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Chicago Manual of Style (16th Edition):

-0977-2774. “Bridging design and manufacturing gap through machine learning and machine-generated layout.” 2018. Doctoral Dissertation, University of Texas – Austin. Accessed September 19, 2019. http://hdl.handle.net/2152/65900.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

MLA Handbook (7th Edition):

-0977-2774. “Bridging design and manufacturing gap through machine learning and machine-generated layout.” 2018. Web. 19 Sep 2019.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Vancouver:

-0977-2774. Bridging design and manufacturing gap through machine learning and machine-generated layout. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2018. [cited 2019 Sep 19]. Available from: http://hdl.handle.net/2152/65900.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Council of Science Editors:

-0977-2774. Bridging design and manufacturing gap through machine learning and machine-generated layout. [Doctoral Dissertation]. University of Texas – Austin; 2018. Available from: http://hdl.handle.net/2152/65900

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

14. -5314-7669. Standard cell optimization and physical design in advanced technology nodes.

Degree: PhD, Electrical and Computer Engineering, 2017, University of Texas – Austin

 Integrated circuits (ICs) are at the heart of modern electronics, which rely heavily on the state-of-the-art semiconductor manufacturing technology. The key to pushing forward semiconductor… (more)

Subjects/Keywords: Standard cell; Physical design; Cell optimization; Integrated circuits; Semiconductor technology; Miniaturization; Unidirectional layout design

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APA (6th Edition):

-5314-7669. (2017). Standard cell optimization and physical design in advanced technology nodes. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/47464

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Chicago Manual of Style (16th Edition):

-5314-7669. “Standard cell optimization and physical design in advanced technology nodes.” 2017. Doctoral Dissertation, University of Texas – Austin. Accessed September 19, 2019. http://hdl.handle.net/2152/47464.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

MLA Handbook (7th Edition):

-5314-7669. “Standard cell optimization and physical design in advanced technology nodes.” 2017. Web. 19 Sep 2019.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Vancouver:

-5314-7669. Standard cell optimization and physical design in advanced technology nodes. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2017. [cited 2019 Sep 19]. Available from: http://hdl.handle.net/2152/47464.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Council of Science Editors:

-5314-7669. Standard cell optimization and physical design in advanced technology nodes. [Doctoral Dissertation]. University of Texas – Austin; 2017. Available from: http://hdl.handle.net/2152/47464

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete


University of Texas – Austin

15. Pak, Jiwoo. Electromigration modeling and layout optimization for advanced VLSI.

Degree: PhD, Electrical and Computer Engineering, 2014, University of Texas – Austin

 Electromigration (EM) is a critical problem for interconnect reliability in advanced VLSI design. Because EM is a strong function of current density, a smaller cross-sectional… (more)

Subjects/Keywords: Electromigration; VLSI; Layout; Physical Design; EDA

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APA (6th Edition):

Pak, J. (2014). Electromigration modeling and layout optimization for advanced VLSI. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/30944

Chicago Manual of Style (16th Edition):

Pak, Jiwoo. “Electromigration modeling and layout optimization for advanced VLSI.” 2014. Doctoral Dissertation, University of Texas – Austin. Accessed September 19, 2019. http://hdl.handle.net/2152/30944.

MLA Handbook (7th Edition):

Pak, Jiwoo. “Electromigration modeling and layout optimization for advanced VLSI.” 2014. Web. 19 Sep 2019.

Vancouver:

Pak J. Electromigration modeling and layout optimization for advanced VLSI. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2014. [cited 2019 Sep 19]. Available from: http://hdl.handle.net/2152/30944.

Council of Science Editors:

Pak J. Electromigration modeling and layout optimization for advanced VLSI. [Doctoral Dissertation]. University of Texas – Austin; 2014. Available from: http://hdl.handle.net/2152/30944

16. Das, Abhishek. simCUDA: A C++ based CUDA simulation framework: simCUDA : a C plus plus based compute unified device architecture simulation framework.

Degree: MSin Engineering, Electrical and Computer engineering, 2016, University of Texas – Austin

 The primary objective of this thesis is to develop a CUDA simulation framework (simCUDA) that effectively maps the existing application written in CUDA to be… (more)

Subjects/Keywords: CUDA; C++; C++11 threads; PTX; Simulator; GPU

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Das, A. (2016). simCUDA: A C++ based CUDA simulation framework: simCUDA : a C plus plus based compute unified device architecture simulation framework. (Masters Thesis). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/41232

Chicago Manual of Style (16th Edition):

Das, Abhishek. “simCUDA: A C++ based CUDA simulation framework: simCUDA : a C plus plus based compute unified device architecture simulation framework.” 2016. Masters Thesis, University of Texas – Austin. Accessed September 19, 2019. http://hdl.handle.net/2152/41232.

MLA Handbook (7th Edition):

Das, Abhishek. “simCUDA: A C++ based CUDA simulation framework: simCUDA : a C plus plus based compute unified device architecture simulation framework.” 2016. Web. 19 Sep 2019.

Vancouver:

Das A. simCUDA: A C++ based CUDA simulation framework: simCUDA : a C plus plus based compute unified device architecture simulation framework. [Internet] [Masters thesis]. University of Texas – Austin; 2016. [cited 2019 Sep 19]. Available from: http://hdl.handle.net/2152/41232.

Council of Science Editors:

Das A. simCUDA: A C++ based CUDA simulation framework: simCUDA : a C plus plus based compute unified device architecture simulation framework. [Masters Thesis]. University of Texas – Austin; 2016. Available from: http://hdl.handle.net/2152/41232


University of Texas – Austin

17. Sangkaralingam, Ranganathan. Techniques for reducing power dissipation during scan testing.

Degree: PhD, Electrical and Computer Engineering, 2002, University of Texas – Austin

 This dissertation addresses the problem of excessive power dissipation during scan testing. High power dissipation problems can be classified into two types: high average power… (more)

Subjects/Keywords: Energy dissipation – Prevention; Electronic circuits – Testing

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Sangkaralingam, R. (2002). Techniques for reducing power dissipation during scan testing. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/899

Chicago Manual of Style (16th Edition):

Sangkaralingam, Ranganathan. “Techniques for reducing power dissipation during scan testing.” 2002. Doctoral Dissertation, University of Texas – Austin. Accessed September 19, 2019. http://hdl.handle.net/2152/899.

MLA Handbook (7th Edition):

Sangkaralingam, Ranganathan. “Techniques for reducing power dissipation during scan testing.” 2002. Web. 19 Sep 2019.

Vancouver:

Sangkaralingam R. Techniques for reducing power dissipation during scan testing. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2002. [cited 2019 Sep 19]. Available from: http://hdl.handle.net/2152/899.

Council of Science Editors:

Sangkaralingam R. Techniques for reducing power dissipation during scan testing. [Doctoral Dissertation]. University of Texas – Austin; 2002. Available from: http://hdl.handle.net/2152/899

.