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University of Texas – Austin
1.
-0199-5938.
QoS and efficiency for FaaS platforms.
Degree: MSin Engineering, Electrical and Computer Engineering, 2019, University of Texas – Austin
URL: http://dx.doi.org/10.26153/tsw/5642 
► Serverless computing or function-as-a-service (FaaS) provides a way to write applications composed of scalable and manageable independent tasks communicating seamlessly without developer involvement. Strict performance…
(more)
▼ Serverless computing or function-as-a-service (FaaS) provides a way to write applications composed of scalable and manageable independent tasks communicating seamlessly without developer involvement. Strict performance guarantees or service-level agreements (SLAs) provided by cloud vendors demand predictable performance of serverless applications. Performance predictability in a datacenter environment suffers due to contention for hardware resources. In this study, we evaluate the effects of contention on two FaaS platforms; AWS Lambda, an industry leader in serverless, and the open-source OpenFaaS serverless stack. We develop a complete set of microbenchmarks as well as end-to-end applications composed of multiple functions as a benchmark suite to facilitate our study.
We quantify baseline system costs of these applications across both stacks given traditional orchestration mechanisms in an isolated system. We also quantify the same with co-located workloads in datacenter-like setting with Kubernetes orchestration. We show, via experiments, that significant performance slack exists at low to moderate loads and we can intelligently colocate workloads to maximize hardware utilization while still meeting QoS target latencies. Finally, we present a contention-aware static scheduling solution for FaaS platforms with predictable performance and compare it to static versions of baseline related works. We find that an intelligent FaaS orchestrator can be based along similar lines (similar hardware-level features) as a microservices one.
Advisors/Committee Members: Tiwari, Mohit (advisor).
Subjects/Keywords: FaaS; Microservices; QoS
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APA (6th Edition):
-0199-5938. (2019). QoS and efficiency for FaaS platforms. (Masters Thesis). University of Texas – Austin. Retrieved from http://dx.doi.org/10.26153/tsw/5642
Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Chicago Manual of Style (16th Edition):
-0199-5938. “QoS and efficiency for FaaS platforms.” 2019. Masters Thesis, University of Texas – Austin. Accessed February 28, 2021.
http://dx.doi.org/10.26153/tsw/5642.
Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
MLA Handbook (7th Edition):
-0199-5938. “QoS and efficiency for FaaS platforms.” 2019. Web. 28 Feb 2021.
Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Vancouver:
-0199-5938. QoS and efficiency for FaaS platforms. [Internet] [Masters thesis]. University of Texas – Austin; 2019. [cited 2021 Feb 28].
Available from: http://dx.doi.org/10.26153/tsw/5642.
Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Council of Science Editors:
-0199-5938. QoS and efficiency for FaaS platforms. [Masters Thesis]. University of Texas – Austin; 2019. Available from: http://dx.doi.org/10.26153/tsw/5642
Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
University of Texas – Austin
2.
Santa Maria, Daniel Ruiz.
Identifying post-silicon bugs and their root causes through a hardware introspection engine.
Degree: MSin Engineering, Electrical and Computer Engineering, 2017, University of Texas – Austin
URL: http://hdl.handle.net/2152/63952
► The goal of this project is to design, build, and evaluate new hardware mechanisms to debug post-silicon bugs in Systems-on-Chip (SoCs). Specifically, we aim to…
(more)
▼ The goal of this project is to design, build, and evaluate new hardware mechanisms to debug post-silicon bugs in Systems-on-Chip (SoCs). Specifically, we aim to accelerate the diagnosis of complex bugs such as deadlocks that are notoriously hard to identify using existing debugging mechanisms such as ARM CoreSight and hardware performance counters. We will design and evaluate programmable introspection mechanisms that will analyze streams of program and hardware-level trace data at test- and run-time, check correctness invariants, and generate event summaries that point to root causes of bugs. This thesis describes an on-chip hardware introspection engine (HIE) that detects anomalous transactions and alerts the user of potential bugs that could lead to deadlock. The HIE is a device that attaches to a bus and snoops on request and response transactions and collects response latency metadata for the transactions it receives. From this metadata, HIE is able to evaluate the normal behavior of transactions and alert engineers when anomalous behavior is detected at run-time. The HIE also separates the metadata it collects for different address ranges, creating a local version of the memory map that allows easy integration into existing systems. Synthesis on a FPGA and simulation of the HIE show that minimal area overhead is required for implementation and 100% detection accuracy is achievable for deadlock scenarios. The concept of learning address ranges and collecting and analyzing metadata for these ranges can have many applications in different fields that leverage anomaly detection, i.e. security, debug, etc.
Advisors/Committee Members: Tiwari, Mohit (advisor).
Subjects/Keywords: Design-for-debug; Anomaly detection; System deadlock; Post-silicon bugs; Hardware introspection engine
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APA (6th Edition):
Santa Maria, D. R. (2017). Identifying post-silicon bugs and their root causes through a hardware introspection engine. (Masters Thesis). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/63952
Chicago Manual of Style (16th Edition):
Santa Maria, Daniel Ruiz. “Identifying post-silicon bugs and their root causes through a hardware introspection engine.” 2017. Masters Thesis, University of Texas – Austin. Accessed February 28, 2021.
http://hdl.handle.net/2152/63952.
MLA Handbook (7th Edition):
Santa Maria, Daniel Ruiz. “Identifying post-silicon bugs and their root causes through a hardware introspection engine.” 2017. Web. 28 Feb 2021.
Vancouver:
Santa Maria DR. Identifying post-silicon bugs and their root causes through a hardware introspection engine. [Internet] [Masters thesis]. University of Texas – Austin; 2017. [cited 2021 Feb 28].
Available from: http://hdl.handle.net/2152/63952.
Council of Science Editors:
Santa Maria DR. Identifying post-silicon bugs and their root causes through a hardware introspection engine. [Masters Thesis]. University of Texas – Austin; 2017. Available from: http://hdl.handle.net/2152/63952
3.
-2178-1988.
Program analysis techniques for algorithmic complexity and relational properties.
Degree: PhD, Computer Science, 2019, University of Texas – Austin
URL: http://dx.doi.org/10.26153/tsw/2181
► Analyzing standard safety properties of a given program has traditionally been the primary focus of the program analysis community. Unfortunately, there are still many interesting…
(more)
▼ Analyzing standard safety properties of a given program has traditionally been
the primary focus of the program analysis community. Unfortunately, there are
still many interesting analysis tasks that cannot be effectively expressed with
standard safety properties. One such example is to derive the asymptotic
complexity of a given program. Another example is to verify relational
properties, i.e. properties that must be satisfied jointly by multiple programs
of multiple runs of one program. Existing program analysis techniques for
standard safety properties are usually not immediately applicable to asymptotic
complexity analysis problems and relational verification problems. New
approaches are therefore needed to solve these unconventional problems.
This thesis studies techniques for algorithmic complexity analysis as well as
relational verification. To that end, we present three case studies: (1) We
propose a new fuzzing technique for automatically finding inputs that trigger a
program's worst-case resource usage. (2) We show how to build a scalable,
end-to-end side channel detection tool by combining static taint analysis and a
program logic designed for verifying non-interference of a given program. (3) We
propose a general and effective relational verification algorithm that combines
reinforcement learning with backtracking search. A common theme
among all these solutions is to exploit problem-specific structures and adapt
existing techniques to exploit those structures accordingly.
Advisors/Committee Members: Dillig, Isil (advisor), Lin, Calvin (committee member), Chidambaram, Vijay (committee member), Tiwari, Mohit (committee member).
Subjects/Keywords: Complexity testing; Optimal program synthesis; Fuzzing; Genetic
programming; Performance bug; Vulnerability detection; Side channel; Static analysis; Relational verification; Reinforcement learning; Policy gradient
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APA (6th Edition):
-2178-1988. (2019). Program analysis techniques for algorithmic complexity and relational properties. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://dx.doi.org/10.26153/tsw/2181
Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Chicago Manual of Style (16th Edition):
-2178-1988. “Program analysis techniques for algorithmic complexity and relational properties.” 2019. Doctoral Dissertation, University of Texas – Austin. Accessed February 28, 2021.
http://dx.doi.org/10.26153/tsw/2181.
Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
MLA Handbook (7th Edition):
-2178-1988. “Program analysis techniques for algorithmic complexity and relational properties.” 2019. Web. 28 Feb 2021.
Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Vancouver:
-2178-1988. Program analysis techniques for algorithmic complexity and relational properties. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2019. [cited 2021 Feb 28].
Available from: http://dx.doi.org/10.26153/tsw/2181.
Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Council of Science Editors:
-2178-1988. Program analysis techniques for algorithmic complexity and relational properties. [Doctoral Dissertation]. University of Texas – Austin; 2019. Available from: http://dx.doi.org/10.26153/tsw/2181
Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
University of Texas – Austin
4.
Zheng, Tianhao, Ph. D.
Efficient fine-grained virtual memory.
Degree: PhD, Electrical and Computer Engineering, 2018, University of Texas – Austin
URL: http://hdl.handle.net/2152/68079
► Virtual memory in modern computer systems provides a single abstraction of the memory hierarchy. By hiding fragmentation and overlays of physical memory, virtual memory frees…
(more)
▼ Virtual memory in modern computer systems provides a single abstraction of the memory hierarchy.
By hiding fragmentation and overlays of physical memory, virtual memory frees applications from managing physical memory and improves programmability.
However, virtual memory often introduces noticeable overhead.
State-of-the-art systems use a paged virtual memory that maps virtual addresses to physical addresses
in page granularity (typically 4 KiB ).This mapping is stored as a page table. Before accessing physically addressed memory, the page table is accessed
to translate virtual addresses to physical addresses. Research shows that the overhead of accessing the page table can even exceed the execution time for some important applications.
In addition, this fine-grained mapping changes the access patterns between virtual and physical address spaces, introducing difficulties to many architecture techniques, such as caches and prefecthers.
In this dissertation, I propose architecture mechanisms to reduce the overhead of accessing and managing fine-grained virtual memory without compromising existing benefits.
There are three main contributions in this dissertation.
First, I investigate the impact of address translation on cache. I examine the restriction of virtually indexed, physically tagged (VIPT) caches with fine-grained paging and conclude that this restriction may lead to sub-optimal cache designs.
I introduce a novel cache strategy, speculatively indexed, physically tagged (SIPT) to enable flexible cache indexing under fine-grained page mapping.
SIPT speculates on the value of a few more index bits (1 - 3 in our experiments) to access the cache speculatively before translation, and then verify that the physical tag matches after translation.
Utilizing the fact that a simple relation generally exists between virtual and physical addresses, because memory allocators often exhibit contiguity, I also propose low-cost mechanisms to predict and correct potential mis-speculations.
Next, I focus on reducing the overhead of address translation for fine-grained virtual memory. I propose a novel architecture mechanism, Embedded Page Translation Information (EMPTI),
to provide general fine-grained page translation information on top of coarse-grained virtual memory.
EMPTI does so by speculating that a virtual address is mapped to a pre-determined physical location and then verifying the translation with a very-low-cost access to metadata embedded with data.
Coarse-grained virtual memory mechanisms (e.g., segmentation) are used to suggest the pre-determined physical location for each virtual page.
Overall, EMPTI achieves the benefits of low overhead translation while keeping the flexibility and programmability of fine-grained paging.
Finally, I improve the efficiency of metadata caching based on the fact that memory mapping contiguity generally exists beyond a page boundary.
In state-of-the-art architectures, caches treat PTEs (page table entries) as regular data. Although this is simple and straightforward,
it…
Advisors/Committee Members: Erez, Mattan (advisor), Reddi, Vijay Janapa (committee member), Tiwari, Mohit (committee member), Lin, Calvin (committee member), Peter, Simon (committee member).
Subjects/Keywords: Memory; Cache; Metadata
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APA (6th Edition):
Zheng, Tianhao, P. D. (2018). Efficient fine-grained virtual memory. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/68079
Chicago Manual of Style (16th Edition):
Zheng, Tianhao, Ph D. “Efficient fine-grained virtual memory.” 2018. Doctoral Dissertation, University of Texas – Austin. Accessed February 28, 2021.
http://hdl.handle.net/2152/68079.
MLA Handbook (7th Edition):
Zheng, Tianhao, Ph D. “Efficient fine-grained virtual memory.” 2018. Web. 28 Feb 2021.
Vancouver:
Zheng, Tianhao PD. Efficient fine-grained virtual memory. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2018. [cited 2021 Feb 28].
Available from: http://hdl.handle.net/2152/68079.
Council of Science Editors:
Zheng, Tianhao PD. Efficient fine-grained virtual memory. [Doctoral Dissertation]. University of Texas – Austin; 2018. Available from: http://hdl.handle.net/2152/68079
University of Texas – Austin
5.
Lee, Kyushick.
Resilient heterogeneous systems with Containment Domains.
Degree: PhD, Electrical and Computer Engineering, 2020, University of Texas – Austin
URL: http://dx.doi.org/10.26153/tsw/8121
► Resilience is a continuing concern for extreme-scale scientific applications. Tolerating the ever-increasing hardware fault rates demands a scalable end-to-end resilience scheme. The fundamental issue of…
(more)
▼ Resilience is a continuing concern for extreme-scale scientific applications. Tolerating the ever-increasing hardware fault rates demands a scalable end-to-end resilience scheme. The fundamental issue of current system-wide techniques, such as checkpoint-restart, is a one-size-fits-all approach, which globally recovers local failures. The challenges for supporting efficient resilience grow at scale with the trend of adopting accelerators. Exploiting resiliency tailored to an application can offer a potential breakthrough that enables efficient localized recovery, because an individual node maintains low failure rate at scale. I propose a framework realizing Containment Domains (CDs) that addresses the resilience challenges for future-scale heterogeneous systems. My dissertation consists of two parts: tackling the resilience problem for CPU-only systems with CDs and extending CDs to systems with GPUs. In the first, I develop the CDs framework and adapt CDs-based resilience to real-world applications to verify its analytical model and show its feasibility. CDs elevate resilience to a first-class abstraction and exploit application properties to enable hierarchically decomposing applications into local domains to contain errors. Confining the range of errors with such logical domains in a program enables localized recovery. The CDs framework validates the analytical model of CDs, which matches the trend of the efficiency results measured by running CD-enabled applications with error injection. Based on the analytical model, I develop an automated workflow to tune Containment Domains by leveraging different likelihood of failures, storage hierarchy, and application characteristics. The CD-based resiliency estimated by the analytical model projects higher efficiency than the state-of-the-art, and promises scalablility toward exascale computing. In the second part of the dissertation, I extend CDs to CUDA applications on high-performance computing (HPC) systems with GPUs. GPUs offer higher computational power at lower energy and cost than homogeneous CPU-only nodes. The heterogeneous nodes in modern HPC systems show a tendency of high GPU-to-CPU ratio. While an accelerator-rich machine reduces the total number of compute nodes required to achieve a performance target, a single node becomes vulnerable to accelerator failures as well as congested intra-node resources. Preserving a large amount of local state within accelerators for checkpointing incurs significant overheads. Node-level resilience reveals a new challenge at the scale of accelerator density of HPC systems. I apply CDs to isolate and recover GPU failures in HPC CUDA applications (CD-CUDA). The extention of CDs to CUDA programs allows to express logical domains at the kernel boundary. CD-CUDA improves the system-level efficiency for resilience compared to host-only CDs by containing GPU failures. Furthermore, I propose and evaluate hardware component to resolve the bursty device-local preservation traffic within a node which is a new challenge…
Advisors/Committee Members: Erez, Mattan (advisor), Touba, Nur A. (committee member), Tiwari, Mohit (committee member), Rossbach, Christopher J. (committee member), Sullivan, Michael B. (committee member).
Subjects/Keywords: Resilience; High performance computing; Runtime system; Computer architecture
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APA (6th Edition):
Lee, K. (2020). Resilient heterogeneous systems with Containment Domains. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://dx.doi.org/10.26153/tsw/8121
Chicago Manual of Style (16th Edition):
Lee, Kyushick. “Resilient heterogeneous systems with Containment Domains.” 2020. Doctoral Dissertation, University of Texas – Austin. Accessed February 28, 2021.
http://dx.doi.org/10.26153/tsw/8121.
MLA Handbook (7th Edition):
Lee, Kyushick. “Resilient heterogeneous systems with Containment Domains.” 2020. Web. 28 Feb 2021.
Vancouver:
Lee K. Resilient heterogeneous systems with Containment Domains. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2020. [cited 2021 Feb 28].
Available from: http://dx.doi.org/10.26153/tsw/8121.
Council of Science Editors:
Lee K. Resilient heterogeneous systems with Containment Domains. [Doctoral Dissertation]. University of Texas – Austin; 2020. Available from: http://dx.doi.org/10.26153/tsw/8121
University of Texas – Austin
6.
-6845-8988.
Scalable virtual memory via tailored and larger page sizes.
Degree: PhD, Electrical and Computer Engineering, 2019, University of Texas – Austin
URL: http://dx.doi.org/10.26153/tsw/3003
► Main memory capacity continues to soar, resulting in TLB misses becoming an increasingly significant performance bottleneck. The 4KB default minimum page size in architectures like…
(more)
▼ Main memory capacity continues to soar, resulting in TLB misses becoming an increasingly significant performance bottleneck. The 4KB default minimum page size in architectures like x86 is decades old and hampers future growth potential. Current coarse grained page sizes, the solution from Intel, ARM, and others, have not helped enough. I propose Tailored Page Sizes on top of a Larger Base Page Size (TPS+). TPS+ allows pages of size 2 [superscript n], for all n greater than the minimum page size. TPS+ means one page table entry (PTE) for each large contiguous virtual memory space mapped to an equivalent-sized large contiguous physical frame. To make this work in a clean, seamless way, I suggest small changes to the ISA, the microarchitecture, and the O/S allocation operation. The result: TPS+ can eliminate more than 99% of all TLB misses and page walk memory accesses across a variety of SPEC17 and big data memory intensive benchmarks, yielding 59.7% average performance improvement in virtualized execution scenarios.
Advisors/Committee Members: Patt, Yale N. (advisor), Erez, Mattan (committee member), Tiwari, Mohit (committee member), Rossbach, Christopher J (committee member), Chappell, Robert S (committee member).
Subjects/Keywords: Virtual memory; Microarchitecture; Computer architecture
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APA (6th Edition):
-6845-8988. (2019). Scalable virtual memory via tailored and larger page sizes. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://dx.doi.org/10.26153/tsw/3003
Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Chicago Manual of Style (16th Edition):
-6845-8988. “Scalable virtual memory via tailored and larger page sizes.” 2019. Doctoral Dissertation, University of Texas – Austin. Accessed February 28, 2021.
http://dx.doi.org/10.26153/tsw/3003.
Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
MLA Handbook (7th Edition):
-6845-8988. “Scalable virtual memory via tailored and larger page sizes.” 2019. Web. 28 Feb 2021.
Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Vancouver:
-6845-8988. Scalable virtual memory via tailored and larger page sizes. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2019. [cited 2021 Feb 28].
Available from: http://dx.doi.org/10.26153/tsw/3003.
Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Council of Science Editors:
-6845-8988. Scalable virtual memory via tailored and larger page sizes. [Doctoral Dissertation]. University of Texas – Austin; 2019. Available from: http://dx.doi.org/10.26153/tsw/3003
Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
7.
-3839-4626.
A framework for device-to-device communication between mobile devices using heterogeneous channels.
Degree: PhD, Electrical and Computer Engineering, 2019, University of Texas – Austin
URL: http://dx.doi.org/10.26153/tsw/3198
► Device-to-device (D2D) communication technologies are growing in availability and popularity and are commonly used to facilitate applications in the Internet of Things (IoT) environments. Such…
(more)
▼ Device-to-device (D2D) communication technologies are growing in availability and popularity and are commonly used to facilitate applications in the Internet of Things (IoT) environments. Such environments are characterized by heterogeneous devices, often employing diverse communication technologies with varying energy consumption, discovery ranges, and transmission rates. These complexities pose a daunting setting for the development of IoT applications that could leverage the direct communication with the proximal mobile and embedded devices in this burgeoning landscape. While current approaches focus either on device discovery in the IoT setting or content transfer once communication channels are established, none facilitate the intelligent discovery of useful devices and the seamless formation of temporary D2D connections to transfer content between said devices. Our Omni middleware provides both of these features critical in the development of applications which desire to leverage proximal devices in the IoT setting. Using Omni, we demonstrate the feasibility of building applications that leverage heterogeneous D2D communication channels in an efficient and realistic (in terms of energy and time) manner.
To address the issue of learning access control policies integral to the usability of Omni in realistic IoT applications, we develop the LAD framework for learning and enforcing data access control policies using context-based attributes derived via D2D links to proximal mobile and embedded devices. Existing approaches use tag-based attributes for such access control policies, which do not afford the same granularity or reusability as seamlessly generated and dynamic context-based attributes. The seamless generation of context-based attributes means that LAD is able to provide finer granularity of attributes without incurring the additional overhead associated with users manually adding tags or training a classifier for tagging. The dynamic nature of the attributes makes them reusable since they evolve with a changing environment.
We deploy an extensive, sensor testbed across multiple floors of an industrial-sized academic building walked by several mobile participants to generate a rich, real-life dataset on which to evaluate the performance of our LAD framework in a variety of access control and anomaly detection use cases.
Advisors/Committee Members: Julien, Christine, D. Sc. (advisor), Gligoric, Milos (committee member), Khurshid, Sarfraz (committee member), Pal, Partha (committee member), Tiwari, Mohit (committee member).
Subjects/Keywords: Computer science; Embedded systems; Smart environments; Middleware; Access control; Internet of Things; Device to device communication
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APA (6th Edition):
-3839-4626. (2019). A framework for device-to-device communication between mobile devices using heterogeneous channels. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://dx.doi.org/10.26153/tsw/3198
Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Chicago Manual of Style (16th Edition):
-3839-4626. “A framework for device-to-device communication between mobile devices using heterogeneous channels.” 2019. Doctoral Dissertation, University of Texas – Austin. Accessed February 28, 2021.
http://dx.doi.org/10.26153/tsw/3198.
Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
MLA Handbook (7th Edition):
-3839-4626. “A framework for device-to-device communication between mobile devices using heterogeneous channels.” 2019. Web. 28 Feb 2021.
Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Vancouver:
-3839-4626. A framework for device-to-device communication between mobile devices using heterogeneous channels. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2019. [cited 2021 Feb 28].
Available from: http://dx.doi.org/10.26153/tsw/3198.
Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Council of Science Editors:
-3839-4626. A framework for device-to-device communication between mobile devices using heterogeneous channels. [Doctoral Dissertation]. University of Texas – Austin; 2019. Available from: http://dx.doi.org/10.26153/tsw/3198
Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
University of Texas – Austin
8.
-9323-7100.
Security of electric power systems : cascading outage analysis, interdiction model and resilience to natural disasters.
Degree: PhD, Electrical and Computer Engineering, 2015, University of Texas – Austin
URL: http://hdl.handle.net/2152/32066
► Secure electric power system operation is key to social warfare. However, recent years have seen numerous natural disasters and terrorist attacks that threat the grid…
(more)
▼ Secure electric power system operation is key to social warfare. However, recent years have seen numerous natural disasters and terrorist attacks that threat the grid security. This dissertation summarizes the efforts to develop a model to analyze cascading outages, an interdiction model to analyze worst-case attacks on power grids, and research on grid resilience to natural disasters. The developed cascading outage analysis model uses outage checkers to systematically simulate the system behavior after an initial disturbance, and calculate the potential cascading outage path and electric load shedding. The new interdiction model combines the previously developed medium-term attack-defense model with the short-term cascading outage analysis model to find worst-case terrorist attack. The dissertation also reviews the research on power grid resilience to natural disaster, and develops a framework to simulate the impacts of hurricanes.
Advisors/Committee Members: Baldick, Ross (advisor), SANTOSO, SURYA (committee member), KWASINSKI, ALEXIS (committee member), HUMPHREYS, TODD (committee member), TIWARI, MOHIT (committee member), BICKEL, ERIC (committee member).
Subjects/Keywords: Electric power systems; Interdiction; Cascading outages; Natural disasters
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APA (6th Edition):
-9323-7100. (2015). Security of electric power systems : cascading outage analysis, interdiction model and resilience to natural disasters. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/32066
Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Chicago Manual of Style (16th Edition):
-9323-7100. “Security of electric power systems : cascading outage analysis, interdiction model and resilience to natural disasters.” 2015. Doctoral Dissertation, University of Texas – Austin. Accessed February 28, 2021.
http://hdl.handle.net/2152/32066.
Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
MLA Handbook (7th Edition):
-9323-7100. “Security of electric power systems : cascading outage analysis, interdiction model and resilience to natural disasters.” 2015. Web. 28 Feb 2021.
Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Vancouver:
-9323-7100. Security of electric power systems : cascading outage analysis, interdiction model and resilience to natural disasters. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2015. [cited 2021 Feb 28].
Available from: http://hdl.handle.net/2152/32066.
Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Council of Science Editors:
-9323-7100. Security of electric power systems : cascading outage analysis, interdiction model and resilience to natural disasters. [Doctoral Dissertation]. University of Texas – Austin; 2015. Available from: http://hdl.handle.net/2152/32066
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Author name may be incomplete
University of Texas – Austin
9.
-6267-2468.
Navigating tradeoffs in context sharing among the Internet of Things.
Degree: PhD, Electrical and Computer engineering, 2016, University of Texas – Austin
URL: http://hdl.handle.net/2152/46513
► This dissertation introduces new perspectives on the sharing context (situational information) among Internet of Things (IoT) devices having different processing power, storage capacity, communication bandwidth,…
(more)
▼ This dissertation introduces new perspectives on the sharing context (situational information) among Internet of Things (IoT) devices having different processing power, storage capacity, communication bandwidth, and energy supply. Emerging IoT applications require devices to share information about their context with one another, often over device-to-device wireless links. However, as each IoT device has different capabilities, it may also have different priorities with respect to sharing its context with other nearby devices; low- end IoT devices with limited communication bandwidth and energy supply can prioritize a small context size (and therefore a reduced burden associated with sharing context information), while high-end IoT devices can prioritize communicating context without loss in data quality. Different IoT applications can also impact the priorities; real-time applications can prioritize fast data processing times, whereas big data server applications can prioritize reduced context sizes due to required massive storage. Prioritizing entails tradeoffs. For example, reducing context size through compression requires more energy consumption; in the case of using lossy compression for even smaller output, the data quality can be degraded. In this dissertation, we explore the tradeoffs in sharing context among IoT devices. Specifically, we present our solutions in three stages; theory, implementation, and execution models. In the theory stage, we present our context sharing model using four strategies; we start with strategies that prioritize a single factor, data quality or size, then, we introduce a novel tunable strategy where users can control the tradeoff factors to meet their application’s requirements. We build a mathematical model, and we analyze and experiment with the model to assess the performance relative to tradeoff factors including size, data quality, and energy consumption. An aggregation strategy, which shows an excellent performance in size reduction and energy consumption will be our fourth strategy. In the implementation stage, we introduce a programming model for IoT devices. We stress three principles: easy availability to accessibility of core functions, simple extension to meet application demands, and portability to the other multiple platforms. We demonstrate how these considerations drive the development of the programming model by providing programming tools that realize the model; developers can use these tools to build context sharing activities into their applications. Ultimately, users’ applications will be deployed on a variety of IoT devices. In the third stage of this research, execution models, we categorize IoT devices using three models: tiny devices, mobile devices, and server/cloudlet devices, depending on how the programming tools are employed. We present how context sharing IoT applications can be developed, deployed, and executed within each of these execution models. We expect that IoT developers can benefit in creating new context sharing applications from not…
Advisors/Committee Members: Julien, Christine, D. Sc. (advisor), Khurshid, Sarfraz (committee member), Perry, Dewayne E (committee member), Tiwari, Mohit (committee member), Qiu, Lili (committee member).
Subjects/Keywords: Software engineering; Pervasive computing; Programming model; Internet of Things; M2M communication; D2D communication; Context sharing
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APA (6th Edition):
-6267-2468. (2016). Navigating tradeoffs in context sharing among the Internet of Things. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/46513
Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Chicago Manual of Style (16th Edition):
-6267-2468. “Navigating tradeoffs in context sharing among the Internet of Things.” 2016. Doctoral Dissertation, University of Texas – Austin. Accessed February 28, 2021.
http://hdl.handle.net/2152/46513.
Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
MLA Handbook (7th Edition):
-6267-2468. “Navigating tradeoffs in context sharing among the Internet of Things.” 2016. Web. 28 Feb 2021.
Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Vancouver:
-6267-2468. Navigating tradeoffs in context sharing among the Internet of Things. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2016. [cited 2021 Feb 28].
Available from: http://hdl.handle.net/2152/46513.
Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Council of Science Editors:
-6267-2468. Navigating tradeoffs in context sharing among the Internet of Things. [Doctoral Dissertation]. University of Texas – Austin; 2016. Available from: http://hdl.handle.net/2152/46513
Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
University of Texas – Austin
10.
-7290-5050.
Broad-based side-channel defenses for modern microprocessors.
Degree: PhD, Computer Science, 2019, University of Texas – Austin
URL: http://dx.doi.org/10.26153/tsw/2661
► Private or confidential information is used in a wide variety of applications, not just including implementations of cryptographic algorithms but also including machine-learning libraries, databases,…
(more)
▼ Private or confidential information is used in a wide variety of applications, not just including implementations of cryptographic algorithms but also including machine-learning libraries, databases, and parsers. However, even after using techniques such as encryption, authentication, and isolation, it is difficult to maintain the privacy or confidentiality of such information due to so-called side channels, with which attackers can infer sensitive information by monitoring program execution. Various side channels exist such as execution time, power consumption, exceptions, or micro-architectural components such as caches and branch predictors, and such side channels have been used to steal intellectual property, financial information, and sensitive document contents. Although numerous solutions exist for closing side channels, they are point solutions, since each solution closes an isolated set of side channels.
In this dissertation, we present three compiler-based solutions – Raccoon, Escort, and Vantage – for closing digital side channels (such as the cache, address trace, and branch predictor side channels) that carry information over discrete bits, and for mitigating the a non-digital side channel, specifically, the power side channel. Additionally, our compilers are customizable, since they permit the defense to be tailored to the threat model, to the program, and to the microarchitecture.
More broadly, our solutions augment the compiler with information about the lower layers of the computing stack, so that the compiler is aware of potential side channels and so that the compiler can rewrite programs to avoid leaking information through those side channels. In doing so, our solutions define new abstractions that enable the compiler to reason about the program's impact on timing, power consumption, and other similar side channels. Through such abstractions, our compilers detect and prevent a broad set of digital and non-digital leakage on modern microarchitectures.
Advisors/Committee Members: Lin, Yun Calvin (advisor), Tiwari, Mohit (advisor), Dillig, Isil (committee member), Witchel, Emmett (committee member), Evans, David (committee member).
Subjects/Keywords: Side-channel defenses
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APA (6th Edition):
-7290-5050. (2019). Broad-based side-channel defenses for modern microprocessors. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://dx.doi.org/10.26153/tsw/2661
Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Chicago Manual of Style (16th Edition):
-7290-5050. “Broad-based side-channel defenses for modern microprocessors.” 2019. Doctoral Dissertation, University of Texas – Austin. Accessed February 28, 2021.
http://dx.doi.org/10.26153/tsw/2661.
Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
MLA Handbook (7th Edition):
-7290-5050. “Broad-based side-channel defenses for modern microprocessors.” 2019. Web. 28 Feb 2021.
Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Vancouver:
-7290-5050. Broad-based side-channel defenses for modern microprocessors. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2019. [cited 2021 Feb 28].
Available from: http://dx.doi.org/10.26153/tsw/2661.
Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Council of Science Editors:
-7290-5050. Broad-based side-channel defenses for modern microprocessors. [Doctoral Dissertation]. University of Texas – Austin; 2019. Available from: http://dx.doi.org/10.26153/tsw/2661
Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
University of Texas – Austin
11.
-4326-5362.
Robust behavioral malware detection.
Degree: PhD, Electrical and Computer Engineering, 2018, University of Texas – Austin
URL: http://hdl.handle.net/2152/67580
► Computer security attacks evolve to evade deployed defenses. Recent attacks have ranged from exploiting generic software vulnerabilities in memory-unsafe languages such as buffer overflows and…
(more)
▼ Computer security attacks evolve to evade deployed defenses. Recent attacks have ranged from exploiting generic software vulnerabilities in memory-unsafe languages such as buffer overflows and format string vulnerabilities to exploiting logic errors in web applications, through means such as SQL injection and cross-site scripting. Furthermore, recent attacks have focused on escalating privileges
and stealing sensitive information by exploiting new hardware or operating system (OS) interfaces. Computer security attacks are also now relying on social engineering techniques to run malicious programs on victims' machines; instances of such abuse include phishing and watering hole attacks, both of which trick people into running malicious code or divulging confidential information. Thus, traditional computer security methods, such as OS confinement and program analysis, will not prevent new attacks that do not violate OS confinement or present illegal program behaviors.
Another challenge is that traditional security approaches have large trusted code bases (TCBs), which include hardware, OSs, and other software components that implement authentication and authorization logic across a distributed system. This is a vulnerable area because these components are complex and often contain vulnerabilities that undermine the overall system's integrity or confidentiality.
Evasive attacks on vulnerable systems – especially in instances where trusted components turn malicious – inspire the creation of defenses that can augment formally specified mechanisms against known threats. Specifically, this thesis advances the state of the art in behavioral malware detection – detecting previously unknown malware in the very early stages of infection within an enterprise network.
Here we assess three fundamental insights of modern-day attacks and then describe a cross-layer defense against such attacks. First, we make a low-level machine state visible to behavioral analysis, significantly minimizing the TCB and its associated vulnerabilities. Specifically, our behavioral detector utilizes an executable code's dynamic properties, with architectural and micro-architectural states as input. Second, we evaluate behavioral detectors against adaptive adversaries. For this purpose, we introduce a new metric to determine a detector's robustness against malware modifications, which serves as a step toward explainability of machine learning-based malware detectors. Finally, we exploit the fact that attacks spread through only a limited number of vectors and propose new techniques to analyze the resulting dynamic correlations created among machines. These insights show that behavioral detectors can efficiently protect both individual devices and end hosts within enterprise networks. We present three types of such behavioral detectors.
Sherlock protects resource-constrained devices, such as mobile phones and Internet-of-things (IoT) devices, without modifying the software/hardware stack. Sherlock's supervised and unsupervised versions outperform…
Advisors/Committee Members: Tiwari, Mohit (advisor), Shakkottai, Sanjay (committee member), Gligoric, Milos (committee member), Khurshid, Sarfraz (committee member), Christodorescu, Mihai (committee member).
Subjects/Keywords: Computer security; Malware detection; Behavioral malware detection; Intrusion detection; Machine learning; Artificial intelligence
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APA (6th Edition):
-4326-5362. (2018). Robust behavioral malware detection. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/67580
Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Chicago Manual of Style (16th Edition):
-4326-5362. “Robust behavioral malware detection.” 2018. Doctoral Dissertation, University of Texas – Austin. Accessed February 28, 2021.
http://hdl.handle.net/2152/67580.
Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
MLA Handbook (7th Edition):
-4326-5362. “Robust behavioral malware detection.” 2018. Web. 28 Feb 2021.
Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Vancouver:
-4326-5362. Robust behavioral malware detection. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2018. [cited 2021 Feb 28].
Available from: http://hdl.handle.net/2152/67580.
Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Council of Science Editors:
-4326-5362. Robust behavioral malware detection. [Doctoral Dissertation]. University of Texas – Austin; 2018. Available from: http://hdl.handle.net/2152/67580
Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
University of Texas – Austin
12.
LeBeane, Michael Wayne.
Optimizing communication for clusters of GPUs.
Degree: PhD, Electrical and Computer Engineering, 2018, University of Texas – Austin
URL: http://hdl.handle.net/2152/71508
► GPUs are frequently used to accelerate data-parallel workloads across a wide variety of application domains. While GPUs offer a large amount of computational throughput within…
(more)
▼ GPUs are frequently used to accelerate data-parallel workloads across a wide variety of application domains. While GPUs offer a large amount of computational throughput within a single node, the largest problems require a cluster of such devices communicating with different compute nodes across a network. These clusters can range in size from a small handful of machines constructed from commodity parts, to several thousand machines built from specialized components. Despite widespread deployment of GPUs across clusters both big and small, communication between GPUs in networks of computers remains unwieldy. Networks of GPUs are currently programmed in a clunky coprocessor style, requiring coordination with a host CPU and driver stack to communicate with other systems. These intra-node bottlenecks for initiating communication operations are often much greater than the cost of sending data over a high-performance network. This dissertation explores new techniques to more tightly integrate GPUs with network adapters to allow efficient communication between GPUs across the network. It evaluates both hardware and software changes to NICs and GPUs to enable end-to-end, user-space communication between networks of GPUs, avoiding critical path CPU interference. First, Extended Task Queuing (XTQ) is proposed to provide the ability to launch remote kernels without intervention of a host CPU at the target. Inspired by classic work on active messaging, XTQ uses NIC architectural modifications to support remote kernel launch without the participation of the remote CPU. Bypassing the remote CPU reduces remote kernel launch latencies and allows a more decentralized, cluster-wide work dispatch system. Next, intra-kernel communication is optimized through the Command Processor Networking (ComP-Net) framework. ComP-Net uses a little-known feature of modern GPUs: embedded, programmable microprocessors that are typically referred to as Command Processors (CPs). GPU communication latency is decreased by running the network software stack on the CP instead of the host CPU. ComP-Net implements a runtime and programming interface that allows the GPU compute units to take advantage of the unique capabilities of a networking CP. Challenges related to the GPU's relaxed memory model and L2 cache thrashing are addressed to reduce the latency of network communication through the CP. Finally, GPU Triggered Networking (GPU-TN) is proposed as an alternative intra-kernel networking scheme that enables a GPU to directly trigger network operations from within a GPU kernel without the involvement of any CPU on the critical path. GPU Triggered Networking implements a NIC hardware mechanism by which the GPU can directly trigger the network adapter to send messages. In this approach, the host CPU is responsible for creating the network command packet on behalf of the GPU and registering it with the NIC. When the GPU is ready to send a message, it “triggers” the NIC using a memory-mapped store operation. A small amount of additional hardware in the…
Advisors/Committee Members: John, Lizy Kurian (advisor), Reinhardt, Steven K (committee member), Breternitz, Mauricio (committee member), Erez, Mattan (committee member), Tiwari, Mohit (committee member).
Subjects/Keywords: GPUs; GPGPU; Computer networks; RDMA networks; Programming models
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APA (6th Edition):
LeBeane, M. W. (2018). Optimizing communication for clusters of GPUs. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/71508
Chicago Manual of Style (16th Edition):
LeBeane, Michael Wayne. “Optimizing communication for clusters of GPUs.” 2018. Doctoral Dissertation, University of Texas – Austin. Accessed February 28, 2021.
http://hdl.handle.net/2152/71508.
MLA Handbook (7th Edition):
LeBeane, Michael Wayne. “Optimizing communication for clusters of GPUs.” 2018. Web. 28 Feb 2021.
Vancouver:
LeBeane MW. Optimizing communication for clusters of GPUs. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2018. [cited 2021 Feb 28].
Available from: http://hdl.handle.net/2152/71508.
Council of Science Editors:
LeBeane MW. Optimizing communication for clusters of GPUs. [Doctoral Dissertation]. University of Texas – Austin; 2018. Available from: http://hdl.handle.net/2152/71508
University of Texas – Austin
13.
-7212-2264.
A synergistic framework for hardware IP privacy and integrity protection.
Degree: PhD, Electrical and Computer Engineering, 2018, University of Texas – Austin
URL: http://hdl.handle.net/2152/68451
► As the technology node scales down to 45nm and beyond, the significant increase in design complexity and cost propels the globalization of the $400-billion semiconductor…
(more)
▼ As the technology node scales down to 45nm and beyond, the significant increase in design complexity and cost propels the globalization of the $400-billion semiconductor industry. However, such globalization comes at a cost. Although it has helped to reduce the overall cost by the worldwide distribution of integrated circuit (IC) design, fabrication, and deployment, it also introduces ever-increasing intellectual property (IP) privacy and integrity infringement. Recently, primary violations, including hardware Trojan, reverse engineering, and fault attack, have been reported by leading semiconductor companies and resulted in billions of dollars loss annually.
While hardware IP protection strategies are highly demanded, the re- searches were just initiated lately and still remain preliminary. Firstly, the lack of the mathematical abstractions for these IP violations makes it difficult to formally evaluate and guarantee the effectiveness of the protections. Secondly, the poor scalability and cost-effectiveness of the state-of-the-art protection strategies make them impractical for real-world applications. Moreover, the absence of a holistic IP protection further diminishes the chance to address these highly correlated IP violations which exploit physical clues throughout the whole IC design flow.
The dissertation proposes a synergistic framework to help IP vendors to protect hardware IP privacy and integrity from design, optimization, and evaluation perspectives. The proposed framework consists of five interacting components that directly target at the primary IP violations. First, to prevent the insertion of the hardware Trojan, a split manufacturing strategy is proposed that achieves formal security guarantee while minimizes the introduced overhead. Then, to hinder reverse engineering, a fast security evaluation algorithm and a provably secure IC camouflaging strategy are proposed. Meanwhile, to impede the fault attacks, a new security primitive, named as public physical unclonable function (PPUF), is designed as an alternative to the existing cryptographic modules. A novel cross-level fault attack evaluation procedure also is proposed to help designers to identify security-critical components to protect general purpose processors and compare different security enhancement strategies against the fault attack. All the five algorithms are developed based on rigorous mathematical modeling for primary IP violations and focus on different stages of IC design, which can be combined synergistically to provide a formal security guarantee.
Advisors/Committee Members: Pan, David Z. (advisor), Touba, Nur A. (committee member), Sun, Nan (committee member), Tiwari, Mohit (committee member), Jin, Yier (committee member).
Subjects/Keywords: Hardware IP; Privacy and integrity protection; Hardware trojan; Split manufacturing; Reverse engineering; IC camouflaging; Fault attack; PPUF
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APA (6th Edition):
-7212-2264. (2018). A synergistic framework for hardware IP privacy and integrity protection. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/68451
Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Chicago Manual of Style (16th Edition):
-7212-2264. “A synergistic framework for hardware IP privacy and integrity protection.” 2018. Doctoral Dissertation, University of Texas – Austin. Accessed February 28, 2021.
http://hdl.handle.net/2152/68451.
Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
MLA Handbook (7th Edition):
-7212-2264. “A synergistic framework for hardware IP privacy and integrity protection.” 2018. Web. 28 Feb 2021.
Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Vancouver:
-7212-2264. A synergistic framework for hardware IP privacy and integrity protection. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2018. [cited 2021 Feb 28].
Available from: http://hdl.handle.net/2152/68451.
Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Council of Science Editors:
-7212-2264. A synergistic framework for hardware IP privacy and integrity protection. [Doctoral Dissertation]. University of Texas – Austin; 2018. Available from: http://hdl.handle.net/2152/68451
Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
14.
Niu, Yichuan.
Quantifying and mitigating wind power variability.
Degree: PhD, Electrical and Computer Engineering, 2015, University of Texas – Austin
URL: http://hdl.handle.net/2152/32845
► Understanding variability and unpredictability of wind power is essential for improving power system reliability and energy dispatch in transmission and distribution systems. The research presented…
(more)
▼ Understanding variability and unpredictability of wind power is essential for improving power system reliability and energy dispatch in transmission and distribution systems. The research presented herein intends to address a major challenge in managing and utilizing wind energy with mitigated fluctuation and intermittency. Caused by the varying wind speed, power variability can be explained as power imbalances. These imbalances create power surplus or deficiency in respect to the desired demand. To ameliorate the aforementioned issue, the fluctuating wind energy needs to be properly quantified, controlled, and re-distributed to the grid. The first major study in this dissertations is to develop accurate wind turbine models and model reductions to generate wind power time-series in a laboratory time-efficient manner. Reliable wind turbine models can also perform power control events and acquire dynamic responses more realistic to a real-world condition. Therefore, a Type 4 direct-drive wind turbine with power electronic converters has been modeled and designed with detailed aerodynamic and electric parameters based on a given generator. Later, using averaging and approximation techniques for power electronic circuits, the order of the original model is lowered to boost the computational efficiency for simulating long-term wind speed data. To quantify the wind power time-series, efforts are made to enhance adaptability and robustness of the original conditional range metric (CRM) algorithm that has been proposed by literatures for quantitatively assessing the power variability within a certain time frame. The improved CRM performs better under scarce and noisy time-series data with a reduced computational complexity. Rather than using a discrete probability model, the improved method implements a continuous gamma distribution with parameters estimated by the maximum likelihood estimators. With the leverage from the aforementioned work, a wind farm level behavior can be revealed by analyzing the data through long-term simulations using individual wind turbine models. Mitigating the power variability by reserved generation sources is attempted and the generation scenarios are generalized using an unsupervised machine learning algorithm regarding power correlations of those individual wind turbines. A systematic blueprint for reducing intra-hour power variations via coordinating a fast- and a slow- response energy storage systems (ESS) has been proposed. Methods for sizing, coordination control, ESS regulation, and power dispatch schemes are illustrated in detail. Applying the real-world data, these methods have been demonstrated desirable for reducing short-term wind power variability to an expected level.
Advisors/Committee Members: Santoso, Surya (advisor), Arapostathis, Aristotle (committee member), Baldick, Ross (committee member), Longoria, Raul G. (committee member), Tiwari, Mohit (committee member).
Subjects/Keywords: Wind power variability; Statistics; Conditional range metric; Energy storage system; Wind turbine; Model reduction; Variability mitigation; Probability; Gamma distribution; Bayesian inference
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APA ·
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APA (6th Edition):
Niu, Y. (2015). Quantifying and mitigating wind power variability. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/32845
Chicago Manual of Style (16th Edition):
Niu, Yichuan. “Quantifying and mitigating wind power variability.” 2015. Doctoral Dissertation, University of Texas – Austin. Accessed February 28, 2021.
http://hdl.handle.net/2152/32845.
MLA Handbook (7th Edition):
Niu, Yichuan. “Quantifying and mitigating wind power variability.” 2015. Web. 28 Feb 2021.
Vancouver:
Niu Y. Quantifying and mitigating wind power variability. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2015. [cited 2021 Feb 28].
Available from: http://hdl.handle.net/2152/32845.
Council of Science Editors:
Niu Y. Quantifying and mitigating wind power variability. [Doctoral Dissertation]. University of Texas – Austin; 2015. Available from: http://hdl.handle.net/2152/32845
15.
-0371-5522.
Memory compression for higher effective capacity and bandwidth.
Degree: PhD, Electrical and Computer Engineering, 2019, University of Texas – Austin
URL: http://dx.doi.org/10.26153/tsw/5812
► Many important client and data-center applications need large memory capacity and high memory bandwidth to achieve their performance and energy efficiency goals. With the increase…
(more)
▼ Many important client and data-center applications need large memory capacity and high memory bandwidth to achieve their performance and energy efficiency goals. With the increase in data-centered computing, these trends are ever-growing. Hardware memory compression provides a promising direction to increase effective memory capacity and bandwidth without increasing system cost. Unfortunately, previously proposed memory compression solutions face significant challenges with respect to their evaluation methodology, performance, and time-to-market.
This dissertation identifies the trade-offs that most influence the performance of compressed main memory. It provides main memory compression solutions for both general purpose CPUs and general purpose GPUs, and evaluates them with holistic and accurate methodology. The dissertation also provides a set of solutions to increase the feasibility of the main memory compression by making it completely transparent to the operating system.
Thesis Statement: Hardware main memory compression is a cost-effective solution to the memory capacity wall and can reduce the total cost of ownership of a system. It can be made feasible by designing it with a focus on less data movement and minimal intrusion. This dissertation aims to provide high compression benefits for memory over-commitment phases, while maintaining high performance for the low memory-pressure phases.
Advisors/Committee Members: Erez, Mattan (advisor), Alameldeen, Alaa (committee member), Patt, Yale (committee member), Pillai, Vijaychidambaram Velayudhan (committee member), Tiwari, Mohit (committee member).
Subjects/Keywords: Memory; Memory architecture; Compression; Memory compression; Main memory compression; GPU; GPU compression; Methodology; Compression methodology; Data movement
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APA (6th Edition):
-0371-5522. (2019). Memory compression for higher effective capacity and bandwidth. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://dx.doi.org/10.26153/tsw/5812
Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Chicago Manual of Style (16th Edition):
-0371-5522. “Memory compression for higher effective capacity and bandwidth.” 2019. Doctoral Dissertation, University of Texas – Austin. Accessed February 28, 2021.
http://dx.doi.org/10.26153/tsw/5812.
Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
MLA Handbook (7th Edition):
-0371-5522. “Memory compression for higher effective capacity and bandwidth.” 2019. Web. 28 Feb 2021.
Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Vancouver:
-0371-5522. Memory compression for higher effective capacity and bandwidth. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2019. [cited 2021 Feb 28].
Available from: http://dx.doi.org/10.26153/tsw/5812.
Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Council of Science Editors:
-0371-5522. Memory compression for higher effective capacity and bandwidth. [Doctoral Dissertation]. University of Texas – Austin; 2019. Available from: http://dx.doi.org/10.26153/tsw/5812
Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
University of Texas – Austin
16.
Zhu, Haishan.
QoS-aware mechanisms for improving cost-efficiency of datacenters.
Degree: PhD, Electrical and Computer Engineering, 2021, University of Texas – Austin
URL: http://dx.doi.org/10.26153/tsw/11372
► Warehouse Scale Computers (WSCs) promise high cost-efficiency by amortizing power, cooling, and management overheads. WSCs today host a large variety of jobs with two broad…
(more)
▼ Warehouse Scale Computers (WSCs) promise high cost-efficiency by amortizing power, cooling, and management overheads. WSCs today host a large variety of jobs with two broad performance requirements categories: latency-critical (LC) and best-effort (BE). Ideally, to fully utilize all hardware resources, WSC operators can simply fill all the nodes with computing jobs. Unfortunately, because colocated jobs contend for shared resources, systems with high loads often experience performance degradation, which negatively impacts the Quality of Service (QoS) for LC jobs. In fact, service providers usually over-provision resources to avoid any interference with LC jobs, leading to significant resource inefficiencies. In this dissertation, I explore opportunities across different system-abstraction layers to improve the cost-efficiency of dataceters by increasing resource utilization of WSCs with little or no impact on the performance of LC jobs. The dissertation has three main components. First, I explore opportunities to improve the throughput of multicore systems by reducing the performance variation of LC jobs. The main insight is that by reshaping the latency distribution curve, performance headroom of LC jobs can be effectively converted to improved BE throughput. I develop, implement, and evaluate a runtime system that achieves this goal with existing hardware. I leverage the cache partitioning, per-core frequency scaling, and thread masking of server processors. Evaluation results show the proposed solution enables 30% higher system throughput compared to solutions proposed in prior works while maintaining at least as good QoS for LC jobs. Second, I study resource contention in near-future heterogeneous memory architectures (HMA). This study is motivated by recent developments in non-volatile memory (NVM) technologies, which enable higher storage density at the cost of same performance. To understand the performance and QoS impact of HMAs, I design and implement a performance emulator in the Linux kernel that runs unmodified workloads with high accuracy, low overhead, and complete transparency. I further propose and evaluate multiple data and resource management QoS mechanisms, such as locality-aware page admission, occupancy management, and write buffer jailing. Third, I focus on accelerated machine learning (ML) systems. By profiling the performance of production workloads and accelerators, I show that accelerated ML tasks are highly sensitive to main memory interference due to fine-grained interaction between CPU and accelerator tasks. As a result, memory resource contention can significantly decreases the performance and efficiency gains of accelerators. I propose a runtime system that leverages existing hardware capabilities and show 17% higher system efficiency compared to previous approaches. This study further exposes opportunities for future processor architectures
Advisors/Committee Members: Erez, Mattan (advisor), Pingali, Keshav (committee member), Chang, Jichuan (committee member), de Veciana, Gustavo (committee member), Tiwari, Mohit (committee member).
Subjects/Keywords: Warehouse Scale Computing; Datacenter; QoS; Cache partitioning; DVFS; Non-volatile memory; Heterogeneous architecture; Machine learning; Acceleration
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APA (6th Edition):
Zhu, H. (2021). QoS-aware mechanisms for improving cost-efficiency of datacenters. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://dx.doi.org/10.26153/tsw/11372
Chicago Manual of Style (16th Edition):
Zhu, Haishan. “QoS-aware mechanisms for improving cost-efficiency of datacenters.” 2021. Doctoral Dissertation, University of Texas – Austin. Accessed February 28, 2021.
http://dx.doi.org/10.26153/tsw/11372.
MLA Handbook (7th Edition):
Zhu, Haishan. “QoS-aware mechanisms for improving cost-efficiency of datacenters.” 2021. Web. 28 Feb 2021.
Vancouver:
Zhu H. QoS-aware mechanisms for improving cost-efficiency of datacenters. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2021. [cited 2021 Feb 28].
Available from: http://dx.doi.org/10.26153/tsw/11372.
Council of Science Editors:
Zhu H. QoS-aware mechanisms for improving cost-efficiency of datacenters. [Doctoral Dissertation]. University of Texas – Austin; 2021. Available from: http://dx.doi.org/10.26153/tsw/11372
17.
-4652-063X.
Bridging the gap between mobile CPU design and user satisfaction via crowdsourcing.
Degree: MSin Engineering, Electrical and Computer engineering, 2016, University of Texas – Austin
URL: http://hdl.handle.net/2152/41648
► This report aims to provide an understanding of how the mobile CPU designs have evolved and its influence on end-user satisfaction. To that end, a…
(more)
▼ This report aims to provide an understanding of how the mobile CPU designs have evolved and its influence on end-user satisfaction. To that end, a quantitative performance analysis is conducted across ten cutting-edge mobile CPU designs studied within top-selling off-the-shelf smartphones released over the past seven years. This analysis is then used to guide a large-scale user study spanning over 25,000 participants via crowdsourcing on the Amazon Mechanical Turk service. The user study asks participants to assess the responsiveness of interactive application use cases for a set of current-generation applications (e.g. Angry Birds and FaceBook) and next-generation applications (i.e. face recognition and augmented reality) relative to the performance capabilities of the devices studied. This framework allows us to quantitatively link how the mobile CPU designs studied impacted end-user satisfaction. The study results indicate that mobile CPU designs have exhibited signifiant performance improvements through aggressive core scaling techniques prevalent in desktop CPUs. Just as was observed in desktop CPU design, these same techniques have lead to excessive mobile CPU power consumption. However, from an end-user perspective this power consumption was not without success. Mobile CPUs have evolved to provide satisfactory experiences for the studied current- generation applications. The reason is that many of these applications rely heavily on single-threaded performance. Other, more recent applications, actually multi-thread user-critical parts of the applications, which also demonstrates that multi- core mobile CPUs are an important design consideration – contrary to conventional wisdom. However, looking ahead, the same mobile CPUs where not able to provide satisfactory experiences for many of the next-generation applications studied, questioning the sustainability of these power-hungry design techniques in future mobile CPU designs.
Advisors/Committee Members: Janapa Reddi, Vijay (advisor), Tiwari, Mohit (committee member).
Subjects/Keywords: Mobile; Computer architecture; Crowdsourcing
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APA (6th Edition):
-4652-063X. (2016). Bridging the gap between mobile CPU design and user satisfaction via crowdsourcing. (Masters Thesis). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/41648
Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Chicago Manual of Style (16th Edition):
-4652-063X. “Bridging the gap between mobile CPU design and user satisfaction via crowdsourcing.” 2016. Masters Thesis, University of Texas – Austin. Accessed February 28, 2021.
http://hdl.handle.net/2152/41648.
Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
MLA Handbook (7th Edition):
-4652-063X. “Bridging the gap between mobile CPU design and user satisfaction via crowdsourcing.” 2016. Web. 28 Feb 2021.
Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Vancouver:
-4652-063X. Bridging the gap between mobile CPU design and user satisfaction via crowdsourcing. [Internet] [Masters thesis]. University of Texas – Austin; 2016. [cited 2021 Feb 28].
Available from: http://hdl.handle.net/2152/41648.
Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Council of Science Editors:
-4652-063X. Bridging the gap between mobile CPU design and user satisfaction via crowdsourcing. [Masters Thesis]. University of Texas – Austin; 2016. Available from: http://hdl.handle.net/2152/41648
Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
18.
Angepat, Hari.
Logical partitioning of parallel system simulations.
Degree: PhD, Electrical and Computer Engineering, 2019, University of Texas – Austin
URL: http://dx.doi.org/10.26153/tsw/3268
► Simulation has been a fundamental tool to prototype, hypothesize, and evaluate new ideas to continue improving system performance. However, increasing levels of processor parallelism and…
(more)
▼ Simulation has been a fundamental tool to prototype, hypothesize, and evaluate
new ideas to continue improving system performance. However, increasing levels
of processor parallelism and heterogeneity have introduced additional
constraints when evaluating new designs. The work embodied in this dissertation
explores how to leverage novel ideas in simulator partitioning to improve
simulator speed and flexibility for simulating these new types of systems.
The contribution of this work includes the introduction of optimistic
partitioned simulation to improve parallelization, and the introduction of
warped partitioned simulation for improved flexibility. These ideas are refined
and demonstrated through the use of prototypes to demonstrate their benefits
compared to state-of-the-art approaches. By leveraging partitioning in a
structured manner, it is possible to design simulators that better address the
open challenges of parallel and heterogeneous systems design.
Advisors/Committee Members: Chiou, Derek (advisor), Erez, Mattan (advisor), Gerstlauer, Andreas (committee member), Tiwari, Mohit (committee member), Holt, Jim (committee member).
Subjects/Keywords: FPGA; Simulation; Parallel
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APA ·
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APA (6th Edition):
Angepat, H. (2019). Logical partitioning of parallel system simulations. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://dx.doi.org/10.26153/tsw/3268
Chicago Manual of Style (16th Edition):
Angepat, Hari. “Logical partitioning of parallel system simulations.” 2019. Doctoral Dissertation, University of Texas – Austin. Accessed February 28, 2021.
http://dx.doi.org/10.26153/tsw/3268.
MLA Handbook (7th Edition):
Angepat, Hari. “Logical partitioning of parallel system simulations.” 2019. Web. 28 Feb 2021.
Vancouver:
Angepat H. Logical partitioning of parallel system simulations. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2019. [cited 2021 Feb 28].
Available from: http://dx.doi.org/10.26153/tsw/3268.
Council of Science Editors:
Angepat H. Logical partitioning of parallel system simulations. [Doctoral Dissertation]. University of Texas – Austin; 2019. Available from: http://dx.doi.org/10.26153/tsw/3268
19.
Wang, Jiajun, 1991-.
Reuse aware data placement schemes for multilevel cache hierarchies.
Degree: PhD, Electrical and Computer Engineering, 2019, University of Texas – Austin
URL: http://dx.doi.org/10.26153/tsw/2949
► Memory subsystem with larger capacity and deeper hierarchy has been designed to achieve the maximum performance of data intensive workloads. What grows with the depth…
(more)
▼ Memory subsystem with larger capacity and deeper hierarchy has been designed to achieve the maximum performance of data intensive workloads. What grows with the depth and capacity is the amount of data movement happened between different levels of caches and the associated energy consumption. Prior art [65] shows that the energy cost of moving data from memory to register is two orders higher than the cost of register-to-register double-precision floating point operations. As the cache hierarchy grows deeper, the energy cost on the large amount of data movement between cache layers has become non-negligible. Energy dissipation of future systems will be dominated by the cost of data movement. Thus, reducing data movement through exploiting data locality becomes essential to build energy-efficient architectures. A promising technique to improve the energy efficiency of modern memory subsystem is to adaptively guide data placement into appropriate
caches with the performance benefit and energy cost of data movement in mind. An intelligent data placement scheme should only move data blocks with future re-reference into cache. As the working set size of emerging workloads exceeds cache capacity and the number of cores and IPs sharing caches keeps increasing, a data movement aware data placement scheme can maximize the performance of cache-sensitive workloads and minimize the cache energy consumption of cache-insensitive workloads. Researchers have noticed that exclusive caches have better performance compared to inclusive caches. However, high performance improvement is always at odds with low energy consumption. The amount of data movement and energy consumption of exclusive caches is higher than inclusive ones. A few state-of-the-art CPU caching insertion/bypass policies have been proposed in literature. However these techniques are either at great expense of metadata overhead when adapting to exclusive caches, or they focus
on reducing data movement at the sacrifice of performance. On the GPU side, designing efficient data placement schemes also faces great challenge. CPU caching schemes do not work for GPU memory subsystems, because the SRAM capacity per GPU thread is far smaller than the number per CPU threads. The capacity of GPU on-chip SRAMs is too small to hold large data structures in the GPU workloads. Data with frequent reuse is evicted before it is re-referenced which results in high GPU cache miss rate. Keeping the above shortcomings of prior work and key limitations in mind, this dissertation focuses on improving the performance and energy efficiency of modern cache subsystems of CPU and GPU by proposing performance and energy sensitive data placement schemes. This dissertation first presents a data placement for multilevel CPU caches to guide data placement into appropriate cache layers based on data reuse patterns. PC is utilized as the prediction heuristic based on the observation of good
correlation between memory instruction and the locality of the data accessed by the instruction. Unlike prior art…
Advisors/Committee Members: John, Lizy Kurian (advisor), Swartzlander, Earl (committee member), Gerstlauer, Andreas (committee member), Biros, George (committee member), Tiwari, Mohit (committee member).
Subjects/Keywords: Reuse distance; Cache replacement policy; GPU
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APA ·
Chicago ·
MLA ·
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Export
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APA (6th Edition):
Wang, Jiajun, 1. (2019). Reuse aware data placement schemes for multilevel cache hierarchies. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://dx.doi.org/10.26153/tsw/2949
Chicago Manual of Style (16th Edition):
Wang, Jiajun, 1991-. “Reuse aware data placement schemes for multilevel cache hierarchies.” 2019. Doctoral Dissertation, University of Texas – Austin. Accessed February 28, 2021.
http://dx.doi.org/10.26153/tsw/2949.
MLA Handbook (7th Edition):
Wang, Jiajun, 1991-. “Reuse aware data placement schemes for multilevel cache hierarchies.” 2019. Web. 28 Feb 2021.
Vancouver:
Wang, Jiajun 1. Reuse aware data placement schemes for multilevel cache hierarchies. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2019. [cited 2021 Feb 28].
Available from: http://dx.doi.org/10.26153/tsw/2949.
Council of Science Editors:
Wang, Jiajun 1. Reuse aware data placement schemes for multilevel cache hierarchies. [Doctoral Dissertation]. University of Texas – Austin; 2019. Available from: http://dx.doi.org/10.26153/tsw/2949
. 
Open Access Theses and Dissertations
