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You searched for +publisher:"University of Texas – Austin" +contributor:("Orshansky, Michael"). Showing records 1 – 30 of 54 total matches.

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University of Texas – Austin

1. -8281-6884. Simulation-based verification of EM side-channel attack resilience of embedded cryptographic systems.

Degree: MSin Engineering, Electrical and Computer Engineering, 2017, University of Texas – Austin

 Electromagnetic (EM) fields emanated due to switching currents in crypto-blocks can be an effective non-invasive channel for extracting secret keys. Accurate design-time simulation tools are… (more)

Subjects/Keywords: Side channel attacks; Electromagnetic attacks; Differential attacks; Design for security

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APA (6th Edition):

-8281-6884. (2017). Simulation-based verification of EM side-channel attack resilience of embedded cryptographic systems. (Masters Thesis). University of Texas – Austin. Retrieved from http://dx.doi.org/10.26153/tsw/2820

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Author name may be incomplete

Chicago Manual of Style (16th Edition):

-8281-6884. “Simulation-based verification of EM side-channel attack resilience of embedded cryptographic systems.” 2017. Masters Thesis, University of Texas – Austin. Accessed October 20, 2020. http://dx.doi.org/10.26153/tsw/2820.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

MLA Handbook (7th Edition):

-8281-6884. “Simulation-based verification of EM side-channel attack resilience of embedded cryptographic systems.” 2017. Web. 20 Oct 2020.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Vancouver:

-8281-6884. Simulation-based verification of EM side-channel attack resilience of embedded cryptographic systems. [Internet] [Masters thesis]. University of Texas – Austin; 2017. [cited 2020 Oct 20]. Available from: http://dx.doi.org/10.26153/tsw/2820.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Council of Science Editors:

-8281-6884. Simulation-based verification of EM side-channel attack resilience of embedded cryptographic systems. [Masters Thesis]. University of Texas – Austin; 2017. Available from: http://dx.doi.org/10.26153/tsw/2820

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Author name may be incomplete


University of Texas – Austin

2. Kalyanaraman, Mukund Murali. Highly secure strong PUF based on nonlinearity of MOSFET subthreshold operation.

Degree: MSin Engineering, Electrical and Computer Engineering, 2012, University of Texas – Austin

 Silicon physical unclonable functions (PUFs) are security primitives relying on the intrinsic randomness of IC manufacturing. Strong PUFs have a very large input-output space which… (more)

Subjects/Keywords: Physical unclonable functions; PUF; Security; SCA; Modeling attacks

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APA (6th Edition):

Kalyanaraman, M. M. (2012). Highly secure strong PUF based on nonlinearity of MOSFET subthreshold operation. (Masters Thesis). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/20019

Chicago Manual of Style (16th Edition):

Kalyanaraman, Mukund Murali. “Highly secure strong PUF based on nonlinearity of MOSFET subthreshold operation.” 2012. Masters Thesis, University of Texas – Austin. Accessed October 20, 2020. http://hdl.handle.net/2152/20019.

MLA Handbook (7th Edition):

Kalyanaraman, Mukund Murali. “Highly secure strong PUF based on nonlinearity of MOSFET subthreshold operation.” 2012. Web. 20 Oct 2020.

Vancouver:

Kalyanaraman MM. Highly secure strong PUF based on nonlinearity of MOSFET subthreshold operation. [Internet] [Masters thesis]. University of Texas – Austin; 2012. [cited 2020 Oct 20]. Available from: http://hdl.handle.net/2152/20019.

Council of Science Editors:

Kalyanaraman MM. Highly secure strong PUF based on nonlinearity of MOSFET subthreshold operation. [Masters Thesis]. University of Texas – Austin; 2012. Available from: http://hdl.handle.net/2152/20019


University of Texas – Austin

3. Gulati, Paridhi. A 10-bit, 10Msps pipelined ADC with first stage conventional SAR ADC and second stage multi-bit per cycle SAR ADC.

Degree: MSin Engineering, Electrical and Computer Engineering, 2016, University of Texas – Austin

 A pipelined ADC is generally used for high speeds and high resolutions in applications where latency is not a major concern. This project involves the… (more)

Subjects/Keywords: Pipelined ADC; SAR ADC

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APA (6th Edition):

Gulati, P. (2016). A 10-bit, 10Msps pipelined ADC with first stage conventional SAR ADC and second stage multi-bit per cycle SAR ADC. (Masters Thesis). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/65964

Chicago Manual of Style (16th Edition):

Gulati, Paridhi. “A 10-bit, 10Msps pipelined ADC with first stage conventional SAR ADC and second stage multi-bit per cycle SAR ADC.” 2016. Masters Thesis, University of Texas – Austin. Accessed October 20, 2020. http://hdl.handle.net/2152/65964.

MLA Handbook (7th Edition):

Gulati, Paridhi. “A 10-bit, 10Msps pipelined ADC with first stage conventional SAR ADC and second stage multi-bit per cycle SAR ADC.” 2016. Web. 20 Oct 2020.

Vancouver:

Gulati P. A 10-bit, 10Msps pipelined ADC with first stage conventional SAR ADC and second stage multi-bit per cycle SAR ADC. [Internet] [Masters thesis]. University of Texas – Austin; 2016. [cited 2020 Oct 20]. Available from: http://hdl.handle.net/2152/65964.

Council of Science Editors:

Gulati P. A 10-bit, 10Msps pipelined ADC with first stage conventional SAR ADC and second stage multi-bit per cycle SAR ADC. [Masters Thesis]. University of Texas – Austin; 2016. Available from: http://hdl.handle.net/2152/65964


University of Texas – Austin

4. Ban, Yong Chan. Lithography variability driven cell characterization and layout optimization for manufacturability.

Degree: PhD, Electrical and Computer Engineering, 2011, University of Texas – Austin

 Standard cells are fundamental circuit building blocks designed at very early design stages. Nanometer standard cells are prone to lithography proximity and process variations. How… (more)

Subjects/Keywords: Lithography; Variability; Standard cell; Characterization; Layout optimization; Patterning; Manufacturing; Design automation; SADP; Self-aligned double patterning; Design for manufacturing; Line-edge roughness

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APA (6th Edition):

Ban, Y. C. (2011). Lithography variability driven cell characterization and layout optimization for manufacturability. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/ETD-UT-2011-05-3372

Chicago Manual of Style (16th Edition):

Ban, Yong Chan. “Lithography variability driven cell characterization and layout optimization for manufacturability.” 2011. Doctoral Dissertation, University of Texas – Austin. Accessed October 20, 2020. http://hdl.handle.net/2152/ETD-UT-2011-05-3372.

MLA Handbook (7th Edition):

Ban, Yong Chan. “Lithography variability driven cell characterization and layout optimization for manufacturability.” 2011. Web. 20 Oct 2020.

Vancouver:

Ban YC. Lithography variability driven cell characterization and layout optimization for manufacturability. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2011. [cited 2020 Oct 20]. Available from: http://hdl.handle.net/2152/ETD-UT-2011-05-3372.

Council of Science Editors:

Ban YC. Lithography variability driven cell characterization and layout optimization for manufacturability. [Doctoral Dissertation]. University of Texas – Austin; 2011. Available from: http://hdl.handle.net/2152/ETD-UT-2011-05-3372

5. -7307-3794. Approximate high-level synthesis of quality and energy optimized hardware processors.

Degree: PhD, Electrical and Computer Engineering, 2018, University of Texas – Austin

 Approximate computing is a technique that exploits trade-offs between energy/performance and quality of computed results. Such techniques have been explored at various design levels for… (more)

Subjects/Keywords: Approximate computing; High-level synthesis

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APA (6th Edition):

-7307-3794. (2018). Approximate high-level synthesis of quality and energy optimized hardware processors. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/63811

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Author name may be incomplete

Chicago Manual of Style (16th Edition):

-7307-3794. “Approximate high-level synthesis of quality and energy optimized hardware processors.” 2018. Doctoral Dissertation, University of Texas – Austin. Accessed October 20, 2020. http://hdl.handle.net/2152/63811.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

MLA Handbook (7th Edition):

-7307-3794. “Approximate high-level synthesis of quality and energy optimized hardware processors.” 2018. Web. 20 Oct 2020.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Vancouver:

-7307-3794. Approximate high-level synthesis of quality and energy optimized hardware processors. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2018. [cited 2020 Oct 20]. Available from: http://hdl.handle.net/2152/63811.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Council of Science Editors:

-7307-3794. Approximate high-level synthesis of quality and energy optimized hardware processors. [Doctoral Dissertation]. University of Texas – Austin; 2018. Available from: http://hdl.handle.net/2152/63811

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete


University of Texas – Austin

6. -3568-5180. Direct sampling receivers for broadband communications.

Degree: PhD, Electrical and Computer Engineering, 2019, University of Texas – Austin

 Today everything tends to be connected in the Internet of Things (IoT) universe, where a broad variety of communication standards and technologies are used for… (more)

Subjects/Keywords: RFPGA; RF front end; ADC; SAR

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APA (6th Edition):

-3568-5180. (2019). Direct sampling receivers for broadband communications. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://dx.doi.org/10.26153/tsw/2178

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Chicago Manual of Style (16th Edition):

-3568-5180. “Direct sampling receivers for broadband communications.” 2019. Doctoral Dissertation, University of Texas – Austin. Accessed October 20, 2020. http://dx.doi.org/10.26153/tsw/2178.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

MLA Handbook (7th Edition):

-3568-5180. “Direct sampling receivers for broadband communications.” 2019. Web. 20 Oct 2020.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Vancouver:

-3568-5180. Direct sampling receivers for broadband communications. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2019. [cited 2020 Oct 20]. Available from: http://dx.doi.org/10.26153/tsw/2178.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Council of Science Editors:

-3568-5180. Direct sampling receivers for broadband communications. [Doctoral Dissertation]. University of Texas – Austin; 2019. Available from: http://dx.doi.org/10.26153/tsw/2178

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete


University of Texas – Austin

7. -8949-6919. Layer assignment and routing optimization for advanced technologies.

Degree: PhD, Electrical and Computer Engineering, 2018, University of Texas – Austin

 As VLSI technology scales to deep sub-micron and beyond, it becomes increasingly challenging to achieve timing closure for VLSI design. Since a complete design flow… (more)

Subjects/Keywords: Layer assignment; Routing; Optical interconnect

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APA (6th Edition):

-8949-6919. (2018). Layer assignment and routing optimization for advanced technologies. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/69109

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Author name may be incomplete

Chicago Manual of Style (16th Edition):

-8949-6919. “Layer assignment and routing optimization for advanced technologies.” 2018. Doctoral Dissertation, University of Texas – Austin. Accessed October 20, 2020. http://hdl.handle.net/2152/69109.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

MLA Handbook (7th Edition):

-8949-6919. “Layer assignment and routing optimization for advanced technologies.” 2018. Web. 20 Oct 2020.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Vancouver:

-8949-6919. Layer assignment and routing optimization for advanced technologies. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2018. [cited 2020 Oct 20]. Available from: http://hdl.handle.net/2152/69109.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Council of Science Editors:

-8949-6919. Layer assignment and routing optimization for advanced technologies. [Doctoral Dissertation]. University of Texas – Austin; 2018. Available from: http://hdl.handle.net/2152/69109

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete


University of Texas – Austin

8. Kim, Youngchun. Signal acquisition challenges in mobile systems.

Degree: PhD, Electrical and Computer Engineering, 2018, University of Texas – Austin

 In recent decades, the advent of mobile computing has changed human lives by providing information that was not available in the past. The mobile computing… (more)

Subjects/Keywords: Sparse signal processing; Compressed sensing; Random sampling; Data converter; Sequential detection

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APA (6th Edition):

Kim, Y. (2018). Signal acquisition challenges in mobile systems. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/68089

Chicago Manual of Style (16th Edition):

Kim, Youngchun. “Signal acquisition challenges in mobile systems.” 2018. Doctoral Dissertation, University of Texas – Austin. Accessed October 20, 2020. http://hdl.handle.net/2152/68089.

MLA Handbook (7th Edition):

Kim, Youngchun. “Signal acquisition challenges in mobile systems.” 2018. Web. 20 Oct 2020.

Vancouver:

Kim Y. Signal acquisition challenges in mobile systems. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2018. [cited 2020 Oct 20]. Available from: http://hdl.handle.net/2152/68089.

Council of Science Editors:

Kim Y. Signal acquisition challenges in mobile systems. [Doctoral Dissertation]. University of Texas – Austin; 2018. Available from: http://hdl.handle.net/2152/68089

9. Song, Hyejeong. PLL-based digitally-intensive wireless transmitter architectures employing RF Pulse-Width Modulation.

Degree: PhD, Electrical and Computer Engineering, 2017, University of Texas – Austin

 3G and 4G wireless networks have been recently proposed for Machine to Machine (M2M) communications in order to achieve ubiquitous coverage, robust security and high… (more)

Subjects/Keywords: Internet of things; Pulse-Width Modulation (PWM); RF-Pulse Width Modulation (RF-PWM); PLL; Cartesian transmitter; Polar transmitter; Wireless; Class-D; Switching PA; CMOS power amplifier; Switched capacitor power amplifier

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APA (6th Edition):

Song, H. (2017). PLL-based digitally-intensive wireless transmitter architectures employing RF Pulse-Width Modulation. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://dx.doi.org/10.26153/tsw/2287

Chicago Manual of Style (16th Edition):

Song, Hyejeong. “PLL-based digitally-intensive wireless transmitter architectures employing RF Pulse-Width Modulation.” 2017. Doctoral Dissertation, University of Texas – Austin. Accessed October 20, 2020. http://dx.doi.org/10.26153/tsw/2287.

MLA Handbook (7th Edition):

Song, Hyejeong. “PLL-based digitally-intensive wireless transmitter architectures employing RF Pulse-Width Modulation.” 2017. Web. 20 Oct 2020.

Vancouver:

Song H. PLL-based digitally-intensive wireless transmitter architectures employing RF Pulse-Width Modulation. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2017. [cited 2020 Oct 20]. Available from: http://dx.doi.org/10.26153/tsw/2287.

Council of Science Editors:

Song H. PLL-based digitally-intensive wireless transmitter architectures employing RF Pulse-Width Modulation. [Doctoral Dissertation]. University of Texas – Austin; 2017. Available from: http://dx.doi.org/10.26153/tsw/2287


University of Texas – Austin

10. Ock, Sungmin. Design of linear transmitters for wireless applications.

Degree: PhD, Electrical and Computer Engineering, 2016, University of Texas – Austin

 Wireless standards for high data-rate communications typically employ complex modulation schemes that have large peak-to-average power ratios (PAPR), along with a significant bandwidth requirement. Transmitters… (more)

Subjects/Keywords: Transmitter; Linearity; Cartesian feedback-feedforward; Cartesian feedback; ACLR

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APA (6th Edition):

Ock, S. (2016). Design of linear transmitters for wireless applications. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/68297

Chicago Manual of Style (16th Edition):

Ock, Sungmin. “Design of linear transmitters for wireless applications.” 2016. Doctoral Dissertation, University of Texas – Austin. Accessed October 20, 2020. http://hdl.handle.net/2152/68297.

MLA Handbook (7th Edition):

Ock, Sungmin. “Design of linear transmitters for wireless applications.” 2016. Web. 20 Oct 2020.

Vancouver:

Ock S. Design of linear transmitters for wireless applications. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2016. [cited 2020 Oct 20]. Available from: http://hdl.handle.net/2152/68297.

Council of Science Editors:

Ock S. Design of linear transmitters for wireless applications. [Doctoral Dissertation]. University of Texas – Austin; 2016. Available from: http://hdl.handle.net/2152/68297


University of Texas – Austin

11. -2180-8629. Layout automation for analog and mixed-signal integrated circuits.

Degree: PhD, Electrical and Computer Engineering, 2019, University of Texas – Austin

 Recently, the demand for analog and mixed-signal (AMS) integrated circuits (ICs) has increased significantly due to various emerging applications. However, most of the AMS IC… (more)

Subjects/Keywords: Analog and mixed-signal integrated circuits; Layout; Physical design automation; Placement; Electronic design automation

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APA (6th Edition):

-2180-8629. (2019). Layout automation for analog and mixed-signal integrated circuits. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://dx.doi.org/10.26153/tsw/3213

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Chicago Manual of Style (16th Edition):

-2180-8629. “Layout automation for analog and mixed-signal integrated circuits.” 2019. Doctoral Dissertation, University of Texas – Austin. Accessed October 20, 2020. http://dx.doi.org/10.26153/tsw/3213.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

MLA Handbook (7th Edition):

-2180-8629. “Layout automation for analog and mixed-signal integrated circuits.” 2019. Web. 20 Oct 2020.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Vancouver:

-2180-8629. Layout automation for analog and mixed-signal integrated circuits. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2019. [cited 2020 Oct 20]. Available from: http://dx.doi.org/10.26153/tsw/3213.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Council of Science Editors:

-2180-8629. Layout automation for analog and mixed-signal integrated circuits. [Doctoral Dissertation]. University of Texas – Austin; 2019. Available from: http://dx.doi.org/10.26153/tsw/3213

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete


University of Texas – Austin

12. Sanyal, Arindam. Digital enhancement techniques for data converters in scaled CMOS technologies.

Degree: PhD, Electrical and Computer Engineering, 2015, University of Texas – Austin

 This thesis presents digital enhancement techniques for data converters in advanced technology nodes. With technology scaling, traditional voltage-domain (VD) analog-to-digital converters (ADCs) face two major… (more)

Subjects/Keywords: Time-domain quantizer; Analog-to-digital converter; Digital-to-analog converter; Successive approximation register; Voltage controlled oscillator; Inter-symbol interference error

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APA (6th Edition):

Sanyal, A. (2015). Digital enhancement techniques for data converters in scaled CMOS technologies. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/32851

Chicago Manual of Style (16th Edition):

Sanyal, Arindam. “Digital enhancement techniques for data converters in scaled CMOS technologies.” 2015. Doctoral Dissertation, University of Texas – Austin. Accessed October 20, 2020. http://hdl.handle.net/2152/32851.

MLA Handbook (7th Edition):

Sanyal, Arindam. “Digital enhancement techniques for data converters in scaled CMOS technologies.” 2015. Web. 20 Oct 2020.

Vancouver:

Sanyal A. Digital enhancement techniques for data converters in scaled CMOS technologies. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2015. [cited 2020 Oct 20]. Available from: http://hdl.handle.net/2152/32851.

Council of Science Editors:

Sanyal A. Digital enhancement techniques for data converters in scaled CMOS technologies. [Doctoral Dissertation]. University of Texas – Austin; 2015. Available from: http://hdl.handle.net/2152/32851


University of Texas – Austin

13. Chung, Jae Yong, 1981-. Refactoring-based statistical timing analysis and its applications to robust design and test synthesis.

Degree: PhD, Electrical and Computer Engineering, 2011, University of Texas – Austin

 Technology scaling in the nanometer era comes with a significant amount of process variation, leading to lower yield and new types of defective parts. These… (more)

Subjects/Keywords: Applied algorithms; Electronic design automation; Computer-aided design; Statistical timing; Process variation; At-speed test; Delay test; Max-plus algebra

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APA (6th Edition):

Chung, Jae Yong, 1. (2011). Refactoring-based statistical timing analysis and its applications to robust design and test synthesis. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/ETD-UT-2011-05-3252

Chicago Manual of Style (16th Edition):

Chung, Jae Yong, 1981-. “Refactoring-based statistical timing analysis and its applications to robust design and test synthesis.” 2011. Doctoral Dissertation, University of Texas – Austin. Accessed October 20, 2020. http://hdl.handle.net/2152/ETD-UT-2011-05-3252.

MLA Handbook (7th Edition):

Chung, Jae Yong, 1981-. “Refactoring-based statistical timing analysis and its applications to robust design and test synthesis.” 2011. Web. 20 Oct 2020.

Vancouver:

Chung, Jae Yong 1. Refactoring-based statistical timing analysis and its applications to robust design and test synthesis. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2011. [cited 2020 Oct 20]. Available from: http://hdl.handle.net/2152/ETD-UT-2011-05-3252.

Council of Science Editors:

Chung, Jae Yong 1. Refactoring-based statistical timing analysis and its applications to robust design and test synthesis. [Doctoral Dissertation]. University of Texas – Austin; 2011. Available from: http://hdl.handle.net/2152/ETD-UT-2011-05-3252


University of Texas – Austin

14. -1404-2730. Designs and calibration of delay-line based ADCs.

Degree: PhD, Electrical and Computer engineering, 2015, University of Texas – Austin

 Delay line ADCs become more and more attractive with technology scaling to smaller dimensions with lower voltages. Time domain resolution can be increased by high… (more)

Subjects/Keywords: Delay-line ADCs; Calibration

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APA (6th Edition):

-1404-2730. (2015). Designs and calibration of delay-line based ADCs. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/33495

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Chicago Manual of Style (16th Edition):

-1404-2730. “Designs and calibration of delay-line based ADCs.” 2015. Doctoral Dissertation, University of Texas – Austin. Accessed October 20, 2020. http://hdl.handle.net/2152/33495.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

MLA Handbook (7th Edition):

-1404-2730. “Designs and calibration of delay-line based ADCs.” 2015. Web. 20 Oct 2020.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Vancouver:

-1404-2730. Designs and calibration of delay-line based ADCs. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2015. [cited 2020 Oct 20]. Available from: http://hdl.handle.net/2152/33495.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Council of Science Editors:

-1404-2730. Designs and calibration of delay-line based ADCs. [Doctoral Dissertation]. University of Texas – Austin; 2015. Available from: http://hdl.handle.net/2152/33495

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete


University of Texas – Austin

15. Yang, Jae-Seok. Nanometer VLSI design-manufacturing interface for large scale integration.

Degree: PhD, Electrical and Computer Engineering, 2011, University of Texas – Austin

 As nanometer Very Large Scale Integration (VLSI) demands more transistor density to fabricate multi-cores and memory blocks in a limited die size, many researches have… (more)

Subjects/Keywords: Double patterning; TSV; 3D integration; 3-D integration; Overlay; Layout decomposition; Lithography

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APA (6th Edition):

Yang, J. (2011). Nanometer VLSI design-manufacturing interface for large scale integration. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/ETD-UT-2011-05-3070

Chicago Manual of Style (16th Edition):

Yang, Jae-Seok. “Nanometer VLSI design-manufacturing interface for large scale integration.” 2011. Doctoral Dissertation, University of Texas – Austin. Accessed October 20, 2020. http://hdl.handle.net/2152/ETD-UT-2011-05-3070.

MLA Handbook (7th Edition):

Yang, Jae-Seok. “Nanometer VLSI design-manufacturing interface for large scale integration.” 2011. Web. 20 Oct 2020.

Vancouver:

Yang J. Nanometer VLSI design-manufacturing interface for large scale integration. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2011. [cited 2020 Oct 20]. Available from: http://hdl.handle.net/2152/ETD-UT-2011-05-3070.

Council of Science Editors:

Yang J. Nanometer VLSI design-manufacturing interface for large scale integration. [Doctoral Dissertation]. University of Texas – Austin; 2011. Available from: http://hdl.handle.net/2152/ETD-UT-2011-05-3070


University of Texas – Austin

16. -1491-8328. Improving test compression and diagnosis for system-on-chip designs.

Degree: PhD, Electrical and Computer Engineering, 2019, University of Texas – Austin

 This dissertation presents new approaches to improve test compression and fault diagnosis for system-on-chip (SOC) designs. SOCs typically contain one or more embedded processors which… (more)

Subjects/Keywords: Test compression; Diagnosis; Compaction; MISR; Propagation cones

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APA (6th Edition):

-1491-8328. (2019). Improving test compression and diagnosis for system-on-chip designs. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/72489

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Author name may be incomplete

Chicago Manual of Style (16th Edition):

-1491-8328. “Improving test compression and diagnosis for system-on-chip designs.” 2019. Doctoral Dissertation, University of Texas – Austin. Accessed October 20, 2020. http://hdl.handle.net/2152/72489.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

MLA Handbook (7th Edition):

-1491-8328. “Improving test compression and diagnosis for system-on-chip designs.” 2019. Web. 20 Oct 2020.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Vancouver:

-1491-8328. Improving test compression and diagnosis for system-on-chip designs. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2019. [cited 2020 Oct 20]. Available from: http://hdl.handle.net/2152/72489.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Council of Science Editors:

-1491-8328. Improving test compression and diagnosis for system-on-chip designs. [Doctoral Dissertation]. University of Texas – Austin; 2019. Available from: http://hdl.handle.net/2152/72489

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Author name may be incomplete

17. Park, Jaeyoung, Ph. D. Probabilistic design for emerging memory and nanometer-scale logic.

Degree: PhD, Electrical and Computer Engineering, 2018, University of Texas – Austin

 As semiconductor technology has scaled down, the impact of stochastic behavior in very large scale integrated circuits (VLSI) has become an ever-more important concern. This… (more)

Subjects/Keywords: Memory; Spin-torque-transfer magnetic RAM; Fault injection; Circuit characterization

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APA (6th Edition):

Park, Jaeyoung, P. D. (2018). Probabilistic design for emerging memory and nanometer-scale logic. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/65731

Chicago Manual of Style (16th Edition):

Park, Jaeyoung, Ph D. “Probabilistic design for emerging memory and nanometer-scale logic.” 2018. Doctoral Dissertation, University of Texas – Austin. Accessed October 20, 2020. http://hdl.handle.net/2152/65731.

MLA Handbook (7th Edition):

Park, Jaeyoung, Ph D. “Probabilistic design for emerging memory and nanometer-scale logic.” 2018. Web. 20 Oct 2020.

Vancouver:

Park, Jaeyoung PD. Probabilistic design for emerging memory and nanometer-scale logic. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2018. [cited 2020 Oct 20]. Available from: http://hdl.handle.net/2152/65731.

Council of Science Editors:

Park, Jaeyoung PD. Probabilistic design for emerging memory and nanometer-scale logic. [Doctoral Dissertation]. University of Texas – Austin; 2018. Available from: http://hdl.handle.net/2152/65731


University of Texas – Austin

18. Pak, Jiwoo. Electromigration modeling and layout optimization for advanced VLSI.

Degree: PhD, Electrical and Computer Engineering, 2014, University of Texas – Austin

 Electromigration (EM) is a critical problem for interconnect reliability in advanced VLSI design. Because EM is a strong function of current density, a smaller cross-sectional… (more)

Subjects/Keywords: Electromigration; VLSI; Layout; Physical Design; EDA

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APA (6th Edition):

Pak, J. (2014). Electromigration modeling and layout optimization for advanced VLSI. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/30944

Chicago Manual of Style (16th Edition):

Pak, Jiwoo. “Electromigration modeling and layout optimization for advanced VLSI.” 2014. Doctoral Dissertation, University of Texas – Austin. Accessed October 20, 2020. http://hdl.handle.net/2152/30944.

MLA Handbook (7th Edition):

Pak, Jiwoo. “Electromigration modeling and layout optimization for advanced VLSI.” 2014. Web. 20 Oct 2020.

Vancouver:

Pak J. Electromigration modeling and layout optimization for advanced VLSI. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2014. [cited 2020 Oct 20]. Available from: http://hdl.handle.net/2152/30944.

Council of Science Editors:

Pak J. Electromigration modeling and layout optimization for advanced VLSI. [Doctoral Dissertation]. University of Texas – Austin; 2014. Available from: http://hdl.handle.net/2152/30944


University of Texas – Austin

19. Krimer, Evgeni. Improving energy efficiency of reliable massively-parallel architectures.

Degree: PhD, Electrical and Computer Engineering, 2012, University of Texas – Austin

 While transistor size continues to shrink every technology generation increasing the amount of transistors on a die, the reduction in energy consumption is less significant.… (more)

Subjects/Keywords: SIMD; Energy-efficiency; Process variation; GPU; GPGPU

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APA (6th Edition):

Krimer, E. (2012). Improving energy efficiency of reliable massively-parallel architectures. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/ETD-UT-2012-05-5473

Chicago Manual of Style (16th Edition):

Krimer, Evgeni. “Improving energy efficiency of reliable massively-parallel architectures.” 2012. Doctoral Dissertation, University of Texas – Austin. Accessed October 20, 2020. http://hdl.handle.net/2152/ETD-UT-2012-05-5473.

MLA Handbook (7th Edition):

Krimer, Evgeni. “Improving energy efficiency of reliable massively-parallel architectures.” 2012. Web. 20 Oct 2020.

Vancouver:

Krimer E. Improving energy efficiency of reliable massively-parallel architectures. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2012. [cited 2020 Oct 20]. Available from: http://hdl.handle.net/2152/ETD-UT-2012-05-5473.

Council of Science Editors:

Krimer E. Improving energy efficiency of reliable massively-parallel architectures. [Doctoral Dissertation]. University of Texas – Austin; 2012. Available from: http://hdl.handle.net/2152/ETD-UT-2012-05-5473

20. -3741-2274. Circuits and architectures for the implementation of broadband channelizers.

Degree: PhD, Electrical and Computer Engineering, 2017, University of Texas – Austin

 Broadband spectrum channelizers sub-divide a broadband input spectrum into multiple sub-bands, where each of the sub-bands is down-converted and further processed at baseband. These designs… (more)

Subjects/Keywords: Interference cancellation; Harmonic transfer matrix; Harmonic rejection mixer

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APA (6th Edition):

-3741-2274. (2017). Circuits and architectures for the implementation of broadband channelizers. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/72753

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Author name may be incomplete

Chicago Manual of Style (16th Edition):

-3741-2274. “Circuits and architectures for the implementation of broadband channelizers.” 2017. Doctoral Dissertation, University of Texas – Austin. Accessed October 20, 2020. http://hdl.handle.net/2152/72753.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

MLA Handbook (7th Edition):

-3741-2274. “Circuits and architectures for the implementation of broadband channelizers.” 2017. Web. 20 Oct 2020.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Vancouver:

-3741-2274. Circuits and architectures for the implementation of broadband channelizers. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2017. [cited 2020 Oct 20]. Available from: http://hdl.handle.net/2152/72753.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Council of Science Editors:

-3741-2274. Circuits and architectures for the implementation of broadband channelizers. [Doctoral Dissertation]. University of Texas – Austin; 2017. Available from: http://hdl.handle.net/2152/72753

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Author name may be incomplete


University of Texas – Austin

21. -3841-5127. Concurrent error detection in 2-D separable linear transform.

Degree: PhD, Electrical and Computer engineering, 2016, University of Texas – Austin

 As process technology continues to scale to smaller geometries and reduces the supply voltage, reliability of the resulting semiconductor becomes a greater concern. The effect… (more)

Subjects/Keywords: Concurrent error detection; Linear transform; Fault tolerant

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APA (6th Edition):

-3841-5127. (2016). Concurrent error detection in 2-D separable linear transform. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/44618

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Author name may be incomplete

Chicago Manual of Style (16th Edition):

-3841-5127. “Concurrent error detection in 2-D separable linear transform.” 2016. Doctoral Dissertation, University of Texas – Austin. Accessed October 20, 2020. http://hdl.handle.net/2152/44618.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

MLA Handbook (7th Edition):

-3841-5127. “Concurrent error detection in 2-D separable linear transform.” 2016. Web. 20 Oct 2020.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Vancouver:

-3841-5127. Concurrent error detection in 2-D separable linear transform. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2016. [cited 2020 Oct 20]. Available from: http://hdl.handle.net/2152/44618.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Council of Science Editors:

-3841-5127. Concurrent error detection in 2-D separable linear transform. [Doctoral Dissertation]. University of Texas – Austin; 2016. Available from: http://hdl.handle.net/2152/44618

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

22. -5314-7669. Standard cell optimization and physical design in advanced technology nodes.

Degree: PhD, Electrical and Computer Engineering, 2017, University of Texas – Austin

 Integrated circuits (ICs) are at the heart of modern electronics, which rely heavily on the state-of-the-art semiconductor manufacturing technology. The key to pushing forward semiconductor… (more)

Subjects/Keywords: Standard cell; Physical design; Cell optimization; Integrated circuits; Semiconductor technology; Miniaturization; Unidirectional layout design

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APA (6th Edition):

-5314-7669. (2017). Standard cell optimization and physical design in advanced technology nodes. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/47464

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Author name may be incomplete

Chicago Manual of Style (16th Edition):

-5314-7669. “Standard cell optimization and physical design in advanced technology nodes.” 2017. Doctoral Dissertation, University of Texas – Austin. Accessed October 20, 2020. http://hdl.handle.net/2152/47464.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

MLA Handbook (7th Edition):

-5314-7669. “Standard cell optimization and physical design in advanced technology nodes.” 2017. Web. 20 Oct 2020.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Vancouver:

-5314-7669. Standard cell optimization and physical design in advanced technology nodes. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2017. [cited 2020 Oct 20]. Available from: http://hdl.handle.net/2152/47464.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Council of Science Editors:

-5314-7669. Standard cell optimization and physical design in advanced technology nodes. [Doctoral Dissertation]. University of Texas – Austin; 2017. Available from: http://hdl.handle.net/2152/47464

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Author name may be incomplete

23. Mitra, Joydeep. Mask synthesis techniques for directed self-assembly.

Degree: PhD, Electrical and Computer Engineering, 2019, University of Texas – Austin

 Semiconductor patterning technologies based on the current generation of 193 nm immersion lithography can no longer sustain advanced process nodes beyond 10 nm. Hence, the… (more)

Subjects/Keywords: Directed self-assembly; Multi-patterning

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APA (6th Edition):

Mitra, J. (2019). Mask synthesis techniques for directed self-assembly. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://dx.doi.org/10.26153/tsw/5813

Chicago Manual of Style (16th Edition):

Mitra, Joydeep. “Mask synthesis techniques for directed self-assembly.” 2019. Doctoral Dissertation, University of Texas – Austin. Accessed October 20, 2020. http://dx.doi.org/10.26153/tsw/5813.

MLA Handbook (7th Edition):

Mitra, Joydeep. “Mask synthesis techniques for directed self-assembly.” 2019. Web. 20 Oct 2020.

Vancouver:

Mitra J. Mask synthesis techniques for directed self-assembly. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2019. [cited 2020 Oct 20]. Available from: http://dx.doi.org/10.26153/tsw/5813.

Council of Science Editors:

Mitra J. Mask synthesis techniques for directed self-assembly. [Doctoral Dissertation]. University of Texas – Austin; 2019. Available from: http://dx.doi.org/10.26153/tsw/5813


University of Texas – Austin

24. -8554-563X. Logic and clock network optimization in nanometer VLSI circuits.

Degree: PhD, Electrical and Computer engineering, 2015, University of Texas – Austin

 Logic optimization and clock network optimization for power, performance and area trade-off have been imperative problems for the very large scale integrated (VLSI) circuit designers.… (more)

Subjects/Keywords: Power; Performance; Prefix adder; Synthesis; Clock tree; Gate sizing; Operating conditions; Logic network

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APA (6th Edition):

-8554-563X. (2015). Logic and clock network optimization in nanometer VLSI circuits. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/31418

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Author name may be incomplete

Chicago Manual of Style (16th Edition):

-8554-563X. “Logic and clock network optimization in nanometer VLSI circuits.” 2015. Doctoral Dissertation, University of Texas – Austin. Accessed October 20, 2020. http://hdl.handle.net/2152/31418.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

MLA Handbook (7th Edition):

-8554-563X. “Logic and clock network optimization in nanometer VLSI circuits.” 2015. Web. 20 Oct 2020.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Vancouver:

-8554-563X. Logic and clock network optimization in nanometer VLSI circuits. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2015. [cited 2020 Oct 20]. Available from: http://hdl.handle.net/2152/31418.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Council of Science Editors:

-8554-563X. Logic and clock network optimization in nanometer VLSI circuits. [Doctoral Dissertation]. University of Texas – Austin; 2015. Available from: http://hdl.handle.net/2152/31418

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Author name may be incomplete


University of Texas – Austin

25. Cho, Kunhee. Integrated circuits for efficient power delivery using pulse-width-modulation.

Degree: PhD, Electrical and Computer Engineering, 2017, University of Texas – Austin

 Circuits and architectures for efficient power delivery have become crucial in emerging smart systems. Switching power amplifiers (PA) are very attractive for such applications, because… (more)

Subjects/Keywords: Analog circuit; Integrated circuits; Pulse-width-modulation; PWM; Power delivery IC; Power management IC; PMIC; Energy-efficient

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APA (6th Edition):

Cho, K. (2017). Integrated circuits for efficient power delivery using pulse-width-modulation. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/72747

Chicago Manual of Style (16th Edition):

Cho, Kunhee. “Integrated circuits for efficient power delivery using pulse-width-modulation.” 2017. Doctoral Dissertation, University of Texas – Austin. Accessed October 20, 2020. http://hdl.handle.net/2152/72747.

MLA Handbook (7th Edition):

Cho, Kunhee. “Integrated circuits for efficient power delivery using pulse-width-modulation.” 2017. Web. 20 Oct 2020.

Vancouver:

Cho K. Integrated circuits for efficient power delivery using pulse-width-modulation. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2017. [cited 2020 Oct 20]. Available from: http://hdl.handle.net/2152/72747.

Council of Science Editors:

Cho K. Integrated circuits for efficient power delivery using pulse-width-modulation. [Doctoral Dissertation]. University of Texas – Austin; 2017. Available from: http://hdl.handle.net/2152/72747


University of Texas – Austin

26. Akram, Waqas. Tunable mismatch shaping for bandpass Delta-Sigma data converters.

Degree: PhD, Electrical and Computer Engineering, 2011, University of Texas – Austin

 Oversampled digital-to-analog converters typically employ an array of unit elements to drive out the analog signal. Manufacturing defects can create errors due to mismatch between… (more)

Subjects/Keywords: Mismatch shaping; ADC; DAC; Delta Sigma modulator; Vector shaper

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APA (6th Edition):

Akram, W. (2011). Tunable mismatch shaping for bandpass Delta-Sigma data converters. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/ETD-UT-2011-05-3575

Chicago Manual of Style (16th Edition):

Akram, Waqas. “Tunable mismatch shaping for bandpass Delta-Sigma data converters.” 2011. Doctoral Dissertation, University of Texas – Austin. Accessed October 20, 2020. http://hdl.handle.net/2152/ETD-UT-2011-05-3575.

MLA Handbook (7th Edition):

Akram, Waqas. “Tunable mismatch shaping for bandpass Delta-Sigma data converters.” 2011. Web. 20 Oct 2020.

Vancouver:

Akram W. Tunable mismatch shaping for bandpass Delta-Sigma data converters. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2011. [cited 2020 Oct 20]. Available from: http://hdl.handle.net/2152/ETD-UT-2011-05-3575.

Council of Science Editors:

Akram W. Tunable mismatch shaping for bandpass Delta-Sigma data converters. [Doctoral Dissertation]. University of Texas – Austin; 2011. Available from: http://hdl.handle.net/2152/ETD-UT-2011-05-3575


University of Texas – Austin

27. Hung, Cheng-Hsien. Reconfigurable dual-mode voltage-controlled oscillator and wideband frequency synthesizer for millimeter-wave applications.

Degree: PhD, Electrical and Computer Engineering, 2015, University of Texas – Austin

 Demands for high data-rate communications and high-precision sensing applications have pushed wireless systems towards higher operating frequencies where wider bandwidth is available. Examples of such… (more)

Subjects/Keywords: Dual-mode; VCO; Oscillator; Phase noise; Tuning range; Varactor; PLL; Millimeter-Wave; Wideband; Frequency synthesizer

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APA (6th Edition):

Hung, C. (2015). Reconfigurable dual-mode voltage-controlled oscillator and wideband frequency synthesizer for millimeter-wave applications. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/63897

Chicago Manual of Style (16th Edition):

Hung, Cheng-Hsien. “Reconfigurable dual-mode voltage-controlled oscillator and wideband frequency synthesizer for millimeter-wave applications.” 2015. Doctoral Dissertation, University of Texas – Austin. Accessed October 20, 2020. http://hdl.handle.net/2152/63897.

MLA Handbook (7th Edition):

Hung, Cheng-Hsien. “Reconfigurable dual-mode voltage-controlled oscillator and wideband frequency synthesizer for millimeter-wave applications.” 2015. Web. 20 Oct 2020.

Vancouver:

Hung C. Reconfigurable dual-mode voltage-controlled oscillator and wideband frequency synthesizer for millimeter-wave applications. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2015. [cited 2020 Oct 20]. Available from: http://hdl.handle.net/2152/63897.

Council of Science Editors:

Hung C. Reconfigurable dual-mode voltage-controlled oscillator and wideband frequency synthesizer for millimeter-wave applications. [Doctoral Dissertation]. University of Texas – Austin; 2015. Available from: http://hdl.handle.net/2152/63897


University of Texas – Austin

28. Chen, Long. Design techniques for low-power SAR ADCs in nano-scale CMOS technologies.

Degree: PhD, Electrical and Computer engineering, 2016, University of Texas – Austin

 This thesis presents low power design techniques for successive approximation register (SAR) analog-to-digital converters (ADCs) in nano-scale CMOS technologies. Low power SAR ADCs face two… (more)

Subjects/Keywords: Analog-to-digital converter; SAR ADC; ADC; Low power; Comparator; High speed

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APA (6th Edition):

Chen, L. (2016). Design techniques for low-power SAR ADCs in nano-scale CMOS technologies. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/40286

Chicago Manual of Style (16th Edition):

Chen, Long. “Design techniques for low-power SAR ADCs in nano-scale CMOS technologies.” 2016. Doctoral Dissertation, University of Texas – Austin. Accessed October 20, 2020. http://hdl.handle.net/2152/40286.

MLA Handbook (7th Edition):

Chen, Long. “Design techniques for low-power SAR ADCs in nano-scale CMOS technologies.” 2016. Web. 20 Oct 2020.

Vancouver:

Chen L. Design techniques for low-power SAR ADCs in nano-scale CMOS technologies. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2016. [cited 2020 Oct 20]. Available from: http://hdl.handle.net/2152/40286.

Council of Science Editors:

Chen L. Design techniques for low-power SAR ADCs in nano-scale CMOS technologies. [Doctoral Dissertation]. University of Texas – Austin; 2016. Available from: http://hdl.handle.net/2152/40286


University of Texas – Austin

29. -8959-7197. Circuits and architectures for broadband radio receivers and spectrum channelizers.

Degree: PhD, Electrical and Computer Engineering, 2017, University of Texas – Austin

 A broadband spectrum channelizer divides the spectrum of an input signal into sub-bands prior to baseband processing. Efficient spectrum channelizer architectures can serve as enablers… (more)

Subjects/Keywords: Channelizer; Frequency-folding; ADC; Broadband; Receiver; Harmonic-rejection; Image-rejection

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APA (6th Edition):

-8959-7197. (2017). Circuits and architectures for broadband radio receivers and spectrum channelizers. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://dx.doi.org/10.26153/tsw/5833

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Author name may be incomplete

Chicago Manual of Style (16th Edition):

-8959-7197. “Circuits and architectures for broadband radio receivers and spectrum channelizers.” 2017. Doctoral Dissertation, University of Texas – Austin. Accessed October 20, 2020. http://dx.doi.org/10.26153/tsw/5833.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

MLA Handbook (7th Edition):

-8959-7197. “Circuits and architectures for broadband radio receivers and spectrum channelizers.” 2017. Web. 20 Oct 2020.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Vancouver:

-8959-7197. Circuits and architectures for broadband radio receivers and spectrum channelizers. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2017. [cited 2020 Oct 20]. Available from: http://dx.doi.org/10.26153/tsw/5833.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Council of Science Editors:

-8959-7197. Circuits and architectures for broadband radio receivers and spectrum channelizers. [Doctoral Dissertation]. University of Texas – Austin; 2017. Available from: http://dx.doi.org/10.26153/tsw/5833

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete


University of Texas – Austin

30. -2362-0195. Efficient error correcting codes for emerging and high-density memory systems.

Degree: PhD, Electrical and Computer Engineering, 2020, University of Texas – Austin

 As memory technology scales, the demand for higher performance and reliable operation is increasing as well. Field studies show increased error rates at dynamic random-access… (more)

Subjects/Keywords: Error correcting codes; Emerging memories; SRAM; DRAM; Phase change memory

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APA (6th Edition):

-2362-0195. (2020). Efficient error correcting codes for emerging and high-density memory systems. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://dx.doi.org/10.26153/tsw/8131

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Author name may be incomplete

Chicago Manual of Style (16th Edition):

-2362-0195. “Efficient error correcting codes for emerging and high-density memory systems.” 2020. Doctoral Dissertation, University of Texas – Austin. Accessed October 20, 2020. http://dx.doi.org/10.26153/tsw/8131.

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Author name may be incomplete

MLA Handbook (7th Edition):

-2362-0195. “Efficient error correcting codes for emerging and high-density memory systems.” 2020. Web. 20 Oct 2020.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Vancouver:

-2362-0195. Efficient error correcting codes for emerging and high-density memory systems. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2020. [cited 2020 Oct 20]. Available from: http://dx.doi.org/10.26153/tsw/8131.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Council of Science Editors:

-2362-0195. Efficient error correcting codes for emerging and high-density memory systems. [Doctoral Dissertation]. University of Texas – Austin; 2020. Available from: http://dx.doi.org/10.26153/tsw/8131

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