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You searched for +publisher:"University of Texas – Austin" +contributor:("Keckler, Stephen W."). Showing records 1 – 14 of 14 total matches.

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1. Gratz, Paul V., 1970-. Network-on-chip implementation and performance improvement through workload characterization and congestion awareness.

Degree: PhD, Electrical and Computer Engineering, 2008, University of Texas – Austin

 Off-chip interconnection networks provide for communication between processors and components within computer systems. Semiconductor process technology trends have led to the inclusion of multiple processors… (more)

Subjects/Keywords: Systems on a chip – Design and construction; Computer networks; Computer architecture

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APA (6th Edition):

Gratz, Paul V., 1. (2008). Network-on-chip implementation and performance improvement through workload characterization and congestion awareness. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/18233

Chicago Manual of Style (16th Edition):

Gratz, Paul V., 1970-. “Network-on-chip implementation and performance improvement through workload characterization and congestion awareness.” 2008. Doctoral Dissertation, University of Texas – Austin. Accessed March 05, 2021. http://hdl.handle.net/2152/18233.

MLA Handbook (7th Edition):

Gratz, Paul V., 1970-. “Network-on-chip implementation and performance improvement through workload characterization and congestion awareness.” 2008. Web. 05 Mar 2021.

Vancouver:

Gratz, Paul V. 1. Network-on-chip implementation and performance improvement through workload characterization and congestion awareness. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2008. [cited 2021 Mar 05]. Available from: http://hdl.handle.net/2152/18233.

Council of Science Editors:

Gratz, Paul V. 1. Network-on-chip implementation and performance improvement through workload characterization and congestion awareness. [Doctoral Dissertation]. University of Texas – Austin; 2008. Available from: http://hdl.handle.net/2152/18233

2. Diamond, Jeffrey Robert. Designing on-chip memory systems for throughput architectures.

Degree: PhD, Computer science, 2015, University of Texas – Austin

 Driven by the high arithmetic intensity and embarrassingly parallel nature of real time computer graphics, GPUs became the first wide spread throughput architecture. With the… (more)

Subjects/Keywords: Computer architecture; Caching; Throughput; Arbitrary modulus indexing

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APA (6th Edition):

Diamond, J. R. (2015). Designing on-chip memory systems for throughput architectures. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/33306

Chicago Manual of Style (16th Edition):

Diamond, Jeffrey Robert. “Designing on-chip memory systems for throughput architectures.” 2015. Doctoral Dissertation, University of Texas – Austin. Accessed March 05, 2021. http://hdl.handle.net/2152/33306.

MLA Handbook (7th Edition):

Diamond, Jeffrey Robert. “Designing on-chip memory systems for throughput architectures.” 2015. Web. 05 Mar 2021.

Vancouver:

Diamond JR. Designing on-chip memory systems for throughput architectures. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2015. [cited 2021 Mar 05]. Available from: http://hdl.handle.net/2152/33306.

Council of Science Editors:

Diamond JR. Designing on-chip memory systems for throughput architectures. [Doctoral Dissertation]. University of Texas – Austin; 2015. Available from: http://hdl.handle.net/2152/33306


University of Texas – Austin

3. Sankaralingam, Karthikeyan. Polymorphous architectures: a unified approach for extracting concurrency of different granularities.

Degree: PhD, Computer Sciences, 2006, University of Texas – Austin

 Processor architects today are faced by two daunting challenges: emerging applications with heterogeneous computation needs and technology limitations of power, wire delay, and process variation.… (more)

Subjects/Keywords: Parallel processing (Electronic computers); Computer architecture; Microprogramming

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APA (6th Edition):

Sankaralingam, K. (2006). Polymorphous architectures: a unified approach for extracting concurrency of different granularities. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/2915

Chicago Manual of Style (16th Edition):

Sankaralingam, Karthikeyan. “Polymorphous architectures: a unified approach for extracting concurrency of different granularities.” 2006. Doctoral Dissertation, University of Texas – Austin. Accessed March 05, 2021. http://hdl.handle.net/2152/2915.

MLA Handbook (7th Edition):

Sankaralingam, Karthikeyan. “Polymorphous architectures: a unified approach for extracting concurrency of different granularities.” 2006. Web. 05 Mar 2021.

Vancouver:

Sankaralingam K. Polymorphous architectures: a unified approach for extracting concurrency of different granularities. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2006. [cited 2021 Mar 05]. Available from: http://hdl.handle.net/2152/2915.

Council of Science Editors:

Sankaralingam K. Polymorphous architectures: a unified approach for extracting concurrency of different granularities. [Doctoral Dissertation]. University of Texas – Austin; 2006. Available from: http://hdl.handle.net/2152/2915


University of Texas – Austin

4. Agaram, Kartik Kandadai. Prefetch mechanisms by application memory access pattern.

Degree: PhD, Computer Sciences, 2007, University of Texas – Austin

 Modern computer systems spend a substantial fraction of their running time waiting for data from memory. While prefetching has been a promising avenue of research… (more)

Subjects/Keywords: Cache memory; Memory management (Computer science)

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APA (6th Edition):

Agaram, K. K. (2007). Prefetch mechanisms by application memory access pattern. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/13140

Chicago Manual of Style (16th Edition):

Agaram, Kartik Kandadai. “Prefetch mechanisms by application memory access pattern.” 2007. Doctoral Dissertation, University of Texas – Austin. Accessed March 05, 2021. http://hdl.handle.net/2152/13140.

MLA Handbook (7th Edition):

Agaram, Kartik Kandadai. “Prefetch mechanisms by application memory access pattern.” 2007. Web. 05 Mar 2021.

Vancouver:

Agaram KK. Prefetch mechanisms by application memory access pattern. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2007. [cited 2021 Mar 05]. Available from: http://hdl.handle.net/2152/13140.

Council of Science Editors:

Agaram KK. Prefetch mechanisms by application memory access pattern. [Doctoral Dissertation]. University of Texas – Austin; 2007. Available from: http://hdl.handle.net/2152/13140


University of Texas – Austin

5. Shivakumar, Premkishore. Techniques to improve the hard and soft error reliability of distributed architectures.

Degree: PhD, Computer Sciences, 2007, University of Texas – Austin

Subjects/Keywords: Electronic digital computers – Reliability; Computer architecture

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APA (6th Edition):

Shivakumar, P. (2007). Techniques to improve the hard and soft error reliability of distributed architectures. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/3304

Chicago Manual of Style (16th Edition):

Shivakumar, Premkishore. “Techniques to improve the hard and soft error reliability of distributed architectures.” 2007. Doctoral Dissertation, University of Texas – Austin. Accessed March 05, 2021. http://hdl.handle.net/2152/3304.

MLA Handbook (7th Edition):

Shivakumar, Premkishore. “Techniques to improve the hard and soft error reliability of distributed architectures.” 2007. Web. 05 Mar 2021.

Vancouver:

Shivakumar P. Techniques to improve the hard and soft error reliability of distributed architectures. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2007. [cited 2021 Mar 05]. Available from: http://hdl.handle.net/2152/3304.

Council of Science Editors:

Shivakumar P. Techniques to improve the hard and soft error reliability of distributed architectures. [Doctoral Dissertation]. University of Texas – Austin; 2007. Available from: http://hdl.handle.net/2152/3304


University of Texas – Austin

6. Hanson, Heather Lynn, 1969-. Coordinated power, energy, and temperature management.

Degree: PhD, Electrical and Computer Engineering, 2007, University of Texas – Austin

 Power and thermal effects have emerged as serious problems for computing systems by limiting performance, degrading reliability, and imposing a high cost in energy resources.… (more)

Subjects/Keywords: Electronic digital computers – Design and construction

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APA (6th Edition):

Hanson, Heather Lynn, 1. (2007). Coordinated power, energy, and temperature management. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/3240

Chicago Manual of Style (16th Edition):

Hanson, Heather Lynn, 1969-. “Coordinated power, energy, and temperature management.” 2007. Doctoral Dissertation, University of Texas – Austin. Accessed March 05, 2021. http://hdl.handle.net/2152/3240.

MLA Handbook (7th Edition):

Hanson, Heather Lynn, 1969-. “Coordinated power, energy, and temperature management.” 2007. Web. 05 Mar 2021.

Vancouver:

Hanson, Heather Lynn 1. Coordinated power, energy, and temperature management. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2007. [cited 2021 Mar 05]. Available from: http://hdl.handle.net/2152/3240.

Council of Science Editors:

Hanson, Heather Lynn 1. Coordinated power, energy, and temperature management. [Doctoral Dissertation]. University of Texas – Austin; 2007. Available from: http://hdl.handle.net/2152/3240

7. Robatmili, Behnam. Efficient execution of sequential applications on multicore systems.

Degree: PhD, Computer Science, 2011, University of Texas – Austin

 Conventional CMOS scaling has been the engine of the technology revolution in most application domains. This trend has changed as in each technology generation, transistor… (more)

Subjects/Keywords: Microarchitecture; EDGE; Multicore; Single-thread performance; Dataflow; Block-atomic execution; Power efficiency; Composable cores

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APA (6th Edition):

Robatmili, B. (2011). Efficient execution of sequential applications on multicore systems. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/ETD-UT-2011-08-3987

Chicago Manual of Style (16th Edition):

Robatmili, Behnam. “Efficient execution of sequential applications on multicore systems.” 2011. Doctoral Dissertation, University of Texas – Austin. Accessed March 05, 2021. http://hdl.handle.net/2152/ETD-UT-2011-08-3987.

MLA Handbook (7th Edition):

Robatmili, Behnam. “Efficient execution of sequential applications on multicore systems.” 2011. Web. 05 Mar 2021.

Vancouver:

Robatmili B. Efficient execution of sequential applications on multicore systems. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2011. [cited 2021 Mar 05]. Available from: http://hdl.handle.net/2152/ETD-UT-2011-08-3987.

Council of Science Editors:

Robatmili B. Efficient execution of sequential applications on multicore systems. [Doctoral Dissertation]. University of Texas – Austin; 2011. Available from: http://hdl.handle.net/2152/ETD-UT-2011-08-3987

8. Grot, Boris. Network-on-chip architectures for scalability and service guarantees.

Degree: PhD, Computer Sciences, 2011, University of Texas – Austin

 Rapidly increasing transistor densities have led to the emergence of richly-integrated substrates in the form of chip multiprocessors and systems-on-a-chip. These devices integrate a variety… (more)

Subjects/Keywords: Network-on-chip; NOC; Interconnection network; Quality-of-service; QOS; Topology; Routing; Flow control

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APA (6th Edition):

Grot, B. (2011). Network-on-chip architectures for scalability and service guarantees. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/ETD-UT-2011-08-3960

Chicago Manual of Style (16th Edition):

Grot, Boris. “Network-on-chip architectures for scalability and service guarantees.” 2011. Doctoral Dissertation, University of Texas – Austin. Accessed March 05, 2021. http://hdl.handle.net/2152/ETD-UT-2011-08-3960.

MLA Handbook (7th Edition):

Grot, Boris. “Network-on-chip architectures for scalability and service guarantees.” 2011. Web. 05 Mar 2021.

Vancouver:

Grot B. Network-on-chip architectures for scalability and service guarantees. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2011. [cited 2021 Mar 05]. Available from: http://hdl.handle.net/2152/ETD-UT-2011-08-3960.

Council of Science Editors:

Grot B. Network-on-chip architectures for scalability and service guarantees. [Doctoral Dissertation]. University of Texas – Austin; 2011. Available from: http://hdl.handle.net/2152/ETD-UT-2011-08-3960

9. Smith, Aaron Lee, 1977-. Explicit data graph compilation.

Degree: PhD, Computer Sciences, 2009, University of Texas – Austin

 Technology trends such as growing wire delays, power consumption limits, and diminishing clock rate improvements, present conventional instruction set architectures such as RISC, CISC, and… (more)

Subjects/Keywords: EDGE; Computer architecture; Compilers

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APA (6th Edition):

Smith, Aaron Lee, 1. (2009). Explicit data graph compilation. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/ETD-UT-2009-12-626

Chicago Manual of Style (16th Edition):

Smith, Aaron Lee, 1977-. “Explicit data graph compilation.” 2009. Doctoral Dissertation, University of Texas – Austin. Accessed March 05, 2021. http://hdl.handle.net/2152/ETD-UT-2009-12-626.

MLA Handbook (7th Edition):

Smith, Aaron Lee, 1977-. “Explicit data graph compilation.” 2009. Web. 05 Mar 2021.

Vancouver:

Smith, Aaron Lee 1. Explicit data graph compilation. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2009. [cited 2021 Mar 05]. Available from: http://hdl.handle.net/2152/ETD-UT-2009-12-626.

Council of Science Editors:

Smith, Aaron Lee 1. Explicit data graph compilation. [Doctoral Dissertation]. University of Texas – Austin; 2009. Available from: http://hdl.handle.net/2152/ETD-UT-2009-12-626

10. Sartor, Jennifer Bedke. Exploiting language abstraction to optimize memory efficiency.

Degree: PhD, Computer Sciences, 2010, University of Texas – Austin

 The programming language and underlying hardware determine application performance, and both are undergoing revolutionary shifts. As applications have become more sophisticated and capable, programmers have… (more)

Subjects/Keywords: Managed languages; Dynamic optimization; Memory management; Abstraction; Memory efficiency

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APA (6th Edition):

Sartor, J. B. (2010). Exploiting language abstraction to optimize memory efficiency. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/ETD-UT-2010-08-1919

Chicago Manual of Style (16th Edition):

Sartor, Jennifer Bedke. “Exploiting language abstraction to optimize memory efficiency.” 2010. Doctoral Dissertation, University of Texas – Austin. Accessed March 05, 2021. http://hdl.handle.net/2152/ETD-UT-2010-08-1919.

MLA Handbook (7th Edition):

Sartor, Jennifer Bedke. “Exploiting language abstraction to optimize memory efficiency.” 2010. Web. 05 Mar 2021.

Vancouver:

Sartor JB. Exploiting language abstraction to optimize memory efficiency. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2010. [cited 2021 Mar 05]. Available from: http://hdl.handle.net/2152/ETD-UT-2010-08-1919.

Council of Science Editors:

Sartor JB. Exploiting language abstraction to optimize memory efficiency. [Doctoral Dissertation]. University of Texas – Austin; 2010. Available from: http://hdl.handle.net/2152/ETD-UT-2010-08-1919

11. Gebhart, Mark Alan. Energy-efficient mechanisms for managing on-chip storage in throughput processors.

Degree: PhD, Computer Science, 2012, University of Texas – Austin

 Modern computer systems are power or energy limited. While the number of transistors per chip continues to increase, classic Dennard voltage scaling has come to… (more)

Subjects/Keywords: Energy efficiency; Multi-threading; Register file organization; Throughput computing

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APA (6th Edition):

Gebhart, M. A. (2012). Energy-efficient mechanisms for managing on-chip storage in throughput processors. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/ETD-UT-2012-05-5141

Chicago Manual of Style (16th Edition):

Gebhart, Mark Alan. “Energy-efficient mechanisms for managing on-chip storage in throughput processors.” 2012. Doctoral Dissertation, University of Texas – Austin. Accessed March 05, 2021. http://hdl.handle.net/2152/ETD-UT-2012-05-5141.

MLA Handbook (7th Edition):

Gebhart, Mark Alan. “Energy-efficient mechanisms for managing on-chip storage in throughput processors.” 2012. Web. 05 Mar 2021.

Vancouver:

Gebhart MA. Energy-efficient mechanisms for managing on-chip storage in throughput processors. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2012. [cited 2021 Mar 05]. Available from: http://hdl.handle.net/2152/ETD-UT-2012-05-5141.

Council of Science Editors:

Gebhart MA. Energy-efficient mechanisms for managing on-chip storage in throughput processors. [Doctoral Dissertation]. University of Texas – Austin; 2012. Available from: http://hdl.handle.net/2152/ETD-UT-2012-05-5141

12. Govindan, Madhu Sarava. E³ : energy-efficient EDGE architectures.

Degree: PhD, Computer Sciences, 2010, University of Texas – Austin

 Increasing power dissipation is one of the most serious challenges facing designers in the microprocessor industry. Power dissipation, increasing wire delays, and increasing design complexity… (more)

Subjects/Keywords: Energy efficiency; EDGE architectures; Power efficiency; Composability; DVFS; Power management; Dynamic voltage and frequency scaling; Explicit Data Graph Execution architectures

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APA (6th Edition):

Govindan, M. S. (2010). E³ : energy-efficient EDGE architectures. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/ETD-UT-2010-08-1934

Chicago Manual of Style (16th Edition):

Govindan, Madhu Sarava. “E³ : energy-efficient EDGE architectures.” 2010. Doctoral Dissertation, University of Texas – Austin. Accessed March 05, 2021. http://hdl.handle.net/2152/ETD-UT-2010-08-1934.

MLA Handbook (7th Edition):

Govindan, Madhu Sarava. “E³ : energy-efficient EDGE architectures.” 2010. Web. 05 Mar 2021.

Vancouver:

Govindan MS. E³ : energy-efficient EDGE architectures. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2010. [cited 2021 Mar 05]. Available from: http://hdl.handle.net/2152/ETD-UT-2010-08-1934.

Council of Science Editors:

Govindan MS. E³ : energy-efficient EDGE architectures. [Doctoral Dissertation]. University of Texas – Austin; 2010. Available from: http://hdl.handle.net/2152/ETD-UT-2010-08-1934


University of Texas – Austin

13. Ha, Jung Woo. Scaling managed runtime systems for future multicore hardware.

Degree: PhD, Computer Sciences, 2009, University of Texas – Austin

 The exponential improvement in single processor performance has recently come to an end, mainly because clock frequency has reached its limit due to power constraints.… (more)

Subjects/Keywords: Scalability; Multicore; Managed Language; Runtime System; Parallelism

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APA (6th Edition):

Ha, J. W. (2009). Scaling managed runtime systems for future multicore hardware. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/ETD-UT-2009-12-480

Chicago Manual of Style (16th Edition):

Ha, Jung Woo. “Scaling managed runtime systems for future multicore hardware.” 2009. Doctoral Dissertation, University of Texas – Austin. Accessed March 05, 2021. http://hdl.handle.net/2152/ETD-UT-2009-12-480.

MLA Handbook (7th Edition):

Ha, Jung Woo. “Scaling managed runtime systems for future multicore hardware.” 2009. Web. 05 Mar 2021.

Vancouver:

Ha JW. Scaling managed runtime systems for future multicore hardware. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2009. [cited 2021 Mar 05]. Available from: http://hdl.handle.net/2152/ETD-UT-2009-12-480.

Council of Science Editors:

Ha JW. Scaling managed runtime systems for future multicore hardware. [Doctoral Dissertation]. University of Texas – Austin; 2009. Available from: http://hdl.handle.net/2152/ETD-UT-2009-12-480


University of Texas – Austin

14. Maher, Bertrand Allen. Atomic block formation for explicit data graph execution architectures.

Degree: PhD, Computer Sciences, 2010, University of Texas – Austin

 Limits on power consumption, complexity, and on-chip latency have focused computer architects on power-efficient designs that exploit parallelism. One approach divides programs into atomic blocks… (more)

Subjects/Keywords: Computer architecture; Compilers; Block formation

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APA (6th Edition):

Maher, B. A. (2010). Atomic block formation for explicit data graph execution architectures. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/ETD-UT-2010-08-1904

Chicago Manual of Style (16th Edition):

Maher, Bertrand Allen. “Atomic block formation for explicit data graph execution architectures.” 2010. Doctoral Dissertation, University of Texas – Austin. Accessed March 05, 2021. http://hdl.handle.net/2152/ETD-UT-2010-08-1904.

MLA Handbook (7th Edition):

Maher, Bertrand Allen. “Atomic block formation for explicit data graph execution architectures.” 2010. Web. 05 Mar 2021.

Vancouver:

Maher BA. Atomic block formation for explicit data graph execution architectures. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2010. [cited 2021 Mar 05]. Available from: http://hdl.handle.net/2152/ETD-UT-2010-08-1904.

Council of Science Editors:

Maher BA. Atomic block formation for explicit data graph execution architectures. [Doctoral Dissertation]. University of Texas – Austin; 2010. Available from: http://hdl.handle.net/2152/ETD-UT-2010-08-1904

.