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You searched for +publisher:"University of Texas – Austin" +contributor:("Burger, Douglas C."). Showing records 1 – 16 of 16 total matches.

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1. Li, Dong, active 21st century. Orchestrating thread scheduling and cache management to improve memory system throughput in throughput processors.

Degree: PhD, Computer Science, 2014, University of Texas – Austin

 Throughput processors such as GPUs continue to provide higher peak arithmetic capability. Designing a high throughput memory system to keep the computational units busy is… (more)

Subjects/Keywords: Throughput processors; GPU; Architecture

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APA (6th Edition):

Li, Dong, a. 2. c. (2014). Orchestrating thread scheduling and cache management to improve memory system throughput in throughput processors. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/25098

Chicago Manual of Style (16th Edition):

Li, Dong, active 21st century. “Orchestrating thread scheduling and cache management to improve memory system throughput in throughput processors.” 2014. Doctoral Dissertation, University of Texas – Austin. Accessed February 26, 2021. http://hdl.handle.net/2152/25098.

MLA Handbook (7th Edition):

Li, Dong, active 21st century. “Orchestrating thread scheduling and cache management to improve memory system throughput in throughput processors.” 2014. Web. 26 Feb 2021.

Vancouver:

Li, Dong a2c. Orchestrating thread scheduling and cache management to improve memory system throughput in throughput processors. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2014. [cited 2021 Feb 26]. Available from: http://hdl.handle.net/2152/25098.

Council of Science Editors:

Li, Dong a2c. Orchestrating thread scheduling and cache management to improve memory system throughput in throughput processors. [Doctoral Dissertation]. University of Texas – Austin; 2014. Available from: http://hdl.handle.net/2152/25098

2. Nagarajan, Ramadass, 1977-. Design and evaluation of a technology-scalable architecture for instruction-level parallelism.

Degree: PhD, Computer Sciences, 2007, University of Texas – Austin

 Future performance improvements must come from the exploitation of concurrency at all levels. Recent approaches that focus on thread-level and data-level concurrency are a natural… (more)

Subjects/Keywords: Computer architecture – Design; Computer architecture – Evaluation; High performance processors – Design and construction; High performance processors – Evaluation; Parallel processing (Electronic computers); Threads (Computer programs)

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APA (6th Edition):

Nagarajan, Ramadass, 1. (2007). Design and evaluation of a technology-scalable architecture for instruction-level parallelism. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/3534

Chicago Manual of Style (16th Edition):

Nagarajan, Ramadass, 1977-. “Design and evaluation of a technology-scalable architecture for instruction-level parallelism.” 2007. Doctoral Dissertation, University of Texas – Austin. Accessed February 26, 2021. http://hdl.handle.net/2152/3534.

MLA Handbook (7th Edition):

Nagarajan, Ramadass, 1977-. “Design and evaluation of a technology-scalable architecture for instruction-level parallelism.” 2007. Web. 26 Feb 2021.

Vancouver:

Nagarajan, Ramadass 1. Design and evaluation of a technology-scalable architecture for instruction-level parallelism. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2007. [cited 2021 Feb 26]. Available from: http://hdl.handle.net/2152/3534.

Council of Science Editors:

Nagarajan, Ramadass 1. Design and evaluation of a technology-scalable architecture for instruction-level parallelism. [Doctoral Dissertation]. University of Texas – Austin; 2007. Available from: http://hdl.handle.net/2152/3534

3. St Amant, Renee Marie. Enabling high-performance, mixed-signal approximate computing.

Degree: PhD, Computer Science, 2014, University of Texas – Austin

 For decades, the semiconductor industry enjoyed exponential improvements in microprocessor power and performance with the device scaling of successive technology generations. Scaling limitations at sub-micron… (more)

Subjects/Keywords: Approximate computing; Neural branch prediction; Neural accelerator; General purpose computing

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APA (6th Edition):

St Amant, R. M. (2014). Enabling high-performance, mixed-signal approximate computing. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/25025

Chicago Manual of Style (16th Edition):

St Amant, Renee Marie. “Enabling high-performance, mixed-signal approximate computing.” 2014. Doctoral Dissertation, University of Texas – Austin. Accessed February 26, 2021. http://hdl.handle.net/2152/25025.

MLA Handbook (7th Edition):

St Amant, Renee Marie. “Enabling high-performance, mixed-signal approximate computing.” 2014. Web. 26 Feb 2021.

Vancouver:

St Amant RM. Enabling high-performance, mixed-signal approximate computing. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2014. [cited 2021 Feb 26]. Available from: http://hdl.handle.net/2152/25025.

Council of Science Editors:

St Amant RM. Enabling high-performance, mixed-signal approximate computing. [Doctoral Dissertation]. University of Texas – Austin; 2014. Available from: http://hdl.handle.net/2152/25025

4. Robatmili, Behnam. Efficient execution of sequential applications on multicore systems.

Degree: PhD, Computer Science, 2011, University of Texas – Austin

 Conventional CMOS scaling has been the engine of the technology revolution in most application domains. This trend has changed as in each technology generation, transistor… (more)

Subjects/Keywords: Microarchitecture; EDGE; Multicore; Single-thread performance; Dataflow; Block-atomic execution; Power efficiency; Composable cores

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APA (6th Edition):

Robatmili, B. (2011). Efficient execution of sequential applications on multicore systems. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/ETD-UT-2011-08-3987

Chicago Manual of Style (16th Edition):

Robatmili, Behnam. “Efficient execution of sequential applications on multicore systems.” 2011. Doctoral Dissertation, University of Texas – Austin. Accessed February 26, 2021. http://hdl.handle.net/2152/ETD-UT-2011-08-3987.

MLA Handbook (7th Edition):

Robatmili, Behnam. “Efficient execution of sequential applications on multicore systems.” 2011. Web. 26 Feb 2021.

Vancouver:

Robatmili B. Efficient execution of sequential applications on multicore systems. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2011. [cited 2021 Feb 26]. Available from: http://hdl.handle.net/2152/ETD-UT-2011-08-3987.

Council of Science Editors:

Robatmili B. Efficient execution of sequential applications on multicore systems. [Doctoral Dissertation]. University of Texas – Austin; 2011. Available from: http://hdl.handle.net/2152/ETD-UT-2011-08-3987

5. Grot, Boris. Network-on-chip architectures for scalability and service guarantees.

Degree: PhD, Computer Sciences, 2011, University of Texas – Austin

 Rapidly increasing transistor densities have led to the emergence of richly-integrated substrates in the form of chip multiprocessors and systems-on-a-chip. These devices integrate a variety… (more)

Subjects/Keywords: Network-on-chip; NOC; Interconnection network; Quality-of-service; QOS; Topology; Routing; Flow control

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APA (6th Edition):

Grot, B. (2011). Network-on-chip architectures for scalability and service guarantees. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/ETD-UT-2011-08-3960

Chicago Manual of Style (16th Edition):

Grot, Boris. “Network-on-chip architectures for scalability and service guarantees.” 2011. Doctoral Dissertation, University of Texas – Austin. Accessed February 26, 2021. http://hdl.handle.net/2152/ETD-UT-2011-08-3960.

MLA Handbook (7th Edition):

Grot, Boris. “Network-on-chip architectures for scalability and service guarantees.” 2011. Web. 26 Feb 2021.

Vancouver:

Grot B. Network-on-chip architectures for scalability and service guarantees. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2011. [cited 2021 Feb 26]. Available from: http://hdl.handle.net/2152/ETD-UT-2011-08-3960.

Council of Science Editors:

Grot B. Network-on-chip architectures for scalability and service guarantees. [Doctoral Dissertation]. University of Texas – Austin; 2011. Available from: http://hdl.handle.net/2152/ETD-UT-2011-08-3960

6. Smith, Aaron Lee, 1977-. Explicit data graph compilation.

Degree: PhD, Computer Sciences, 2009, University of Texas – Austin

 Technology trends such as growing wire delays, power consumption limits, and diminishing clock rate improvements, present conventional instruction set architectures such as RISC, CISC, and… (more)

Subjects/Keywords: EDGE; Computer architecture; Compilers

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APA (6th Edition):

Smith, Aaron Lee, 1. (2009). Explicit data graph compilation. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/ETD-UT-2009-12-626

Chicago Manual of Style (16th Edition):

Smith, Aaron Lee, 1977-. “Explicit data graph compilation.” 2009. Doctoral Dissertation, University of Texas – Austin. Accessed February 26, 2021. http://hdl.handle.net/2152/ETD-UT-2009-12-626.

MLA Handbook (7th Edition):

Smith, Aaron Lee, 1977-. “Explicit data graph compilation.” 2009. Web. 26 Feb 2021.

Vancouver:

Smith, Aaron Lee 1. Explicit data graph compilation. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2009. [cited 2021 Feb 26]. Available from: http://hdl.handle.net/2152/ETD-UT-2009-12-626.

Council of Science Editors:

Smith, Aaron Lee 1. Explicit data graph compilation. [Doctoral Dissertation]. University of Texas – Austin; 2009. Available from: http://hdl.handle.net/2152/ETD-UT-2009-12-626

7. Gebhart, Mark Alan. Energy-efficient mechanisms for managing on-chip storage in throughput processors.

Degree: PhD, Computer Science, 2012, University of Texas – Austin

 Modern computer systems are power or energy limited. While the number of transistors per chip continues to increase, classic Dennard voltage scaling has come to… (more)

Subjects/Keywords: Energy efficiency; Multi-threading; Register file organization; Throughput computing

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APA (6th Edition):

Gebhart, M. A. (2012). Energy-efficient mechanisms for managing on-chip storage in throughput processors. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/ETD-UT-2012-05-5141

Chicago Manual of Style (16th Edition):

Gebhart, Mark Alan. “Energy-efficient mechanisms for managing on-chip storage in throughput processors.” 2012. Doctoral Dissertation, University of Texas – Austin. Accessed February 26, 2021. http://hdl.handle.net/2152/ETD-UT-2012-05-5141.

MLA Handbook (7th Edition):

Gebhart, Mark Alan. “Energy-efficient mechanisms for managing on-chip storage in throughput processors.” 2012. Web. 26 Feb 2021.

Vancouver:

Gebhart MA. Energy-efficient mechanisms for managing on-chip storage in throughput processors. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2012. [cited 2021 Feb 26]. Available from: http://hdl.handle.net/2152/ETD-UT-2012-05-5141.

Council of Science Editors:

Gebhart MA. Energy-efficient mechanisms for managing on-chip storage in throughput processors. [Doctoral Dissertation]. University of Texas – Austin; 2012. Available from: http://hdl.handle.net/2152/ETD-UT-2012-05-5141


University of Texas – Austin

8. Kim, Changkyu. A technology-scalable composable architecture.

Degree: PhD, Computer Sciences, 2007, University of Texas – Austin

 Clock rate scaling can no longer sustain computer system performance scaling due to power and thermal constraints and diminishing performance returns of deep pipelining. Future… (more)

Subjects/Keywords: Computer architecture; Computer storage devices; Memory management (Computer science); Multiprocessors

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APA (6th Edition):

Kim, C. (2007). A technology-scalable composable architecture. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/3279

Chicago Manual of Style (16th Edition):

Kim, Changkyu. “A technology-scalable composable architecture.” 2007. Doctoral Dissertation, University of Texas – Austin. Accessed February 26, 2021. http://hdl.handle.net/2152/3279.

MLA Handbook (7th Edition):

Kim, Changkyu. “A technology-scalable composable architecture.” 2007. Web. 26 Feb 2021.

Vancouver:

Kim C. A technology-scalable composable architecture. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2007. [cited 2021 Feb 26]. Available from: http://hdl.handle.net/2152/3279.

Council of Science Editors:

Kim C. A technology-scalable composable architecture. [Doctoral Dissertation]. University of Texas – Austin; 2007. Available from: http://hdl.handle.net/2152/3279


University of Texas – Austin

9. Ranganathan, Nitya. Control flow speculation for distributed architectures.

Degree: PhD, Computer Sciences, 2009, University of Texas – Austin

 As transistor counts, power dissipation, and wire delays increase, the microprocessor industry is transitioning from chips containing large monolithic processors to multi-core architectures. The granularity… (more)

Subjects/Keywords: Distributed architectures; Control flow prediction

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APA (6th Edition):

Ranganathan, N. (2009). Control flow speculation for distributed architectures. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/6586

Chicago Manual of Style (16th Edition):

Ranganathan, Nitya. “Control flow speculation for distributed architectures.” 2009. Doctoral Dissertation, University of Texas – Austin. Accessed February 26, 2021. http://hdl.handle.net/2152/6586.

MLA Handbook (7th Edition):

Ranganathan, Nitya. “Control flow speculation for distributed architectures.” 2009. Web. 26 Feb 2021.

Vancouver:

Ranganathan N. Control flow speculation for distributed architectures. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2009. [cited 2021 Feb 26]. Available from: http://hdl.handle.net/2152/6586.

Council of Science Editors:

Ranganathan N. Control flow speculation for distributed architectures. [Doctoral Dissertation]. University of Texas – Austin; 2009. Available from: http://hdl.handle.net/2152/6586


University of Texas – Austin

10. Sethumadhavan, Lakshminarasimhan, 1978-. Scalable hardware memory disambiguation.

Degree: PhD, Computer Sciences, 2007, University of Texas – Austin

 This dissertation deals with one of the long-standing problems in Computer Architecture – the problem of memory disambiguation. Microprocessors typically reorder memory instructions during execution… (more)

Subjects/Keywords: Memory management (Computer science); Computer storage devices; Microprocessors – Design and construction; Computer architecture

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APA (6th Edition):

Sethumadhavan, Lakshminarasimhan, 1. (2007). Scalable hardware memory disambiguation. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/3682

Chicago Manual of Style (16th Edition):

Sethumadhavan, Lakshminarasimhan, 1978-. “Scalable hardware memory disambiguation.” 2007. Doctoral Dissertation, University of Texas – Austin. Accessed February 26, 2021. http://hdl.handle.net/2152/3682.

MLA Handbook (7th Edition):

Sethumadhavan, Lakshminarasimhan, 1978-. “Scalable hardware memory disambiguation.” 2007. Web. 26 Feb 2021.

Vancouver:

Sethumadhavan, Lakshminarasimhan 1. Scalable hardware memory disambiguation. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2007. [cited 2021 Feb 26]. Available from: http://hdl.handle.net/2152/3682.

Council of Science Editors:

Sethumadhavan, Lakshminarasimhan 1. Scalable hardware memory disambiguation. [Doctoral Dissertation]. University of Texas – Austin; 2007. Available from: http://hdl.handle.net/2152/3682


University of Texas – Austin

11. Desikan, Rajagopalan. Distributed selective re-execution for EDGE architectures.

Degree: PhD, Electrical and Computer Engineering, 2005, University of Texas – Austin

Subjects/Keywords: Computer architecture; High performance computing

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APA (6th Edition):

Desikan, R. (2005). Distributed selective re-execution for EDGE architectures. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/2414

Chicago Manual of Style (16th Edition):

Desikan, Rajagopalan. “Distributed selective re-execution for EDGE architectures.” 2005. Doctoral Dissertation, University of Texas – Austin. Accessed February 26, 2021. http://hdl.handle.net/2152/2414.

MLA Handbook (7th Edition):

Desikan, Rajagopalan. “Distributed selective re-execution for EDGE architectures.” 2005. Web. 26 Feb 2021.

Vancouver:

Desikan R. Distributed selective re-execution for EDGE architectures. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2005. [cited 2021 Feb 26]. Available from: http://hdl.handle.net/2152/2414.

Council of Science Editors:

Desikan R. Distributed selective re-execution for EDGE architectures. [Doctoral Dissertation]. University of Texas – Austin; 2005. Available from: http://hdl.handle.net/2152/2414


University of Texas – Austin

12. Liu, Haiming. Hardware techniques to improve cache efficiency.

Degree: PhD, Computer Sciences, 2009, University of Texas – Austin

 Modern microprocessors devote a large portion of their chip area to caches in order to bridge the speed and bandwidth gap between the core and… (more)

Subjects/Keywords: Data cache efficiency; Instruction cache efficiency; Explicit Data Graph Execution; Dead-block prediction

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APA (6th Edition):

Liu, H. (2009). Hardware techniques to improve cache efficiency. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/6566

Chicago Manual of Style (16th Edition):

Liu, Haiming. “Hardware techniques to improve cache efficiency.” 2009. Doctoral Dissertation, University of Texas – Austin. Accessed February 26, 2021. http://hdl.handle.net/2152/6566.

MLA Handbook (7th Edition):

Liu, Haiming. “Hardware techniques to improve cache efficiency.” 2009. Web. 26 Feb 2021.

Vancouver:

Liu H. Hardware techniques to improve cache efficiency. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2009. [cited 2021 Feb 26]. Available from: http://hdl.handle.net/2152/6566.

Council of Science Editors:

Liu H. Hardware techniques to improve cache efficiency. [Doctoral Dissertation]. University of Texas – Austin; 2009. Available from: http://hdl.handle.net/2152/6566


University of Texas – Austin

13. Huh, Jaehyuk. Hardware techniques to reduce communication costs in multiprocessors.

Degree: PhD, Computer Sciences, 2006, University of Texas – Austin

 This dissertation explores techniques for reducing the costs of inter-processor communication in shared memory multiprocessors (MP). We seek to improve MP performance by enhancing three… (more)

Subjects/Keywords: Multiprocessors – Design and construction; Cache memory

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APA (6th Edition):

Huh, J. (2006). Hardware techniques to reduce communication costs in multiprocessors. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/2533

Chicago Manual of Style (16th Edition):

Huh, Jaehyuk. “Hardware techniques to reduce communication costs in multiprocessors.” 2006. Doctoral Dissertation, University of Texas – Austin. Accessed February 26, 2021. http://hdl.handle.net/2152/2533.

MLA Handbook (7th Edition):

Huh, Jaehyuk. “Hardware techniques to reduce communication costs in multiprocessors.” 2006. Web. 26 Feb 2021.

Vancouver:

Huh J. Hardware techniques to reduce communication costs in multiprocessors. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2006. [cited 2021 Feb 26]. Available from: http://hdl.handle.net/2152/2533.

Council of Science Editors:

Huh J. Hardware techniques to reduce communication costs in multiprocessors. [Doctoral Dissertation]. University of Texas – Austin; 2006. Available from: http://hdl.handle.net/2152/2533

14. Govindan, Madhu Sarava. E³ : energy-efficient EDGE architectures.

Degree: PhD, Computer Sciences, 2010, University of Texas – Austin

 Increasing power dissipation is one of the most serious challenges facing designers in the microprocessor industry. Power dissipation, increasing wire delays, and increasing design complexity… (more)

Subjects/Keywords: Energy efficiency; EDGE architectures; Power efficiency; Composability; DVFS; Power management; Dynamic voltage and frequency scaling; Explicit Data Graph Execution architectures

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APA (6th Edition):

Govindan, M. S. (2010). E³ : energy-efficient EDGE architectures. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/ETD-UT-2010-08-1934

Chicago Manual of Style (16th Edition):

Govindan, Madhu Sarava. “E³ : energy-efficient EDGE architectures.” 2010. Doctoral Dissertation, University of Texas – Austin. Accessed February 26, 2021. http://hdl.handle.net/2152/ETD-UT-2010-08-1934.

MLA Handbook (7th Edition):

Govindan, Madhu Sarava. “E³ : energy-efficient EDGE architectures.” 2010. Web. 26 Feb 2021.

Vancouver:

Govindan MS. E³ : energy-efficient EDGE architectures. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2010. [cited 2021 Feb 26]. Available from: http://hdl.handle.net/2152/ETD-UT-2010-08-1934.

Council of Science Editors:

Govindan MS. E³ : energy-efficient EDGE architectures. [Doctoral Dissertation]. University of Texas – Austin; 2010. Available from: http://hdl.handle.net/2152/ETD-UT-2010-08-1934


University of Texas – Austin

15. Murukkathampoondi, Hrishikesh Sathyavasu. Design of wide-issue high-frequency processors in wire delay dominated technologies.

Degree: PhD, Electrical and Computer Engineering, 2004, University of Texas – Austin

Subjects/Keywords: Microprocessors – Design and construction; Computer architecture

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APA (6th Edition):

Murukkathampoondi, H. S. (2004). Design of wide-issue high-frequency processors in wire delay dominated technologies. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/1279

Chicago Manual of Style (16th Edition):

Murukkathampoondi, Hrishikesh Sathyavasu. “Design of wide-issue high-frequency processors in wire delay dominated technologies.” 2004. Doctoral Dissertation, University of Texas – Austin. Accessed February 26, 2021. http://hdl.handle.net/2152/1279.

MLA Handbook (7th Edition):

Murukkathampoondi, Hrishikesh Sathyavasu. “Design of wide-issue high-frequency processors in wire delay dominated technologies.” 2004. Web. 26 Feb 2021.

Vancouver:

Murukkathampoondi HS. Design of wide-issue high-frequency processors in wire delay dominated technologies. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2004. [cited 2021 Feb 26]. Available from: http://hdl.handle.net/2152/1279.

Council of Science Editors:

Murukkathampoondi HS. Design of wide-issue high-frequency processors in wire delay dominated technologies. [Doctoral Dissertation]. University of Texas – Austin; 2004. Available from: http://hdl.handle.net/2152/1279


University of Texas – Austin

16. Maher, Bertrand Allen. Atomic block formation for explicit data graph execution architectures.

Degree: PhD, Computer Sciences, 2010, University of Texas – Austin

 Limits on power consumption, complexity, and on-chip latency have focused computer architects on power-efficient designs that exploit parallelism. One approach divides programs into atomic blocks… (more)

Subjects/Keywords: Computer architecture; Compilers; Block formation

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APA (6th Edition):

Maher, B. A. (2010). Atomic block formation for explicit data graph execution architectures. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/ETD-UT-2010-08-1904

Chicago Manual of Style (16th Edition):

Maher, Bertrand Allen. “Atomic block formation for explicit data graph execution architectures.” 2010. Doctoral Dissertation, University of Texas – Austin. Accessed February 26, 2021. http://hdl.handle.net/2152/ETD-UT-2010-08-1904.

MLA Handbook (7th Edition):

Maher, Bertrand Allen. “Atomic block formation for explicit data graph execution architectures.” 2010. Web. 26 Feb 2021.

Vancouver:

Maher BA. Atomic block formation for explicit data graph execution architectures. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2010. [cited 2021 Feb 26]. Available from: http://hdl.handle.net/2152/ETD-UT-2010-08-1904.

Council of Science Editors:

Maher BA. Atomic block formation for explicit data graph execution architectures. [Doctoral Dissertation]. University of Texas – Austin; 2010. Available from: http://hdl.handle.net/2152/ETD-UT-2010-08-1904

.