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You searched for +publisher:"University of Notre Dame" +contributor:("Alexei O. Orlov, Research Director"). Showing records 1 – 2 of 2 total matches.

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University of Notre Dame

1. Michael S. McConnell. Effect of Platinum Oxidation and Reduction on Single Electron Transistors Fabricated by Atomic Layer Deposition</h1>.

Degree: MSin Electrical Engineering, Electrical Engineering, 2016, University of Notre Dame

This work describes the fabrication of single electron transistors using electron beam lithography and atomic layer deposition to form nanoscale tunnel transparent junctions of alumina (Al2O3) on platinum nanowires using either water or ozone as the oxygen precursor and trimethylaluminum as the aluminum precursor. Using room temperature, low frequency conductance measurements between the source and drain, it was found that devices fabricated using water had higher conductance than devices fabricated with ozone. Subsequent annealing caused both water- and ozone-based devices to increase in conductance by more than 2 orders of magnitude. Furthermore, comparison of devices at low temperatures (~4 K) showed that annealed devices displayed much closer to the ideal behavior (i.e., constant differential conductance) outside of the Coulomb blockade region and that untreated devices showed nonlinear behavior outside of the Coulomb blockade region (i.e., an increase in differential conductance with source-drain voltage bias). Transmission electron microscopy cross-sectional images showed that annealing did not significantly change device geometry, but energy dispersive x-ray spectroscopy showed an unusually large amount of oxygen in the bottom platinum layer. This suggests that the atomic layer deposition process results in the formation of a thin platinum surface oxide, which either decomposes or is reduced during the anneal step, resulting in a tunnel barrier without the in-series native oxide contribution. Furthermore, the difference between ozone- and water-based devices suggests that ozone promotes atomic layer deposition nucleation by oxidizing the surface but that water relies on physisorption of the precursors. To test this theory, devices were exposed to forming gas at room temperature, which also reduces platinum oxide, and a decrease in resistance was observed, as expected. Advisors/Committee Members: Craig S. Lent, Committee Member, Alexei O. Orlov, Research Director, Patrick Fay, Committee Member, Gregory L. Snider, Research Director.

Subjects/Keywords: single electronics; single electron transistor; atomic layer deposition

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

McConnell, M. S. (2016). Effect of Platinum Oxidation and Reduction on Single Electron Transistors Fabricated by Atomic Layer Deposition</h1>. (Masters Thesis). University of Notre Dame. Retrieved from https://curate.nd.edu/show/vx021c2104k

Chicago Manual of Style (16th Edition):

McConnell, Michael S.. “Effect of Platinum Oxidation and Reduction on Single Electron Transistors Fabricated by Atomic Layer Deposition</h1>.” 2016. Masters Thesis, University of Notre Dame. Accessed December 19, 2018. https://curate.nd.edu/show/vx021c2104k.

MLA Handbook (7th Edition):

McConnell, Michael S.. “Effect of Platinum Oxidation and Reduction on Single Electron Transistors Fabricated by Atomic Layer Deposition</h1>.” 2016. Web. 19 Dec 2018.

Vancouver:

McConnell MS. Effect of Platinum Oxidation and Reduction on Single Electron Transistors Fabricated by Atomic Layer Deposition</h1>. [Internet] [Masters thesis]. University of Notre Dame; 2016. [cited 2018 Dec 19]. Available from: https://curate.nd.edu/show/vx021c2104k.

Council of Science Editors:

McConnell MS. Effect of Platinum Oxidation and Reduction on Single Electron Transistors Fabricated by Atomic Layer Deposition</h1>. [Masters Thesis]. University of Notre Dame; 2016. Available from: https://curate.nd.edu/show/vx021c2104k


University of Notre Dame

2. Golnaz Karbasian. Fabrication of Metallic Single Electron Transistors Featuring Plasma Enhanced Atomic Layer Deposition of Tunnel Barriers</h1>.

Degree: PhD, Electrical Engineering, 2015, University of Notre Dame

The continuing increase of the device density in integrated circuits (ICs) gives rise to the high level of power that is dissipated per unit area and consequently a high temperature in the circuits. Since temperature affects the performance and reliability of the circuits, minimization of the energy consumption in logic devices is now the center of attention. According to the International Technology Roadmaps for Semiconductors (ITRS), single electron transistors (SETs) hold the promise of achieving the lowest power of any known logic device, as low as 1×10−18 J per switching event. Moreover, SETs are the most sensitive electrometers to date, and are capable of detecting a fraction of an electron charge. Despite their low power consumption and high sensitivity for charge detection, room temperature operation of these devices is quite challenging mainly due to lithographical constraints in fabricating structures with the required dimensions of less than 10 nm. Silicon based SETs have been reported to operate at room temperature. However, they all suffer from significant variation in batch-to-batch performance, low fabrication yield, and temperature-dependent tunnel barrier height. In this project, we explored the fabrication of SETs featuring metal-insulator-metal (MIM) tunnel junctions. While Si-based SETs suffer from undesirable effect of dopants that result in irregularities in the device behavior, in metal-based SETs the device components (tunnel barrier, island, and the leads) are well-defined. Therefore, metal SETs are potentially more predictable in behavior, making them easier to incorporate into circuits, and easier to check against theoretical models.<a href="#_ENREF_1" title="Lee, 201080">1</a> Here, the proposed fabrication method takes advantage of unique properties of chemical mechanical polishing (CMP) and plasma enhanced atomic layer deposition (PEALD). Chemical mechanical polishing provides a path for tuning the dimensions of the tunnel junctions, surpassing the limits imposed by electron beam lithography and lift-off, while atomic layer deposition provides precise control over the thickness of the tunnel barrier and significantly increases the choices for barrier materials. As described below in detail, the fabrication of ultra-thin (~1nm) tunnel transparent barriers with PEALD is in fact challenging; we demonstrate that in fabrication of SETs with PEALD to form the barrier in the Ni-insulator-Ni tunnel junctions, additional NiO layers are parasitically formed in the Ni layers that form the top and bottom electrodes of the tunnel junctions. The NiO on the bottom electrode is formed due to oxidizing effect of the O2 plasma used in the PEALD process, while the NiO on the bottom of the top electrode is believed to form during the metal deposition due to oxygen-containing contaminants on the surface of the deposited tunnel barrier. We also show that due to the presence of these surface parasitic layers of NiO, the resistance of… Advisors/Committee Members: Carig Lent, Committee Member, Alan Seabaugh, Committee Member, Gary Bernstein, Committee Member, Gregory L. Snider, Research Director, Alexei O. Orlov, Research Director.

Subjects/Keywords: Tunnel junctions; Nickel oxide, NiO, reduction; Single electron transistors; Plasma enhanced atomic layer deposition

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Karbasian, G. (2015). Fabrication of Metallic Single Electron Transistors Featuring Plasma Enhanced Atomic Layer Deposition of Tunnel Barriers</h1>. (Doctoral Dissertation). University of Notre Dame. Retrieved from https://curate.nd.edu/show/bz60cv45s9j

Chicago Manual of Style (16th Edition):

Karbasian, Golnaz. “Fabrication of Metallic Single Electron Transistors Featuring Plasma Enhanced Atomic Layer Deposition of Tunnel Barriers</h1>.” 2015. Doctoral Dissertation, University of Notre Dame. Accessed December 19, 2018. https://curate.nd.edu/show/bz60cv45s9j.

MLA Handbook (7th Edition):

Karbasian, Golnaz. “Fabrication of Metallic Single Electron Transistors Featuring Plasma Enhanced Atomic Layer Deposition of Tunnel Barriers</h1>.” 2015. Web. 19 Dec 2018.

Vancouver:

Karbasian G. Fabrication of Metallic Single Electron Transistors Featuring Plasma Enhanced Atomic Layer Deposition of Tunnel Barriers</h1>. [Internet] [Doctoral dissertation]. University of Notre Dame; 2015. [cited 2018 Dec 19]. Available from: https://curate.nd.edu/show/bz60cv45s9j.

Council of Science Editors:

Karbasian G. Fabrication of Metallic Single Electron Transistors Featuring Plasma Enhanced Atomic Layer Deposition of Tunnel Barriers</h1>. [Doctoral Dissertation]. University of Notre Dame; 2015. Available from: https://curate.nd.edu/show/bz60cv45s9j

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