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You searched for +publisher:"University of Michigan" +contributor:("Tyson, Gary S."). Showing records 1 – 6 of 6 total matches.

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University of Michigan

1. Lee, Hsien-Hsin Sean. Improving energy and performance of data cache architectures by exploiting memory reference characteristics.

Degree: PhD, Electrical engineering, 2001, University of Michigan

 Minimizing power, increasing performance, and delivering effective memory bandwidth are today's primary microprocessor design goals for the embedded, high-end and multimedia workstation markets. In this… (more)

Subjects/Keywords: Architectures; Characteristics; Data Cache; Energy; Exploiting; Improving; Memory Reference; Microprocessor Caches; Performance; Writeback Policy

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APA (6th Edition):

Lee, H. S. (2001). Improving energy and performance of data cache architectures by exploiting memory reference characteristics. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/127956

Chicago Manual of Style (16th Edition):

Lee, Hsien-Hsin Sean. “Improving energy and performance of data cache architectures by exploiting memory reference characteristics.” 2001. Doctoral Dissertation, University of Michigan. Accessed January 22, 2021. http://hdl.handle.net/2027.42/127956.

MLA Handbook (7th Edition):

Lee, Hsien-Hsin Sean. “Improving energy and performance of data cache architectures by exploiting memory reference characteristics.” 2001. Web. 22 Jan 2021.

Vancouver:

Lee HS. Improving energy and performance of data cache architectures by exploiting memory reference characteristics. [Internet] [Doctoral dissertation]. University of Michigan; 2001. [cited 2021 Jan 22]. Available from: http://hdl.handle.net/2027.42/127956.

Council of Science Editors:

Lee HS. Improving energy and performance of data cache architectures by exploiting memory reference characteristics. [Doctoral Dissertation]. University of Michigan; 2001. Available from: http://hdl.handle.net/2027.42/127956


University of Michigan

2. Srinivasan, Vijayalakshmi. Hardware solutions to reduce effective memory access time.

Degree: PhD, Electrical engineering, 2001, University of Michigan

 In this dissertation, we provide hardware solutions to increase the efficiency of the cache hierarchy, thereby reducing the effective memory access time. Specifically, we focus… (more)

Subjects/Keywords: Branch History Guided; Branch History-guided; Effective; Hardware Prefetch; Memory Access Time; Reduce; Solutions; Split Latency Cache

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APA (6th Edition):

Srinivasan, V. (2001). Hardware solutions to reduce effective memory access time. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/124069

Chicago Manual of Style (16th Edition):

Srinivasan, Vijayalakshmi. “Hardware solutions to reduce effective memory access time.” 2001. Doctoral Dissertation, University of Michigan. Accessed January 22, 2021. http://hdl.handle.net/2027.42/124069.

MLA Handbook (7th Edition):

Srinivasan, Vijayalakshmi. “Hardware solutions to reduce effective memory access time.” 2001. Web. 22 Jan 2021.

Vancouver:

Srinivasan V. Hardware solutions to reduce effective memory access time. [Internet] [Doctoral dissertation]. University of Michigan; 2001. [cited 2021 Jan 22]. Available from: http://hdl.handle.net/2027.42/124069.

Council of Science Editors:

Srinivasan V. Hardware solutions to reduce effective memory access time. [Doctoral Dissertation]. University of Michigan; 2001. Available from: http://hdl.handle.net/2027.42/124069


University of Michigan

3. Rivers, Jude A. Performance aspects of high-bandwidth multi-lateral cache organizations.

Degree: PhD, Computer science, 1998, University of Michigan

 As the issue widths of processors continue to increase, efficient data supply will become ever more critical. Unfortunately, with processor speeds increasing faster than memory… (more)

Subjects/Keywords: Aspects; Bandwidth; Cache; High; Lateral; Management; Multi; Organizations; Performance

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APA (6th Edition):

Rivers, J. A. (1998). Performance aspects of high-bandwidth multi-lateral cache organizations. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/131086

Chicago Manual of Style (16th Edition):

Rivers, Jude A. “Performance aspects of high-bandwidth multi-lateral cache organizations.” 1998. Doctoral Dissertation, University of Michigan. Accessed January 22, 2021. http://hdl.handle.net/2027.42/131086.

MLA Handbook (7th Edition):

Rivers, Jude A. “Performance aspects of high-bandwidth multi-lateral cache organizations.” 1998. Web. 22 Jan 2021.

Vancouver:

Rivers JA. Performance aspects of high-bandwidth multi-lateral cache organizations. [Internet] [Doctoral dissertation]. University of Michigan; 1998. [cited 2021 Jan 22]. Available from: http://hdl.handle.net/2027.42/131086.

Council of Science Editors:

Rivers JA. Performance aspects of high-bandwidth multi-lateral cache organizations. [Doctoral Dissertation]. University of Michigan; 1998. Available from: http://hdl.handle.net/2027.42/131086


University of Michigan

4. Tam, Edward S. Improving cache performance via active management.

Degree: PhD, Electrical engineering, 1999, University of Michigan

 This dissertation analyzes a way to improve cache performance via active management of a target cache space. As microprocessor speeds continue to grow faster than… (more)

Subjects/Keywords: Active Management; Allocation By Conflict; Cache; Improving; Performance; Via

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APA (6th Edition):

Tam, E. S. (1999). Improving cache performance via active management. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/132017

Chicago Manual of Style (16th Edition):

Tam, Edward S. “Improving cache performance via active management.” 1999. Doctoral Dissertation, University of Michigan. Accessed January 22, 2021. http://hdl.handle.net/2027.42/132017.

MLA Handbook (7th Edition):

Tam, Edward S. “Improving cache performance via active management.” 1999. Web. 22 Jan 2021.

Vancouver:

Tam ES. Improving cache performance via active management. [Internet] [Doctoral dissertation]. University of Michigan; 1999. [cited 2021 Jan 22]. Available from: http://hdl.handle.net/2027.42/132017.

Council of Science Editors:

Tam ES. Improving cache performance via active management. [Doctoral Dissertation]. University of Michigan; 1999. Available from: http://hdl.handle.net/2027.42/132017


University of Michigan

5. Geiger, Michael J. Improving performance and energy consumption in region-based caching architectures.

Degree: PhD, Electrical engineering, 2006, University of Michigan

 Embedded systems must simultaneously deliver high performance and low energy consumption. Meeting these goals requires customized designs that fit the requirements of the targeted applications.… (more)

Subjects/Keywords: Architectures; Based; Drowsy Caching; Energy Consumption; Improving; Performance; Prefetching; Region

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APA (6th Edition):

Geiger, M. J. (2006). Improving performance and energy consumption in region-based caching architectures. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/126157

Chicago Manual of Style (16th Edition):

Geiger, Michael J. “Improving performance and energy consumption in region-based caching architectures.” 2006. Doctoral Dissertation, University of Michigan. Accessed January 22, 2021. http://hdl.handle.net/2027.42/126157.

MLA Handbook (7th Edition):

Geiger, Michael J. “Improving performance and energy consumption in region-based caching architectures.” 2006. Web. 22 Jan 2021.

Vancouver:

Geiger MJ. Improving performance and energy consumption in region-based caching architectures. [Internet] [Doctoral dissertation]. University of Michigan; 2006. [cited 2021 Jan 22]. Available from: http://hdl.handle.net/2027.42/126157.

Council of Science Editors:

Geiger MJ. Improving performance and energy consumption in region-based caching architectures. [Doctoral Dissertation]. University of Michigan; 2006. Available from: http://hdl.handle.net/2027.42/126157


University of Michigan

6. Cheng, Allen Chao-Hung. Application-specific architecture framework for high-performance low -power embedded computing.

Degree: PhD, Electrical engineering, 2006, University of Michigan

 The design space of embedded systems is enormously large. These embedded applications have strict requirements on power consumption, performance, cost, and time to market. It… (more)

Subjects/Keywords: Application; Computer Architecture; Embedded Computing; Framework; High; Instruction Sets; Low-power; Microprocessors; Performance; Specific

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APA (6th Edition):

Cheng, A. C. (2006). Application-specific architecture framework for high-performance low -power embedded computing. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/125632

Chicago Manual of Style (16th Edition):

Cheng, Allen Chao-Hung. “Application-specific architecture framework for high-performance low -power embedded computing.” 2006. Doctoral Dissertation, University of Michigan. Accessed January 22, 2021. http://hdl.handle.net/2027.42/125632.

MLA Handbook (7th Edition):

Cheng, Allen Chao-Hung. “Application-specific architecture framework for high-performance low -power embedded computing.” 2006. Web. 22 Jan 2021.

Vancouver:

Cheng AC. Application-specific architecture framework for high-performance low -power embedded computing. [Internet] [Doctoral dissertation]. University of Michigan; 2006. [cited 2021 Jan 22]. Available from: http://hdl.handle.net/2027.42/125632.

Council of Science Editors:

Cheng AC. Application-specific architecture framework for high-performance low -power embedded computing. [Doctoral Dissertation]. University of Michigan; 2006. Available from: http://hdl.handle.net/2027.42/125632

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