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You searched for +publisher:"University of Michigan" +contributor:("Mudge, Trevor N"). Showing records 1 – 30 of 67 total matches.

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University of Michigan

1. Woh, Mark. Architecture and Analysis for Next Generation Mobile Signal Processing.

Degree: PhD, Electrical Engineering, 2011, University of Michigan

 Mobile devices have proliferated at a spectacular rate, with more than 3.3 billion active cell phones in the world. With sales totaling hundreds of billions… (more)

Subjects/Keywords: Computer Architecture; Software Defined Radio; Signal Processing; Embedded Systems; Low Power Computing; SIMD; Electrical Engineering; Engineering

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APA (6th Edition):

Woh, M. (2011). Architecture and Analysis for Next Generation Mobile Signal Processing. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/86344

Chicago Manual of Style (16th Edition):

Woh, Mark. “Architecture and Analysis for Next Generation Mobile Signal Processing.” 2011. Doctoral Dissertation, University of Michigan. Accessed May 07, 2021. http://hdl.handle.net/2027.42/86344.

MLA Handbook (7th Edition):

Woh, Mark. “Architecture and Analysis for Next Generation Mobile Signal Processing.” 2011. Web. 07 May 2021.

Vancouver:

Woh M. Architecture and Analysis for Next Generation Mobile Signal Processing. [Internet] [Doctoral dissertation]. University of Michigan; 2011. [cited 2021 May 07]. Available from: http://hdl.handle.net/2027.42/86344.

Council of Science Editors:

Woh M. Architecture and Analysis for Next Generation Mobile Signal Processing. [Doctoral Dissertation]. University of Michigan; 2011. Available from: http://hdl.handle.net/2027.42/86344


University of Michigan

2. Fojtik, Matthew R. Architecture Independent Timing Speculation Techniques in VLSI Circuits.

Degree: PhD, Electrical Engineering, 2013, University of Michigan

 Conventional digital circuits must ensure correct operation throughout a wide range of operating conditions including process, voltage, and temperature variation. These conditions have an effect… (more)

Subjects/Keywords: VLSI; Digital Circuits; Timing Speculation; Variation Tolerance; Two-Phase Latches; Razor; Electrical Engineering; Engineering

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APA (6th Edition):

Fojtik, M. R. (2013). Architecture Independent Timing Speculation Techniques in VLSI Circuits. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/102461

Chicago Manual of Style (16th Edition):

Fojtik, Matthew R. “Architecture Independent Timing Speculation Techniques in VLSI Circuits.” 2013. Doctoral Dissertation, University of Michigan. Accessed May 07, 2021. http://hdl.handle.net/2027.42/102461.

MLA Handbook (7th Edition):

Fojtik, Matthew R. “Architecture Independent Timing Speculation Techniques in VLSI Circuits.” 2013. Web. 07 May 2021.

Vancouver:

Fojtik MR. Architecture Independent Timing Speculation Techniques in VLSI Circuits. [Internet] [Doctoral dissertation]. University of Michigan; 2013. [cited 2021 May 07]. Available from: http://hdl.handle.net/2027.42/102461.

Council of Science Editors:

Fojtik MR. Architecture Independent Timing Speculation Techniques in VLSI Circuits. [Doctoral Dissertation]. University of Michigan; 2013. Available from: http://hdl.handle.net/2027.42/102461


University of Michigan

3. Kloosterman, John. Data Resource Management in Throughput Processors.

Degree: PhD, Computer Science & Engineering, 2018, University of Michigan

 Graphics Processing Units (GPUs) are becoming common in data centers for tasks like neural network training and image processing due to their high performance and… (more)

Subjects/Keywords: Computer Architecture; Computer Science; Engineering

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APA (6th Edition):

Kloosterman, J. (2018). Data Resource Management in Throughput Processors. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/146122

Chicago Manual of Style (16th Edition):

Kloosterman, John. “Data Resource Management in Throughput Processors.” 2018. Doctoral Dissertation, University of Michigan. Accessed May 07, 2021. http://hdl.handle.net/2027.42/146122.

MLA Handbook (7th Edition):

Kloosterman, John. “Data Resource Management in Throughput Processors.” 2018. Web. 07 May 2021.

Vancouver:

Kloosterman J. Data Resource Management in Throughput Processors. [Internet] [Doctoral dissertation]. University of Michigan; 2018. [cited 2021 May 07]. Available from: http://hdl.handle.net/2027.42/146122.

Council of Science Editors:

Kloosterman J. Data Resource Management in Throughput Processors. [Doctoral Dissertation]. University of Michigan; 2018. Available from: http://hdl.handle.net/2027.42/146122


University of Michigan

4. Lukefahr, Andrew. Composite Cores: Improving Energy Efficiency Through Fine-Grained Heterogeneity.

Degree: PhD, Computer Science & Engineering, 2016, University of Michigan

 From the smartphone to the data center, the world today demands computers that are both responsive and energy-efficient. While Moore’s law has continued to provide… (more)

Subjects/Keywords: fine-grained heterogeneity; microarchitecture; Computer Science; Engineering

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APA (6th Edition):

Lukefahr, A. (2016). Composite Cores: Improving Energy Efficiency Through Fine-Grained Heterogeneity. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/135925

Chicago Manual of Style (16th Edition):

Lukefahr, Andrew. “Composite Cores: Improving Energy Efficiency Through Fine-Grained Heterogeneity.” 2016. Doctoral Dissertation, University of Michigan. Accessed May 07, 2021. http://hdl.handle.net/2027.42/135925.

MLA Handbook (7th Edition):

Lukefahr, Andrew. “Composite Cores: Improving Energy Efficiency Through Fine-Grained Heterogeneity.” 2016. Web. 07 May 2021.

Vancouver:

Lukefahr A. Composite Cores: Improving Energy Efficiency Through Fine-Grained Heterogeneity. [Internet] [Doctoral dissertation]. University of Michigan; 2016. [cited 2021 May 07]. Available from: http://hdl.handle.net/2027.42/135925.

Council of Science Editors:

Lukefahr A. Composite Cores: Improving Energy Efficiency Through Fine-Grained Heterogeneity. [Doctoral Dissertation]. University of Michigan; 2016. Available from: http://hdl.handle.net/2027.42/135925


University of Michigan

5. Jeloka, Supreet. Cross-point Circuits for Computation, Interconnects, Security and Storage.

Degree: PhD, Electrical Engineering, 2017, University of Michigan

 Limited supply-voltage scaling in newer semiconductor technology nodes, has led to an increase in power-density and stagnation of the clock frequency of microprocessors. To overcome… (more)

Subjects/Keywords: Interconnect fabric; Content addressable memory; In-memory compute; Hardware security; Flash memory; Ferroelectric RAM; Electrical Engineering; Engineering

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APA (6th Edition):

Jeloka, S. (2017). Cross-point Circuits for Computation, Interconnects, Security and Storage. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/137048

Chicago Manual of Style (16th Edition):

Jeloka, Supreet. “Cross-point Circuits for Computation, Interconnects, Security and Storage.” 2017. Doctoral Dissertation, University of Michigan. Accessed May 07, 2021. http://hdl.handle.net/2027.42/137048.

MLA Handbook (7th Edition):

Jeloka, Supreet. “Cross-point Circuits for Computation, Interconnects, Security and Storage.” 2017. Web. 07 May 2021.

Vancouver:

Jeloka S. Cross-point Circuits for Computation, Interconnects, Security and Storage. [Internet] [Doctoral dissertation]. University of Michigan; 2017. [cited 2021 May 07]. Available from: http://hdl.handle.net/2027.42/137048.

Council of Science Editors:

Jeloka S. Cross-point Circuits for Computation, Interconnects, Security and Storage. [Doctoral Dissertation]. University of Michigan; 2017. Available from: http://hdl.handle.net/2027.42/137048


University of Michigan

6. Seo, Sangwon. Energy-Efficient Computing for Mobile Signal Processing.

Degree: PhD, Electrical Engineering, 2011, University of Michigan

 Mobile devices have rapidly proliferated, and deployment of handheld devices continues to increase at a spectacular rate. As today's devices not only support advanced signal… (more)

Subjects/Keywords: Near-threshold Computing; SIMD Architecture; Software Defined Radio; Electrical Engineering; Engineering

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APA (6th Edition):

Seo, S. (2011). Energy-Efficient Computing for Mobile Signal Processing. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/86356

Chicago Manual of Style (16th Edition):

Seo, Sangwon. “Energy-Efficient Computing for Mobile Signal Processing.” 2011. Doctoral Dissertation, University of Michigan. Accessed May 07, 2021. http://hdl.handle.net/2027.42/86356.

MLA Handbook (7th Edition):

Seo, Sangwon. “Energy-Efficient Computing for Mobile Signal Processing.” 2011. Web. 07 May 2021.

Vancouver:

Seo S. Energy-Efficient Computing for Mobile Signal Processing. [Internet] [Doctoral dissertation]. University of Michigan; 2011. [cited 2021 May 07]. Available from: http://hdl.handle.net/2027.42/86356.

Council of Science Editors:

Seo S. Energy-Efficient Computing for Mobile Signal Processing. [Doctoral Dissertation]. University of Michigan; 2011. Available from: http://hdl.handle.net/2027.42/86356


University of Michigan

7. Beaumont, Jonathan. Rethinking Context Management of Data Parallel Processors in an Era of Irregular Computing.

Degree: PhD, Computer Science & Engineering, 2019, University of Michigan

 Data parallel architectures such as general purpose GPUs and those using SIMD extensions have become increasingly prevalent in high performance computing due to their power… (more)

Subjects/Keywords: GPU Architecture; Irregular Parallelism; Computer Science; Engineering

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APA (6th Edition):

Beaumont, J. (2019). Rethinking Context Management of Data Parallel Processors in an Era of Irregular Computing. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/153379

Chicago Manual of Style (16th Edition):

Beaumont, Jonathan. “Rethinking Context Management of Data Parallel Processors in an Era of Irregular Computing.” 2019. Doctoral Dissertation, University of Michigan. Accessed May 07, 2021. http://hdl.handle.net/2027.42/153379.

MLA Handbook (7th Edition):

Beaumont, Jonathan. “Rethinking Context Management of Data Parallel Processors in an Era of Irregular Computing.” 2019. Web. 07 May 2021.

Vancouver:

Beaumont J. Rethinking Context Management of Data Parallel Processors in an Era of Irregular Computing. [Internet] [Doctoral dissertation]. University of Michigan; 2019. [cited 2021 May 07]. Available from: http://hdl.handle.net/2027.42/153379.

Council of Science Editors:

Beaumont J. Rethinking Context Management of Data Parallel Processors in an Era of Irregular Computing. [Doctoral Dissertation]. University of Michigan; 2019. Available from: http://hdl.handle.net/2027.42/153379


University of Michigan

8. Sethia, Ankit. Dynamic Hardware Resource Management for Efficient Throughput Processing.

Degree: PhD, Computer Science and Engineering, 2015, University of Michigan

 High performance computing is evolving at a rapid pace, with throughput oriented processors such as graphics processing units (GPUs), substituting for traditional processors as the… (more)

Subjects/Keywords: GPGPU Computing; Runtime Resource Management; Throughput Processing; GPU DVFS; GPU Warp Scheduling; GPU Prefetching; Computer Science; Engineering

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APA (6th Edition):

Sethia, A. (2015). Dynamic Hardware Resource Management for Efficient Throughput Processing. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/113356

Chicago Manual of Style (16th Edition):

Sethia, Ankit. “Dynamic Hardware Resource Management for Efficient Throughput Processing.” 2015. Doctoral Dissertation, University of Michigan. Accessed May 07, 2021. http://hdl.handle.net/2027.42/113356.

MLA Handbook (7th Edition):

Sethia, Ankit. “Dynamic Hardware Resource Management for Efficient Throughput Processing.” 2015. Web. 07 May 2021.

Vancouver:

Sethia A. Dynamic Hardware Resource Management for Efficient Throughput Processing. [Internet] [Doctoral dissertation]. University of Michigan; 2015. [cited 2021 May 07]. Available from: http://hdl.handle.net/2027.42/113356.

Council of Science Editors:

Sethia A. Dynamic Hardware Resource Management for Efficient Throughput Processing. [Doctoral Dissertation]. University of Michigan; 2015. Available from: http://hdl.handle.net/2027.42/113356


University of Michigan

9. Pinckney, Nathaniel Ross. Near-Threshold Computing: Past, Present, and Future.

Degree: PhD, Electrical Engineering, 2015, University of Michigan

 Transistor threshold voltages have stagnated in recent years, deviating from constant-voltage scaling theory and directly limiting supply voltage scaling. To overcome the resulting energy and… (more)

Subjects/Keywords: Near Threshold Computing; Energy Efficiency; Low Power; Voltage Boosting; Electrical Engineering; Engineering

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APA (6th Edition):

Pinckney, N. R. (2015). Near-Threshold Computing: Past, Present, and Future. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/113600

Chicago Manual of Style (16th Edition):

Pinckney, Nathaniel Ross. “Near-Threshold Computing: Past, Present, and Future.” 2015. Doctoral Dissertation, University of Michigan. Accessed May 07, 2021. http://hdl.handle.net/2027.42/113600.

MLA Handbook (7th Edition):

Pinckney, Nathaniel Ross. “Near-Threshold Computing: Past, Present, and Future.” 2015. Web. 07 May 2021.

Vancouver:

Pinckney NR. Near-Threshold Computing: Past, Present, and Future. [Internet] [Doctoral dissertation]. University of Michigan; 2015. [cited 2021 May 07]. Available from: http://hdl.handle.net/2027.42/113600.

Council of Science Editors:

Pinckney NR. Near-Threshold Computing: Past, Present, and Future. [Doctoral Dissertation]. University of Michigan; 2015. Available from: http://hdl.handle.net/2027.42/113600


University of Michigan

10. Gao, Cao. Heterogeneous Mobile Platform Characterization and Accelerator Design.

Degree: PhD, Computer Science & Engineering, 2017, University of Michigan

 Lysosomes play an active role in sensing, signaling, and responding to nutrient availability, in addition to their well-established role in degradation. Lysosomes undergo multifaceted changes… (more)

Subjects/Keywords: Computer Architecture; Mobile Platform; Computer Science; Electrical Engineering; Engineering

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APA (6th Edition):

Gao, C. (2017). Heterogeneous Mobile Platform Characterization and Accelerator Design. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/138799

Chicago Manual of Style (16th Edition):

Gao, Cao. “Heterogeneous Mobile Platform Characterization and Accelerator Design.” 2017. Doctoral Dissertation, University of Michigan. Accessed May 07, 2021. http://hdl.handle.net/2027.42/138799.

MLA Handbook (7th Edition):

Gao, Cao. “Heterogeneous Mobile Platform Characterization and Accelerator Design.” 2017. Web. 07 May 2021.

Vancouver:

Gao C. Heterogeneous Mobile Platform Characterization and Accelerator Design. [Internet] [Doctoral dissertation]. University of Michigan; 2017. [cited 2021 May 07]. Available from: http://hdl.handle.net/2027.42/138799.

Council of Science Editors:

Gao C. Heterogeneous Mobile Platform Characterization and Accelerator Design. [Doctoral Dissertation]. University of Michigan; 2017. Available from: http://hdl.handle.net/2027.42/138799


University of Michigan

11. Zheng, Qi. Datacenter Design for Future Cloud Radio Access Network.

Degree: PhD, Computer Science and Engineering, 2016, University of Michigan

 Cloud radio access network (C-RAN), an emerging cloud service that combines the traditional radio access network (RAN) with cloud computing technology, has been proposed as… (more)

Subjects/Keywords: Cloud radio access network; Datacenter design; GPU; Resource management; Computer Science; Engineering

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APA (6th Edition):

Zheng, Q. (2016). Datacenter Design for Future Cloud Radio Access Network. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/120825

Chicago Manual of Style (16th Edition):

Zheng, Qi. “Datacenter Design for Future Cloud Radio Access Network.” 2016. Doctoral Dissertation, University of Michigan. Accessed May 07, 2021. http://hdl.handle.net/2027.42/120825.

MLA Handbook (7th Edition):

Zheng, Qi. “Datacenter Design for Future Cloud Radio Access Network.” 2016. Web. 07 May 2021.

Vancouver:

Zheng Q. Datacenter Design for Future Cloud Radio Access Network. [Internet] [Doctoral dissertation]. University of Michigan; 2016. [cited 2021 May 07]. Available from: http://hdl.handle.net/2027.42/120825.

Council of Science Editors:

Zheng Q. Datacenter Design for Future Cloud Radio Access Network. [Doctoral Dissertation]. University of Michigan; 2016. Available from: http://hdl.handle.net/2027.42/120825


University of Michigan

12. Lu, Shengshuo. Secure and Energy-Efficient Processors.

Degree: PhD, Electrical Engineering, 2017, University of Michigan

 Security has become an essential part of digital information storage and processing. Both high-end and low-end applications, such as data centers and Internet of Things… (more)

Subjects/Keywords: Energy efficient ASICs; Advanced Encryption Standard (AES); Side channel attacks; Differential Power Analysis (DPA); Charge recovery logic; Electrical Engineering; Engineering

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APA (6th Edition):

Lu, S. (2017). Secure and Energy-Efficient Processors. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/138791

Chicago Manual of Style (16th Edition):

Lu, Shengshuo. “Secure and Energy-Efficient Processors.” 2017. Doctoral Dissertation, University of Michigan. Accessed May 07, 2021. http://hdl.handle.net/2027.42/138791.

MLA Handbook (7th Edition):

Lu, Shengshuo. “Secure and Energy-Efficient Processors.” 2017. Web. 07 May 2021.

Vancouver:

Lu S. Secure and Energy-Efficient Processors. [Internet] [Doctoral dissertation]. University of Michigan; 2017. [cited 2021 May 07]. Available from: http://hdl.handle.net/2027.42/138791.

Council of Science Editors:

Lu S. Secure and Energy-Efficient Processors. [Doctoral Dissertation]. University of Michigan; 2017. Available from: http://hdl.handle.net/2027.42/138791


University of Michigan

13. Feng, Shuguang. Delivering Affordable Fault-tolerance to Commodity Computer Systems.

Degree: PhD, Computer Science & Engineering, 2011, University of Michigan

 To meet an insatiable consumer demand for greater performance at less power, silicon technology has scaled to unprecedented dimensions. This aggressive scaling has provided designers… (more)

Subjects/Keywords: Fault Tolerant Computing; Computer Architecture; Compiler Analysis; Computer Science; Electrical Engineering; Engineering

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APA (6th Edition):

Feng, S. (2011). Delivering Affordable Fault-tolerance to Commodity Computer Systems. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/86483

Chicago Manual of Style (16th Edition):

Feng, Shuguang. “Delivering Affordable Fault-tolerance to Commodity Computer Systems.” 2011. Doctoral Dissertation, University of Michigan. Accessed May 07, 2021. http://hdl.handle.net/2027.42/86483.

MLA Handbook (7th Edition):

Feng, Shuguang. “Delivering Affordable Fault-tolerance to Commodity Computer Systems.” 2011. Web. 07 May 2021.

Vancouver:

Feng S. Delivering Affordable Fault-tolerance to Commodity Computer Systems. [Internet] [Doctoral dissertation]. University of Michigan; 2011. [cited 2021 May 07]. Available from: http://hdl.handle.net/2027.42/86483.

Council of Science Editors:

Feng S. Delivering Affordable Fault-tolerance to Commodity Computer Systems. [Doctoral Dissertation]. University of Michigan; 2011. Available from: http://hdl.handle.net/2027.42/86483


University of Michigan

14. Wu, Hsi-Shou. Energy-Efficient Neural Network Architectures.

Degree: PhD, Electrical and Computer Engineering, 2018, University of Michigan

 Emerging systems for artificial intelligence (AI) are expected to rely on deep neural networks (DNNs) to achieve high accuracy for a broad variety of applications,… (more)

Subjects/Keywords: Computer Architecture; Energy-Efficient Computing; Neural Networks; Machine Learning; Image and Audio Processing; VLSI Design; Electrical Engineering; Engineering

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APA (6th Edition):

Wu, H. (2018). Energy-Efficient Neural Network Architectures. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/147614

Chicago Manual of Style (16th Edition):

Wu, Hsi-Shou. “Energy-Efficient Neural Network Architectures.” 2018. Doctoral Dissertation, University of Michigan. Accessed May 07, 2021. http://hdl.handle.net/2027.42/147614.

MLA Handbook (7th Edition):

Wu, Hsi-Shou. “Energy-Efficient Neural Network Architectures.” 2018. Web. 07 May 2021.

Vancouver:

Wu H. Energy-Efficient Neural Network Architectures. [Internet] [Doctoral dissertation]. University of Michigan; 2018. [cited 2021 May 07]. Available from: http://hdl.handle.net/2027.42/147614.

Council of Science Editors:

Wu H. Energy-Efficient Neural Network Architectures. [Doctoral Dissertation]. University of Michigan; 2018. Available from: http://hdl.handle.net/2027.42/147614


University of Michigan

15. Lee, Hyunseok. A baseband processor for software defined radio terminals.

Degree: PhD, Computer science, 2007, University of Michigan

 Software defined radio (SDR) is a technical effort to use programmable hardware in wireless communication systems so that various protocols can be easily supported by… (more)

Subjects/Keywords: Baseband; Processor; Radio Terminals; Software-defined Radio

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APA (6th Edition):

Lee, H. (2007). A baseband processor for software defined radio terminals. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/126758

Chicago Manual of Style (16th Edition):

Lee, Hyunseok. “A baseband processor for software defined radio terminals.” 2007. Doctoral Dissertation, University of Michigan. Accessed May 07, 2021. http://hdl.handle.net/2027.42/126758.

MLA Handbook (7th Edition):

Lee, Hyunseok. “A baseband processor for software defined radio terminals.” 2007. Web. 07 May 2021.

Vancouver:

Lee H. A baseband processor for software defined radio terminals. [Internet] [Doctoral dissertation]. University of Michigan; 2007. [cited 2021 May 07]. Available from: http://hdl.handle.net/2027.42/126758.

Council of Science Editors:

Lee H. A baseband processor for software defined radio terminals. [Doctoral Dissertation]. University of Michigan; 2007. Available from: http://hdl.handle.net/2027.42/126758


University of Michigan

16. Kaiser, Dan Richard. Loop optimization techniques on multi-issue architectures.

Degree: PhD, Computer science, 1995, University of Michigan

 This work examines the interaction of compiler scheduling techniques with processor features such as the instruction issue policy. Scheduling techniques designed to exploit instruction level… (more)

Subjects/Keywords: Architectures; Issue; Loop; Multi; Optimization; Techniques

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APA (6th Edition):

Kaiser, D. R. (1995). Loop optimization techniques on multi-issue architectures. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/129534

Chicago Manual of Style (16th Edition):

Kaiser, Dan Richard. “Loop optimization techniques on multi-issue architectures.” 1995. Doctoral Dissertation, University of Michigan. Accessed May 07, 2021. http://hdl.handle.net/2027.42/129534.

MLA Handbook (7th Edition):

Kaiser, Dan Richard. “Loop optimization techniques on multi-issue architectures.” 1995. Web. 07 May 2021.

Vancouver:

Kaiser DR. Loop optimization techniques on multi-issue architectures. [Internet] [Doctoral dissertation]. University of Michigan; 1995. [cited 2021 May 07]. Available from: http://hdl.handle.net/2027.42/129534.

Council of Science Editors:

Kaiser DR. Loop optimization techniques on multi-issue architectures. [Doctoral Dissertation]. University of Michigan; 1995. Available from: http://hdl.handle.net/2027.42/129534


University of Michigan

17. Olukotun, Oyekunle Ayinde. Technology-organization tradeoffs in the architecture of a high-performance processor.

Degree: PhD, Electrical engineering, 1991, University of Michigan

 To design computers which reach the performance limits of the implementation technology, one must understand the relationships between the technology and organization of the processor.… (more)

Subjects/Keywords: Architecture; High; Microprocessor; Organization; Performance; Process; Processor; Technology; Tradeoffs

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APA (6th Edition):

Olukotun, O. A. (1991). Technology-organization tradeoffs in the architecture of a high-performance processor. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/128829

Chicago Manual of Style (16th Edition):

Olukotun, Oyekunle Ayinde. “Technology-organization tradeoffs in the architecture of a high-performance processor.” 1991. Doctoral Dissertation, University of Michigan. Accessed May 07, 2021. http://hdl.handle.net/2027.42/128829.

MLA Handbook (7th Edition):

Olukotun, Oyekunle Ayinde. “Technology-organization tradeoffs in the architecture of a high-performance processor.” 1991. Web. 07 May 2021.

Vancouver:

Olukotun OA. Technology-organization tradeoffs in the architecture of a high-performance processor. [Internet] [Doctoral dissertation]. University of Michigan; 1991. [cited 2021 May 07]. Available from: http://hdl.handle.net/2027.42/128829.

Council of Science Editors:

Olukotun OA. Technology-organization tradeoffs in the architecture of a high-performance processor. [Doctoral Dissertation]. University of Michigan; 1991. Available from: http://hdl.handle.net/2027.42/128829


University of Michigan

18. Clapp, Russell Mace. Run-time support for parallel programs.

Degree: PhD, Computer science, 1991, University of Michigan

 The emergence of commercial multiprocessors has prompted computer scientists to take a closer look at parallel programming. Apart from the intrinsic limitations to parallelism imposed… (more)

Subjects/Keywords: Parallel; Programs; Run; Support; Time

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APA (6th Edition):

Clapp, R. M. (1991). Run-time support for parallel programs. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/128743

Chicago Manual of Style (16th Edition):

Clapp, Russell Mace. “Run-time support for parallel programs.” 1991. Doctoral Dissertation, University of Michigan. Accessed May 07, 2021. http://hdl.handle.net/2027.42/128743.

MLA Handbook (7th Edition):

Clapp, Russell Mace. “Run-time support for parallel programs.” 1991. Web. 07 May 2021.

Vancouver:

Clapp RM. Run-time support for parallel programs. [Internet] [Doctoral dissertation]. University of Michigan; 1991. [cited 2021 May 07]. Available from: http://hdl.handle.net/2027.42/128743.

Council of Science Editors:

Clapp RM. Run-time support for parallel programs. [Doctoral Dissertation]. University of Michigan; 1991. Available from: http://hdl.handle.net/2027.42/128743


University of Michigan

19. Eden, Avinoam Nomik. Of limits and myths in branch prediction.

Degree: PhD, Electrical engineering, 2001, University of Michigan

 The need to flush pipelines when miss-predicting branches occur can throttle the performance of a pipelined super-scalar microprocessor. It is argued that by the year… (more)

Subjects/Keywords: Aliasing; Branch Prediction; Hybrid Predictors; Limits; Myths

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APA (6th Edition):

Eden, A. N. (2001). Of limits and myths in branch prediction. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/125179

Chicago Manual of Style (16th Edition):

Eden, Avinoam Nomik. “Of limits and myths in branch prediction.” 2001. Doctoral Dissertation, University of Michigan. Accessed May 07, 2021. http://hdl.handle.net/2027.42/125179.

MLA Handbook (7th Edition):

Eden, Avinoam Nomik. “Of limits and myths in branch prediction.” 2001. Web. 07 May 2021.

Vancouver:

Eden AN. Of limits and myths in branch prediction. [Internet] [Doctoral dissertation]. University of Michigan; 2001. [cited 2021 May 07]. Available from: http://hdl.handle.net/2027.42/125179.

Council of Science Editors:

Eden AN. Of limits and myths in branch prediction. [Doctoral Dissertation]. University of Michigan; 2001. Available from: http://hdl.handle.net/2027.42/125179


University of Michigan

20. Oehmke, David W. Virtualizing register context.

Degree: PhD, Computer science, 2005, University of Michigan

 A processor designer may wish for an implementation to support multiple register contexts for several reasons: to support multithreading, to reduce context switch overhead, or… (more)

Subjects/Keywords: Compilers; Computer Architecture; Context; Register; Virtualizing

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APA (6th Edition):

Oehmke, D. W. (2005). Virtualizing register context. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/125175

Chicago Manual of Style (16th Edition):

Oehmke, David W. “Virtualizing register context.” 2005. Doctoral Dissertation, University of Michigan. Accessed May 07, 2021. http://hdl.handle.net/2027.42/125175.

MLA Handbook (7th Edition):

Oehmke, David W. “Virtualizing register context.” 2005. Web. 07 May 2021.

Vancouver:

Oehmke DW. Virtualizing register context. [Internet] [Doctoral dissertation]. University of Michigan; 2005. [cited 2021 May 07]. Available from: http://hdl.handle.net/2027.42/125175.

Council of Science Editors:

Oehmke DW. Virtualizing register context. [Doctoral Dissertation]. University of Michigan; 2005. Available from: http://hdl.handle.net/2027.42/125175


University of Michigan

21. Golden, Michael Leonard. Reducing the penalty of branch and load hazards in pipelined microprocessors.

Degree: PhD, Computer science, 1995, University of Michigan

 Pipelined microprocessors allow the simultaneous execution of several machine instructions at a time, increasing the total throughput of instructions. Because an instruction being executed by… (more)

Subjects/Keywords: Branch Instructions; Hazards; Load; Microprocessors; Penalty; Pipelined; Reducing

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APA (6th Edition):

Golden, M. L. (1995). Reducing the penalty of branch and load hazards in pipelined microprocessors. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/129692

Chicago Manual of Style (16th Edition):

Golden, Michael Leonard. “Reducing the penalty of branch and load hazards in pipelined microprocessors.” 1995. Doctoral Dissertation, University of Michigan. Accessed May 07, 2021. http://hdl.handle.net/2027.42/129692.

MLA Handbook (7th Edition):

Golden, Michael Leonard. “Reducing the penalty of branch and load hazards in pipelined microprocessors.” 1995. Web. 07 May 2021.

Vancouver:

Golden ML. Reducing the penalty of branch and load hazards in pipelined microprocessors. [Internet] [Doctoral dissertation]. University of Michigan; 1995. [cited 2021 May 07]. Available from: http://hdl.handle.net/2027.42/129692.

Council of Science Editors:

Golden ML. Reducing the penalty of branch and load hazards in pipelined microprocessors. [Doctoral Dissertation]. University of Michigan; 1995. Available from: http://hdl.handle.net/2027.42/129692


University of Michigan

22. Kim, Nam Sung. Circuit and microarchitectural techniques for processor on -chip cache leakage power reduction.

Degree: PhD, Electrical engineering, 2004, University of Michigan

 On-chip L1 and L2 caches dissipate a sizeable fraction of the total power of processors. As feature sizes shrink and threshold voltages decrease, sub-threshold leakage… (more)

Subjects/Keywords: Circuit; Low-leakage; Microarchitectural; On-chip Cache; Power Reduction; Processor; Techniques

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APA (6th Edition):

Kim, N. S. (2004). Circuit and microarchitectural techniques for processor on -chip cache leakage power reduction. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/124100

Chicago Manual of Style (16th Edition):

Kim, Nam Sung. “Circuit and microarchitectural techniques for processor on -chip cache leakage power reduction.” 2004. Doctoral Dissertation, University of Michigan. Accessed May 07, 2021. http://hdl.handle.net/2027.42/124100.

MLA Handbook (7th Edition):

Kim, Nam Sung. “Circuit and microarchitectural techniques for processor on -chip cache leakage power reduction.” 2004. Web. 07 May 2021.

Vancouver:

Kim NS. Circuit and microarchitectural techniques for processor on -chip cache leakage power reduction. [Internet] [Doctoral dissertation]. University of Michigan; 2004. [cited 2021 May 07]. Available from: http://hdl.handle.net/2027.42/124100.

Council of Science Editors:

Kim NS. Circuit and microarchitectural techniques for processor on -chip cache leakage power reduction. [Doctoral Dissertation]. University of Michigan; 2004. Available from: http://hdl.handle.net/2027.42/124100

23. Blake, Geoffrey Wyman. A Hardware/Software Approach for Alleviating Scalability Bottlenecks in Transactional Memory Applications.

Degree: PhD, Computer Science & Engineering, 2011, University of Michigan

 Scaling processor performance with future technology nodes is essential to enable future applications for devices ranging from smart-phones to servers. But the traditional methods of… (more)

Subjects/Keywords: Hardware Transactional Memory; Scheduling; Chip Multi-processors; Computer Science; Engineering

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APA (6th Edition):

Blake, G. W. (2011). A Hardware/Software Approach for Alleviating Scalability Bottlenecks in Transactional Memory Applications. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/86452

Chicago Manual of Style (16th Edition):

Blake, Geoffrey Wyman. “A Hardware/Software Approach for Alleviating Scalability Bottlenecks in Transactional Memory Applications.” 2011. Doctoral Dissertation, University of Michigan. Accessed May 07, 2021. http://hdl.handle.net/2027.42/86452.

MLA Handbook (7th Edition):

Blake, Geoffrey Wyman. “A Hardware/Software Approach for Alleviating Scalability Bottlenecks in Transactional Memory Applications.” 2011. Web. 07 May 2021.

Vancouver:

Blake GW. A Hardware/Software Approach for Alleviating Scalability Bottlenecks in Transactional Memory Applications. [Internet] [Doctoral dissertation]. University of Michigan; 2011. [cited 2021 May 07]. Available from: http://hdl.handle.net/2027.42/86452.

Council of Science Editors:

Blake GW. A Hardware/Software Approach for Alleviating Scalability Bottlenecks in Transactional Memory Applications. [Doctoral Dissertation]. University of Michigan; 2011. Available from: http://hdl.handle.net/2027.42/86452

24. Ringenberg, Jeffrey Stuart. The Fast, Efficient, and Representative Benchmarking of Future Microarchitectures.

Degree: PhD, Computer Science & Engineering, 2008, University of Michigan

 A methodology is introduced to reduce the overall simulation time of large benchmarking suites. Previous work shows that it is possible to simulate only small… (more)

Subjects/Keywords: Benchmarking; Performance Analysis; Microprocessor Design; Computer Science; Electrical Engineering; Engineering

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APA (6th Edition):

Ringenberg, J. S. (2008). The Fast, Efficient, and Representative Benchmarking of Future Microarchitectures. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/60726

Chicago Manual of Style (16th Edition):

Ringenberg, Jeffrey Stuart. “The Fast, Efficient, and Representative Benchmarking of Future Microarchitectures.” 2008. Doctoral Dissertation, University of Michigan. Accessed May 07, 2021. http://hdl.handle.net/2027.42/60726.

MLA Handbook (7th Edition):

Ringenberg, Jeffrey Stuart. “The Fast, Efficient, and Representative Benchmarking of Future Microarchitectures.” 2008. Web. 07 May 2021.

Vancouver:

Ringenberg JS. The Fast, Efficient, and Representative Benchmarking of Future Microarchitectures. [Internet] [Doctoral dissertation]. University of Michigan; 2008. [cited 2021 May 07]. Available from: http://hdl.handle.net/2027.42/60726.

Council of Science Editors:

Ringenberg JS. The Fast, Efficient, and Representative Benchmarking of Future Microarchitectures. [Doctoral Dissertation]. University of Michigan; 2008. Available from: http://hdl.handle.net/2027.42/60726

25. Dasika, Ganesh Suryanarayan. Power-Efficient Accelerators for High-Performance Applications.

Degree: PhD, Computer Science & Engineering, 2011, University of Michigan

 Computers, regardless of their function, are always better if they can operate more quickly. The addition of computation resources allows for improved response times, greater… (more)

Subjects/Keywords: High-performance Computing; Low-power Computing; Power-efficient Computing; SIMD Architectures; Streaming Architectures; Application-specific Processors; Computer Science; Electrical Engineering; Engineering

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APA (6th Edition):

Dasika, G. S. (2011). Power-Efficient Accelerators for High-Performance Applications. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/86478

Chicago Manual of Style (16th Edition):

Dasika, Ganesh Suryanarayan. “Power-Efficient Accelerators for High-Performance Applications.” 2011. Doctoral Dissertation, University of Michigan. Accessed May 07, 2021. http://hdl.handle.net/2027.42/86478.

MLA Handbook (7th Edition):

Dasika, Ganesh Suryanarayan. “Power-Efficient Accelerators for High-Performance Applications.” 2011. Web. 07 May 2021.

Vancouver:

Dasika GS. Power-Efficient Accelerators for High-Performance Applications. [Internet] [Doctoral dissertation]. University of Michigan; 2011. [cited 2021 May 07]. Available from: http://hdl.handle.net/2027.42/86478.

Council of Science Editors:

Dasika GS. Power-Efficient Accelerators for High-Performance Applications. [Doctoral Dissertation]. University of Michigan; 2011. Available from: http://hdl.handle.net/2027.42/86478

26. Kim, Daeyeon. Design and Analysis of Robust Low Voltage Static Random Access Memories.

Degree: PhD, Electrical Engineering, 2012, University of Michigan

 Static Random Access Memory (SRAM) is an indispensable part of most modern VLSI designs and dominates silicon area in many applications. In scaled technologies, maintaining… (more)

Subjects/Keywords: SRAM; Low Power; VLSI; Digital Circuit; Electrical Engineering; Engineering

…sensor application developed by University of Michigan also spends about 50% of its area for… …Photo of University of Michigan 0.18µm Sensor System [11] 5 Solution Power… 

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APA (6th Edition):

Kim, D. (2012). Design and Analysis of Robust Low Voltage Static Random Access Memories. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/91569

Chicago Manual of Style (16th Edition):

Kim, Daeyeon. “Design and Analysis of Robust Low Voltage Static Random Access Memories.” 2012. Doctoral Dissertation, University of Michigan. Accessed May 07, 2021. http://hdl.handle.net/2027.42/91569.

MLA Handbook (7th Edition):

Kim, Daeyeon. “Design and Analysis of Robust Low Voltage Static Random Access Memories.” 2012. Web. 07 May 2021.

Vancouver:

Kim D. Design and Analysis of Robust Low Voltage Static Random Access Memories. [Internet] [Doctoral dissertation]. University of Michigan; 2012. [cited 2021 May 07]. Available from: http://hdl.handle.net/2027.42/91569.

Council of Science Editors:

Kim D. Design and Analysis of Robust Low Voltage Static Random Access Memories. [Doctoral Dissertation]. University of Michigan; 2012. Available from: http://hdl.handle.net/2027.42/91569

27. Oh, Byoungchan. Architecting Memory Systems for Emerging Technologies.

Degree: PhD, Electrical Engineering, 2018, University of Michigan

 The advance of traditional dynamic random access memory (DRAM) technology has slowed down, while the capacity and performance needs of memory system have continued to… (more)

Subjects/Keywords: Memory System; Computer Architecture; Electrical Engineering; Engineering

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APA (6th Edition):

Oh, B. (2018). Architecting Memory Systems for Emerging Technologies. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/145988

Chicago Manual of Style (16th Edition):

Oh, Byoungchan. “Architecting Memory Systems for Emerging Technologies.” 2018. Doctoral Dissertation, University of Michigan. Accessed May 07, 2021. http://hdl.handle.net/2027.42/145988.

MLA Handbook (7th Edition):

Oh, Byoungchan. “Architecting Memory Systems for Emerging Technologies.” 2018. Web. 07 May 2021.

Vancouver:

Oh B. Architecting Memory Systems for Emerging Technologies. [Internet] [Doctoral dissertation]. University of Michigan; 2018. [cited 2021 May 07]. Available from: http://hdl.handle.net/2027.42/145988.

Council of Science Editors:

Oh B. Architecting Memory Systems for Emerging Technologies. [Doctoral Dissertation]. University of Michigan; 2018. Available from: http://hdl.handle.net/2027.42/145988

28. Park, Youn Sung. Energy-Efficient Decoders of Near-Capacity Channel Codes.

Degree: PhD, Electrical Engineering, 2014, University of Michigan

 Channel coding has become essential in state-of-the-art communication and storage systems for ensuring reliable transmission and storage of information. Their goal is to achieve high… (more)

Subjects/Keywords: Energy-Efficient Decoders of Near-Capacity Channel Codes; Low-Power High-Throughput LDPC Decoder Using Non-Refresh Embedded DRAM; A Fully Parallel Nonbinary LDPC Decoder With Fine-Grained Dynamic Clock Gating; A Belief Propagation Polar Decoder With Bit-Splitting Register File; Electrical Engineering; Engineering

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APA (6th Edition):

Park, Y. S. (2014). Energy-Efficient Decoders of Near-Capacity Channel Codes. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/108731

Chicago Manual of Style (16th Edition):

Park, Youn Sung. “Energy-Efficient Decoders of Near-Capacity Channel Codes.” 2014. Doctoral Dissertation, University of Michigan. Accessed May 07, 2021. http://hdl.handle.net/2027.42/108731.

MLA Handbook (7th Edition):

Park, Youn Sung. “Energy-Efficient Decoders of Near-Capacity Channel Codes.” 2014. Web. 07 May 2021.

Vancouver:

Park YS. Energy-Efficient Decoders of Near-Capacity Channel Codes. [Internet] [Doctoral dissertation]. University of Michigan; 2014. [cited 2021 May 07]. Available from: http://hdl.handle.net/2027.42/108731.

Council of Science Editors:

Park YS. Energy-Efficient Decoders of Near-Capacity Channel Codes. [Doctoral Dissertation]. University of Michigan; 2014. Available from: http://hdl.handle.net/2027.42/108731

29. Kang, Yiping. From Compute to Data: Across-the-Stack System Design for Intelligent Applications.

Degree: PhD, Computer Science & Engineering, 2018, University of Michigan

 Intelligent applications such as Apple Siri, Google Assistant and Amazon Alexa have gained tremendous popularity in recent years. With human-like understanding capabilities and natural language… (more)

Subjects/Keywords: System Design; Intelligent Application; Datacenter; Machine Learning; Data Collection; Mobile Computation; Computer Science; Engineering

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APA (6th Edition):

Kang, Y. (2018). From Compute to Data: Across-the-Stack System Design for Intelligent Applications. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/145886

Chicago Manual of Style (16th Edition):

Kang, Yiping. “From Compute to Data: Across-the-Stack System Design for Intelligent Applications.” 2018. Doctoral Dissertation, University of Michigan. Accessed May 07, 2021. http://hdl.handle.net/2027.42/145886.

MLA Handbook (7th Edition):

Kang, Yiping. “From Compute to Data: Across-the-Stack System Design for Intelligent Applications.” 2018. Web. 07 May 2021.

Vancouver:

Kang Y. From Compute to Data: Across-the-Stack System Design for Intelligent Applications. [Internet] [Doctoral dissertation]. University of Michigan; 2018. [cited 2021 May 07]. Available from: http://hdl.handle.net/2027.42/145886.

Council of Science Editors:

Kang Y. From Compute to Data: Across-the-Stack System Design for Intelligent Applications. [Doctoral Dissertation]. University of Michigan; 2018. Available from: http://hdl.handle.net/2027.42/145886

30. Kim, Jaeyoung. Ultra Low-power Wireless Sensor Node Design for ECG Sensing Applications.

Degree: PhD, Electrical Engineering, 2017, University of Michigan

 Ubiquitous computing, such as smart homes, smart cars, and smart grid, connects our world closely so that we can easily access to the world through… (more)

Subjects/Keywords: Body sensor networks; Low-power electronics; Wireless sensor networks; Electrical Engineering; Engineering

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APA (6th Edition):

Kim, J. (2017). Ultra Low-power Wireless Sensor Node Design for ECG Sensing Applications. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/137081

Chicago Manual of Style (16th Edition):

Kim, Jaeyoung. “Ultra Low-power Wireless Sensor Node Design for ECG Sensing Applications.” 2017. Doctoral Dissertation, University of Michigan. Accessed May 07, 2021. http://hdl.handle.net/2027.42/137081.

MLA Handbook (7th Edition):

Kim, Jaeyoung. “Ultra Low-power Wireless Sensor Node Design for ECG Sensing Applications.” 2017. Web. 07 May 2021.

Vancouver:

Kim J. Ultra Low-power Wireless Sensor Node Design for ECG Sensing Applications. [Internet] [Doctoral dissertation]. University of Michigan; 2017. [cited 2021 May 07]. Available from: http://hdl.handle.net/2027.42/137081.

Council of Science Editors:

Kim J. Ultra Low-power Wireless Sensor Node Design for ECG Sensing Applications. [Doctoral Dissertation]. University of Michigan; 2017. Available from: http://hdl.handle.net/2027.42/137081

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