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You searched for +publisher:"University of Michigan" +contributor:("Markov, Igor L."). Showing records 1 – 23 of 23 total matches.

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University of Michigan

1. Alaghi, Armin. The Logic of Random Pulses: Stochastic Computing.

Degree: PhD, Computer Science and Engineering, 2015, University of Michigan

 Recent developments in the field of electronics have produced nano-scale devices whose operation can only be described in probabilistic terms. In contrast with the conventional… (more)

Subjects/Keywords: Stochastic computing; Logic design; Approximate computing; Embedded signal processing; Computer Science; Electrical Engineering; Engineering

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APA (6th Edition):

Alaghi, A. (2015). The Logic of Random Pulses: Stochastic Computing. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/113561

Chicago Manual of Style (16th Edition):

Alaghi, Armin. “The Logic of Random Pulses: Stochastic Computing.” 2015. Doctoral Dissertation, University of Michigan. Accessed December 12, 2019. http://hdl.handle.net/2027.42/113561.

MLA Handbook (7th Edition):

Alaghi, Armin. “The Logic of Random Pulses: Stochastic Computing.” 2015. Web. 12 Dec 2019.

Vancouver:

Alaghi A. The Logic of Random Pulses: Stochastic Computing. [Internet] [Doctoral dissertation]. University of Michigan; 2015. [cited 2019 Dec 12]. Available from: http://hdl.handle.net/2027.42/113561.

Council of Science Editors:

Alaghi A. The Logic of Random Pulses: Stochastic Computing. [Doctoral Dissertation]. University of Michigan; 2015. Available from: http://hdl.handle.net/2027.42/113561


University of Michigan

2. Garcia-Ramirez, Hector J. Hybrid Techniques for Simulating Quantum Circuits using the Heisenberg Representation.

Degree: PhD, Computer Science and Engineering, 2014, University of Michigan

 Simulation of quantum information processing remains a major challenge with important applications in quantum computer science and engineering. Generic quantum-circuit simulation appears intractable for conventional… (more)

Subjects/Keywords: Quantum-circuit Simulation; Stabilizer-based Simulation of Generic Quantum Circuits; Stabilizer Frames, Multiframes and P-blocked Multiframes; Pauli Decision Diagrams and Matrix Product Multivalued Decision Diagrams; Metric and Computational Geometry of Stabilizer States; Heisenberg Representation for Quantum Computers; Computer Science; Engineering

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APA (6th Edition):

Garcia-Ramirez, H. J. (2014). Hybrid Techniques for Simulating Quantum Circuits using the Heisenberg Representation. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/107198

Chicago Manual of Style (16th Edition):

Garcia-Ramirez, Hector J. “Hybrid Techniques for Simulating Quantum Circuits using the Heisenberg Representation.” 2014. Doctoral Dissertation, University of Michigan. Accessed December 12, 2019. http://hdl.handle.net/2027.42/107198.

MLA Handbook (7th Edition):

Garcia-Ramirez, Hector J. “Hybrid Techniques for Simulating Quantum Circuits using the Heisenberg Representation.” 2014. Web. 12 Dec 2019.

Vancouver:

Garcia-Ramirez HJ. Hybrid Techniques for Simulating Quantum Circuits using the Heisenberg Representation. [Internet] [Doctoral dissertation]. University of Michigan; 2014. [cited 2019 Dec 12]. Available from: http://hdl.handle.net/2027.42/107198.

Council of Science Editors:

Garcia-Ramirez HJ. Hybrid Techniques for Simulating Quantum Circuits using the Heisenberg Representation. [Doctoral Dissertation]. University of Michigan; 2014. Available from: http://hdl.handle.net/2027.42/107198


University of Michigan

3. Lee, Dong Jin. High-performance and Low-power Clock Network Synthesis in the Presence of Variation.

Degree: PhD, Electrical Engineering, 2011, University of Michigan

 Semiconductor technology scaling requires continuous evolution of all aspects of physical design of integrated circuits. Among the major design steps, clock-network synthesis has been greatly… (more)

Subjects/Keywords: Clock Network Synthesis; Clock Tree; EDA; Low Power; VLSI; Electrical Engineering; Engineering

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APA (6th Edition):

Lee, D. J. (2011). High-performance and Low-power Clock Network Synthesis in the Presence of Variation. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/89711

Chicago Manual of Style (16th Edition):

Lee, Dong Jin. “High-performance and Low-power Clock Network Synthesis in the Presence of Variation.” 2011. Doctoral Dissertation, University of Michigan. Accessed December 12, 2019. http://hdl.handle.net/2027.42/89711.

MLA Handbook (7th Edition):

Lee, Dong Jin. “High-performance and Low-power Clock Network Synthesis in the Presence of Variation.” 2011. Web. 12 Dec 2019.

Vancouver:

Lee DJ. High-performance and Low-power Clock Network Synthesis in the Presence of Variation. [Internet] [Doctoral dissertation]. University of Michigan; 2011. [cited 2019 Dec 12]. Available from: http://hdl.handle.net/2027.42/89711.

Council of Science Editors:

Lee DJ. High-performance and Low-power Clock Network Synthesis in the Presence of Variation. [Doctoral Dissertation]. University of Michigan; 2011. Available from: http://hdl.handle.net/2027.42/89711


University of Michigan

4. Seo, Jae-Sun. High-Speed and Low-Energy On-Chip Communication Circuits.

Degree: PhD, Electrical Engineering, 2010, University of Michigan

 Continuous technology scaling sharply reduces transistor delays, while fixed-length global wire delays have increased due to less wiring pitch with higher resistance and coupling capacitance.… (more)

Subjects/Keywords: Circuit Techniques for Energy-efficient On-chip Communication; High-speed and Low-power Interconnect; Global On-chip Signaling for High-performance VLSI Systems; Electrical Engineering; Engineering

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APA (6th Edition):

Seo, J. (2010). High-Speed and Low-Energy On-Chip Communication Circuits. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/75800

Chicago Manual of Style (16th Edition):

Seo, Jae-Sun. “High-Speed and Low-Energy On-Chip Communication Circuits.” 2010. Doctoral Dissertation, University of Michigan. Accessed December 12, 2019. http://hdl.handle.net/2027.42/75800.

MLA Handbook (7th Edition):

Seo, Jae-Sun. “High-Speed and Low-Energy On-Chip Communication Circuits.” 2010. Web. 12 Dec 2019.

Vancouver:

Seo J. High-Speed and Low-Energy On-Chip Communication Circuits. [Internet] [Doctoral dissertation]. University of Michigan; 2010. [cited 2019 Dec 12]. Available from: http://hdl.handle.net/2027.42/75800.

Council of Science Editors:

Seo J. High-Speed and Low-Energy On-Chip Communication Circuits. [Doctoral Dissertation]. University of Michigan; 2010. Available from: http://hdl.handle.net/2027.42/75800


University of Michigan

5. Papa, David Anthony. Broadening the Scope of Multi-Objective Optimizations in Physical Synthesis of Integrated Circuits.

Degree: PhD, Computer Science & Engineering, 2010, University of Michigan

 In modern VLSI design, physical synthesis tools are primarily responsible for satisfying chip-performance constraints by invoking a broad range of circuit optimizations, such as buffer… (more)

Subjects/Keywords: Physical Synthesis; Timing Closure; Timing-Driven Placement; Circuit Optimization; Mathematical Programming; Multi-Objective Optimization; Computer Science; Electrical Engineering; Engineering; Science

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APA (6th Edition):

Papa, D. A. (2010). Broadening the Scope of Multi-Objective Optimizations in Physical Synthesis of Integrated Circuits. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/78744

Chicago Manual of Style (16th Edition):

Papa, David Anthony. “Broadening the Scope of Multi-Objective Optimizations in Physical Synthesis of Integrated Circuits.” 2010. Doctoral Dissertation, University of Michigan. Accessed December 12, 2019. http://hdl.handle.net/2027.42/78744.

MLA Handbook (7th Edition):

Papa, David Anthony. “Broadening the Scope of Multi-Objective Optimizations in Physical Synthesis of Integrated Circuits.” 2010. Web. 12 Dec 2019.

Vancouver:

Papa DA. Broadening the Scope of Multi-Objective Optimizations in Physical Synthesis of Integrated Circuits. [Internet] [Doctoral dissertation]. University of Michigan; 2010. [cited 2019 Dec 12]. Available from: http://hdl.handle.net/2027.42/78744.

Council of Science Editors:

Papa DA. Broadening the Scope of Multi-Objective Optimizations in Physical Synthesis of Integrated Circuits. [Doctoral Dissertation]. University of Michigan; 2010. Available from: http://hdl.handle.net/2027.42/78744

6. Hu, Jin. High-performance Global Routing for Trillion-gate Systems-on-Chips.

Degree: PhD, Computer Science and Engineering, 2013, University of Michigan

 Due to aggressive transistor scaling, modern-day CMOS circuits have continually increased in both complexity and productivity. Modern semiconductor designs have narrower and more resistive wires,… (more)

Subjects/Keywords: Global Routing; Electronic Design Automation; Placement and Routing Integration; Computer Science; Engineering

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APA (6th Edition):

Hu, J. (2013). High-performance Global Routing for Trillion-gate Systems-on-Chips. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/98025

Chicago Manual of Style (16th Edition):

Hu, Jin. “High-performance Global Routing for Trillion-gate Systems-on-Chips.” 2013. Doctoral Dissertation, University of Michigan. Accessed December 12, 2019. http://hdl.handle.net/2027.42/98025.

MLA Handbook (7th Edition):

Hu, Jin. “High-performance Global Routing for Trillion-gate Systems-on-Chips.” 2013. Web. 12 Dec 2019.

Vancouver:

Hu J. High-performance Global Routing for Trillion-gate Systems-on-Chips. [Internet] [Doctoral dissertation]. University of Michigan; 2013. [cited 2019 Dec 12]. Available from: http://hdl.handle.net/2027.42/98025.

Council of Science Editors:

Hu J. High-performance Global Routing for Trillion-gate Systems-on-Chips. [Doctoral Dissertation]. University of Michigan; 2013. Available from: http://hdl.handle.net/2027.42/98025

7. Katebi, Hadi. Symmetry in Finite Combinatorial Objects: Scalable Methods and Applications.

Degree: PhD, Computer Science & Engineering, 2013, University of Michigan

 Symmetries of combinatorial objects are known to complicate search algorithms, but such obstacles can often be removed by detecting symmetries early and discarding symmetric subproblems.… (more)

Subjects/Keywords: Symmetry of Graphs; Canonical Labeling of Graphs; Symmetry of Boolean Functions; Simultaneous Partition Refinement; Coset and Orbit Pruning; Permutation Group; Computer Science; Engineering

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APA (6th Edition):

Katebi, H. (2013). Symmetry in Finite Combinatorial Objects: Scalable Methods and Applications. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/100003

Chicago Manual of Style (16th Edition):

Katebi, Hadi. “Symmetry in Finite Combinatorial Objects: Scalable Methods and Applications.” 2013. Doctoral Dissertation, University of Michigan. Accessed December 12, 2019. http://hdl.handle.net/2027.42/100003.

MLA Handbook (7th Edition):

Katebi, Hadi. “Symmetry in Finite Combinatorial Objects: Scalable Methods and Applications.” 2013. Web. 12 Dec 2019.

Vancouver:

Katebi H. Symmetry in Finite Combinatorial Objects: Scalable Methods and Applications. [Internet] [Doctoral dissertation]. University of Michigan; 2013. [cited 2019 Dec 12]. Available from: http://hdl.handle.net/2027.42/100003.

Council of Science Editors:

Katebi H. Symmetry in Finite Combinatorial Objects: Scalable Methods and Applications. [Doctoral Dissertation]. University of Michigan; 2013. Available from: http://hdl.handle.net/2027.42/100003

8. Chatterjee, Debapriya. Harnessing Simulation Acceleration to Solve the Digital Design Verification Challenge.

Degree: PhD, Computer Science and Engineering, 2013, University of Michigan

 Today, design verification is by far the most resource and time-consuming activity of any new digital integrated circuit development. Within this area, the vast majority… (more)

Subjects/Keywords: Digital Design Simulation Acceleration; Design Verification; Computer Science; Engineering

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APA (6th Edition):

Chatterjee, D. (2013). Harnessing Simulation Acceleration to Solve the Digital Design Verification Challenge. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/99781

Chicago Manual of Style (16th Edition):

Chatterjee, Debapriya. “Harnessing Simulation Acceleration to Solve the Digital Design Verification Challenge.” 2013. Doctoral Dissertation, University of Michigan. Accessed December 12, 2019. http://hdl.handle.net/2027.42/99781.

MLA Handbook (7th Edition):

Chatterjee, Debapriya. “Harnessing Simulation Acceleration to Solve the Digital Design Verification Challenge.” 2013. Web. 12 Dec 2019.

Vancouver:

Chatterjee D. Harnessing Simulation Acceleration to Solve the Digital Design Verification Challenge. [Internet] [Doctoral dissertation]. University of Michigan; 2013. [cited 2019 Dec 12]. Available from: http://hdl.handle.net/2027.42/99781.

Council of Science Editors:

Chatterjee D. Harnessing Simulation Acceleration to Solve the Digital Design Verification Challenge. [Doctoral Dissertation]. University of Michigan; 2013. Available from: http://hdl.handle.net/2027.42/99781

9. Xu, Zhao. Terahertz (THz) Waveguiding Architecture Featuring Doubly-Corrugated Spoofed Surface Plasmon Polariton (DC-SSPP): Theory and Applications in Micro-Electronics and Sensing.

Degree: PhD, Electrical Engineering, 2017, University of Michigan

 Terahertz (1012 Hz) has long been considered a missing link between microwave and optical IR spectra. This frequency range has attracted enormous research attentions in… (more)

Subjects/Keywords: Terahertz; Electromagnetics; Engineering

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APA (6th Edition):

Xu, Z. (2017). Terahertz (THz) Waveguiding Architecture Featuring Doubly-Corrugated Spoofed Surface Plasmon Polariton (DC-SSPP): Theory and Applications in Micro-Electronics and Sensing. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/137130

Chicago Manual of Style (16th Edition):

Xu, Zhao. “Terahertz (THz) Waveguiding Architecture Featuring Doubly-Corrugated Spoofed Surface Plasmon Polariton (DC-SSPP): Theory and Applications in Micro-Electronics and Sensing.” 2017. Doctoral Dissertation, University of Michigan. Accessed December 12, 2019. http://hdl.handle.net/2027.42/137130.

MLA Handbook (7th Edition):

Xu, Zhao. “Terahertz (THz) Waveguiding Architecture Featuring Doubly-Corrugated Spoofed Surface Plasmon Polariton (DC-SSPP): Theory and Applications in Micro-Electronics and Sensing.” 2017. Web. 12 Dec 2019.

Vancouver:

Xu Z. Terahertz (THz) Waveguiding Architecture Featuring Doubly-Corrugated Spoofed Surface Plasmon Polariton (DC-SSPP): Theory and Applications in Micro-Electronics and Sensing. [Internet] [Doctoral dissertation]. University of Michigan; 2017. [cited 2019 Dec 12]. Available from: http://hdl.handle.net/2027.42/137130.

Council of Science Editors:

Xu Z. Terahertz (THz) Waveguiding Architecture Featuring Doubly-Corrugated Spoofed Surface Plasmon Polariton (DC-SSPP): Theory and Applications in Micro-Electronics and Sensing. [Doctoral Dissertation]. University of Michigan; 2017. Available from: http://hdl.handle.net/2027.42/137130

10. Ebong, Idongesit Effiong. Training Memristors for Reliable Computing.

Degree: PhD, Electrical Engineering, 2013, University of Michigan

 The computation goals of the digital computing world have been segmented into different factions. The goals are no longer rooted in a purely speed/performance standpoint… (more)

Subjects/Keywords: Memristor; Adaptive Method to Crossbar Memory; Spike Timing Dependent Plasticity; Electrical Engineering; Engineering

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APA (6th Edition):

Ebong, I. E. (2013). Training Memristors for Reliable Computing. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/97890

Chicago Manual of Style (16th Edition):

Ebong, Idongesit Effiong. “Training Memristors for Reliable Computing.” 2013. Doctoral Dissertation, University of Michigan. Accessed December 12, 2019. http://hdl.handle.net/2027.42/97890.

MLA Handbook (7th Edition):

Ebong, Idongesit Effiong. “Training Memristors for Reliable Computing.” 2013. Web. 12 Dec 2019.

Vancouver:

Ebong IE. Training Memristors for Reliable Computing. [Internet] [Doctoral dissertation]. University of Michigan; 2013. [cited 2019 Dec 12]. Available from: http://hdl.handle.net/2027.42/97890.

Council of Science Editors:

Ebong IE. Training Memristors for Reliable Computing. [Doctoral Dissertation]. University of Michigan; 2013. Available from: http://hdl.handle.net/2027.42/97890

11. Wu, Xiaodi. Space-efficient Simulations of Quantum Interactive Proofs.

Degree: PhD, Computer Science & Engineering, 2013, University of Michigan

 Interactive proof systems form an important complexity model that has been central to many prominent results in computational complexity theory, such as those on probabilistically… (more)

Subjects/Keywords: Quantum Interactive Proofs; Space-efficient Simulation; PSPACE; Computer Science; Engineering

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APA (6th Edition):

Wu, X. (2013). Space-efficient Simulations of Quantum Interactive Proofs. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/102362

Chicago Manual of Style (16th Edition):

Wu, Xiaodi. “Space-efficient Simulations of Quantum Interactive Proofs.” 2013. Doctoral Dissertation, University of Michigan. Accessed December 12, 2019. http://hdl.handle.net/2027.42/102362.

MLA Handbook (7th Edition):

Wu, Xiaodi. “Space-efficient Simulations of Quantum Interactive Proofs.” 2013. Web. 12 Dec 2019.

Vancouver:

Wu X. Space-efficient Simulations of Quantum Interactive Proofs. [Internet] [Doctoral dissertation]. University of Michigan; 2013. [cited 2019 Dec 12]. Available from: http://hdl.handle.net/2027.42/102362.

Council of Science Editors:

Wu X. Space-efficient Simulations of Quantum Interactive Proofs. [Doctoral Dissertation]. University of Michigan; 2013. Available from: http://hdl.handle.net/2027.42/102362

12. Song, Kyungjun. Modeling, Simulation and Design of Plasmonic Nanoarchitectures for Ultrafast Circuit Systems.

Degree: PhD, Mechanical Engineering, 2010, University of Michigan

 The dissertation focuses on a new ultrafast circuit system based on plasmonic nanoarchitectures. To achieve this goal, we investigate novel plasmonic devices to integrate with… (more)

Subjects/Keywords: Plasmonics; Metamaterial; Electrical Engineering; Engineering

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APA (6th Edition):

Song, K. (2010). Modeling, Simulation and Design of Plasmonic Nanoarchitectures for Ultrafast Circuit Systems. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/78912

Chicago Manual of Style (16th Edition):

Song, Kyungjun. “Modeling, Simulation and Design of Plasmonic Nanoarchitectures for Ultrafast Circuit Systems.” 2010. Doctoral Dissertation, University of Michigan. Accessed December 12, 2019. http://hdl.handle.net/2027.42/78912.

MLA Handbook (7th Edition):

Song, Kyungjun. “Modeling, Simulation and Design of Plasmonic Nanoarchitectures for Ultrafast Circuit Systems.” 2010. Web. 12 Dec 2019.

Vancouver:

Song K. Modeling, Simulation and Design of Plasmonic Nanoarchitectures for Ultrafast Circuit Systems. [Internet] [Doctoral dissertation]. University of Michigan; 2010. [cited 2019 Dec 12]. Available from: http://hdl.handle.net/2027.42/78912.

Council of Science Editors:

Song K. Modeling, Simulation and Design of Plasmonic Nanoarchitectures for Ultrafast Circuit Systems. [Doctoral Dissertation]. University of Michigan; 2010. Available from: http://hdl.handle.net/2027.42/78912

13. Kim, Myung Chul. Multiobjective Placement Optimization for High-performance Nanoscale Integrated Circuits.

Degree: PhD, Electrical Engineering, 2012, University of Michigan

 With aggressive scaling of semiconductor manufacturing technology in recent decades, the complexity of integrated circuits has increased rapidly leading to multi-million gate chips that require… (more)

Subjects/Keywords: Electronic Design Automation; Placement; Electrical Engineering; Engineering

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APA (6th Edition):

Kim, M. C. (2012). Multiobjective Placement Optimization for High-performance Nanoscale Integrated Circuits. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/96055

Chicago Manual of Style (16th Edition):

Kim, Myung Chul. “Multiobjective Placement Optimization for High-performance Nanoscale Integrated Circuits.” 2012. Doctoral Dissertation, University of Michigan. Accessed December 12, 2019. http://hdl.handle.net/2027.42/96055.

MLA Handbook (7th Edition):

Kim, Myung Chul. “Multiobjective Placement Optimization for High-performance Nanoscale Integrated Circuits.” 2012. Web. 12 Dec 2019.

Vancouver:

Kim MC. Multiobjective Placement Optimization for High-performance Nanoscale Integrated Circuits. [Internet] [Doctoral dissertation]. University of Michigan; 2012. [cited 2019 Dec 12]. Available from: http://hdl.handle.net/2027.42/96055.

Council of Science Editors:

Kim MC. Multiobjective Placement Optimization for High-performance Nanoscale Integrated Circuits. [Doctoral Dissertation]. University of Michigan; 2012. Available from: http://hdl.handle.net/2027.42/96055

14. Pant, Sanjay. Design and Analysis of Power Distribution Networks in VLSI Circuits.

Degree: PhD, Electrical Engineering, 2008, University of Michigan

 Rapidly switching currents of the on-chip devices can cause fluctuations in the supply voltage which can be classified as IR and Ldi/dt drops. The voltage… (more)

Subjects/Keywords: Supply Noise Signal Integrity Verification, On-chip Supply Noise Measurement and Supply Noise Suppression in High-performance VLSI Designs; Electrical Engineering; Engineering

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APA (6th Edition):

Pant, S. (2008). Design and Analysis of Power Distribution Networks in VLSI Circuits. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/58508

Chicago Manual of Style (16th Edition):

Pant, Sanjay. “Design and Analysis of Power Distribution Networks in VLSI Circuits.” 2008. Doctoral Dissertation, University of Michigan. Accessed December 12, 2019. http://hdl.handle.net/2027.42/58508.

MLA Handbook (7th Edition):

Pant, Sanjay. “Design and Analysis of Power Distribution Networks in VLSI Circuits.” 2008. Web. 12 Dec 2019.

Vancouver:

Pant S. Design and Analysis of Power Distribution Networks in VLSI Circuits. [Internet] [Doctoral dissertation]. University of Michigan; 2008. [cited 2019 Dec 12]. Available from: http://hdl.handle.net/2027.42/58508.

Council of Science Editors:

Pant S. Design and Analysis of Power Distribution Networks in VLSI Circuits. [Doctoral Dissertation]. University of Michigan; 2008. Available from: http://hdl.handle.net/2027.42/58508

15. Plaza, Stephen M. Synthesis and Verification of Digital Circuits using Functional Simulation and Boolean Satisfiability.

Degree: PhD, Computer Science & Engineering, 2008, University of Michigan

 The semiconductor industry has long relied on the steady trend of transistor scaling, that is, the shrinking of the dimensions of silicon transistor devices, as… (more)

Subjects/Keywords: Logic Synthesis; Electronic Design Automation (EDA); Computer Aided Design (CAD); Satisfiability (SAT); Physical Design; Constraint-guided Simulation; Computer Science; Engineering

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APA (6th Edition):

Plaza, S. M. (2008). Synthesis and Verification of Digital Circuits using Functional Simulation and Boolean Satisfiability. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/61793

Chicago Manual of Style (16th Edition):

Plaza, Stephen M. “Synthesis and Verification of Digital Circuits using Functional Simulation and Boolean Satisfiability.” 2008. Doctoral Dissertation, University of Michigan. Accessed December 12, 2019. http://hdl.handle.net/2027.42/61793.

MLA Handbook (7th Edition):

Plaza, Stephen M. “Synthesis and Verification of Digital Circuits using Functional Simulation and Boolean Satisfiability.” 2008. Web. 12 Dec 2019.

Vancouver:

Plaza SM. Synthesis and Verification of Digital Circuits using Functional Simulation and Boolean Satisfiability. [Internet] [Doctoral dissertation]. University of Michigan; 2008. [cited 2019 Dec 12]. Available from: http://hdl.handle.net/2027.42/61793.

Council of Science Editors:

Plaza SM. Synthesis and Verification of Digital Circuits using Functional Simulation and Boolean Satisfiability. [Doctoral Dissertation]. University of Michigan; 2008. Available from: http://hdl.handle.net/2027.42/61793

16. Kudlur, Manjunath V. Streamroller : A Unified Compilation and Synthesis System for Streaming Applications.

Degree: PhD, Computer Science & Engineering, 2008, University of Michigan

 The growing complexity of applications has increased the need for higher processing power. In the embedded domain, the convergence of audio, video, and networking on… (more)

Subjects/Keywords: Compiler; Stream Programming; Multicore; Scheduling; IBM Cell Processor; High Level Synthesis; Computer Science; Engineering

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APA (6th Edition):

Kudlur, M. V. (2008). Streamroller : A Unified Compilation and Synthesis System for Streaming Applications. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/61662

Chicago Manual of Style (16th Edition):

Kudlur, Manjunath V. “Streamroller : A Unified Compilation and Synthesis System for Streaming Applications.” 2008. Doctoral Dissertation, University of Michigan. Accessed December 12, 2019. http://hdl.handle.net/2027.42/61662.

MLA Handbook (7th Edition):

Kudlur, Manjunath V. “Streamroller : A Unified Compilation and Synthesis System for Streaming Applications.” 2008. Web. 12 Dec 2019.

Vancouver:

Kudlur MV. Streamroller : A Unified Compilation and Synthesis System for Streaming Applications. [Internet] [Doctoral dissertation]. University of Michigan; 2008. [cited 2019 Dec 12]. Available from: http://hdl.handle.net/2027.42/61662.

Council of Science Editors:

Kudlur MV. Streamroller : A Unified Compilation and Synthesis System for Streaming Applications. [Doctoral Dissertation]. University of Michigan; 2008. Available from: http://hdl.handle.net/2027.42/61662


University of Michigan

17. Chu, Michael L. Cooperative Data and Computation Partitioning for Decentralized Architectures.

Degree: PhD, Computer Science & Engineering, 2007, University of Michigan

 Scalability of future wide-issue processor designs is severely hampered by the use of centralized resources such as register files, memories and interconnect networks. While the… (more)

Subjects/Keywords: Compiler Code Generation; Multicluster Compilation; Decentralized Architectures; Data and Code Partitioning; Automatic Parallelization; Computer Science; Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chu, M. L. (2007). Cooperative Data and Computation Partitioning for Decentralized Architectures. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/57649

Chicago Manual of Style (16th Edition):

Chu, Michael L. “Cooperative Data and Computation Partitioning for Decentralized Architectures.” 2007. Doctoral Dissertation, University of Michigan. Accessed December 12, 2019. http://hdl.handle.net/2027.42/57649.

MLA Handbook (7th Edition):

Chu, Michael L. “Cooperative Data and Computation Partitioning for Decentralized Architectures.” 2007. Web. 12 Dec 2019.

Vancouver:

Chu ML. Cooperative Data and Computation Partitioning for Decentralized Architectures. [Internet] [Doctoral dissertation]. University of Michigan; 2007. [cited 2019 Dec 12]. Available from: http://hdl.handle.net/2027.42/57649.

Council of Science Editors:

Chu ML. Cooperative Data and Computation Partitioning for Decentralized Architectures. [Doctoral Dissertation]. University of Michigan; 2007. Available from: http://hdl.handle.net/2027.42/57649


University of Michigan

18. Chopra, Kaviraj. Statistical Performance Analysis Optimization of Digital Circuits.

Degree: PhD, Computer Science & Engineering, 2008, University of Michigan

 Aggressive device scaling has made it imperative to account for process variations in the design flow. A robust model of process variations is an essential… (more)

Subjects/Keywords: Statistical Timing Analysis; Computer Science; Engineering

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APA (6th Edition):

Chopra, K. (2008). Statistical Performance Analysis Optimization of Digital Circuits. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/60747

Chicago Manual of Style (16th Edition):

Chopra, Kaviraj. “Statistical Performance Analysis Optimization of Digital Circuits.” 2008. Doctoral Dissertation, University of Michigan. Accessed December 12, 2019. http://hdl.handle.net/2027.42/60747.

MLA Handbook (7th Edition):

Chopra, Kaviraj. “Statistical Performance Analysis Optimization of Digital Circuits.” 2008. Web. 12 Dec 2019.

Vancouver:

Chopra K. Statistical Performance Analysis Optimization of Digital Circuits. [Internet] [Doctoral dissertation]. University of Michigan; 2008. [cited 2019 Dec 12]. Available from: http://hdl.handle.net/2027.42/60747.

Council of Science Editors:

Chopra K. Statistical Performance Analysis Optimization of Digital Circuits. [Doctoral Dissertation]. University of Michigan; 2008. Available from: http://hdl.handle.net/2027.42/60747


University of Michigan

19. Liffiton, Mark H. Analyzing Infeasible Constraint Systems.

Degree: PhD, Computer Science & Engineering, 2009, University of Michigan

 Constraint systems, problems defined by sets of variables and constraints affecting the allowed assignments to those variables, arise in a wide range of real-world problems,… (more)

Subjects/Keywords: Constraint Processing; Constraint Systems; Infeasibility; Infeasible; Unsatisfiable; Overconstrained; Computer Science; Engineering

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APA (6th Edition):

Liffiton, M. H. (2009). Analyzing Infeasible Constraint Systems. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/63772

Chicago Manual of Style (16th Edition):

Liffiton, Mark H. “Analyzing Infeasible Constraint Systems.” 2009. Doctoral Dissertation, University of Michigan. Accessed December 12, 2019. http://hdl.handle.net/2027.42/63772.

MLA Handbook (7th Edition):

Liffiton, Mark H. “Analyzing Infeasible Constraint Systems.” 2009. Web. 12 Dec 2019.

Vancouver:

Liffiton MH. Analyzing Infeasible Constraint Systems. [Internet] [Doctoral dissertation]. University of Michigan; 2009. [cited 2019 Dec 12]. Available from: http://hdl.handle.net/2027.42/63772.

Council of Science Editors:

Liffiton MH. Analyzing Infeasible Constraint Systems. [Doctoral Dissertation]. University of Michigan; 2009. Available from: http://hdl.handle.net/2027.42/63772


University of Michigan

20. Gandikota, Ravikishore. Crosstalk Noise Analysis for Nano-Meter VLSI Circuits.

Degree: PhD, Electrical Engineering, 2009, University of Michigan

 Scaling of device dimensions into the nanometer process technology has led to a considerable reduction in the gate delays. However, interconnect delays have not scaled… (more)

Subjects/Keywords: Crosstalk Noise; Signal Integrity; Noise Analysis; Capacitive Coupling; Delay Noise; Electrical Engineering; Engineering

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APA (6th Edition):

Gandikota, R. (2009). Crosstalk Noise Analysis for Nano-Meter VLSI Circuits. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/64663

Chicago Manual of Style (16th Edition):

Gandikota, Ravikishore. “Crosstalk Noise Analysis for Nano-Meter VLSI Circuits.” 2009. Doctoral Dissertation, University of Michigan. Accessed December 12, 2019. http://hdl.handle.net/2027.42/64663.

MLA Handbook (7th Edition):

Gandikota, Ravikishore. “Crosstalk Noise Analysis for Nano-Meter VLSI Circuits.” 2009. Web. 12 Dec 2019.

Vancouver:

Gandikota R. Crosstalk Noise Analysis for Nano-Meter VLSI Circuits. [Internet] [Doctoral dissertation]. University of Michigan; 2009. [cited 2019 Dec 12]. Available from: http://hdl.handle.net/2027.42/64663.

Council of Science Editors:

Gandikota R. Crosstalk Noise Analysis for Nano-Meter VLSI Circuits. [Doctoral Dissertation]. University of Michigan; 2009. Available from: http://hdl.handle.net/2027.42/64663


University of Michigan

21. Zhu, Yufan. Quantum Communication Complexity and Nonlocality of Bipartite Quantum Operations.

Degree: PhD, Computer Science & Engineering, 2008, University of Michigan

 This dissertation is motivated by the following fundamental questions: (a) are there any exponential gaps between quantum and classical communication complexities? (b) what is the… (more)

Subjects/Keywords: Quantum Computation; Communication Complexity; Quantum Entanglement; Bipartite Quantum Operations; Nonlocality of Quantum Operations; Computer Science; Engineering

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APA (6th Edition):

Zhu, Y. (2008). Quantum Communication Complexity and Nonlocality of Bipartite Quantum Operations. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/58538

Chicago Manual of Style (16th Edition):

Zhu, Yufan. “Quantum Communication Complexity and Nonlocality of Bipartite Quantum Operations.” 2008. Doctoral Dissertation, University of Michigan. Accessed December 12, 2019. http://hdl.handle.net/2027.42/58538.

MLA Handbook (7th Edition):

Zhu, Yufan. “Quantum Communication Complexity and Nonlocality of Bipartite Quantum Operations.” 2008. Web. 12 Dec 2019.

Vancouver:

Zhu Y. Quantum Communication Complexity and Nonlocality of Bipartite Quantum Operations. [Internet] [Doctoral dissertation]. University of Michigan; 2008. [cited 2019 Dec 12]. Available from: http://hdl.handle.net/2027.42/58538.

Council of Science Editors:

Zhu Y. Quantum Communication Complexity and Nonlocality of Bipartite Quantum Operations. [Doctoral Dissertation]. University of Michigan; 2008. Available from: http://hdl.handle.net/2027.42/58538


University of Michigan

22. Krishnaswamy, Smita. Design, Analysis and Test of Logic Circuits under Uncertainty.

Degree: PhD, Computer Science & Engineering, 2008, University of Michigan

 Integrated circuits are increasingly susceptible to uncertainty caused by soft errors, inherently probabilistic devices, and manufacturing variability. As device technologies scale, these effects become detrimental… (more)

Subjects/Keywords: Logic Design; Electronic Design Automation; Soft Error; Circuit Reliability; Circuit Testing; Soft Error Rate Analysis; Engineering

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APA (6th Edition):

Krishnaswamy, S. (2008). Design, Analysis and Test of Logic Circuits under Uncertainty. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/61584

Chicago Manual of Style (16th Edition):

Krishnaswamy, Smita. “Design, Analysis and Test of Logic Circuits under Uncertainty.” 2008. Doctoral Dissertation, University of Michigan. Accessed December 12, 2019. http://hdl.handle.net/2027.42/61584.

MLA Handbook (7th Edition):

Krishnaswamy, Smita. “Design, Analysis and Test of Logic Circuits under Uncertainty.” 2008. Web. 12 Dec 2019.

Vancouver:

Krishnaswamy S. Design, Analysis and Test of Logic Circuits under Uncertainty. [Internet] [Doctoral dissertation]. University of Michigan; 2008. [cited 2019 Dec 12]. Available from: http://hdl.handle.net/2027.42/61584.

Council of Science Editors:

Krishnaswamy S. Design, Analysis and Test of Logic Circuits under Uncertainty. [Doctoral Dissertation]. University of Michigan; 2008. Available from: http://hdl.handle.net/2027.42/61584


University of Michigan

23. Roy, Jarrod Alexander. High-Performance Placement and Routing for the Nanometer Scale.

Degree: PhD, Computer Science & Engineering, 2009, University of Michigan

 Modern semiconductor manufacturing facilitates single-chip electronic systems that only five years ago required ten to twenty chips. Naturally, design complexity has grown within this period.… (more)

Subjects/Keywords: Physical Design of Integrated Circuits; Placement; Routing; VLSI; Computer Science; Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Roy, J. A. (2009). High-Performance Placement and Routing for the Nanometer Scale. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/64639

Chicago Manual of Style (16th Edition):

Roy, Jarrod Alexander. “High-Performance Placement and Routing for the Nanometer Scale.” 2009. Doctoral Dissertation, University of Michigan. Accessed December 12, 2019. http://hdl.handle.net/2027.42/64639.

MLA Handbook (7th Edition):

Roy, Jarrod Alexander. “High-Performance Placement and Routing for the Nanometer Scale.” 2009. Web. 12 Dec 2019.

Vancouver:

Roy JA. High-Performance Placement and Routing for the Nanometer Scale. [Internet] [Doctoral dissertation]. University of Michigan; 2009. [cited 2019 Dec 12]. Available from: http://hdl.handle.net/2027.42/64639.

Council of Science Editors:

Roy JA. High-Performance Placement and Routing for the Nanometer Scale. [Doctoral Dissertation]. University of Michigan; 2009. Available from: http://hdl.handle.net/2027.42/64639

.