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You searched for +publisher:"University of Michigan" +contributor:("Davidson, Edward S."). Showing records 1 – 20 of 20 total matches.

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University of Michigan

1. Boyd, Eric Logan. Performance evaluation and improvement of parallel applications on high performance architectures.

Degree: PhD, Computer Science and Engineering, 1995, University of Michigan

 An effective methodology of performance evaluation and improvement enables application developers to quickly and efficiently tune their applications to achieve good performance. One efficient approach… (more)

Subjects/Keywords: Engineering, Electronics and Electrical; Computer Science

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APA (6th Edition):

Boyd, E. L. (1995). Performance evaluation and improvement of parallel applications on high performance architectures. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/104748

Chicago Manual of Style (16th Edition):

Boyd, Eric Logan. “Performance evaluation and improvement of parallel applications on high performance architectures.” 1995. Doctoral Dissertation, University of Michigan. Accessed January 22, 2021. http://hdl.handle.net/2027.42/104748.

MLA Handbook (7th Edition):

Boyd, Eric Logan. “Performance evaluation and improvement of parallel applications on high performance architectures.” 1995. Web. 22 Jan 2021.

Vancouver:

Boyd EL. Performance evaluation and improvement of parallel applications on high performance architectures. [Internet] [Doctoral dissertation]. University of Michigan; 1995. [cited 2021 Jan 22]. Available from: http://hdl.handle.net/2027.42/104748.

Council of Science Editors:

Boyd EL. Performance evaluation and improvement of parallel applications on high performance architectures. [Doctoral Dissertation]. University of Michigan; 1995. Available from: http://hdl.handle.net/2027.42/104748


University of Michigan

2. Abandah, Gheith Ali. Reducing communication cost in scalable shared memory systems.

Degree: PhD, Computer science, 1998, University of Michigan

 Distributed shared-memory systems provide scalable performance and a convenient model for parallel programming. However, their non-uniform memory latency often makes it difficult to develop efficient… (more)

Subjects/Keywords: Communication; Cost; Microbenchmarking; Reducing; Scalable; Shared Memory; Systems

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APA (6th Edition):

Abandah, G. A. (1998). Reducing communication cost in scalable shared memory systems. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/130888

Chicago Manual of Style (16th Edition):

Abandah, Gheith Ali. “Reducing communication cost in scalable shared memory systems.” 1998. Doctoral Dissertation, University of Michigan. Accessed January 22, 2021. http://hdl.handle.net/2027.42/130888.

MLA Handbook (7th Edition):

Abandah, Gheith Ali. “Reducing communication cost in scalable shared memory systems.” 1998. Web. 22 Jan 2021.

Vancouver:

Abandah GA. Reducing communication cost in scalable shared memory systems. [Internet] [Doctoral dissertation]. University of Michigan; 1998. [cited 2021 Jan 22]. Available from: http://hdl.handle.net/2027.42/130888.

Council of Science Editors:

Abandah GA. Reducing communication cost in scalable shared memory systems. [Doctoral Dissertation]. University of Michigan; 1998. Available from: http://hdl.handle.net/2027.42/130888


University of Michigan

3. Meleis, Waleed M. Optimal instruction scheduling and register allocation for multiple-issue processors.

Degree: PhD, Computer Science and Engineering, 1996, University of Michigan

 As processors make use of wider instruction issue and deeper pipelines, the number of instructions in flight and consequently the number of simultaneously live values… (more)

Subjects/Keywords: Computer Science

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APA (6th Edition):

Meleis, W. M. (1996). Optimal instruction scheduling and register allocation for multiple-issue processors. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/105122

Chicago Manual of Style (16th Edition):

Meleis, Waleed M. “Optimal instruction scheduling and register allocation for multiple-issue processors.” 1996. Doctoral Dissertation, University of Michigan. Accessed January 22, 2021. http://hdl.handle.net/2027.42/105122.

MLA Handbook (7th Edition):

Meleis, Waleed M. “Optimal instruction scheduling and register allocation for multiple-issue processors.” 1996. Web. 22 Jan 2021.

Vancouver:

Meleis WM. Optimal instruction scheduling and register allocation for multiple-issue processors. [Internet] [Doctoral dissertation]. University of Michigan; 1996. [cited 2021 Jan 22]. Available from: http://hdl.handle.net/2027.42/105122.

Council of Science Editors:

Meleis WM. Optimal instruction scheduling and register allocation for multiple-issue processors. [Doctoral Dissertation]. University of Michigan; 1996. Available from: http://hdl.handle.net/2027.42/105122


University of Michigan

4. Annavaram, Murali Mohan Kumar. Prefetch mechanisms that acquire and exploit application specific knowledge.

Degree: PhD, Electrical engineering, 2001, University of Michigan

 The large number of cache misses of current applications coupled with the increasing cache miss latencies in current processor designs cause significant performance degradation, even… (more)

Subjects/Keywords: Acquire; Application-specific Knowledge; Call Graph Prefetching; Database Performance; Exploit; Mechanisms; Prefetch

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APA (6th Edition):

Annavaram, M. M. K. (2001). Prefetch mechanisms that acquire and exploit application specific knowledge. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/124668

Chicago Manual of Style (16th Edition):

Annavaram, Murali Mohan Kumar. “Prefetch mechanisms that acquire and exploit application specific knowledge.” 2001. Doctoral Dissertation, University of Michigan. Accessed January 22, 2021. http://hdl.handle.net/2027.42/124668.

MLA Handbook (7th Edition):

Annavaram, Murali Mohan Kumar. “Prefetch mechanisms that acquire and exploit application specific knowledge.” 2001. Web. 22 Jan 2021.

Vancouver:

Annavaram MMK. Prefetch mechanisms that acquire and exploit application specific knowledge. [Internet] [Doctoral dissertation]. University of Michigan; 2001. [cited 2021 Jan 22]. Available from: http://hdl.handle.net/2027.42/124668.

Council of Science Editors:

Annavaram MMK. Prefetch mechanisms that acquire and exploit application specific knowledge. [Doctoral Dissertation]. University of Michigan; 2001. Available from: http://hdl.handle.net/2027.42/124668


University of Michigan

5. Shih, Tien-Pao. Goal-directed performance tuning for scientific applications.

Degree: PhD, Computer Science and Engineering, 1996, University of Michigan

 Performance tuning, as carried out by compiler designers and application programmers to close the performance gap between the achievable peak and delivered performance, becomes increasingly… (more)

Subjects/Keywords: Computer Science

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APA (6th Edition):

Shih, T. (1996). Goal-directed performance tuning for scientific applications. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/105149

Chicago Manual of Style (16th Edition):

Shih, Tien-Pao. “Goal-directed performance tuning for scientific applications.” 1996. Doctoral Dissertation, University of Michigan. Accessed January 22, 2021. http://hdl.handle.net/2027.42/105149.

MLA Handbook (7th Edition):

Shih, Tien-Pao. “Goal-directed performance tuning for scientific applications.” 1996. Web. 22 Jan 2021.

Vancouver:

Shih T. Goal-directed performance tuning for scientific applications. [Internet] [Doctoral dissertation]. University of Michigan; 1996. [cited 2021 Jan 22]. Available from: http://hdl.handle.net/2027.42/105149.

Council of Science Editors:

Shih T. Goal-directed performance tuning for scientific applications. [Doctoral Dissertation]. University of Michigan; 1996. Available from: http://hdl.handle.net/2027.42/105149


University of Michigan

6. Chang, Chuan-Hua. Performance optimization of pipeline circuits with latches and wave pipelining.

Degree: PhD, Computer Science and Engineering, 1996, University of Michigan

 The use of level-sensitive latches and wave-pipelining techniques are two aggressive methods to increase the performance of pipelined circuits. However, they do present difficult analysis… (more)

Subjects/Keywords: Engineering, Electronics and Electrical; Computer Science

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APA (6th Edition):

Chang, C. (1996). Performance optimization of pipeline circuits with latches and wave pipelining. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/104927

Chicago Manual of Style (16th Edition):

Chang, Chuan-Hua. “Performance optimization of pipeline circuits with latches and wave pipelining.” 1996. Doctoral Dissertation, University of Michigan. Accessed January 22, 2021. http://hdl.handle.net/2027.42/104927.

MLA Handbook (7th Edition):

Chang, Chuan-Hua. “Performance optimization of pipeline circuits with latches and wave pipelining.” 1996. Web. 22 Jan 2021.

Vancouver:

Chang C. Performance optimization of pipeline circuits with latches and wave pipelining. [Internet] [Doctoral dissertation]. University of Michigan; 1996. [cited 2021 Jan 22]. Available from: http://hdl.handle.net/2027.42/104927.

Council of Science Editors:

Chang C. Performance optimization of pipeline circuits with latches and wave pipelining. [Doctoral Dissertation]. University of Michigan; 1996. Available from: http://hdl.handle.net/2027.42/104927


University of Michigan

7. Hung, Shih-Hao. Optimizing parallel applications.

Degree: PhD, Electrical engineering, 1998, University of Michigan

 While parallel computing offers an attractive perspective for the future, developing efficient parallel applications today is a labor-intensive process that requires an intimate knowledge of… (more)

Subjects/Keywords: High-performance Computing; Optimizing; Parallel Applications; Performance Optimization

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APA (6th Edition):

Hung, S. (1998). Optimizing parallel applications. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/131229

Chicago Manual of Style (16th Edition):

Hung, Shih-Hao. “Optimizing parallel applications.” 1998. Doctoral Dissertation, University of Michigan. Accessed January 22, 2021. http://hdl.handle.net/2027.42/131229.

MLA Handbook (7th Edition):

Hung, Shih-Hao. “Optimizing parallel applications.” 1998. Web. 22 Jan 2021.

Vancouver:

Hung S. Optimizing parallel applications. [Internet] [Doctoral dissertation]. University of Michigan; 1998. [cited 2021 Jan 22]. Available from: http://hdl.handle.net/2027.42/131229.

Council of Science Editors:

Hung S. Optimizing parallel applications. [Doctoral Dissertation]. University of Michigan; 1998. Available from: http://hdl.handle.net/2027.42/131229


University of Michigan

8. Vlaovic, Steven Alexander. Modeling and analysis of x86-based front -end architectures.

Degree: PhD, Electrical engineering, 2002, University of Michigan

 This dissertation analyzes x86 processor models in order to better understand the impact that the x86 instruction set architecture (ISA) has on the front end… (more)

Subjects/Keywords: Analysis; Front-end Architectures; Instruction Set; Processor Modeling; X86-based

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APA (6th Edition):

Vlaovic, S. A. (2002). Modeling and analysis of x86-based front -end architectures. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/130766

Chicago Manual of Style (16th Edition):

Vlaovic, Steven Alexander. “Modeling and analysis of x86-based front -end architectures.” 2002. Doctoral Dissertation, University of Michigan. Accessed January 22, 2021. http://hdl.handle.net/2027.42/130766.

MLA Handbook (7th Edition):

Vlaovic, Steven Alexander. “Modeling and analysis of x86-based front -end architectures.” 2002. Web. 22 Jan 2021.

Vancouver:

Vlaovic SA. Modeling and analysis of x86-based front -end architectures. [Internet] [Doctoral dissertation]. University of Michigan; 2002. [cited 2021 Jan 22]. Available from: http://hdl.handle.net/2027.42/130766.

Council of Science Editors:

Vlaovic SA. Modeling and analysis of x86-based front -end architectures. [Doctoral Dissertation]. University of Michigan; 2002. Available from: http://hdl.handle.net/2027.42/130766


University of Michigan

9. Wellman, John-David. Processor modeling and evaluation techniques for early design stage performance comparison.

Degree: PhD, Electrical engineering, 1996, University of Michigan

 This thesis develops two techniques and a design space search hierarchy that can be used to examine a large space of processor designs early in… (more)

Subjects/Keywords: Comparison; Design; Early; Evaluation; Modeling; Performance; Processor; Reduced Trace Analysis; Resource Conflict Methodology; Stage; Techniques

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APA (6th Edition):

Wellman, J. (1996). Processor modeling and evaluation techniques for early design stage performance comparison. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/130159

Chicago Manual of Style (16th Edition):

Wellman, John-David. “Processor modeling and evaluation techniques for early design stage performance comparison.” 1996. Doctoral Dissertation, University of Michigan. Accessed January 22, 2021. http://hdl.handle.net/2027.42/130159.

MLA Handbook (7th Edition):

Wellman, John-David. “Processor modeling and evaluation techniques for early design stage performance comparison.” 1996. Web. 22 Jan 2021.

Vancouver:

Wellman J. Processor modeling and evaluation techniques for early design stage performance comparison. [Internet] [Doctoral dissertation]. University of Michigan; 1996. [cited 2021 Jan 22]. Available from: http://hdl.handle.net/2027.42/130159.

Council of Science Editors:

Wellman J. Processor modeling and evaluation techniques for early design stage performance comparison. [Doctoral Dissertation]. University of Michigan; 1996. Available from: http://hdl.handle.net/2027.42/130159

10. Ernst, Elizabeth Ann. Optimal Combinational Multi-Level Logic Synthesis.

Degree: PhD, Computer Science & Engineering, 2009, University of Michigan

 Within the field of automated logic design, the optimal synthesis of combinational logic has remained one of the most basic design objectives. However, the computational… (more)

Subjects/Keywords: Optimal Logic Synthesis; Computer Science; Engineering

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APA (6th Edition):

Ernst, E. A. (2009). Optimal Combinational Multi-Level Logic Synthesis. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/62373

Chicago Manual of Style (16th Edition):

Ernst, Elizabeth Ann. “Optimal Combinational Multi-Level Logic Synthesis.” 2009. Doctoral Dissertation, University of Michigan. Accessed January 22, 2021. http://hdl.handle.net/2027.42/62373.

MLA Handbook (7th Edition):

Ernst, Elizabeth Ann. “Optimal Combinational Multi-Level Logic Synthesis.” 2009. Web. 22 Jan 2021.

Vancouver:

Ernst EA. Optimal Combinational Multi-Level Logic Synthesis. [Internet] [Doctoral dissertation]. University of Michigan; 2009. [cited 2021 Jan 22]. Available from: http://hdl.handle.net/2027.42/62373.

Council of Science Editors:

Ernst EA. Optimal Combinational Multi-Level Logic Synthesis. [Doctoral Dissertation]. University of Michigan; 2009. Available from: http://hdl.handle.net/2027.42/62373


University of Michigan

11. Srinivasan, Vijayalakshmi. Hardware solutions to reduce effective memory access time.

Degree: PhD, Electrical engineering, 2001, University of Michigan

 In this dissertation, we provide hardware solutions to increase the efficiency of the cache hierarchy, thereby reducing the effective memory access time. Specifically, we focus… (more)

Subjects/Keywords: Branch History Guided; Branch History-guided; Effective; Hardware Prefetch; Memory Access Time; Reduce; Solutions; Split Latency Cache

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APA (6th Edition):

Srinivasan, V. (2001). Hardware solutions to reduce effective memory access time. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/124069

Chicago Manual of Style (16th Edition):

Srinivasan, Vijayalakshmi. “Hardware solutions to reduce effective memory access time.” 2001. Doctoral Dissertation, University of Michigan. Accessed January 22, 2021. http://hdl.handle.net/2027.42/124069.

MLA Handbook (7th Edition):

Srinivasan, Vijayalakshmi. “Hardware solutions to reduce effective memory access time.” 2001. Web. 22 Jan 2021.

Vancouver:

Srinivasan V. Hardware solutions to reduce effective memory access time. [Internet] [Doctoral dissertation]. University of Michigan; 2001. [cited 2021 Jan 22]. Available from: http://hdl.handle.net/2027.42/124069.

Council of Science Editors:

Srinivasan V. Hardware solutions to reduce effective memory access time. [Doctoral Dissertation]. University of Michigan; 2001. Available from: http://hdl.handle.net/2027.42/124069


University of Michigan

12. Mangione-Smith, William Henry. Performance bounds and buffer space requirements for concurrent processors.

Degree: PhD, Electrical engineering, 1992, University of Michigan

 Scientific programs are typically characterized as floating-point intensive loop-dominated tasks with large amounts of exploitable parallelism. A wide range of concurrent processor architectures have been… (more)

Subjects/Keywords: Bounds; Buffer; Concurrent; Performance; Processors; Requirements; Space

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APA (6th Edition):

Mangione-Smith, W. H. (1992). Performance bounds and buffer space requirements for concurrent processors. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/128895

Chicago Manual of Style (16th Edition):

Mangione-Smith, William Henry. “Performance bounds and buffer space requirements for concurrent processors.” 1992. Doctoral Dissertation, University of Michigan. Accessed January 22, 2021. http://hdl.handle.net/2027.42/128895.

MLA Handbook (7th Edition):

Mangione-Smith, William Henry. “Performance bounds and buffer space requirements for concurrent processors.” 1992. Web. 22 Jan 2021.

Vancouver:

Mangione-Smith WH. Performance bounds and buffer space requirements for concurrent processors. [Internet] [Doctoral dissertation]. University of Michigan; 1992. [cited 2021 Jan 22]. Available from: http://hdl.handle.net/2027.42/128895.

Council of Science Editors:

Mangione-Smith WH. Performance bounds and buffer space requirements for concurrent processors. [Doctoral Dissertation]. University of Michigan; 1992. Available from: http://hdl.handle.net/2027.42/128895


University of Michigan

13. Rivers, Jude A. Performance aspects of high-bandwidth multi-lateral cache organizations.

Degree: PhD, Computer science, 1998, University of Michigan

 As the issue widths of processors continue to increase, efficient data supply will become ever more critical. Unfortunately, with processor speeds increasing faster than memory… (more)

Subjects/Keywords: Aspects; Bandwidth; Cache; High; Lateral; Management; Multi; Organizations; Performance

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APA (6th Edition):

Rivers, J. A. (1998). Performance aspects of high-bandwidth multi-lateral cache organizations. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/131086

Chicago Manual of Style (16th Edition):

Rivers, Jude A. “Performance aspects of high-bandwidth multi-lateral cache organizations.” 1998. Doctoral Dissertation, University of Michigan. Accessed January 22, 2021. http://hdl.handle.net/2027.42/131086.

MLA Handbook (7th Edition):

Rivers, Jude A. “Performance aspects of high-bandwidth multi-lateral cache organizations.” 1998. Web. 22 Jan 2021.

Vancouver:

Rivers JA. Performance aspects of high-bandwidth multi-lateral cache organizations. [Internet] [Doctoral dissertation]. University of Michigan; 1998. [cited 2021 Jan 22]. Available from: http://hdl.handle.net/2027.42/131086.

Council of Science Editors:

Rivers JA. Performance aspects of high-bandwidth multi-lateral cache organizations. [Doctoral Dissertation]. University of Michigan; 1998. Available from: http://hdl.handle.net/2027.42/131086


University of Michigan

14. Tam, Edward S. Improving cache performance via active management.

Degree: PhD, Electrical engineering, 1999, University of Michigan

 This dissertation analyzes a way to improve cache performance via active management of a target cache space. As microprocessor speeds continue to grow faster than… (more)

Subjects/Keywords: Active Management; Allocation By Conflict; Cache; Improving; Performance; Via

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APA (6th Edition):

Tam, E. S. (1999). Improving cache performance via active management. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/132017

Chicago Manual of Style (16th Edition):

Tam, Edward S. “Improving cache performance via active management.” 1999. Doctoral Dissertation, University of Michigan. Accessed January 22, 2021. http://hdl.handle.net/2027.42/132017.

MLA Handbook (7th Edition):

Tam, Edward S. “Improving cache performance via active management.” 1999. Web. 22 Jan 2021.

Vancouver:

Tam ES. Improving cache performance via active management. [Internet] [Doctoral dissertation]. University of Michigan; 1999. [cited 2021 Jan 22]. Available from: http://hdl.handle.net/2027.42/132017.

Council of Science Editors:

Tam ES. Improving cache performance via active management. [Doctoral Dissertation]. University of Michigan; 1999. Available from: http://hdl.handle.net/2027.42/132017


University of Michigan

15. Chaar, Jarir Kamel. A methodology for developing real-time control software for efficient and dependable manufacturing systems.

Degree: PhD, Computer Science and Engineering, 1990, University of Michigan

 Designing efficient and dependable manufacturing systems has always been a major goal of modern computer-integrated manufacturing. The dissertation proposes a methodology for developing the control… (more)

Subjects/Keywords: Engineering, Industrial; Computer Science

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APA (6th Edition):

Chaar, J. K. (1990). A methodology for developing real-time control software for efficient and dependable manufacturing systems. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/103284

Chicago Manual of Style (16th Edition):

Chaar, Jarir Kamel. “A methodology for developing real-time control software for efficient and dependable manufacturing systems.” 1990. Doctoral Dissertation, University of Michigan. Accessed January 22, 2021. http://hdl.handle.net/2027.42/103284.

MLA Handbook (7th Edition):

Chaar, Jarir Kamel. “A methodology for developing real-time control software for efficient and dependable manufacturing systems.” 1990. Web. 22 Jan 2021.

Vancouver:

Chaar JK. A methodology for developing real-time control software for efficient and dependable manufacturing systems. [Internet] [Doctoral dissertation]. University of Michigan; 1990. [cited 2021 Jan 22]. Available from: http://hdl.handle.net/2027.42/103284.

Council of Science Editors:

Chaar JK. A methodology for developing real-time control software for efficient and dependable manufacturing systems. [Doctoral Dissertation]. University of Michigan; 1990. Available from: http://hdl.handle.net/2027.42/103284


University of Michigan

16. Eichenberger, Alexandre Edouard. Modulo scheduling, machine representations, and register-sensitive algorithms.

Degree: PhD, Electrical engineering, 1996, University of Michigan

 High performance compilers increasingly rely on accurate modeling of the machine resources to efficiently exploit the instruction level parallelism of an application. In this dissertation,… (more)

Subjects/Keywords: Algorithms; Machine; Modulo; Register; Representations; Scheduling; Sensitive

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APA (6th Edition):

Eichenberger, A. E. (1996). Modulo scheduling, machine representations, and register-sensitive algorithms. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/129979

Chicago Manual of Style (16th Edition):

Eichenberger, Alexandre Edouard. “Modulo scheduling, machine representations, and register-sensitive algorithms.” 1996. Doctoral Dissertation, University of Michigan. Accessed January 22, 2021. http://hdl.handle.net/2027.42/129979.

MLA Handbook (7th Edition):

Eichenberger, Alexandre Edouard. “Modulo scheduling, machine representations, and register-sensitive algorithms.” 1996. Web. 22 Jan 2021.

Vancouver:

Eichenberger AE. Modulo scheduling, machine representations, and register-sensitive algorithms. [Internet] [Doctoral dissertation]. University of Michigan; 1996. [cited 2021 Jan 22]. Available from: http://hdl.handle.net/2027.42/129979.

Council of Science Editors:

Eichenberger AE. Modulo scheduling, machine representations, and register-sensitive algorithms. [Doctoral Dissertation]. University of Michigan; 1996. Available from: http://hdl.handle.net/2027.42/129979


University of Michigan

17. Smelyanskiy, Mikhail. Hardware/software mechanisms for increasing resource utilization on VLIW/EPIC processors.

Degree: C.S.E., Computer science, 2004, University of Michigan

 VLIW/EPIC (Very Large Instruction Word/Explicitly Parallel Instruction Computing) processors are increasingly used in signal processing, embedded and general-purpose applications. To achieve efficient instruction schedules in… (more)

Subjects/Keywords: Hardware/software; Increasing; Mechanisms; Processors; Resource Utilization; Vliw/epic

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APA (6th Edition):

Smelyanskiy, M. (2004). Hardware/software mechanisms for increasing resource utilization on VLIW/EPIC processors. (Thesis). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/124185

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Smelyanskiy, Mikhail. “Hardware/software mechanisms for increasing resource utilization on VLIW/EPIC processors.” 2004. Thesis, University of Michigan. Accessed January 22, 2021. http://hdl.handle.net/2027.42/124185.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Smelyanskiy, Mikhail. “Hardware/software mechanisms for increasing resource utilization on VLIW/EPIC processors.” 2004. Web. 22 Jan 2021.

Vancouver:

Smelyanskiy M. Hardware/software mechanisms for increasing resource utilization on VLIW/EPIC processors. [Internet] [Thesis]. University of Michigan; 2004. [cited 2021 Jan 22]. Available from: http://hdl.handle.net/2027.42/124185.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Smelyanskiy M. Hardware/software mechanisms for increasing resource utilization on VLIW/EPIC processors. [Thesis]. University of Michigan; 2004. Available from: http://hdl.handle.net/2027.42/124185

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Michigan

18. Chappell, Robert Sommer. Simultaneous subordinate microthreading.

Degree: PhD, Electrical engineering, 2004, University of Michigan

 Tomorrow's ultra-wide microprocessors will be unable to supply enough work from single-threaded programs to take advantage of all available execution resources. Instruction processing bottlenecks, such… (more)

Subjects/Keywords: Microthread; Multithreading; Simultaneous Subordinate Microthreading

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APA (6th Edition):

Chappell, R. S. (2004). Simultaneous subordinate microthreading. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/124027

Chicago Manual of Style (16th Edition):

Chappell, Robert Sommer. “Simultaneous subordinate microthreading.” 2004. Doctoral Dissertation, University of Michigan. Accessed January 22, 2021. http://hdl.handle.net/2027.42/124027.

MLA Handbook (7th Edition):

Chappell, Robert Sommer. “Simultaneous subordinate microthreading.” 2004. Web. 22 Jan 2021.

Vancouver:

Chappell RS. Simultaneous subordinate microthreading. [Internet] [Doctoral dissertation]. University of Michigan; 2004. [cited 2021 Jan 22]. Available from: http://hdl.handle.net/2027.42/124027.

Council of Science Editors:

Chappell RS. Simultaneous subordinate microthreading. [Doctoral Dissertation]. University of Michigan; 2004. Available from: http://hdl.handle.net/2027.42/124027


University of Michigan

19. Racunas, Paul Brian. Reducing load latency through memory instruction characterization.

Degree: PhD, Electrical engineering, 2003, University of Michigan

 Processor performance is directly impacted by the latency of the memory system. As processor core cycle times decrease, the disparity between the latency of an… (more)

Subjects/Keywords: Characterization; Load Latency; Memory Instruction; Partitioning; Reducing; Superscalar

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Racunas, P. B. (2003). Reducing load latency through memory instruction characterization. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/123938

Chicago Manual of Style (16th Edition):

Racunas, Paul Brian. “Reducing load latency through memory instruction characterization.” 2003. Doctoral Dissertation, University of Michigan. Accessed January 22, 2021. http://hdl.handle.net/2027.42/123938.

MLA Handbook (7th Edition):

Racunas, Paul Brian. “Reducing load latency through memory instruction characterization.” 2003. Web. 22 Jan 2021.

Vancouver:

Racunas PB. Reducing load latency through memory instruction characterization. [Internet] [Doctoral dissertation]. University of Michigan; 2003. [cited 2021 Jan 22]. Available from: http://hdl.handle.net/2027.42/123938.

Council of Science Editors:

Racunas PB. Reducing load latency through memory instruction characterization. [Doctoral Dissertation]. University of Michigan; 2003. Available from: http://hdl.handle.net/2027.42/123938


University of Michigan

20. Tomko, Karen Arnold. Domain decomposition, irregular applications, and parallel computers.

Degree: PhD, Computer Science and Engineering, 1995, University of Michigan

 Many large-scale computational problems are based on irregular (unstructured) domains. Some examples are finite element methods in structural analysis, finite volume methods in fluid dynamics,… (more)

Subjects/Keywords: Computer Science

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Tomko, K. A. (1995). Domain decomposition, irregular applications, and parallel computers. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/104873

Chicago Manual of Style (16th Edition):

Tomko, Karen Arnold. “Domain decomposition, irregular applications, and parallel computers.” 1995. Doctoral Dissertation, University of Michigan. Accessed January 22, 2021. http://hdl.handle.net/2027.42/104873.

MLA Handbook (7th Edition):

Tomko, Karen Arnold. “Domain decomposition, irregular applications, and parallel computers.” 1995. Web. 22 Jan 2021.

Vancouver:

Tomko KA. Domain decomposition, irregular applications, and parallel computers. [Internet] [Doctoral dissertation]. University of Michigan; 1995. [cited 2021 Jan 22]. Available from: http://hdl.handle.net/2027.42/104873.

Council of Science Editors:

Tomko KA. Domain decomposition, irregular applications, and parallel computers. [Doctoral Dissertation]. University of Michigan; 1995. Available from: http://hdl.handle.net/2027.42/104873

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