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You searched for +publisher:"University of Michigan" +contributor:("Ahmed, Omar Jamil"). Showing records 1 – 3 of 3 total matches.

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University of Michigan

1. Zheng, Nan. Algorithm/Architecture Co-Design for Low-Power Neuromorphic Computing.

Degree: PhD, Electrical Engineering, 2017, University of Michigan

The development of computing systems based on the conventional von Neumann architecture has slowed down in the past decade as complementary metal-oxide-semiconductor (CMOS) technology scaling becomes more and more difficult. To satisfy the ever-increasing demands in computing power, neuromorphic computing has emerged as an attractive alternative. This dissertation focuses on developing learning algorithm, hardware architecture, circuit components, and design methodologies for low-power neuromorphic computing that can be employed in various energy-constrained applications. A top-down approach is adopted in this research. Starting from the algorithm-architecture co-design, a hardware-friendly learning algorithm is developed for spiking neural networks (SNNs). The possibility of estimating gradients from spike timings is explored. The learning algorithm is developed for the ease of hardware implementation, as well as the compatibility with many well-established learning techniques developed for classic artificial neural networks (ANNs). An SNN hardware equipped with the proposed on-chip learning algorithm is implemented in CMOS technology. In this design, two unique features of SNNs, the event-driven computation and the inferring with a progressive precision, are leveraged to reduce the energy consumption. In addition to low-power SNN hardware, accelerators for ANNs are also presented to accelerate the adaptive dynamic programing algorithm. An efficient and flexible single-instruction-multiple-data architecture is proposed to exploit the inherent data-level parallelism in the inference and learning of ANNs. In addition, the accelerator is augmented with a virtual update technique, which helps improve the throughput and energy efficiency remarkably. Lastly, two techniques in the architecture-circuit level are introduced to mitigate the degraded reliability of the memory system in a neuromorphic hardware owing to the aggressively-scaled supply voltage and integration density. The first method uses on-chip feedback to compensate for the process variation and the second technique improves the throughput and energy efficiency of a conventional error-correction method. Advisors/Committee Members: Mazumder, Pinaki (committee member), Ahmed, Omar Jamil (committee member), Scott, Clayton D (committee member), Stark, Wayne E (committee member).

Subjects/Keywords: Neuromorphic computing; Neural network; Machine learning; Low-power circuit; Hardware architecture; Algorithm-architecture co-design; Computer Science; Electrical Engineering; Engineering; Science

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zheng, N. (2017). Algorithm/Architecture Co-Design for Low-Power Neuromorphic Computing. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/144149

Chicago Manual of Style (16th Edition):

Zheng, Nan. “Algorithm/Architecture Co-Design for Low-Power Neuromorphic Computing.” 2017. Doctoral Dissertation, University of Michigan. Accessed September 19, 2019. http://hdl.handle.net/2027.42/144149.

MLA Handbook (7th Edition):

Zheng, Nan. “Algorithm/Architecture Co-Design for Low-Power Neuromorphic Computing.” 2017. Web. 19 Sep 2019.

Vancouver:

Zheng N. Algorithm/Architecture Co-Design for Low-Power Neuromorphic Computing. [Internet] [Doctoral dissertation]. University of Michigan; 2017. [cited 2019 Sep 19]. Available from: http://hdl.handle.net/2027.42/144149.

Council of Science Editors:

Zheng N. Algorithm/Architecture Co-Design for Low-Power Neuromorphic Computing. [Doctoral Dissertation]. University of Michigan; 2017. Available from: http://hdl.handle.net/2027.42/144149


University of Michigan

2. Mendrela, Adam. Bidirectional Neural Interface Circuits with On-Chip Stimulation Artifact Reduction Schemes.

Degree: PhD, Electrical Engineering, 2018, University of Michigan

Bidirectional neural interfaces are tools designed to “communicate” with the brain via recording and modulation of neuronal activity. The bidirectional interface systems have been adopted for many applications. Neuroscientists employ them to map neuronal circuits through precise stimulation and recording. Medical doctors deploy them as adaptable medical devices which control therapeutic stimulation parameters based on monitoring real-time neural activity. Brain-machine-interface (BMI) researchers use neural interfaces to bypass the nervous system and directly control neuroprosthetics or brain-computer-interface (BCI) spellers. In bidirectional interfaces, the implantable transducers as well as the corresponding electronic circuits and systems face several challenges. A high channel count, low power consumption, and reduced system size are desirable for potential chronic deployment and wider applicability. Moreover, a neural interface designed for robust closed-loop operation requires the mitigation of stimulation artifacts which corrupt the recorded signals. This dissertation introduces several techniques targeting low power consumption, small size, and reduction of stimulation artifacts. These techniques are implemented for extracellular electrophysiological recording and two stimulation modalities: direct current stimulation for closed-loop control of seizure detection/quench and optical stimulation for optogenetic studies. While the two modalities differ in their mechanisms, hardware implementation, and applications, they share many crucial system-level challenges. The first method aims at solving the critical issue of stimulation artifacts saturating the preamplifier in the recording front-end. To prevent saturation, a novel mixed-signal stimulation artifact cancellation circuit is devised to subtract the artifact before amplification and maintain the standard input range of a power-hungry preamplifier. Additional novel techniques have been also implemented to lower the noise and power consumption. A common average referencing (CAR) front-end circuit eliminates the cross-channel common mode noise by averaging and subtracting it in analog domain. A range-adapting SAR ADC saves additional power by eliminating unnecessary conversion cycles when the input signal is small. Measurements of an integrated circuit (IC) prototype demonstrate the attenuation of stimulation artifacts by up to 42 dB and cross-channel noise suppression by up to 39.8 dB. The power consumption per channel is maintained at 330 nW, while the area per channel is only 0.17 mm2. The second system implements a compact headstage for closed-loop optogenetic stimulation and electrophysiological recording. This design targets a miniaturized form factor, high channel count, and high-precision stimulation control suitable for rodent in-vivo optogenetic studies. Monolithically integrated optoelectrodes (which include 12 µLEDs for optical stimulation and 12 electrical recording sites) are combined with an off-the-shelf recording IC and a custom-designed… Advisors/Committee Members: Flynn, Michael (committee member), Yoon, Euisik (committee member), Ahmed, Omar Jamil (committee member), Seymour, John Paul (committee member), Wise, Kensall D (committee member).

Subjects/Keywords: neural interface; optogenetics; mixed-signal IC; electrophysiology; Electrical Engineering; Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mendrela, A. (2018). Bidirectional Neural Interface Circuits with On-Chip Stimulation Artifact Reduction Schemes. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/147674

Chicago Manual of Style (16th Edition):

Mendrela, Adam. “Bidirectional Neural Interface Circuits with On-Chip Stimulation Artifact Reduction Schemes.” 2018. Doctoral Dissertation, University of Michigan. Accessed September 19, 2019. http://hdl.handle.net/2027.42/147674.

MLA Handbook (7th Edition):

Mendrela, Adam. “Bidirectional Neural Interface Circuits with On-Chip Stimulation Artifact Reduction Schemes.” 2018. Web. 19 Sep 2019.

Vancouver:

Mendrela A. Bidirectional Neural Interface Circuits with On-Chip Stimulation Artifact Reduction Schemes. [Internet] [Doctoral dissertation]. University of Michigan; 2018. [cited 2019 Sep 19]. Available from: http://hdl.handle.net/2027.42/147674.

Council of Science Editors:

Mendrela A. Bidirectional Neural Interface Circuits with On-Chip Stimulation Artifact Reduction Schemes. [Doctoral Dissertation]. University of Michigan; 2018. Available from: http://hdl.handle.net/2027.42/147674


University of Michigan

3. Sandoughsaz Zardini, Seyed Amin. Sea of Electrodes Array (SEA): Customizable 3D High-Density High-Count Neural Probe Array Technology.

Degree: PhD, Electrical Engineering, 2019, University of Michigan

Accurate mapping of neural circuits and interfacing with neurons for control of brain-machine interfaces require simultaneous large-scale and high spatiotemporal resolution recordings and stimulation of neurons in multiple layers and areas of the brain. Conventional penetrating micro-electrode arrays (MEAs) are limited to a few thousand electrodes at best, with limited volumetric 3D spatial resolution. This is mainly due to the types of fabrication technologies and available designs and materials for making such probes. Based on the strengths and shortcomings of the available MEAs, we present a new fabrication technology for a new class of 3D neural electrode array that provides the characteristics of a near-ideal neural interface. This research addresses some of the limitations of previous works in terms of electrode scale, density and spatial coverage (depth and span). In order to realize a scalable 3D out-of-plane array of extremely dense, slender, and sharp needles with recording sites at each of their tips, a number of techniques are developed. These includes: 1- A custom-developed silicon DRIE process to make deep (500 µm) high aspect-ratio (20-30) thru-wafer holes with controlled sidewall slope, 2- A method of extending the thru-wafer holes depth by aligning and then fusion bonding multiple silicon substrates already having holes etched in them, 3- A process for conformal refilling of ultra-deep (~2 mm) ultra-high aspect-ratio (80-100) holes with dielectric and conductive films using LPCVD process, 4- Methods of forming recording sites using self-aligned mask-less metallization processes, and 5- A method based on wet silicon etching to dissolve away the support substrate containing the refilled holes to release the electrodes. Using these technologies, we have fabricated millimeter-long (1.2mm), narrow (10-20µm diameter), sharp (submicron tip size), high-density (400 electrodes/mm2) high-count (5000+) silicon electrode arrays. Electrodes robustness, insertion and recording functionality have been demonstrated by acute in vivo recordings in rats under anesthesia using 2×2 and 3×3 arrays, where local field potentials (LFP) have been recorded. Innovative features of this technology could be utilized to produce arrays with arbitrary 3D design to target specific brain structures to achieve 3D spatial coverage over the convoluted topography of the brain. These include: 1- Length of side-by-side electrodes can be varied from tens of microns to several millimeters independently. 2- Electrodes spacing can be modified by the designer to obtain a desirable density and distribution of the array needles. 3- Electrode cross-sectional size can be controlled to obtain extremely fine, sharp and slender needles, crucial for minimizing tissue damage and improving chronic stability of implanted probes. 4- Any desired distribution of electrodes with customizable length, diameter and pitch across the array can be obtained to realize near-ideal application-specific neural probes. Potential capabilities of this work are… Advisors/Committee Members: Najafi, Khalil (committee member), Ahmed, Omar Jamil (committee member), Gianchandani, Yogesh B (committee member), Wise, Kensall D (committee member).

Subjects/Keywords: Electrode Array; Neural Interface; MEMS; Brain-Machine Interfaces; Neural Probe; Neural Recording and Stimulation; Electrical Engineering; Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Sandoughsaz Zardini, S. A. (2019). Sea of Electrodes Array (SEA): Customizable 3D High-Density High-Count Neural Probe Array Technology. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/149834

Chicago Manual of Style (16th Edition):

Sandoughsaz Zardini, Seyed Amin. “Sea of Electrodes Array (SEA): Customizable 3D High-Density High-Count Neural Probe Array Technology.” 2019. Doctoral Dissertation, University of Michigan. Accessed September 19, 2019. http://hdl.handle.net/2027.42/149834.

MLA Handbook (7th Edition):

Sandoughsaz Zardini, Seyed Amin. “Sea of Electrodes Array (SEA): Customizable 3D High-Density High-Count Neural Probe Array Technology.” 2019. Web. 19 Sep 2019.

Vancouver:

Sandoughsaz Zardini SA. Sea of Electrodes Array (SEA): Customizable 3D High-Density High-Count Neural Probe Array Technology. [Internet] [Doctoral dissertation]. University of Michigan; 2019. [cited 2019 Sep 19]. Available from: http://hdl.handle.net/2027.42/149834.

Council of Science Editors:

Sandoughsaz Zardini SA. Sea of Electrodes Array (SEA): Customizable 3D High-Density High-Count Neural Probe Array Technology. [Doctoral Dissertation]. University of Michigan; 2019. Available from: http://hdl.handle.net/2027.42/149834

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