peer-reviewed

Today’s automation and control networks are typically viewed as networks of devices and the necessary software developed piecemeal from each individual device’s perspective. The IEC 61499 standard defines a generic architecture and presents guidelines for the use of function blocks in distributed industrial-process measurement and control systems. With IEC 61499, systems are modelled as networks of function blocks. Application models are constructed independent of the resources to which they will ultimately be deployed. Deployment models describe how application models should be divided up amongst the resources of the network. IEC 61499 applications can be constructed as layers of functionality and deployments can then be constructed as compositions of those layers. IEC 61499 solutions can be modelled independent of their physical realisation resulting in great re-usability of design artefacts. An embedded solution comprises one or more embedded devices which when configured and deployed in unison serve to deliver the solution to some higher level requirement. Furthermore, it is quite common for devices to be internally composed of one or more micro-processors and/or one or more Field Programmable Gate Arrays (FPGAs). The processors themselves may even be composed of multiple processor cores and the FPGAs may include one or more so called soft processor cores. The author proposes that such systems can be viewed as networks of resources and that IEC 61499 based techniques can be applied in the development of embedded systems at both the network level and at the device level. A platform facilitating the design and implementation of embedded systems using IEC 61499 models is presented herein. This platform makes it easy to create a model, perform initial simulation or testing on a PC and subsequently deploy it to an embedded target. Furthermore, the embedded target can be changed, altered, modified, etc. and the solution redeployed with the absolute minimum of effort. The presented platform allows IEC 61499 models to be deployed as homogenous or heterogeneous networks of devices and computing technologies. Models can be deployed to a single hardware platform, e.g. an embedded microprocessor or a PC. Alternatively, they can be distributed across multiple different hardware platforms, e.g. part of the solution on an FPGA and part of the solution on a microprocessor. The presented platform consists of an IEC 61499 editor, a compiler toolchain and a runtime engine. Central to this platform is a proposed new architecture allowing IEC 61499 models to be deployed as custom logic within an FPGA, as software on various micro-processors and operating systems, or as a mixture of both. Any IEC 61499 compliant editor can be used to construct application models. The compiler toolchain converts these application models to their custom logic and/or software equivalent representation. For a pure custom logic solution, the compiler’s output consists of a set of source modules and an FPGA tool specific project…

peer-reviewed

This thesis is concerned with the development of a novel technical solution that is aimed to improve the quality of cable crimp terminations in the electronics industry. The automotive, aero and military vehicle industries are of special interest due to their stringent requirements for guaranteed quality assurances in relation to their safety-critical products. The emphasis is on handheld crimping tools, where a new scheme for measuring the relevant crimp force is proposed using a small embedded computer to process information; so as to make an on-instrument statement regarding the crimp process quality. The thesis includes a detailed review of the current technical practices in the cable termination business, with a particular emphasis on the quality estimations for crimped connections using the crimp force monitoring (CFM) scheme. A comprehensive study of the state-of-the-art crimp force monitoring schemes and technologies is presented. A gap in the tool chain is identified whereby the industry has a preference for the use of hand tools in some selected processes; but the CFM scheme cannot be currently integrated directly with such hand tools. The bulk of the work in this thesis is thus focused on the development of a technical solution that will address this need for integration of hand tools with the CFM scheme. The concept is to develop a fully embedded subsystem that can be attached directly to a hand tool and this system will perform all of the signal processing and the statistical analysis so that each crimped joint can be trusted to meet the relevant stated quality parameters. In the course of development work a fully functional prototype subsystem is developed for the CFM solution, for application to hand tools. Analytical and statistical measurement and assessment algorithms were developed to a standard, which allows a final quality rating to be applied to crimped joint connections. Such algorithms are designed to be embedded directly onto the instrument’s microcomputer. The new system has been evaluated and tested in the course of this research project and it has currently been accepted by a number of industries for a planned volume qualification assessment.

peer-reviewed

Networked control systems have been widely used in Industrial Automation since the latter part of the 20st century. Such networks have evolved from small systems with proprietary and slow Fieldbus technology to a much larger scope. Today, Ethernet-based automation systems encompass whole factories and carry large amounts of data traffic with differing latency requirements. Proprietary real-time Ethernet technologies such as Profinet IRT (Isochronous Real-Time) have demonstrated the feasibility of real-time Ethernet for even the most demanding applications such as functional safety and motion control. The drawback of these vendor-specific solutions is their dependence on proprietary ASICs (Application-Specific Integrated Circuit) and their very limited compatibility to standard Ethernet and Bridging as defined by IEEE (Institute of Electrical and Electronics Engineers) 802.3 and IEEE 802.1. Up to the present day, this has limited the widespread success of Ethernet as a real-time network solution. With the emerging AVB (Audio- and Video Bridging) technology, IEEE 802.1 has defined the first vendor-neutral real-time Ethernet, enabling the possibility of a standardised solution for Industrial Automation. However, the home automation scope in which AVB was developed leaves large feature gaps that prevent its adoption in mission-critical systems, for example the lack in support for faulttolerance technologies that are specific to Industrial Automation. These networks require built-in redundancy to prevent critical failures. While industrial-grade redundancy technologies are designed to support mission-critical automation with standard Ethernet, their combined usage with AVB mechanisms fails to meet many application requirements. This research work, carried out for the Advanced Development department of Hirschmann Automation & Control GmbH, investigates methods to enhance IEEE 802.1 AVB so it can be better used in networks that have firm fault-tolerance requirements. A requirement of particular interest is to enhance AVB so it can interoperate with any arbitrary and application-specific fault tolerance technology, so as to maximise its reach into new application domains. This work proposes an enhancement to the AVB Stream Reservation Protocol (SRP) to enable it to register communication streams over multiple network paths simultaneously. To verify the feasibility of the proposal, the protocol enhancement is implemented and verified by simulation within a detailed model of an Industrial Ethernet network. This simulation contains Ethernet switch and protocol models with behaviours and parameters that are based on existing products and specifications. This helps to ensure that the simulation results carry significance for real-world behaviour. This research also investigates the specific protocol requirements that are needed for the feasible use of the proposed solutions in future real-time network design, such as optimal methods to influence stream paths in relation to…

peer-reviewed

The hypothesis of this research is that new techniques are required to facilitate software verification on the highly-integrated, but resource constrained, real-time embedded systems; which are widely used in safety-critical applications. Software verification is an essential but expensive undertaking which often consumes as much or more resources than design activities; this is particularly the case in embedded systems that require functional safety. This research explores the existing techniques for software verification on these systems and the verification challenges posed by modern highly-integrated devices. The author then proposes a novel target-level verification approach which addresses some of these challenges. Advances in semiconductor manufacturing processes have fuelled the relentless shrinking of IC design geometries. This has dramatically reduced the area required for each functional block, reduced costs, and allowed more complex circuits to be realised; which has led to the System-on-Chip (SoC) designs which now include multiple processors within a single die. Undoubtedly many benefits result from this increased integration, but one significant drawback is the loss of access to the many signals indicating the internal operational state. Visibility of these signals is essential for many embedded software verification purposes. In parallel with increasing SoC complexity, verification technology has transformed from using full in-circuit emulation, to bond-out devices, to on-chip instrumentation (OCI), each providing less visibility to the execution state of the processor. A key benefit of OCI approaches is the associated reduced physical interface requirements; unfortunately this also limits the real-time data that can be captured and transferred to external analysis tools. The author proposes the alternative of using this OCI in conjunction with a co-processor to perform monitoring and verification tasks on-chip; thus overcoming the interface limitations and enhancing visibility. The experimental platform used to explore the feasibility of using a co-processor and OCI for software verification activities is described; and several case studies are examined. The results demonstrate that this approach does offer a means of addressing several software verification challenges and provides some unique capabilities, but also has some limitations. These benefits and limitations are discussed and suggestions for future work to advance this research topic are provided.

Non-peer-reviewed

Reliability prediction of a software product is complex due to interdependencies and interactions among components and the difficulty of representing this behavior with tractable models. Models developed by making simplifying assumptions about the software structure may be simple to use but their result may be far from what happens in reality. Making assumptions closer to reality that allows complex interactions and interdependences among components results in models that are too complex to use and/or their results may be too difficult to interpret. The reliability predication problem is aggravated by the absence of precise information on the behavior of components and their interactions, information that is relevant for reliability modeling. Usually, the interactions are not known precisely because of subtle undocumented side effects. Without accurate precise information, even mathematically correct models will not yield accurate reliability predications. Deriving the necessary information from program code is not practical if not impossible because the code contains too much implementation detail to be useful in creating a tractable model and because it is difficult to fully analyze. This author approached the problem from three tracks: 1. Identifying design imperatives that will make the system behavior easier to predict 2. Identifying mathematical documentation techniques to describe the behavior of software systems 3. Adapting structural reliability modeling techniques to predict the reliability of software systems based on their mathematical description This thesis documents the resulting novel approach of designing, specifying, and describing the behavior of software systems in a way that helps to predict their reliability from the reliability of the components and their interactions. The design approach, which the author names design for reliability redictability (DRP), integrates design for change, precise behavioral documentation and structure based reliability prediction to achieve improved reliability prediction of software systems. The specification and documentation approach builds upon precise behavioral specification of interfaces using the trace function method (TFM) and introduces a number of connection documents or structure functions. These functions capture both the static and dynamic behaviors of component based software systems and are used as a basis for a novel document driven structure based reliability predication model. System reliability assessment is studied in at least three levels: component reliability, which is assumed to be known, interaction reliability, a novel approach in studying software reliability and service reliability, whose estimation is the primary objective of reliability assessment. The approach is applied successfully as a case study in the construction of an industrial product which is described in this thesis.

peer-reviewed

Trusted Computing is a relatively new approach to computer security in which a system should be permanently maintained in a well-defined state - and therefore it will reside in a trustworthy state. The word "trustworthy" in this context means that the system always behaves in a specific way as defined by the platform manufacturer and/or the administrator/owner. A key element of this approach is to employ a security module, which is implemented in hardware, and which is tied to the platform so as to serve as a trust anchor. Based on that ’root of trust’ and other features, an effective security architecture is proposed in this research. Virtualization techniques, which were formerly developed for server consolidation, cost reduction, and conservation of energy are now gaining more and more interest in the field of trusted computing. Virtualization can greatly enhance the security of a system by isolating applications, or even whole operating systems, by splitting the computer system into smaller parts, whose integrity can be more easily assured. This project is concerned with the development of a system that will effectively combine the isolation features of the virtualization schemes with a state-of-the-art hardware security module. This system will provide reliable protection against sophisticated software-based attacks and will withstand elementary hardware-based attacks. The building block approach of this proposed security architecture makes sure that many different application fields can archive a high level of security by combining the appropriate components. The research examines some emerging approaches to computer security and proposes a novel security architecture based on a hardware trust anchor. An experimental system is developed to provide a ’proof-of-concept’ model for evaluation. The target application area for the architecture is the embedded computing space, in particular x86 based architectures. The selection of hardware elements and the choice of hypervisor are discussed and justified. The assumptions on the features of the architecture are evaluated and validated in the context of potential security improvements. Future research in this niche area is proposed.