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You searched for +publisher:"University of Illinois – Urbana-Champaign" +contributor:("Wong, Martin D. F."). Showing records 1 – 17 of 17 total matches.

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University of Illinois – Urbana-Champaign

1. Chang, Yun Wei. Single-layer bus routing for high-speed boards.

Degree: MS, 1200, 2012, University of Illinois – Urbana-Champaign

 As the clock frequencies used in industry increase, the timing requirements on high-speed boards become very tight. Since wire length is directly proportional to wire… (more)

Subjects/Keywords: Single Layer Bus; High-Speed Printed Circuit Board

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chang, Y. W. (2012). Single-layer bus routing for high-speed boards. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/29764

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chang, Yun Wei. “Single-layer bus routing for high-speed boards.” 2012. Thesis, University of Illinois – Urbana-Champaign. Accessed April 15, 2021. http://hdl.handle.net/2142/29764.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chang, Yun Wei. “Single-layer bus routing for high-speed boards.” 2012. Web. 15 Apr 2021.

Vancouver:

Chang YW. Single-layer bus routing for high-speed boards. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2012. [cited 2021 Apr 15]. Available from: http://hdl.handle.net/2142/29764.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chang YW. Single-layer bus routing for high-speed boards. [Thesis]. University of Illinois – Urbana-Champaign; 2012. Available from: http://hdl.handle.net/2142/29764

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

2. Lai, Tin-Yin. An efficient and accurate timing macro-modeling algorithm for large hierarchical designs.

Degree: MS, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign

 Ever-increasing circuit design complexity is driving the need for fast and accurate macro-modeling algorithms to accelerate hierarchical timing. We introduce LibAbs, an effective macro-modeling algorithm… (more)

Subjects/Keywords: Timing macro-modeling; Algorithm; Timing analysis

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APA (6th Edition):

Lai, T. (2017). An efficient and accurate timing macro-modeling algorithm for large hierarchical designs. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/98236

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lai, Tin-Yin. “An efficient and accurate timing macro-modeling algorithm for large hierarchical designs.” 2017. Thesis, University of Illinois – Urbana-Champaign. Accessed April 15, 2021. http://hdl.handle.net/2142/98236.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lai, Tin-Yin. “An efficient and accurate timing macro-modeling algorithm for large hierarchical designs.” 2017. Web. 15 Apr 2021.

Vancouver:

Lai T. An efficient and accurate timing macro-modeling algorithm for large hierarchical designs. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2017. [cited 2021 Apr 15]. Available from: http://hdl.handle.net/2142/98236.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lai T. An efficient and accurate timing macro-modeling algorithm for large hierarchical designs. [Thesis]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/98236

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

3. Lin, Chun-Xun. Advances in parallel programming for electronic design automation.

Degree: PhD, Electrical & Computer Engr, 2020, University of Illinois – Urbana-Champaign

 The continued miniaturization of the technology node increases not only the chip capacity but also the circuit design complexity. How does one efficiently design a… (more)

Subjects/Keywords: Electronic design automation; Parallel programming

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APA (6th Edition):

Lin, C. (2020). Advances in parallel programming for electronic design automation. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/108425

Chicago Manual of Style (16th Edition):

Lin, Chun-Xun. “Advances in parallel programming for electronic design automation.” 2020. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed April 15, 2021. http://hdl.handle.net/2142/108425.

MLA Handbook (7th Edition):

Lin, Chun-Xun. “Advances in parallel programming for electronic design automation.” 2020. Web. 15 Apr 2021.

Vancouver:

Lin C. Advances in parallel programming for electronic design automation. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2020. [cited 2021 Apr 15]. Available from: http://hdl.handle.net/2142/108425.

Council of Science Editors:

Lin C. Advances in parallel programming for electronic design automation. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2020. Available from: http://hdl.handle.net/2142/108425


University of Illinois – Urbana-Champaign

4. Yan, Tan. Algorithmic studies on PCB routing.

Degree: PhD, 1200, 2011, University of Illinois – Urbana-Champaign

 As IC technology advances, the package size keeps shrinking while the pin count of a package keeps increasing. A modern IC package can have a… (more)

Subjects/Keywords: Algorithm; printed circuit board (PCB) routing; Escape routing; Length-matching routing; Length-constrained routing; Layer assignment; Network flow; Pin Grid Array; Ball Grid Array

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APA (6th Edition):

Yan, T. (2011). Algorithmic studies on PCB routing. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/18367

Chicago Manual of Style (16th Edition):

Yan, Tan. “Algorithmic studies on PCB routing.” 2011. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed April 15, 2021. http://hdl.handle.net/2142/18367.

MLA Handbook (7th Edition):

Yan, Tan. “Algorithmic studies on PCB routing.” 2011. Web. 15 Apr 2021.

Vancouver:

Yan T. Algorithmic studies on PCB routing. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2011. [cited 2021 Apr 15]. Available from: http://hdl.handle.net/2142/18367.

Council of Science Editors:

Yan T. Algorithmic studies on PCB routing. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2011. Available from: http://hdl.handle.net/2142/18367


University of Illinois – Urbana-Champaign

5. Huang, Tsung-Wei. Distributed timing analysis.

Degree: PhD, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign

 As design complexities continue to grow larger, the need to efficiently analyze circuit timing with billions of transistors across multiple modes and corners is quickly… (more)

Subjects/Keywords: Distributed systems; Timing analysis

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APA (6th Edition):

Huang, T. (2017). Distributed timing analysis. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/99302

Chicago Manual of Style (16th Edition):

Huang, Tsung-Wei. “Distributed timing analysis.” 2017. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed April 15, 2021. http://hdl.handle.net/2142/99302.

MLA Handbook (7th Edition):

Huang, Tsung-Wei. “Distributed timing analysis.” 2017. Web. 15 Apr 2021.

Vancouver:

Huang T. Distributed timing analysis. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2017. [cited 2021 Apr 15]. Available from: http://hdl.handle.net/2142/99302.

Council of Science Editors:

Huang T. Distributed timing analysis. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/99302


University of Illinois – Urbana-Champaign

6. Lin, Chen-Hsuan. Design automation for circuit reliability and energy efficiency.

Degree: PhD, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign

 This dissertation presents approaches to improve circuit reliability and energy efficiency from different angles, such as verification, logic synthesis, and functional unit design. A variety… (more)

Subjects/Keywords: Electronic design automation; Reliability; Energy efficiency; Data mining; Satisfiability (SAT) solving; Logic restructuring; Assertion; Negative bias temperature instability (NBTI) effect; Modulo arithmetic; Shadow datapath

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APA (6th Edition):

Lin, C. (2017). Design automation for circuit reliability and energy efficiency. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/99237

Chicago Manual of Style (16th Edition):

Lin, Chen-Hsuan. “Design automation for circuit reliability and energy efficiency.” 2017. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed April 15, 2021. http://hdl.handle.net/2142/99237.

MLA Handbook (7th Edition):

Lin, Chen-Hsuan. “Design automation for circuit reliability and energy efficiency.” 2017. Web. 15 Apr 2021.

Vancouver:

Lin C. Design automation for circuit reliability and energy efficiency. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2017. [cited 2021 Apr 15]. Available from: http://hdl.handle.net/2142/99237.

Council of Science Editors:

Lin C. Design automation for circuit reliability and energy efficiency. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/99237

7. Du, Yuelin. Characterization of the Performance Variation for Regular Standard Cells with Process Non-idealities.

Degree: MS, 1200, 2011, University of Illinois – Urbana-Champaign

 In IC manufacturing, the performance of standard cells often varies due to process non-idealities. Some research work on 2-D cell characterization shows that the timing… (more)

Subjects/Keywords: 1-D Patterning; Dense Line Printing; Standard Cell Characterization

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APA (6th Edition):

Du, Y. (2011). Characterization of the Performance Variation for Regular Standard Cells with Process Non-idealities. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/24335

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Du, Yuelin. “Characterization of the Performance Variation for Regular Standard Cells with Process Non-idealities.” 2011. Thesis, University of Illinois – Urbana-Champaign. Accessed April 15, 2021. http://hdl.handle.net/2142/24335.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Du, Yuelin. “Characterization of the Performance Variation for Regular Standard Cells with Process Non-idealities.” 2011. Web. 15 Apr 2021.

Vancouver:

Du Y. Characterization of the Performance Variation for Regular Standard Cells with Process Non-idealities. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2011. [cited 2021 Apr 15]. Available from: http://hdl.handle.net/2142/24335.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Du Y. Characterization of the Performance Variation for Regular Standard Cells with Process Non-idealities. [Thesis]. University of Illinois – Urbana-Champaign; 2011. Available from: http://hdl.handle.net/2142/24335

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

8. Han, Khine. Shape Approximation of Printed Images in VLSI Design.

Degree: MS, Electrical and Computer Engineering, 2009, University of Illinois – Urbana-Champaign

 Despite application of optical proximity correction (OPC) and resolution enhancement techniques (RET) to improve printing, limitations in lithography and manufacturing processes still lead to undesirable… (more)

Subjects/Keywords: vlsi; polygon; approximation

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APA (6th Edition):

Han, K. (2009). Shape Approximation of Printed Images in VLSI Design. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/11990

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Han, Khine. “Shape Approximation of Printed Images in VLSI Design.” 2009. Thesis, University of Illinois – Urbana-Champaign. Accessed April 15, 2021. http://hdl.handle.net/2142/11990.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Han, Khine. “Shape Approximation of Printed Images in VLSI Design.” 2009. Web. 15 Apr 2021.

Vancouver:

Han K. Shape Approximation of Printed Images in VLSI Design. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2009. [cited 2021 Apr 15]. Available from: http://hdl.handle.net/2142/11990.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Han K. Shape Approximation of Printed Images in VLSI Design. [Thesis]. University of Illinois – Urbana-Champaign; 2009. Available from: http://hdl.handle.net/2142/11990

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

9. Luo, Lijuan. New strategies for electronic design automation problems.

Degree: PhD, 1200, 2011, University of Illinois – Urbana-Champaign

 As the semiconductor industry marches towards 22 nm technology and beyond, circuit design has become unprecedentedly omplicated. This presents many new challenges for EDA (electronic… (more)

Subjects/Keywords: printed circuit board (PCB) routing; escape routing; Boolean satisfiability; graphics processing unit (GPU); CUDA; breadth-first search; R-tree

Page 1 Page 2 Page 3 Page 4 Page 5 Page 6 Page 7 Sample image

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APA (6th Edition):

Luo, L. (2011). New strategies for electronic design automation problems. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/24504

Chicago Manual of Style (16th Edition):

Luo, Lijuan. “New strategies for electronic design automation problems.” 2011. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed April 15, 2021. http://hdl.handle.net/2142/24504.

MLA Handbook (7th Edition):

Luo, Lijuan. “New strategies for electronic design automation problems.” 2011. Web. 15 Apr 2021.

Vancouver:

Luo L. New strategies for electronic design automation problems. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2011. [cited 2021 Apr 15]. Available from: http://hdl.handle.net/2142/24504.

Council of Science Editors:

Luo L. New strategies for electronic design automation problems. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2011. Available from: http://hdl.handle.net/2142/24504

10. Kong, Hui. New strategies for PCB routing.

Degree: PhD, 1200, 2011, University of Illinois – Urbana-Champaign

 As IC technology advances rapidly, the dimensions of packages and PCBs are decreasing while the pin counts and routing layers keep increasing. Today, a high-performance… (more)

Subjects/Keywords: Circuits; Algorithms; Printed Circuit Board (PCB) Routing

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APA (6th Edition):

Kong, H. (2011). New strategies for PCB routing. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/18462

Chicago Manual of Style (16th Edition):

Kong, Hui. “New strategies for PCB routing.” 2011. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed April 15, 2021. http://hdl.handle.net/2142/18462.

MLA Handbook (7th Edition):

Kong, Hui. “New strategies for PCB routing.” 2011. Web. 15 Apr 2021.

Vancouver:

Kong H. New strategies for PCB routing. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2011. [cited 2021 Apr 15]. Available from: http://hdl.handle.net/2142/18462.

Council of Science Editors:

Kong H. New strategies for PCB routing. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2011. Available from: http://hdl.handle.net/2142/18462

11. Konigsmark, Sven Tenzing Choden. Hardware security design from circuits to systems.

Degree: PhD, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign

 The security of hardware implementations is of considerable importance, as even the most secure and carefully analyzed algorithms and protocols can be vulnerable in their… (more)

Subjects/Keywords: Hardware security; Physically unclonable function; Hardware Trojan horse; Authentication; Invasive attacks; Carbon nanotubes

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APA (6th Edition):

Konigsmark, S. T. C. (2017). Hardware security design from circuits to systems. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/97659

Chicago Manual of Style (16th Edition):

Konigsmark, Sven Tenzing Choden. “Hardware security design from circuits to systems.” 2017. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed April 15, 2021. http://hdl.handle.net/2142/97659.

MLA Handbook (7th Edition):

Konigsmark, Sven Tenzing Choden. “Hardware security design from circuits to systems.” 2017. Web. 15 Apr 2021.

Vancouver:

Konigsmark STC. Hardware security design from circuits to systems. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2017. [cited 2021 Apr 15]. Available from: http://hdl.handle.net/2142/97659.

Council of Science Editors:

Konigsmark STC. Hardware security design from circuits to systems. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/97659


University of Illinois – Urbana-Champaign

12. Hwang, Leslie K. Stochastic shortest path algorithm based on Lagrangian relaxation.

Degree: MS, 1200, 2010, University of Illinois – Urbana-Champaign

 In VLSI circuit design, graph algorithms are widely used and graph structure can model many problems. As technology continues to scale into nanometer design, the… (more)

Subjects/Keywords: Stochastic shortest path; Variation; Lagrangian relaxation

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APA (6th Edition):

Hwang, L. K. (2010). Stochastic shortest path algorithm based on Lagrangian relaxation. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/16806

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hwang, Leslie K. “Stochastic shortest path algorithm based on Lagrangian relaxation.” 2010. Thesis, University of Illinois – Urbana-Champaign. Accessed April 15, 2021. http://hdl.handle.net/2142/16806.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hwang, Leslie K. “Stochastic shortest path algorithm based on Lagrangian relaxation.” 2010. Web. 15 Apr 2021.

Vancouver:

Hwang LK. Stochastic shortest path algorithm based on Lagrangian relaxation. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2010. [cited 2021 Apr 15]. Available from: http://hdl.handle.net/2142/16806.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hwang LK. Stochastic shortest path algorithm based on Lagrangian relaxation. [Thesis]. University of Illinois – Urbana-Champaign; 2010. Available from: http://hdl.handle.net/2142/16806

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

13. Hsu, Chih-Wei. Solving Automated Planning Problems with Parallel Decomposition.

Degree: PhD, 0112, 2012, University of Illinois – Urbana-Champaign

 In this dissertation, we present a parallel decomposition method to address the complexity of solving automated planning problems. We have found many planning problems have… (more)

Subjects/Keywords: Planning; Scheduling; Parallel Decomposition; Action Partitioning Heuristic Search

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APA (6th Edition):

Hsu, C. (2012). Solving Automated Planning Problems with Parallel Decomposition. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/29488

Chicago Manual of Style (16th Edition):

Hsu, Chih-Wei. “Solving Automated Planning Problems with Parallel Decomposition.” 2012. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed April 15, 2021. http://hdl.handle.net/2142/29488.

MLA Handbook (7th Edition):

Hsu, Chih-Wei. “Solving Automated Planning Problems with Parallel Decomposition.” 2012. Web. 15 Apr 2021.

Vancouver:

Hsu C. Solving Automated Planning Problems with Parallel Decomposition. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2012. [cited 2021 Apr 15]. Available from: http://hdl.handle.net/2142/29488.

Council of Science Editors:

Hsu C. Solving Automated Planning Problems with Parallel Decomposition. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2012. Available from: http://hdl.handle.net/2142/29488

14. Huang, Pingli. SHA-less pipeline ADC design with sampling clock skew calibration.

Degree: PhD, 1200, 2012, University of Illinois – Urbana-Champaign

 The power efficiency of pipeline analog-to-digital converters (ADCs) can be substantially improved by eliminating the front-end sample-and-hold amplifier (SHA). However, in a SHA-less architecture the… (more)

Subjects/Keywords: Sample-and-hold amplifier (SHA); SHA-less; pipelined ADC; multi-bit pipeline architecture; sampling clock skew; skew calibration.; analog-to-digital converters (ADCs)

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APA (6th Edition):

Huang, P. (2012). SHA-less pipeline ADC design with sampling clock skew calibration. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/29565

Chicago Manual of Style (16th Edition):

Huang, Pingli. “SHA-less pipeline ADC design with sampling clock skew calibration.” 2012. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed April 15, 2021. http://hdl.handle.net/2142/29565.

MLA Handbook (7th Edition):

Huang, Pingli. “SHA-less pipeline ADC design with sampling clock skew calibration.” 2012. Web. 15 Apr 2021.

Vancouver:

Huang P. SHA-less pipeline ADC design with sampling clock skew calibration. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2012. [cited 2021 Apr 15]. Available from: http://hdl.handle.net/2142/29565.

Council of Science Editors:

Huang P. SHA-less pipeline ADC design with sampling clock skew calibration. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2012. Available from: http://hdl.handle.net/2142/29565

15. Campbell, Keith A. Robust and reliable hardware accelerator design through high-level synthesis.

Degree: PhD, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign

 System-on-chip design is becoming increasingly complex as technology scaling enables more and more functionality on a chip. This scaling-driven complexity has resulted in a variety… (more)

Subjects/Keywords: High-level synthesis (HLS); Automation; Error detection; Scheduling; Binding; Compiler transformation; Compiler optimization; Pipelining; Modulo arithmetic; Modulo-3; Logic optimization; State machine; Datapath; Control logic; Shadow datapath; Modulo datapath; Low cost; High performance; Electrical bug; Aliasing; Stuck-at fault; Soft error; Timing error; Checkpointing; Rollback; Recovery; Pre-silicon validation; Post-silicon validation; Pre-silicon debug; Post-silicon debug; Accelerator; System on a chip; Signature generation; Execution signature; Execution hash; Logic bug; Nondeterministic bug; Masked error; Circuit reliability; Hot spot; Wear out; Silent data corruption; Observability; Detection latency; Mixed datapath; Diversity; Checkpoint corruption; Error injection; Error removal; Quick Error Detection (QED); Hybrid Quick Error Detection (H-QED); Instrumentation; Hybrid co-simulation; Hardware/software; Integration testing; Hybrid tracing; Hybrid hashing; Source-code localization; Software debugging tool; Valgrind; Clang sanitizer; Clang static analyzer; Cppcheck; Root cause analysis; Execution tracing; Realtime error detection; Simulation trigger; Nonintrusive; Address conversion; Undefined behavior; High-level synthesis (HLS) bug; Detection coverage; Gate-level architecture; Mersenne modulus; Full adder; Half adder; Quarter adder; Wraparound; Modulo reducer; Modulo adder; Modulo multiplier; Modulo comparator; Cross-layer; Algorithm; Instruction; Architecture; Logic synthesis; Physical design; Algorithm-based fault tolerance (ABFT); Error detection by duplicated instructions (EDDI); Parity; Flip-flop hardening; Layout design through error-aware transistor positioning dual interlocked storage cell (LEAP-DICE); Cost-effective; Place-and-route; Field programmable gate array (FPGA) emulation; Application specific integrated circuit (ASIC); Field programmable gate array (FPGA); Energy; Area; Latency

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APA (6th Edition):

Campbell, K. A. (2017). Robust and reliable hardware accelerator design through high-level synthesis. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/99294

Chicago Manual of Style (16th Edition):

Campbell, Keith A. “Robust and reliable hardware accelerator design through high-level synthesis.” 2017. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed April 15, 2021. http://hdl.handle.net/2142/99294.

MLA Handbook (7th Edition):

Campbell, Keith A. “Robust and reliable hardware accelerator design through high-level synthesis.” 2017. Web. 15 Apr 2021.

Vancouver:

Campbell KA. Robust and reliable hardware accelerator design through high-level synthesis. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2017. [cited 2021 Apr 15]. Available from: http://hdl.handle.net/2142/99294.

Council of Science Editors:

Campbell KA. Robust and reliable hardware accelerator design through high-level synthesis. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/99294


University of Illinois – Urbana-Champaign

16. Ramachandran, Anand. Methodologies for Transient Simulation of Hybrid Electromagnetic/Circuit Systems with Multiple Time Scales.

Degree: PhD, Electrical and Computer Engineering, 2009, University of Illinois – Urbana-Champaign

 This work presents methodologies to facilitate the efficient cosimulation of electromagnetic/circuit systems while exploiting the multiple time scales that are often present in the numerical… (more)

Subjects/Keywords: Hybrid simulation; multiple time scales; FDTD; time domain methods; electromagnetic simulation

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ramachandran, A. (2009). Methodologies for Transient Simulation of Hybrid Electromagnetic/Circuit Systems with Multiple Time Scales. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/11977

Chicago Manual of Style (16th Edition):

Ramachandran, Anand. “Methodologies for Transient Simulation of Hybrid Electromagnetic/Circuit Systems with Multiple Time Scales.” 2009. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed April 15, 2021. http://hdl.handle.net/2142/11977.

MLA Handbook (7th Edition):

Ramachandran, Anand. “Methodologies for Transient Simulation of Hybrid Electromagnetic/Circuit Systems with Multiple Time Scales.” 2009. Web. 15 Apr 2021.

Vancouver:

Ramachandran A. Methodologies for Transient Simulation of Hybrid Electromagnetic/Circuit Systems with Multiple Time Scales. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2009. [cited 2021 Apr 15]. Available from: http://hdl.handle.net/2142/11977.

Council of Science Editors:

Ramachandran A. Methodologies for Transient Simulation of Hybrid Electromagnetic/Circuit Systems with Multiple Time Scales. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2009. Available from: http://hdl.handle.net/2142/11977


University of Illinois – Urbana-Champaign

17. Sun, Lin. An enhanced volume integral equation method and augmented equivalence principle algorithm for low frequency problems.

Degree: PhD, 1200, 2010, University of Illinois – Urbana-Champaign

 Two techniques based on integral equation methods are addressed. Firstly, a novel volume integral equation method is proposed to characterize the scattering properties of dielectric… (more)

Subjects/Keywords: Enhanced Volume Integral Equation Method; Equivalence Principle Algorithm; Augmentation Technique; Low Frequency Problems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Sun, L. (2010). An enhanced volume integral equation method and augmented equivalence principle algorithm for low frequency problems. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/15564

Chicago Manual of Style (16th Edition):

Sun, Lin. “An enhanced volume integral equation method and augmented equivalence principle algorithm for low frequency problems.” 2010. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed April 15, 2021. http://hdl.handle.net/2142/15564.

MLA Handbook (7th Edition):

Sun, Lin. “An enhanced volume integral equation method and augmented equivalence principle algorithm for low frequency problems.” 2010. Web. 15 Apr 2021.

Vancouver:

Sun L. An enhanced volume integral equation method and augmented equivalence principle algorithm for low frequency problems. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2010. [cited 2021 Apr 15]. Available from: http://hdl.handle.net/2142/15564.

Council of Science Editors:

Sun L. An enhanced volume integral equation method and augmented equivalence principle algorithm for low frequency problems. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2010. Available from: http://hdl.handle.net/2142/15564

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