+publisher:"University of Illinois – Urbana-Champaign" +contributor:("Wong, Martin D F")

University of Illinois – Urbana-Champaign

1. Chang, Yun Wei. Single-layer bus routing for high-speed boards.

Degree: MS, 1200, 2012, University of Illinois – Urbana-Champaign

► As the clock frequencies used in industry increase, the timing requirements on high-speed boards become very tight. Since wire length is directly proportional to wire… (more)

Subjects/Keywords: Single Layer Bus; High-Speed Printed Circuit Board

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APA (6^th Edition):

Chang, Y. W. (2012). Single-layer bus routing for high-speed boards. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/29764

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Chang, Yun Wei. “Single-layer bus routing for high-speed boards.” 2012. Thesis, University of Illinois – Urbana-Champaign. Accessed March 04, 2021. http://hdl.handle.net/2142/29764.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Chang, Yun Wei. “Single-layer bus routing for high-speed boards.” 2012. Web. 04 Mar 2021.

Vancouver:

Chang YW. Single-layer bus routing for high-speed boards. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2012. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/2142/29764.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chang YW. Single-layer bus routing for high-speed boards. [Thesis]. University of Illinois – Urbana-Champaign; 2012. Available from: http://hdl.handle.net/2142/29764

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of Illinois – Urbana-Champaign

2. Lai, Tin-Yin. An efficient and accurate timing macro-modeling algorithm for large hierarchical designs.

Degree: MS, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign

URL: http://hdl.handle.net/2142/98236

► Ever-increasing circuit design complexity is driving the need for fast and accurate macro-modeling algorithms to accelerate hierarchical timing. We introduce LibAbs, an effective macro-modeling algorithm… (more)

Subjects/Keywords: Timing macro-modeling; Algorithm; Timing analysis

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Lai, T. (2017). An efficient and accurate timing macro-modeling algorithm for large hierarchical designs. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/98236

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Lai, Tin-Yin. “An efficient and accurate timing macro-modeling algorithm for large hierarchical designs.” 2017. Thesis, University of Illinois – Urbana-Champaign. Accessed March 04, 2021. http://hdl.handle.net/2142/98236.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Lai, Tin-Yin. “An efficient and accurate timing macro-modeling algorithm for large hierarchical designs.” 2017. Web. 04 Mar 2021.

Vancouver:

Lai T. An efficient and accurate timing macro-modeling algorithm for large hierarchical designs. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2017. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/2142/98236.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lai T. An efficient and accurate timing macro-modeling algorithm for large hierarchical designs. [Thesis]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/98236

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of Illinois – Urbana-Champaign

3. Lin, Chun-Xun. Advances in parallel programming for electronic design automation.

Degree: PhD, Electrical & Computer Engr, 2020, University of Illinois – Urbana-Champaign

URL: http://hdl.handle.net/2142/108425

► The continued miniaturization of the technology node increases not only the chip capacity but also the circuit design complexity. How does one efficiently design a… (more)

▼ The continued miniaturization of the technology node increases not only the chip capacity but also the circuit design complexity. How does one efficiently design a chip with millions or billions transistors? This has become a challenging problem in the integrated circuit (IC) design industry, especially for the developers of electronic design automation (EDA) tools. To boost the performance of EDA tools, one promising direction is via parallel computing. In this dissertation, we explore different parallel computing approaches, from CPU to GPU to distributed computing, for EDA applications. Nowadays multi-core processors are prevalent from mobile devices to laptops to desktop, and it is natural for software developers to utilize the available cores to maximize the performance of their applications. Therefore, in this dissertation we first focus on multi-threaded programming. We begin by reviewing a C++ parallel programming library called Cpp-Taskflow. Cpp-Taskflow is designed to facilitate programming parallel applications, and has been successfully applied to an EDA timing analysis tool. We will demonstrate Cpp-Taskflow’s programming model and interface, software architecture and execution flow. Then, we improve Cpp-Taskflow in several aspects. First, we enhance Cpp-Taskflow’s usability through restructuring the software architecture. Second, we introduce task graph composition to support composability and modularity, which makes it easier for users to construct large and complex parallel patterns. Third, we add a new task type in Cpp-Taskflow to let users control the graph execution flow. This feature empowers the graph model with the ability to describe complex control flow. Aside from the above enhancements, we have designed a new scheduler to adaptively manage the threads based on available parallelism. The new scheduler uses a simple and effective strategy which can not only prevent resource from being underutilized, but also mitigate resource over-subscription. We have evaluated the new scheduler on both micro-benchmarks and a very-large-scale integration (VLSI) application, and the results show that the new scheduler can achieve good performance and is very energy-efficient. Next we study the applicability of heterogeneous computing, specifically the graphics processing unit (GPU), to EDA. We demonstrate how to use GPU to accelerate VLSI placement, and we show that GPU can bring substantial performance gain to VLSI placement. Finally, as the design size keeps increasing, a more scalable solution will be distributed computing. We introduce a distributed power grid analysis framework built on top of DtCraft. This framework allows users to flexibly partition the design and automatically deploy the computations across several machines. In addition, we propose a job scheduler that can efficiently utilize cluster resource to improve the framework’s performance. Advisors/Committee Members: Champaign%22%20%2Bcontributor%3A%28%22Wong%2C%20Martin%20D%20F%22%29&pagesize-30">Wong, Martin D F (advisor), Champaign%22%20%2Bcontributor%3A%28%22Wong%2C%20Martin%20D%20F%22%29&pagesize-30">Wong, Martin D F (Committee Chair), Champaign%22%20%2Bcontributor%3A%28%22Hwu%2C%20Wen-Mei%22%29&pagesize-30">Hwu, Wen-Mei (committee member), Champaign%22%20%2Bcontributor%3A%28%22Chen%2C%20Deming%22%29&pagesize-30">Chen, Deming (committee member), Champaign%22%20%2Bcontributor%3A%28%22Xiong%2C%20Jinjun%22%29&pagesize-30">Xiong, Jinjun (committee member).

Subjects/Keywords: Electronic design automation; Parallel programming

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Lin, C. (2020). Advances in parallel programming for electronic design automation. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/108425

Chicago Manual of Style (16^th Edition):

Lin, Chun-Xun. “Advances in parallel programming for electronic design automation.” 2020. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed March 04, 2021. http://hdl.handle.net/2142/108425.

MLA Handbook (7^th Edition):

Lin, Chun-Xun. “Advances in parallel programming for electronic design automation.” 2020. Web. 04 Mar 2021.

Vancouver:

Lin C. Advances in parallel programming for electronic design automation. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2020. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/2142/108425.

Council of Science Editors:

Lin C. Advances in parallel programming for electronic design automation. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2020. Available from: http://hdl.handle.net/2142/108425

University of Illinois – Urbana-Champaign

4. Yan, Tan. Algorithmic studies on PCB routing.

Degree: PhD, 1200, 2011, University of Illinois – Urbana-Champaign

URL: http://hdl.handle.net/2142/18367

► As IC technology advances, the package size keeps shrinking while the pin count of a package keeps increasing. A modern IC package can have a… (more)

▼ As IC technology advances, the package size keeps shrinking while the pin count of a package keeps increasing. A modern IC package can have a pin count of thousands. As a result, a complex printed circuit board (PCB) can host more than ten thousand signal nets. Such a huge pin count and net count make manual design of packages and PCBs an extremely time-consuming and error-prone task. On the other hand, increasing clock frequency imposes various physical constraints on PCB routing. These constraints make traditional IC and PCB routers not applicable to modern PCB routing. To the best of our knowledge, there is no mature commercial or academic automated router that handles these constraints well. Therefore, automated PCB routers that are tuned to handle such constraints become a necessity in modern design. In this dissertation, we propose novel algorithms for three major aspects of PCB routing: escape routing, area routing and layer assignment. Escape routing for packages and PCBs has been studied extensively in the past. Network flow is pervasively used to model this problem. However, previous studies are incomplete in two senses. First, none of the previous works correctly model the diagonal capacity, which is essential for 45 degree routing in most packages and PCBs. As a result, existing algorithms may either produce routing solutions that violate the diagonal capacity or fail to output a legal routing even though one exists. Second, few works discuss the escape routing problem of differential pairs. In high-performance PCBs, many critical nets use differential pairs to transmit signals. How to escape differential pairs from a pin array is an important issue that has received too little attention in the literature. In this dissertation, we propose a new network flow model that guarantees the correctness when diagonal capacity is taken into consideration. This model leads to the first optimal algorithm for escape routing. We also extend our model to handle missing pins. We then propose two algorithms for the differential pair escape routing problem. The first one computes the optimal routing for a single differential pair while the second one is able to simultaneously route multiple differential pairs considering both routability and wire length. We then propose a two-stage routing scheme based on the two algorithms. In our routing scheme, the second algorithm is used to generate initial routing and the first algorithm is used to perform rip-up and reroute. Length-constrained routing is another very important problem for PCB routing. Previous length-constrained routers all have assumptions on the routing topology. We propose a routing scheme that is free of any restriction on the routing topology. The novelty of our proposed routing scheme is that we view the length-constrained routing problem as an area assignment problem and use a placement structure to help transform the area assignment problem into a mathematical programming problem. Experimental results show that our routing scheme can handle… Advisors/Committee Members: Champaign%22%20%2Bcontributor%3A%28%22Wong%2C%20Martin%20D.%20F.%22%29&pagesize-30">Wong, Martin D. F. (advisor), Champaign%22%20%2Bcontributor%3A%28%22Wong%2C%20Martin%20D.%20F.%22%29&pagesize-30">Wong, Martin D. F. (Committee Chair), Champaign%22%20%2Bcontributor%3A%28%22Chen%2C%20Deming%22%29&pagesize-30">Chen, Deming (committee member), Champaign%22%20%2Bcontributor%3A%28%22Lumetta%2C%20Steven%20S.%22%29&pagesize-30">Lumetta, Steven S. (committee member), Champaign%22%20%2Bcontributor%3A%28%22Rutenbar%2C%20Robin%20A.%22%29&pagesize-30">Rutenbar, Robin A. (committee member).

Subjects/Keywords: Algorithm; printed circuit board (PCB) routing; Escape routing; Length-matching routing; Length-constrained routing; Layer assignment; Network flow; Pin Grid Array; Ball Grid Array

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Yan, T. (2011). Algorithmic studies on PCB routing. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/18367

Chicago Manual of Style (16^th Edition):

Yan, Tan. “Algorithmic studies on PCB routing.” 2011. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed March 04, 2021. http://hdl.handle.net/2142/18367.

MLA Handbook (7^th Edition):

Yan, Tan. “Algorithmic studies on PCB routing.” 2011. Web. 04 Mar 2021.

Vancouver:

Yan T. Algorithmic studies on PCB routing. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2011. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/2142/18367.

Council of Science Editors:

Yan T. Algorithmic studies on PCB routing. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2011. Available from: http://hdl.handle.net/2142/18367

University of Illinois – Urbana-Champaign

5. Huang, Tsung-Wei. Distributed timing analysis.

Degree: PhD, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign

URL: http://hdl.handle.net/2142/99302

► As design complexities continue to grow larger, the need to efficiently analyze circuit timing with billions of transistors across multiple modes and corners is quickly… (more)

▼ As design complexities continue to grow larger, the need to efficiently analyze circuit timing with billions of transistors across multiple modes and corners is quickly becoming the major bottleneck to the overall chip design closure process. To alleviate the long runtimes, recent trends are driving the need of distributed timing analysis (DTA) in electronic design automation (EDA) tools. However, DTA has received little research attention so far and remains a critical problem. In this thesis, we introduce several methods to approach DTA problems. We present a near-optimal algorithm to speed up the path-based timing analysis in Chapter 1. Path-based timing analysis is a key step in the overall timing flow to reduce unwanted pessimism, for example, common path pessimism removal (CPPR). In Chapter 2, we introduce a MapReduce-based distributed Path-based timing analysis framework that can scale up to hundreds of machines. In Chapter 3, we introduce our standalone timer, OpenTimer, an open-source high-performance timing analysis tool for very large scale integration (VLSI) systems. OpenTimer efficiently supports (1) both block-based and path-based timing propagations, (2) CPPR, and (3) incremental timing. OpenTimer works on industry formats (e.g., .v, .spef, .lib, .sdc) and is designed to be parallel and portable. To further facilitate integration between timing and timing-driven optimizations, OpenTimer provides user-friendly application programming interface (API) for inactive analysis. Experimental results on industry benchmarks re- leased from TAU 2015 timing analysis contest have demonstrated remarkable results achieved by OpenTimer, especially in its order-of-magnitude speedup over existing timers. In Chapter 4 we present a DTA framework built on top of our standalone timer OpenTimer. We investigated into existing cluster computing frameworks from big data community and demonstrated DTA is a difficult fit here in terms of computation patterns and performance concern. Our specialized DTA framework supports (1) general design partitions (logical, physical, hierarchical, etc.) stored in a distributed file system, (2) non-blocking IO with event-driven programming for effective communication and computation overlap, and (3) an efficient messaging interface between application and network layers. The effectiveness and scalability of our framework has been evaluated on large hierarchical industry designs over a cluster with hundreds of machines. In Chapter 5, we present our system DtCraft, a distributed execution engine for compute-intensive applications. Motivated by our DTA framework, DtCraft introduces a high-level programming model that lets users without detailed experience of distributed computing utilize the cluster resources. The major goal is to simplify the coding efforts on building distributed applications based on our system. In contrast to existing data-parallel cluster computing frameworks, DtCraft targets on high-performance or compute- intensive applications including simulations, modeling, and most… Advisors/Committee Members: Champaign%22%20%2Bcontributor%3A%28%22Wong%2C%20Martin%20D.%20F.%22%29&pagesize-30">Wong, Martin D. F. (advisor), Champaign%22%20%2Bcontributor%3A%28%22Wong%2C%20Martin%20D.%20F.%22%29&pagesize-30">Wong, Martin D. F. (Committee Chair), Champaign%22%20%2Bcontributor%3A%28%22Chen%2C%20Deming%22%29&pagesize-30">Chen, Deming (committee member), Champaign%22%20%2Bcontributor%3A%28%22Hwu%2C%20Wen-Mei%22%29&pagesize-30">Hwu, Wen-Mei (committee member), Champaign%22%20%2Bcontributor%3A%28%22Rutenbar%2C%20Rob%20A.%22%29&pagesize-30">Rutenbar, Rob A. (committee member).

Subjects/Keywords: Distributed systems; Timing analysis

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Huang, T. (2017). Distributed timing analysis. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/99302

Chicago Manual of Style (16^th Edition):

Huang, Tsung-Wei. “Distributed timing analysis.” 2017. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed March 04, 2021. http://hdl.handle.net/2142/99302.

MLA Handbook (7^th Edition):

Huang, Tsung-Wei. “Distributed timing analysis.” 2017. Web. 04 Mar 2021.

Vancouver:

Huang T. Distributed timing analysis. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2017. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/2142/99302.

Council of Science Editors:

Huang T. Distributed timing analysis. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/99302

University of Illinois – Urbana-Champaign

6. Lin, Chen-Hsuan. Design automation for circuit reliability and energy efficiency.

Degree: PhD, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign

URL: http://hdl.handle.net/2142/99237

► This dissertation presents approaches to improve circuit reliability and energy efficiency from different angles, such as verification, logic synthesis, and functional unit design. A variety… (more)

Subjects/Keywords: Electronic design automation; Reliability; Energy efficiency; Data mining; Satisfiability (SAT) solving; Logic restructuring; Assertion; Negative bias temperature instability (NBTI) effect; Modulo arithmetic; Shadow datapath

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Lin, C. (2017). Design automation for circuit reliability and energy efficiency. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/99237

Chicago Manual of Style (16^th Edition):

Lin, Chen-Hsuan. “Design automation for circuit reliability and energy efficiency.” 2017. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed March 04, 2021. http://hdl.handle.net/2142/99237.

MLA Handbook (7^th Edition):

Lin, Chen-Hsuan. “Design automation for circuit reliability and energy efficiency.” 2017. Web. 04 Mar 2021.

Vancouver:

Lin C. Design automation for circuit reliability and energy efficiency. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2017. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/2142/99237.

Council of Science Editors:

Lin C. Design automation for circuit reliability and energy efficiency. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/99237

7. Du, Yuelin. Characterization of the Performance Variation for Regular Standard Cells with Process Non-idealities.

Degree: MS, 1200, 2011, University of Illinois – Urbana-Champaign

URL: http://hdl.handle.net/2142/24335

► In IC manufacturing, the performance of standard cells often varies due to process non-idealities. Some research work on 2-D cell characterization shows that the timing… (more)

Subjects/Keywords: 1-D Patterning; Dense Line Printing; Standard Cell Characterization

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Du, Y. (2011). Characterization of the Performance Variation for Regular Standard Cells with Process Non-idealities. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/24335

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Du, Yuelin. “Characterization of the Performance Variation for Regular Standard Cells with Process Non-idealities.” 2011. Thesis, University of Illinois – Urbana-Champaign. Accessed March 04, 2021. http://hdl.handle.net/2142/24335.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Du, Yuelin. “Characterization of the Performance Variation for Regular Standard Cells with Process Non-idealities.” 2011. Web. 04 Mar 2021.

Vancouver:

Du Y. Characterization of the Performance Variation for Regular Standard Cells with Process Non-idealities. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2011. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/2142/24335.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Du Y. Characterization of the Performance Variation for Regular Standard Cells with Process Non-idealities. [Thesis]. University of Illinois – Urbana-Champaign; 2011. Available from: http://hdl.handle.net/2142/24335

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

8. Han, Khine. Shape Approximation of Printed Images in VLSI Design.

Degree: MS, Electrical and Computer Engineering, 2009, University of Illinois – Urbana-Champaign

URL: http://hdl.handle.net/2142/11990

► Despite application of optical proximity correction (OPC) and resolution enhancement techniques (RET) to improve printing, limitations in lithography and manufacturing processes still lead to undesirable… (more)

▼ Despite application of optical proximity correction (OPC) and resolution enhancement techniques (RET) to improve printing, limitations in lithography and manufacturing processes still lead to undesirable irregularities in printed images on wafer. These post-lithographic distorted shapes are of interest for electrical extraction of printed circuits. To reduce processing time, it is desirable to approximate the resulting two-dimensional contours with simpler polygons. For the case of capacitance extraction algorithms, pairs of outer and inner approximate polygons, which approach the original shape with tighter error restriction, are preferable. Many existing approximation algorithms produce a single approximate polygon per shape, utilizing two main approaches: piecewise linear fit with a fixed number of segments or bounded error, and identification of subsets of dominant points in the resultant polygon. This research presents an approximation algorithm of the former approach using simple one-dimensional methods to efficiently approximate two-dimensional closed shapes by pairs of outer and inner polygons. Each input shape is first decomposed using a greedy strategy into a set of connected functions; the set size is assumed to be small compared to the input size, and each function is assigned an x or y approximation direction. Each decomposed function is approximated with an optimal number of subdivision points within a certain bounded error restricted to one particular assigned direction; the upper- and lower-bound vertices associated with each subdivision are also calculated. A decision method is employed to determine the relative locations of the outer and inner regions of the two-dimensional curve, the results are pieced together to generate the complete outer and inner approximate polygons. The one-dimensional approach guarantees linear-time approximation of each function. Under the assumption of possible decomposition into a small set of connected functions, the total approximation time of the proposed algorithm is linear in the number of input vertices. For verification, the algorithm is applied to several test files containing either post-lithographic or arbitrary two-dimensional closed shapes for several specified bounded error values. A few techniques are also discussed for further performance improvements. Advisors/Committee Members: Champaign%22%20%2Bcontributor%3A%28%22Wong%2C%20Martin%20D.%20F.%22%29&pagesize-30">Wong, Martin D. F. (advisor).

Subjects/Keywords: vlsi; polygon; approximation

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Han, K. (2009). Shape Approximation of Printed Images in VLSI Design. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/11990

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Han, Khine. “Shape Approximation of Printed Images in VLSI Design.” 2009. Thesis, University of Illinois – Urbana-Champaign. Accessed March 04, 2021. http://hdl.handle.net/2142/11990.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Han, Khine. “Shape Approximation of Printed Images in VLSI Design.” 2009. Web. 04 Mar 2021.

Vancouver:

Han K. Shape Approximation of Printed Images in VLSI Design. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2009. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/2142/11990.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Han K. Shape Approximation of Printed Images in VLSI Design. [Thesis]. University of Illinois – Urbana-Champaign; 2009. Available from: http://hdl.handle.net/2142/11990

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

9. Luo, Lijuan. New strategies for electronic design automation problems.

Degree: PhD, 1200, 2011, University of Illinois – Urbana-Champaign

URL: http://hdl.handle.net/2142/24504

► As the semiconductor industry marches towards 22 nm technology and beyond, circuit design has become unprecedentedly omplicated. This presents many new challenges for EDA (electronic… (more)

▼ As the semiconductor industry marches towards 22 nm technology and beyond, circuit design has become unprecedentedly omplicated. This presents many new challenges for EDA (electronic design automation), such as lack of effective tools for analog circuit or high-volume and high-frequency printed circuit board (PCB) design, the contradiction between complex EDA compute workloads and time-to-market pressure, manufacturing variability and power management, to name but a few. In this dissertation, we will propose several new strategies to handle the challenges in the EDA field. Wire routing is an important step in the design of PCBs. Although there are many industrial tools to handle IC routing problems, very few tools can handle the routing on high-density and high-frequency boards effectively. Nowadays, most of the PCB routing is still done by tedious and time-consuming manual work. We provide new strategies to solve an important problem in PCB routing, the escape routing problem. Our first strategy is to use Boolean satisfiability to optimally solve the escape routing problem on one PCB component. Our second strategy is to use a novel boundary routing methodology to finish escape routing from two connected PCB components simultaneously. This router can achieve much better routability than industrial tools with less CPU time. Another challenge seen in the EDA field is the increasing CPU time to handle larger and larger designs. On the other hand, many fundamental algorithms and data structures used in the EDA tools have shown great parallelism, such as the well-known BFS (breadth-first search) algorithm and the R-tree structure. Therefore, we propose strategies to use the cost-effective GPU platform to parallelize and accelerate BFS and R-tree query. These strategies are potentially applicable to many EDA problems. Advisors/Committee Members: Champaign%22%20%2Bcontributor%3A%28%22Wong%2C%20Martin%20D.%20F.%22%29&pagesize-30">Wong, Martin D. F. (advisor), Champaign%22%20%2Bcontributor%3A%28%22Wong%2C%20Martin%20D.%20F.%22%29&pagesize-30">Wong, Martin D. F. (Committee Chair), Champaign%22%20%2Bcontributor%3A%28%22Hwu%2C%20Wen-Mei%20W.%22%29&pagesize-30">Hwu, Wen-Mei W. (committee member), Champaign%22%20%2Bcontributor%3A%28%22Patel%2C%20Janak%20H.%22%29&pagesize-30">Patel, Janak H. (committee member), Champaign%22%20%2Bcontributor%3A%28%22Chen%2C%20Deming%22%29&pagesize-30">Chen, Deming (committee member).

Subjects/Keywords: printed circuit board (PCB) routing; escape routing; Boolean satisfiability; graphics processing unit (GPU); CUDA; breadth-first search; R-tree

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APA (6^th Edition):

Luo, L. (2011). New strategies for electronic design automation problems. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/24504

Chicago Manual of Style (16^th Edition):

Luo, Lijuan. “New strategies for electronic design automation problems.” 2011. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed March 04, 2021. http://hdl.handle.net/2142/24504.

MLA Handbook (7^th Edition):

Luo, Lijuan. “New strategies for electronic design automation problems.” 2011. Web. 04 Mar 2021.

Vancouver:

Luo L. New strategies for electronic design automation problems. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2011. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/2142/24504.

Council of Science Editors:

Luo L. New strategies for electronic design automation problems. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2011. Available from: http://hdl.handle.net/2142/24504

10. Kong, Hui. New strategies for PCB routing.

Degree: PhD, 1200, 2011, University of Illinois – Urbana-Champaign

URL: http://hdl.handle.net/2142/18462

► As IC technology advances rapidly, the dimensions of packages and PCBs are decreasing while the pin counts and routing layers keep increasing. Today, a high-performance… (more)

Subjects/Keywords: Circuits; Algorithms; Printed Circuit Board (PCB) Routing

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APA (6^th Edition):

Kong, H. (2011). New strategies for PCB routing. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/18462

Chicago Manual of Style (16^th Edition):

Kong, Hui. “New strategies for PCB routing.” 2011. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed March 04, 2021. http://hdl.handle.net/2142/18462.

MLA Handbook (7^th Edition):

Kong, Hui. “New strategies for PCB routing.” 2011. Web. 04 Mar 2021.

Vancouver:

Kong H. New strategies for PCB routing. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2011. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/2142/18462.

Council of Science Editors:

Kong H. New strategies for PCB routing. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2011. Available from: http://hdl.handle.net/2142/18462

11. Konigsmark, Sven Tenzing Choden. Hardware security design from circuits to systems.

Degree: PhD, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign

URL: http://hdl.handle.net/2142/97659

► The security of hardware implementations is of considerable importance, as even the most secure and carefully analyzed algorithms and protocols can be vulnerable in their… (more)

▼ The security of hardware implementations is of considerable importance, as even the most secure and carefully analyzed algorithms and protocols can be vulnerable in their hardware realization. For instance, numerous successful attacks have been presented against the Advanced Encryption Standard, which is approved for top secret information by the National Security Agency. There are numerous challenges for hardware security, ranging from critical power and resource constraints in sensor networks to scalability and automation for large Internet of Things (IoT) applications. The physically unclonable function (PUF) is a promising building block for hardware security, as it exposes a device-unique challenge-response behavior which depends on process variations in fabrication. It can be used in a variety of applications including random number generation, authentication, fingerprinting, and encryption. The primary concerns for PUF are reliability in presence of environmental variations, area and power overhead, and process-dependent randomness of the challenge-response behavior. Carbon nanotube field-effect transistors (CNFETs) have been shown to have excellent electrical and unique physical characteristics. They are a promising candidate to replace silicon transistors in future very large scale integration (VLSI) designs. We present the Carbon Nanotube PUF (CNPUF), which is the first PUF design that takes advantage of unique CNFET characteristics. CNPUF achieves higher reliability against environmental variations and increases the resistance against modeling attacks. Furthermore, CNPUF has a considerable power and energy reduction in comparison to previous ultra-low power PUF designs of 89.6% and 98%, respectively. Moreover, CNPUF allows a power-security tradeoff in an extended design, which can greatly increase the resilience against modeling attacks. Despite increasing focus on defenses against physical attacks, consistent security oriented design of embedded systems remains a challenge, as most formalizations and security models are concerned with isolated physical components or a high-level concept. Therefore, we build on existing work on hardware security and provide four contributions to system-oriented physical defense: (i) A system-level security model to overcome the chasm between secure components and requirements of high-level protocols; this enables synergy between component-oriented security formalizations and theoretically proven protocols. (ii) An analysis of current practices in PUF protocols using the proposed system-level security model; we identify significant issues and expose assumptions that require costly security techniques. (iii) A System-of-PUF (SoP) that utilizes the large PUF design-space to achieve security requirements with minimal resource utilization; SoP requires 64% less gate-equivalent units than recently published schemes. (iv) A multilevel authentication protocol based on SoP which is validated using our system-level security model and which overcomes current vulnerabilities.… Advisors/Committee Members: Champaign%22%20%2Bcontributor%3A%28%22Chen%2C%20Deming%22%29&pagesize-30">Chen, Deming (advisor), Champaign%22%20%2Bcontributor%3A%28%22Wong%2C%20Martin%20D.%20F.%22%29&pagesize-30">Wong, Martin D. F. (advisor), Champaign%22%20%2Bcontributor%3A%28%22Chen%2C%20Deming%22%29&pagesize-30">Chen, Deming (Committee Chair), Champaign%22%20%2Bcontributor%3A%28%22Wong%2C%20Martin%20D.%20F.%22%29&pagesize-30">Wong, Martin D. F. (Committee Chair), Champaign%22%20%2Bcontributor%3A%28%22Sanders%2C%20William%20H.%22%29&pagesize-30">Sanders, William H. (committee member), Champaign%22%20%2Bcontributor%3A%28%22Nicol%2C%20David%20M.%22%29&pagesize-30">Nicol, David M. (committee member).

Subjects/Keywords: Hardware security; Physically unclonable function; Hardware Trojan horse; Authentication; Invasive attacks; Carbon nanotubes

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APA (6^th Edition):

Konigsmark, S. T. C. (2017). Hardware security design from circuits to systems. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/97659

Chicago Manual of Style (16^th Edition):

Konigsmark, Sven Tenzing Choden. “Hardware security design from circuits to systems.” 2017. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed March 04, 2021. http://hdl.handle.net/2142/97659.

MLA Handbook (7^th Edition):

Konigsmark, Sven Tenzing Choden. “Hardware security design from circuits to systems.” 2017. Web. 04 Mar 2021.

Vancouver:

Konigsmark STC. Hardware security design from circuits to systems. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2017. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/2142/97659.

Council of Science Editors:

Konigsmark STC. Hardware security design from circuits to systems. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/97659

University of Illinois – Urbana-Champaign

12. Hwang, Leslie K. Stochastic shortest path algorithm based on Lagrangian relaxation.

Degree: MS, 1200, 2010, University of Illinois – Urbana-Champaign

URL: http://hdl.handle.net/2142/16806

► In VLSI circuit design, graph algorithms are widely used and graph structure can model many problems. As technology continues to scale into nanometer design, the… (more)

Subjects/Keywords: Stochastic shortest path; Variation; Lagrangian relaxation

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APA (6^th Edition):

Hwang, L. K. (2010). Stochastic shortest path algorithm based on Lagrangian relaxation. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/16806

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Hwang, Leslie K. “Stochastic shortest path algorithm based on Lagrangian relaxation.” 2010. Thesis, University of Illinois – Urbana-Champaign. Accessed March 04, 2021. http://hdl.handle.net/2142/16806.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Hwang, Leslie K. “Stochastic shortest path algorithm based on Lagrangian relaxation.” 2010. Web. 04 Mar 2021.

Vancouver:

Hwang LK. Stochastic shortest path algorithm based on Lagrangian relaxation. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2010. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/2142/16806.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hwang LK. Stochastic shortest path algorithm based on Lagrangian relaxation. [Thesis]. University of Illinois – Urbana-Champaign; 2010. Available from: http://hdl.handle.net/2142/16806

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

13. Hsu, Chih-Wei. Solving Automated Planning Problems with Parallel Decomposition.

Degree: PhD, 0112, 2012, University of Illinois – Urbana-Champaign

URL: http://hdl.handle.net/2142/29488

► In this dissertation, we present a parallel decomposition method to address the complexity of solving automated planning problems. We have found many planning problems have… (more)

▼ In this dissertation, we present a parallel decomposition method to address the complexity of solving automated planning problems. We have found many planning problems have good locality which means their actions can be clustered in such a way that nearby actions in the solution plan are usually also from the same cluster. We have also observed that the problem structure is regular and has lots of repetitions. The repetitions come from symmetric objects in the planning problem and a simplified instance with similar problem structure can be generated by reducing the number of symmetric objects. We improve heuristic search in planning by utilizing locality and symmetry and applying parallel decomposition. Our parallel decomposition approach exploits these structural properties in a domain-independent way in three steps: action partitioning, constraint resolution, and subproblem solutions. In each step, we propose solutions to exploit localities and symmetries for minimizing solution time. Our key contribution lies in the design of simplification and generalization procedures to find good heuristics in action partitioning and constraint resolution. In application of our method to solve propositional and temporal planning problems in three of the past International Planning Competitions, our results show that \SGPlansix, our proposed planner, can solve more instances than other top planners. We demonstrate \SGPlansix performs well when action partitioning is useful in decreasing heuristic value. We also show \SGPlansix can achieve better quality-time trade-off. By using the symmetry and locality, we are able to achieve good coverage using our domain-independent planner but still have good performance like domain-specific planners. Advisors/Committee Members: Champaign%22%20%2Bcontributor%3A%28%22Wah%2C%20Benjamin%20W.%22%29&pagesize-30">Wah, Benjamin W. (advisor), Champaign%22%20%2Bcontributor%3A%28%22DeJong%2C%20Gerald%20F.%22%29&pagesize-30">DeJong, Gerald F. (committee member), Champaign%22%20%2Bcontributor%3A%28%22LaValle%2C%20Steven%20M.%22%29&pagesize-30">LaValle, Steven M. (committee member), Champaign%22%20%2Bcontributor%3A%28%22Wong%2C%20Martin%20D.%20F.%22%29&pagesize-30">Wong, Martin D. F. (committee member).

Subjects/Keywords: Planning; Scheduling; Parallel Decomposition; Action Partitioning Heuristic Search

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Hsu, C. (2012). Solving Automated Planning Problems with Parallel Decomposition. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/29488

Chicago Manual of Style (16^th Edition):

Hsu, Chih-Wei. “Solving Automated Planning Problems with Parallel Decomposition.” 2012. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed March 04, 2021. http://hdl.handle.net/2142/29488.

MLA Handbook (7^th Edition):

Hsu, Chih-Wei. “Solving Automated Planning Problems with Parallel Decomposition.” 2012. Web. 04 Mar 2021.

Vancouver:

Hsu C. Solving Automated Planning Problems with Parallel Decomposition. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2012. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/2142/29488.

Council of Science Editors:

Hsu C. Solving Automated Planning Problems with Parallel Decomposition. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2012. Available from: http://hdl.handle.net/2142/29488

14. Huang, Pingli. SHA-less pipeline ADC design with sampling clock skew calibration.

Degree: PhD, 1200, 2012, University of Illinois – Urbana-Champaign

URL: http://hdl.handle.net/2142/29565

► The power efficiency of pipeline analog-to-digital converters (ADCs) can be substantially improved by eliminating the front-end sample-and-hold amplifier (SHA). However, in a SHA-less architecture the… (more)

▼ The power efficiency of pipeline analog-to-digital converters (ADCs) can be substantially improved by eliminating the front-end sample-and-hold amplifier (SHA). However, in a SHA-less architecture the sampling clock skew between the sub-ADC and the multiplying digital-to-analog converter (MDAC) in the pipeline first stage results in gross conversion errors at high input frequencies. This skew effect is aggravated in a SHA-less multi-bit-per-stage pipeline architecture, where the built-in redundancy is limited. Sampling clock skew is an essential problem in SHA-less pipeline ADCs that prohibits their use at high input frequency applications. In this thesis, a mostly digital background calibration technique is developed to remove the sampling clock skew in SHA-less pipeline ADCs. The skew information is extracted from the first-stage residue output with two comparators sensing out-of-range errors; a gradient-descent algorithm is used to adaptively adjust the timing of the sub-ADC to synchronize with that of the sample-and-hold (S/H) in the MDAC. A prototype 10-bit, 100-MS/s SHA-less pipeline ADC incorporating this calibration technique was designed and fabricated in 90-nm CMOS process. The prototype ADC converts from DC to the 12th Nyquist band with a 3.5-bit front-end stage. It digitizes inputs up to 610 MHz without skew errors in experiments; in contrast, the same ADC fails at 130 MHz with calibration disabled. The calibration circuits were fully integrated on chip. The ADC consumes 12.2 mW and occupies 0.26-mm2 silicon area, while the calibration circuits dissipate 0.9 mW and occupy 0.01 mm2. A 71-dB spurious-free dynamic range (SFDR) and a 55-dB signal-to-noise-and-distortion ratio (SNDR) were measured with a 20-MHz sine-wave input, and a larger than 55-dB SFDR was measured in the 10th Nyquist band. Advisors/Committee Members: Champaign%22%20%2Bcontributor%3A%28%22Chiu%2C%20Yun%22%29&pagesize-30">Chiu, Yun (advisor), Champaign%22%20%2Bcontributor%3A%28%22Feng%2C%20Milton%22%29&pagesize-30">Feng, Milton (committee member), Champaign%22%20%2Bcontributor%3A%28%22Rosenbaum%2C%20Elyse%22%29&pagesize-30">Rosenbaum, Elyse (committee member), Champaign%22%20%2Bcontributor%3A%28%22Wong%2C%20Martin%20D.%20F.%22%29&pagesize-30">Wong, Martin D. F. (committee member).

Subjects/Keywords: Sample-and-hold amplifier (SHA); SHA-less; pipelined ADC; multi-bit pipeline architecture; sampling clock skew; skew calibration.; analog-to-digital converters (ADCs)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Huang, P. (2012). SHA-less pipeline ADC design with sampling clock skew calibration. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/29565

Chicago Manual of Style (16^th Edition):

Huang, Pingli. “SHA-less pipeline ADC design with sampling clock skew calibration.” 2012. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed March 04, 2021. http://hdl.handle.net/2142/29565.

MLA Handbook (7^th Edition):

Huang, Pingli. “SHA-less pipeline ADC design with sampling clock skew calibration.” 2012. Web. 04 Mar 2021.

Vancouver:

Huang P. SHA-less pipeline ADC design with sampling clock skew calibration. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2012. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/2142/29565.

Council of Science Editors:

Huang P. SHA-less pipeline ADC design with sampling clock skew calibration. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2012. Available from: http://hdl.handle.net/2142/29565

15. Campbell, Keith A. Robust and reliable hardware accelerator design through high-level synthesis.

Degree: PhD, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign

URL: http://hdl.handle.net/2142/99294

► System-on-chip design is becoming increasingly complex as technology scaling enables more and more functionality on a chip. This scaling-driven complexity has resulted in a variety… (more)

▼ System-on-chip design is becoming increasingly complex as technology scaling enables more and more functionality on a chip. This scaling-driven complexity has resulted in a variety of reliability and validation challenges including logic bugs, hot spots, wear-out, and soft errors. To make matters worse, as we reach the limits of Dennard scaling, efforts to improve system performance and energy efficiency have resulted in the integration of a wide variety of complex hardware accelerators in SoCs. Thus the challenge is to design complex, custom hardware that is efficient, but also correct and reliable. High-level synthesis shows promise to address the problem of complex hardware design by providing a bridge from the high-productivity software domain to the hardware design process. Much research has been done on high-level synthesis efficiency optimizations. This dissertation shows that high-level synthesis also has the power to address validation and reliability challenges through three automated solutions targeting three key stages in the hardware design and use cycle: pre-silicon debugging, post-silicon validation, and post-deployment error detection. Our solution for rapid pre-silicon debugging of accelerator designs is hybrid tracing: comparing a datapath-level trace of hardware execution with a reference software implementation at a fine temporal and spatial granularity to detect logic bugs. An integrated backtrace process delivers source-code meaning to the hardware designer, pinpointing the location of bug activation and providing a strong hint for potential bug fixes. Experimental results show that we are able to detect and aid in localization of logic bugs from both C/C++ specifications as well as the high-level synthesis engine itself. A variation of this solution tailored for rapid post-silicon validation of accelerator designs is hybrid hashing: inserting signature generation logic in a hardware design to create a heavily compressed signature stream that captures the internal behavior of the design at a fine temporal and spatial granularity for comparison with a reference set of signatures generated by high-level simulation to detect bugs. Using hybrid hashing, we demonstrate an improvement in error detection latency (time elapsed from when a bug is activated to when it manifests as an observable failure) of two orders of magnitude and a threefold improvement in bug coverage compared to traditional post-silicon validation techniques. Hybrid hashing also uncovered previously unknown bugs in the CHStone benchmark suite, which is widely used by the HLS community. Hybrid hashing incurs less than 10% area overhead for the accelerator it validates with negligible performance impact, and we also introduce techniques to minimize any possible intrusiveness introduced by hybrid hashing. Finally, our solution for post-deployment error detection is modulo-3 shadow datapaths: performing lightweight shadow computations in modulo-3 space for each main computation. We leverage the binding and scheduling… Advisors/Committee Members: Champaign%22%20%2Bcontributor%3A%28%22Chen%2C%20Deming%22%29&pagesize-30">Chen, Deming (advisor), Champaign%22%20%2Bcontributor%3A%28%22Chen%2C%20Deming%22%29&pagesize-30">Chen, Deming (Committee Chair), Champaign%22%20%2Bcontributor%3A%28%22Hwu%2C%20Wen-Mei%20W%22%29&pagesize-30">Hwu, Wen-Mei W (committee member), Champaign%22%20%2Bcontributor%3A%28%22Wong%2C%20Martin%20D%20F%22%29&pagesize-30">Wong, Martin D F (committee member), Champaign%22%20%2Bcontributor%3A%28%22Kim%2C%20Nam%20Sung%22%29&pagesize-30">Kim, Nam Sung (committee member).

Subjects/Keywords: High-level synthesis (HLS); Automation; Error detection; Scheduling; Binding; Compiler transformation; Compiler optimization; Pipelining; Modulo arithmetic; Modulo-3; Logic optimization; State machine; Datapath; Control logic; Shadow datapath; Modulo datapath; Low cost; High performance; Electrical bug; Aliasing; Stuck-at fault; Soft error; Timing error; Checkpointing; Rollback; Recovery; Pre-silicon validation; Post-silicon validation; Pre-silicon debug; Post-silicon debug; Accelerator; System on a chip; Signature generation; Execution signature; Execution hash; Logic bug; Nondeterministic bug; Masked error; Circuit reliability; Hot spot; Wear out; Silent data corruption; Observability; Detection latency; Mixed datapath; Diversity; Checkpoint corruption; Error injection; Error removal; Quick Error Detection (QED); Hybrid Quick Error Detection (H-QED); Instrumentation; Hybrid co-simulation; Hardware/software; Integration testing; Hybrid tracing; Hybrid hashing; Source-code localization; Software debugging tool; Valgrind; Clang sanitizer; Clang static analyzer; Cppcheck; Root cause analysis; Execution tracing; Realtime error detection; Simulation trigger; Nonintrusive; Address conversion; Undefined behavior; High-level synthesis (HLS) bug; Detection coverage; Gate-level architecture; Mersenne modulus; Full adder; Half adder; Quarter adder; Wraparound; Modulo reducer; Modulo adder; Modulo multiplier; Modulo comparator; Cross-layer; Algorithm; Instruction; Architecture; Logic synthesis; Physical design; Algorithm-based fault tolerance (ABFT); Error detection by duplicated instructions (EDDI); Parity; Flip-flop hardening; Layout design through error-aware transistor positioning dual interlocked storage cell (LEAP-DICE); Cost-effective; Place-and-route; Field programmable gate array (FPGA) emulation; Application specific integrated circuit (ASIC); Field programmable gate array (FPGA); Energy; Area; Latency

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Campbell, K. A. (2017). Robust and reliable hardware accelerator design through high-level synthesis. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/99294

Chicago Manual of Style (16^th Edition):

Campbell, Keith A. “Robust and reliable hardware accelerator design through high-level synthesis.” 2017. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed March 04, 2021. http://hdl.handle.net/2142/99294.

MLA Handbook (7^th Edition):

Campbell, Keith A. “Robust and reliable hardware accelerator design through high-level synthesis.” 2017. Web. 04 Mar 2021.

Vancouver:

Campbell KA. Robust and reliable hardware accelerator design through high-level synthesis. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2017. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/2142/99294.

Council of Science Editors:

Campbell KA. Robust and reliable hardware accelerator design through high-level synthesis. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/99294

University of Illinois – Urbana-Champaign

16. Ramachandran, Anand. Methodologies for Transient Simulation of Hybrid Electromagnetic/Circuit Systems with Multiple Time Scales.

Degree: PhD, Electrical and Computer Engineering, 2009, University of Illinois – Urbana-Champaign

URL: http://hdl.handle.net/2142/11977

► This work presents methodologies to facilitate the efficient cosimulation of electromagnetic/circuit systems while exploiting the multiple time scales that are often present in the numerical… (more)

▼ This work presents methodologies to facilitate the efficient cosimulation of electromagnetic/circuit systems while exploiting the multiple time scales that are often present in the numerical simulation of such systems. Three distinct approaches are presented to expedite such a simulation process, with the common theme that the methodologies should allow for the ability to utilize different timesteps in the simulation procedure for the different components appearing in a hybrid system. The first contribution involves a direct representation of each of Maxwell???s curl equations in terms of SPICE-equivalent circuit stamps. This provides for a full-wave, circuit-compatible description of a distributed structure that can very naturally be incorporated into a circuit simulation environment. This capability can be applied to circuit simulations of distributed structures, or it can facilitate the detailed simulation of an electrically small structure with full electromagnetic accuracy. The second contribution allows for the utilization of different numerical integration schemes and timesteps in the simulation of hybrid structures via a domain decomposition approach. By introducing a novel scheme to combine finite-difference time-domain simulation with SPICE-like circuit simulation, it is shown that the timestep used in the lumped circuit portions need not be limited by the Courant-Friedrichs-Lewy (CFL) limit which governs the timestep used in distributed portions. Additionally, the use of the Crank-Nicolson integration scheme is investigated for the simulation of transmission line structures, and an efficient methodology is proposed by combining the Crank-Nicolson integration of transmission lines and standard integration of circuits. Finally, the third contribution in this work involves efficient simulation of circuits involving multirate signals with widely separated time scales. An efficient representation of multirate signals is found by introducing a different time variable for each time scale in order to overcome the significant oversampling of such signals that arises from more traditional, univariate representations. This representation is then directly applied to the simulation of transmission line structures. It is found that the resulting methodologies provide for a significant speedup in the overall simulation time. Advisors/Committee Members: Champaign%22%20%2Bcontributor%3A%28%22Cangellaris%2C%20Andreas%20C.%22%29&pagesize-30">Cangellaris, Andreas C. (advisor), Champaign%22%20%2Bcontributor%3A%28%22Cangellaris%2C%20Andreas%20C.%22%29&pagesize-30">Cangellaris, Andreas C. (Committee Chair), Champaign%22%20%2Bcontributor%3A%28%22Ravaioli%2C%20Umberto%22%29&pagesize-30">Ravaioli, Umberto (committee member), Champaign%22%20%2Bcontributor%3A%28%22Schutt-Ain%3F%3F%2C%20Jos%3F%3F%20E.%22%29&pagesize-30">Schutt-Ain??, Jos?? E. (committee member), Champaign%22%20%2Bcontributor%3A%28%22Wong%2C%20Martin%20D.%20F.%22%29&pagesize-30">Wong, Martin D. F. (committee member).

Subjects/Keywords: Hybrid simulation; multiple time scales; FDTD; time domain methods; electromagnetic simulation

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Ramachandran, A. (2009). Methodologies for Transient Simulation of Hybrid Electromagnetic/Circuit Systems with Multiple Time Scales. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/11977

Chicago Manual of Style (16^th Edition):

Ramachandran, Anand. “Methodologies for Transient Simulation of Hybrid Electromagnetic/Circuit Systems with Multiple Time Scales.” 2009. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed March 04, 2021. http://hdl.handle.net/2142/11977.

MLA Handbook (7^th Edition):

Ramachandran, Anand. “Methodologies for Transient Simulation of Hybrid Electromagnetic/Circuit Systems with Multiple Time Scales.” 2009. Web. 04 Mar 2021.

Vancouver:

Ramachandran A. Methodologies for Transient Simulation of Hybrid Electromagnetic/Circuit Systems with Multiple Time Scales. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2009. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/2142/11977.

Council of Science Editors:

Ramachandran A. Methodologies for Transient Simulation of Hybrid Electromagnetic/Circuit Systems with Multiple Time Scales. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2009. Available from: http://hdl.handle.net/2142/11977

University of Illinois – Urbana-Champaign

17. Sun, Lin. An enhanced volume integral equation method and augmented equivalence principle algorithm for low frequency problems.

Degree: PhD, 1200, 2010, University of Illinois – Urbana-Champaign

URL: http://hdl.handle.net/2142/15564

► Two techniques based on integral equation methods are addressed. Firstly, a novel volume integral equation method is proposed to characterize the scattering properties of dielectric… (more)

▼ Two techniques based on integral equation methods are addressed. Firstly, a novel volume integral equation method is proposed to characterize the scattering properties of dielectric objects involving inhomogeneous and anisotropic permittivity and permeability. Two algorithms are available: conventional method of moments and reciprocity preserving method. Both of them are applied to both the permittivity and permeability terms. Curl-conforming edge elements are used to model the electric field distributions. Integration by parts is applied to deal with the singularities at the boundary introduced by the discontinuities of the material properties. Duffy's method formulations are derived for all the surface and volume singular integrations. Moreover, the multilevel fast multipole algorithm (MLFMA) is utilized to accelerate the matrix vector product process for large problems. Representative numerical results are shown to be excellent. Secondly, the present equivalence principle algorithm (EPA) is augmented by introducing charge densities as extra unknowns. This helps to separate the vector potential term and scalar potential term and avoid the imbalance at low frequencies. The current continuity constraint is enforced in both the scattering operator and translation operator. These further form a new augmented EPA equation system. With this technique, the low-frequency breakdown of EPA is removed. The augmented system serves not only as a stable low-frequency method, but also as a substitute over the whole frequency band. The new scheme is verified by numerical examples. Advisors/Committee Members: Champaign%22%20%2Bcontributor%3A%28%22Chew%2C%20Weng%20Cho%22%29&pagesize-30">Chew, Weng Cho (advisor), Champaign%22%20%2Bcontributor%3A%28%22Chew%2C%20Weng%20Cho%22%29&pagesize-30">Chew, Weng Cho (Committee Chair), Champaign%22%20%2Bcontributor%3A%28%22Jin%2C%20Jianming%22%29&pagesize-30">Jin, Jianming (committee member), Champaign%22%20%2Bcontributor%3A%28%22Bernhard%2C%20Jennifer%20T.%22%29&pagesize-30">Bernhard, Jennifer T. (committee member), Champaign%22%20%2Bcontributor%3A%28%22Wong%2C%20Martin%20D.%20F.%22%29&pagesize-30">Wong, Martin D. F. (committee member).

Subjects/Keywords: Enhanced Volume Integral Equation Method; Equivalence Principle Algorithm; Augmentation Technique; Low Frequency Problems

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APA (6^th Edition):

Sun, L. (2010). An enhanced volume integral equation method and augmented equivalence principle algorithm for low frequency problems. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/15564

Chicago Manual of Style (16^th Edition):

Sun, Lin. “An enhanced volume integral equation method and augmented equivalence principle algorithm for low frequency problems.” 2010. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed March 04, 2021. http://hdl.handle.net/2142/15564.

MLA Handbook (7^th Edition):

Sun, Lin. “An enhanced volume integral equation method and augmented equivalence principle algorithm for low frequency problems.” 2010. Web. 04 Mar 2021.

Vancouver:

Sun L. An enhanced volume integral equation method and augmented equivalence principle algorithm for low frequency problems. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2010. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/2142/15564.

Council of Science Editors:

Sun L. An enhanced volume integral equation method and augmented equivalence principle algorithm for low frequency problems. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2010. Available from: http://hdl.handle.net/2142/15564

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