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You searched for +publisher:"University of Illinois – Urbana-Champaign" +contributor:("Torrellas, Josep"). Showing records 1 – 30 of 44 total matches.

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University of Illinois – Urbana-Champaign

1. Heidarshenas, Azin. Architectural support for work-efficient relaxed priority queueing.

Degree: MS, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign

 Many parallel algorithms in domains such as graph analytics and simulations execute more efficiently if some parallel tasks are executed before others. To implement such… (more)

Subjects/Keywords: Priority queues; Concurrency; Scheduling

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Heidarshenas, A. (2017). Architectural support for work-efficient relaxed priority queueing. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/97627

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Heidarshenas, Azin. “Architectural support for work-efficient relaxed priority queueing.” 2017. Thesis, University of Illinois – Urbana-Champaign. Accessed February 28, 2021. http://hdl.handle.net/2142/97627.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Heidarshenas, Azin. “Architectural support for work-efficient relaxed priority queueing.” 2017. Web. 28 Feb 2021.

Vancouver:

Heidarshenas A. Architectural support for work-efficient relaxed priority queueing. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2017. [cited 2021 Feb 28]. Available from: http://hdl.handle.net/2142/97627.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Heidarshenas A. Architectural support for work-efficient relaxed priority queueing. [Thesis]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/97627

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

2. Jain, Prabhat. Refrint: intelligent refresh to minimize power in on-chip multiprocessor cache hierarchies.

Degree: MS, 0112, 2012, University of Illinois – Urbana-Champaign

 As manycores use dynamic energy ever more efficiently, static power consumption becomes a major concern. In particular, in a large manycore running at a low… (more)

Subjects/Keywords: Static random-access memory (SRAM); Embedded dynamic random-access memory (eDRAM); memory hierarchy; computer architecture; leakage; refresh power

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APA (6th Edition):

Jain, P. (2012). Refrint: intelligent refresh to minimize power in on-chip multiprocessor cache hierarchies. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/34585

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Jain, Prabhat. “Refrint: intelligent refresh to minimize power in on-chip multiprocessor cache hierarchies.” 2012. Thesis, University of Illinois – Urbana-Champaign. Accessed February 28, 2021. http://hdl.handle.net/2142/34585.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Jain, Prabhat. “Refrint: intelligent refresh to minimize power in on-chip multiprocessor cache hierarchies.” 2012. Web. 28 Feb 2021.

Vancouver:

Jain P. Refrint: intelligent refresh to minimize power in on-chip multiprocessor cache hierarchies. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2012. [cited 2021 Feb 28]. Available from: http://hdl.handle.net/2142/34585.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Jain P. Refrint: intelligent refresh to minimize power in on-chip multiprocessor cache hierarchies. [Thesis]. University of Illinois – Urbana-Champaign; 2012. Available from: http://hdl.handle.net/2142/34585

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

3. Ahrens, Benjamin. Exploring alternatives to hardware support for fine-grain synchronization.

Degree: MS, 1200, 2013, University of Illinois – Urbana-Champaign

 As we prepare for the extreme-scale era of computing, communication overhead and synchronization between cores will soon become extremely important. In this work we study… (more)

Subjects/Keywords: fine-grain synchronization; compare-and-swap; full/empty bits

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APA (6th Edition):

Ahrens, B. (2013). Exploring alternatives to hardware support for fine-grain synchronization. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/42154

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ahrens, Benjamin. “Exploring alternatives to hardware support for fine-grain synchronization.” 2013. Thesis, University of Illinois – Urbana-Champaign. Accessed February 28, 2021. http://hdl.handle.net/2142/42154.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ahrens, Benjamin. “Exploring alternatives to hardware support for fine-grain synchronization.” 2013. Web. 28 Feb 2021.

Vancouver:

Ahrens B. Exploring alternatives to hardware support for fine-grain synchronization. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2013. [cited 2021 Feb 28]. Available from: http://hdl.handle.net/2142/42154.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ahrens B. Exploring alternatives to hardware support for fine-grain synchronization. [Thesis]. University of Illinois – Urbana-Champaign; 2013. Available from: http://hdl.handle.net/2142/42154

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

4. Pothukuchi, Raghavendra Pradyumna. Systematically controlling the error rates in variation-prone networks-on-chip for energy efficiency.

Degree: MS, 0112, 2015, University of Illinois – Urbana-Champaign

 Networks-on-Chip (NoCs) are prone to within-die process variation as they span the whole chip. To tolerate variation, their voltages (Vdd) carry overprovisioned guardbands. As a… (more)

Subjects/Keywords: Computer Architecture; Reliability; Energy efficiency

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APA (6th Edition):

Pothukuchi, R. P. (2015). Systematically controlling the error rates in variation-prone networks-on-chip for energy efficiency. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/73090

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Pothukuchi, Raghavendra Pradyumna. “Systematically controlling the error rates in variation-prone networks-on-chip for energy efficiency.” 2015. Thesis, University of Illinois – Urbana-Champaign. Accessed February 28, 2021. http://hdl.handle.net/2142/73090.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Pothukuchi, Raghavendra Pradyumna. “Systematically controlling the error rates in variation-prone networks-on-chip for energy efficiency.” 2015. Web. 28 Feb 2021.

Vancouver:

Pothukuchi RP. Systematically controlling the error rates in variation-prone networks-on-chip for energy efficiency. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2015. [cited 2021 Feb 28]. Available from: http://hdl.handle.net/2142/73090.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Pothukuchi RP. Systematically controlling the error rates in variation-prone networks-on-chip for energy efficiency. [Thesis]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/73090

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

5. Yan, Mengjia. Performance evaluation of VM-level record-and-replay techniques and applications.

Degree: MS, Computer Science, 2016, University of Illinois – Urbana-Champaign

 Virtual machine level record and replay can be used for complex system debugging and analysis, fault-tolerance replication and forensic analysis. Previous work on performance evaluation… (more)

Subjects/Keywords: Record and Replay; Virtualization; Checkpointing; VMI Analysis

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APA (6th Edition):

Yan, M. (2016). Performance evaluation of VM-level record-and-replay techniques and applications. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/90958

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yan, Mengjia. “Performance evaluation of VM-level record-and-replay techniques and applications.” 2016. Thesis, University of Illinois – Urbana-Champaign. Accessed February 28, 2021. http://hdl.handle.net/2142/90958.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yan, Mengjia. “Performance evaluation of VM-level record-and-replay techniques and applications.” 2016. Web. 28 Feb 2021.

Vancouver:

Yan M. Performance evaluation of VM-level record-and-replay techniques and applications. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2016. [cited 2021 Feb 28]. Available from: http://hdl.handle.net/2142/90958.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yan M. Performance evaluation of VM-level record-and-replay techniques and applications. [Thesis]. University of Illinois – Urbana-Champaign; 2016. Available from: http://hdl.handle.net/2142/90958

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

6. Shalabi, Yasser Hussein. Record and replay based virtual-machine introspection for system security.

Degree: MS, Electrical & Computer Engr, 2016, University of Illinois – Urbana-Champaign

 Hardware security features need to strike a careful balance between design intrusiveness and completeness of methods. Securing against attacks like Return Oriented Programming (ROP) requires… (more)

Subjects/Keywords: Security; Operating systems (OS); Return oriented programming (ROP); Virtual machine; Virtual machine introspection (VMI); Control flow integrity (CFI)

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APA (6th Edition):

Shalabi, Y. H. (2016). Record and replay based virtual-machine introspection for system security. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/95601

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Shalabi, Yasser Hussein. “Record and replay based virtual-machine introspection for system security.” 2016. Thesis, University of Illinois – Urbana-Champaign. Accessed February 28, 2021. http://hdl.handle.net/2142/95601.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Shalabi, Yasser Hussein. “Record and replay based virtual-machine introspection for system security.” 2016. Web. 28 Feb 2021.

Vancouver:

Shalabi YH. Record and replay based virtual-machine introspection for system security. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2016. [cited 2021 Feb 28]. Available from: http://hdl.handle.net/2142/95601.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Shalabi YH. Record and replay based virtual-machine introspection for system security. [Thesis]. University of Illinois – Urbana-Champaign; 2016. Available from: http://hdl.handle.net/2142/95601

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

7. Skarlatos, Dimitrios State. Opportunistic power reassignment between processor and memory in 3D stacks.

Degree: MS, Computer Science, 2016, University of Illinois – Urbana-Champaign

 The pin count largely determines the cost of a chip package, which is often comparable to the cost of a die. In 3D processor-memory designs,… (more)

Subjects/Keywords: 3D die-stacking; Power management; Processor; Memory; Low-power; Energy efficiency; Mobile processors; Voltage regulation; Computer architecture

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APA (6th Edition):

Skarlatos, D. S. (2016). Opportunistic power reassignment between processor and memory in 3D stacks. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/95609

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Skarlatos, Dimitrios State. “Opportunistic power reassignment between processor and memory in 3D stacks.” 2016. Thesis, University of Illinois – Urbana-Champaign. Accessed February 28, 2021. http://hdl.handle.net/2142/95609.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Skarlatos, Dimitrios State. “Opportunistic power reassignment between processor and memory in 3D stacks.” 2016. Web. 28 Feb 2021.

Vancouver:

Skarlatos DS. Opportunistic power reassignment between processor and memory in 3D stacks. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2016. [cited 2021 Feb 28]. Available from: http://hdl.handle.net/2142/95609.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Skarlatos DS. Opportunistic power reassignment between processor and memory in 3D stacks. [Thesis]. University of Illinois – Urbana-Champaign; 2016. Available from: http://hdl.handle.net/2142/95609

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

8. Bohloolizamani, Ali. Efficient mobile computing.

Degree: MS, Computer Science, 2017, University of Illinois – Urbana-Champaign

 Smart handheld devices such as phones, tablets and watches are becoming more and more common rapidly. From a computer architect point of view, processor design… (more)

Subjects/Keywords: big.LITTLE; Linux scheduler; Efficiency; Mobile processor

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APA (6th Edition):

Bohloolizamani, A. (2017). Efficient mobile computing. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/97250

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Bohloolizamani, Ali. “Efficient mobile computing.” 2017. Thesis, University of Illinois – Urbana-Champaign. Accessed February 28, 2021. http://hdl.handle.net/2142/97250.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Bohloolizamani, Ali. “Efficient mobile computing.” 2017. Web. 28 Feb 2021.

Vancouver:

Bohloolizamani A. Efficient mobile computing. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2017. [cited 2021 Feb 28]. Available from: http://hdl.handle.net/2142/97250.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Bohloolizamani A. Efficient mobile computing. [Thesis]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/97250

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

9. Agarwal, Rishi. Rebound: Scalable checkpointing for coherent shared memory.

Degree: MS, 0112, 2011, University of Illinois – Urbana-Champaign

 As we move to large manycores, the hardware-based global checkpointing schemes that have been proposed for small shared-memory machines do not scale. Scalability barriers include… (more)

Subjects/Keywords: Scalable Checkpointing; Shared-Memory Multiprocessors; Faults

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APA (6th Edition):

Agarwal, R. (2011). Rebound: Scalable checkpointing for coherent shared memory. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/24039

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Agarwal, Rishi. “Rebound: Scalable checkpointing for coherent shared memory.” 2011. Thesis, University of Illinois – Urbana-Champaign. Accessed February 28, 2021. http://hdl.handle.net/2142/24039.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Agarwal, Rishi. “Rebound: Scalable checkpointing for coherent shared memory.” 2011. Web. 28 Feb 2021.

Vancouver:

Agarwal R. Rebound: Scalable checkpointing for coherent shared memory. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2011. [cited 2021 Feb 28]. Available from: http://hdl.handle.net/2142/24039.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Agarwal R. Rebound: Scalable checkpointing for coherent shared memory. [Thesis]. University of Illinois – Urbana-Champaign; 2011. Available from: http://hdl.handle.net/2142/24039

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

10. Shull, Thomas Edward. Making non-volatile memory programmable.

Degree: PhD, Computer Science, 2020, University of Illinois – Urbana-Champaign

 Byte-addressable, non-volatile memory (NVM) is emerging as a revolutionary memory technology that provides persistence, near-DRAM performance, and scalable capacity. By using NVM, applications can directly… (more)

Subjects/Keywords: non-volatile memory; java; instruction set architecture; memory models

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APA (6th Edition):

Shull, T. E. (2020). Making non-volatile memory programmable. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/108493

Chicago Manual of Style (16th Edition):

Shull, Thomas Edward. “Making non-volatile memory programmable.” 2020. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed February 28, 2021. http://hdl.handle.net/2142/108493.

MLA Handbook (7th Edition):

Shull, Thomas Edward. “Making non-volatile memory programmable.” 2020. Web. 28 Feb 2021.

Vancouver:

Shull TE. Making non-volatile memory programmable. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2020. [cited 2021 Feb 28]. Available from: http://hdl.handle.net/2142/108493.

Council of Science Editors:

Shull TE. Making non-volatile memory programmable. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2020. Available from: http://hdl.handle.net/2142/108493


University of Illinois – Urbana-Champaign

11. Qi, Shanxiang. Techniques to detect and avert advanced software concurrency bugs.

Degree: PhD, 0112, 2013, University of Illinois – Urbana-Champaign

 Multicore machines have become pervasive and, as a result, parallel programming has received renewed interest. Unfortunately, writing correct parallel programs is notoriously hard. One challenging… (more)

Subjects/Keywords: concurrency bugs; data race detection; dynamic analysis

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Qi, S. (2013). Techniques to detect and avert advanced software concurrency bugs. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/45603

Chicago Manual of Style (16th Edition):

Qi, Shanxiang. “Techniques to detect and avert advanced software concurrency bugs.” 2013. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed February 28, 2021. http://hdl.handle.net/2142/45603.

MLA Handbook (7th Edition):

Qi, Shanxiang. “Techniques to detect and avert advanced software concurrency bugs.” 2013. Web. 28 Feb 2021.

Vancouver:

Qi S. Techniques to detect and avert advanced software concurrency bugs. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2013. [cited 2021 Feb 28]. Available from: http://hdl.handle.net/2142/45603.

Council of Science Editors:

Qi S. Techniques to detect and avert advanced software concurrency bugs. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2013. Available from: http://hdl.handle.net/2142/45603


University of Illinois – Urbana-Champaign

12. Agrawal, Aditya. Refresh reduction in dynamic memories.

Degree: PhD, 1200, 2015, University of Illinois – Urbana-Champaign

 An effective approach to reduce the static energy consumption of large on-chip memories is to use a low-leakage technology such as embedded DRAM (eDRAM). Unfortunately,… (more)

Subjects/Keywords: dynamic random-access memory (DRAM); embedded dynamic random-access memory (eDRAM); Cache; dynamic memory; refresh; three-dimensional (3D); stacking; retention time; Through Silicon Vias (TSV); Thermal Through Silicon Vias (TTSV); temperature; leakage; variation; spatial

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Agrawal, A. (2015). Refresh reduction in dynamic memories. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/72970

Chicago Manual of Style (16th Edition):

Agrawal, Aditya. “Refresh reduction in dynamic memories.” 2015. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed February 28, 2021. http://hdl.handle.net/2142/72970.

MLA Handbook (7th Edition):

Agrawal, Aditya. “Refresh reduction in dynamic memories.” 2015. Web. 28 Feb 2021.

Vancouver:

Agrawal A. Refresh reduction in dynamic memories. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2015. [cited 2021 Feb 28]. Available from: http://hdl.handle.net/2142/72970.

Council of Science Editors:

Agrawal A. Refresh reduction in dynamic memories. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/72970


University of Illinois – Urbana-Champaign

13. Kim, Wooil. Architecting, programming, and evaluating an on-chip incoherent multi-processor memory hierarchy.

Degree: PhD, Computer Science, 2015, University of Illinois – Urbana-Champaign

 New architectures for extreme-scale computing need to be designed for higher energy efficiency than current systems. The DOE-funded Traleika Glacier architecture is a recently-proposed extreme-scale… (more)

Subjects/Keywords: incoherent cache hierarchy; scratchpad hierarchy; compiler-directed coherence; Runnemede architecture

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APA (6th Edition):

Kim, W. (2015). Architecting, programming, and evaluating an on-chip incoherent multi-processor memory hierarchy. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/89128

Chicago Manual of Style (16th Edition):

Kim, Wooil. “Architecting, programming, and evaluating an on-chip incoherent multi-processor memory hierarchy.” 2015. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed February 28, 2021. http://hdl.handle.net/2142/89128.

MLA Handbook (7th Edition):

Kim, Wooil. “Architecting, programming, and evaluating an on-chip incoherent multi-processor memory hierarchy.” 2015. Web. 28 Feb 2021.

Vancouver:

Kim W. Architecting, programming, and evaluating an on-chip incoherent multi-processor memory hierarchy. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2015. [cited 2021 Feb 28]. Available from: http://hdl.handle.net/2142/89128.

Council of Science Editors:

Kim W. Architecting, programming, and evaluating an on-chip incoherent multi-processor memory hierarchy. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/89128


University of Illinois – Urbana-Champaign

14. Katelman, Michael. A meta-language for functional verification.

Degree: PhD, 0112, 2012, University of Illinois – Urbana-Champaign

 This dissertation perceives a similarity between two activities: that of coordinating the search for simulation traces toward reaching verification closure, and that of coordinating the… (more)

Subjects/Keywords: Programming Languages; Formal Methods; Hardware Verification

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APA (6th Edition):

Katelman, M. (2012). A meta-language for functional verification. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/29614

Chicago Manual of Style (16th Edition):

Katelman, Michael. “A meta-language for functional verification.” 2012. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed February 28, 2021. http://hdl.handle.net/2142/29614.

MLA Handbook (7th Edition):

Katelman, Michael. “A meta-language for functional verification.” 2012. Web. 28 Feb 2021.

Vancouver:

Katelman M. A meta-language for functional verification. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2012. [cited 2021 Feb 28]. Available from: http://hdl.handle.net/2142/29614.

Council of Science Editors:

Katelman M. A meta-language for functional verification. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2012. Available from: http://hdl.handle.net/2142/29614


University of Illinois – Urbana-Champaign

15. Muzahid, Abdullah. Effective architectural support for detecting concurrency bugs.

Degree: PhD, 0112, 2012, University of Illinois – Urbana-Champaign

 Multicore machines have become pervasive and, as a result, parallel programming has received renewed interest. Unfortunately, writing correct parallel programs is notoriously hard. Therefore, it… (more)

Subjects/Keywords: Debugging; Concurrency Bugs; Multithreaded Programs; Multicore

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APA (6th Edition):

Muzahid, A. (2012). Effective architectural support for detecting concurrency bugs. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/34513

Chicago Manual of Style (16th Edition):

Muzahid, Abdullah. “Effective architectural support for detecting concurrency bugs.” 2012. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed February 28, 2021. http://hdl.handle.net/2142/34513.

MLA Handbook (7th Edition):

Muzahid, Abdullah. “Effective architectural support for detecting concurrency bugs.” 2012. Web. 28 Feb 2021.

Vancouver:

Muzahid A. Effective architectural support for detecting concurrency bugs. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2012. [cited 2021 Feb 28]. Available from: http://hdl.handle.net/2142/34513.

Council of Science Editors:

Muzahid A. Effective architectural support for detecting concurrency bugs. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2012. Available from: http://hdl.handle.net/2142/34513


University of Illinois – Urbana-Champaign

16. Karpuzcu, Rahmet. Novel many-core architectures for energy-efficiency.

Degree: PhD, 1200, 2012, University of Illinois – Urbana-Champaign

 Ideal CMOS device scaling relies on scaling voltages down with lithographic dimensions at every technology generation. This gives rise to faster circuits due to higher… (more)

Subjects/Keywords: Power constraints; Dark silicon; Near-threshold voltage; Many-core architectures; Process variations; Static random-access memory (SRAM) fault models; Wear-Out

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APA (6th Edition):

Karpuzcu, R. (2012). Novel many-core architectures for energy-efficiency. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/34560

Chicago Manual of Style (16th Edition):

Karpuzcu, Rahmet. “Novel many-core architectures for energy-efficiency.” 2012. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed February 28, 2021. http://hdl.handle.net/2142/34560.

MLA Handbook (7th Edition):

Karpuzcu, Rahmet. “Novel many-core architectures for energy-efficiency.” 2012. Web. 28 Feb 2021.

Vancouver:

Karpuzcu R. Novel many-core architectures for energy-efficiency. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2012. [cited 2021 Feb 28]. Available from: http://hdl.handle.net/2142/34560.

Council of Science Editors:

Karpuzcu R. Novel many-core architectures for energy-efficiency. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2012. Available from: http://hdl.handle.net/2142/34560


University of Illinois – Urbana-Champaign

17. Ahn, Daniel. Software and architecture support for the bulk multicore.

Degree: PhD, 0112, 2012, University of Illinois – Urbana-Champaign

 Research on transactional memory began as a tool to improve the experience of programmers working on parallel code. Just as transactions in databases, it was… (more)

Subjects/Keywords: Computer Architecture; Compiler; Transactional Memory; Transactional Execution; Speculative Optimization; Bloomfilter; Signature; Memory Model; Sequential Consistency; Function Memoization; Alias Analysis

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APA (6th Edition):

Ahn, D. (2012). Software and architecture support for the bulk multicore. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/32076

Chicago Manual of Style (16th Edition):

Ahn, Daniel. “Software and architecture support for the bulk multicore.” 2012. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed February 28, 2021. http://hdl.handle.net/2142/32076.

MLA Handbook (7th Edition):

Ahn, Daniel. “Software and architecture support for the bulk multicore.” 2012. Web. 28 Feb 2021.

Vancouver:

Ahn D. Software and architecture support for the bulk multicore. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2012. [cited 2021 Feb 28]. Available from: http://hdl.handle.net/2142/32076.

Council of Science Editors:

Ahn D. Software and architecture support for the bulk multicore. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2012. Available from: http://hdl.handle.net/2142/32076


University of Illinois – Urbana-Champaign

18. Gopi Reddy, Bhargava Reddy. Energy efficient core designs for upcoming process technologies.

Degree: PhD, Computer Science, 2019, University of Illinois – Urbana-Champaign

 Energy efficiency has been a first order constraint in the design of micro processors for the last decade. As Moore's law sunsets, new technologies are… (more)

Subjects/Keywords: Energy efficient architecture; TFET; Monolithic 3D; ScalCore; HetCore; Microarchitecture; Processor; CPU; Low Voltage

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APA (6th Edition):

Gopi Reddy, B. R. (2019). Energy efficient core designs for upcoming process technologies. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/104832

Chicago Manual of Style (16th Edition):

Gopi Reddy, Bhargava Reddy. “Energy efficient core designs for upcoming process technologies.” 2019. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed February 28, 2021. http://hdl.handle.net/2142/104832.

MLA Handbook (7th Edition):

Gopi Reddy, Bhargava Reddy. “Energy efficient core designs for upcoming process technologies.” 2019. Web. 28 Feb 2021.

Vancouver:

Gopi Reddy BR. Energy efficient core designs for upcoming process technologies. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2019. [cited 2021 Feb 28]. Available from: http://hdl.handle.net/2142/104832.

Council of Science Editors:

Gopi Reddy BR. Energy efficient core designs for upcoming process technologies. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2019. Available from: http://hdl.handle.net/2142/104832


University of Illinois – Urbana-Champaign

19. Nistor, Adrian. Understanding, detecting, and repairing performance bugs.

Degree: PhD, 0112, 2014, University of Illinois – Urbana-Champaign

 Software performance is critical for how end-users perceive the quality of software products. Performance bugs – programming errors that cause performance degradation—lead to poor user experience… (more)

Subjects/Keywords: Performance bugs

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Nistor, A. (2014). Understanding, detecting, and repairing performance bugs. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/49706

Chicago Manual of Style (16th Edition):

Nistor, Adrian. “Understanding, detecting, and repairing performance bugs.” 2014. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed February 28, 2021. http://hdl.handle.net/2142/49706.

MLA Handbook (7th Edition):

Nistor, Adrian. “Understanding, detecting, and repairing performance bugs.” 2014. Web. 28 Feb 2021.

Vancouver:

Nistor A. Understanding, detecting, and repairing performance bugs. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2014. [cited 2021 Feb 28]. Available from: http://hdl.handle.net/2142/49706.

Council of Science Editors:

Nistor A. Understanding, detecting, and repairing performance bugs. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2014. Available from: http://hdl.handle.net/2142/49706


University of Illinois – Urbana-Champaign

20. Jain, Nikhil. Optimization of communication intensive applications on HPC networks.

Degree: PhD, Computer Science, 2016, University of Illinois – Urbana-Champaign

 Communication is a necessary but overhead inducing component of parallel programming. Its impact on application design and performance is due to several related aspects of… (more)

Subjects/Keywords: Network; Communication; Parallel computing; Applications; Simulation; Modeling; Prediction; Machine learning; Topology-aware mapping

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APA (6th Edition):

Jain, N. (2016). Optimization of communication intensive applications on HPC networks. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/90472

Chicago Manual of Style (16th Edition):

Jain, Nikhil. “Optimization of communication intensive applications on HPC networks.” 2016. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed February 28, 2021. http://hdl.handle.net/2142/90472.

MLA Handbook (7th Edition):

Jain, Nikhil. “Optimization of communication intensive applications on HPC networks.” 2016. Web. 28 Feb 2021.

Vancouver:

Jain N. Optimization of communication intensive applications on HPC networks. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2016. [cited 2021 Feb 28]. Available from: http://hdl.handle.net/2142/90472.

Council of Science Editors:

Jain N. Optimization of communication intensive applications on HPC networks. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2016. Available from: http://hdl.handle.net/2142/90472


University of Illinois – Urbana-Champaign

21. Jian, Xun. Common-case optimized memory hierarchy for data centers and HPC systems.

Degree: PhD, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign

 The memory hierarchy is predicted to consume up to 40% to 70% of total system power in future data centers and high performance computing (HPC)… (more)

Subjects/Keywords: Memory hierarchy; Computer architecture; Energy-efficient computing; Fault-tolerant computing

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APA (6th Edition):

Jian, X. (2017). Common-case optimized memory hierarchy for data centers and HPC systems. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/99448

Chicago Manual of Style (16th Edition):

Jian, Xun. “Common-case optimized memory hierarchy for data centers and HPC systems.” 2017. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed February 28, 2021. http://hdl.handle.net/2142/99448.

MLA Handbook (7th Edition):

Jian, Xun. “Common-case optimized memory hierarchy for data centers and HPC systems.” 2017. Web. 28 Feb 2021.

Vancouver:

Jian X. Common-case optimized memory hierarchy for data centers and HPC systems. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2017. [cited 2021 Feb 28]. Available from: http://hdl.handle.net/2142/99448.

Council of Science Editors:

Jian X. Common-case optimized memory hierarchy for data centers and HPC systems. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/99448


University of Illinois – Urbana-Champaign

22. Acun, Bilge. Mitigating variability in HPC systems and applications for performance and power efficiency.

Degree: PhD, Computer Science, 2017, University of Illinois – Urbana-Champaign

 Power consumption and process variability are two important, interconnected, challenges of future generation large-scale High Performance Computing (HPC) data centers. For example, current production petaflop… (more)

Subjects/Keywords: Power; Energy; Temperature; Frequency; High performance computing (HPC); Variability; Data center; Performance; Supercomputer; Energy consumption; Power variation; Frequency variation; Temperature variation; Energy efficient algorithms; Cooling power; Fan control; Runtime systems; Load balancing; Dynamic runtimes; Manufacturing variations; Turbo-boost; Dynamic voltage and frequency scaling (DVFS); Parallel computing

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APA (6th Edition):

Acun, B. (2017). Mitigating variability in HPC systems and applications for performance and power efficiency. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/99502

Chicago Manual of Style (16th Edition):

Acun, Bilge. “Mitigating variability in HPC systems and applications for performance and power efficiency.” 2017. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed February 28, 2021. http://hdl.handle.net/2142/99502.

MLA Handbook (7th Edition):

Acun, Bilge. “Mitigating variability in HPC systems and applications for performance and power efficiency.” 2017. Web. 28 Feb 2021.

Vancouver:

Acun B. Mitigating variability in HPC systems and applications for performance and power efficiency. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2017. [cited 2021 Feb 28]. Available from: http://hdl.handle.net/2142/99502.

Council of Science Editors:

Acun B. Mitigating variability in HPC systems and applications for performance and power efficiency. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/99502


University of Illinois – Urbana-Champaign

23. Pothukuchi, Raghavendra Pradyumna. Intelligent systems for efficiency and security.

Degree: PhD, Computer Science, 2020, University of Illinois – Urbana-Champaign

 As computing becomes ubiquitous and personalized, resources like energy, storage and time are becoming increasingly scarce and, at the same time, computing systems must deliver… (more)

Subjects/Keywords: resource management; computer architecture; computer systems; control theory; processors; performance management; power management; thermal management; energy efficiency; power side channels; security; machine learning; adaptive systems; robust control; MIMO; distributed resource management; heterogeneous computers; computer science

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Pothukuchi, R. P. (2020). Intelligent systems for efficiency and security. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/108504

Chicago Manual of Style (16th Edition):

Pothukuchi, Raghavendra Pradyumna. “Intelligent systems for efficiency and security.” 2020. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed February 28, 2021. http://hdl.handle.net/2142/108504.

MLA Handbook (7th Edition):

Pothukuchi, Raghavendra Pradyumna. “Intelligent systems for efficiency and security.” 2020. Web. 28 Feb 2021.

Vancouver:

Pothukuchi RP. Intelligent systems for efficiency and security. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2020. [cited 2021 Feb 28]. Available from: http://hdl.handle.net/2142/108504.

Council of Science Editors:

Pothukuchi RP. Intelligent systems for efficiency and security. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2020. Available from: http://hdl.handle.net/2142/108504


University of Illinois – Urbana-Champaign

24. Alian, Mohammad. A cross-stack, network-centric architectural design for next-generation datacenters.

Degree: PhD, Electrical & Computer Engr, 2020, University of Illinois – Urbana-Champaign

 This thesis proposes a full-stack, cross-layer datacenter architecture based on in-network computing and near-memory processing paradigms. The proposed datacenter architecture is built atop two principles:… (more)

Subjects/Keywords: datacenter architecture; near-data processing; near-memory processing; in-network computing; distributed simulation; datacenter network architecture; scale-out processing

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APA (6th Edition):

Alian, M. (2020). A cross-stack, network-centric architectural design for next-generation datacenters. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/108449

Chicago Manual of Style (16th Edition):

Alian, Mohammad. “A cross-stack, network-centric architectural design for next-generation datacenters.” 2020. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed February 28, 2021. http://hdl.handle.net/2142/108449.

MLA Handbook (7th Edition):

Alian, Mohammad. “A cross-stack, network-centric architectural design for next-generation datacenters.” 2020. Web. 28 Feb 2021.

Vancouver:

Alian M. A cross-stack, network-centric architectural design for next-generation datacenters. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2020. [cited 2021 Feb 28]. Available from: http://hdl.handle.net/2142/108449.

Council of Science Editors:

Alian M. A cross-stack, network-centric architectural design for next-generation datacenters. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2020. Available from: http://hdl.handle.net/2142/108449

25. Gangwani, Tanmay. Breaking serialization in lock-free multicore synchronization.

Degree: MS, Electrical & Computer Engr, 2016, University of Illinois – Urbana-Champaign

 In multicores, performance-critical synchronization is increasingly performed in a lock-free manner using atomic instructions such as CAS or LL/SC. However, when many processors synchronize on… (more)

Subjects/Keywords: lock-free synchronization; serialization; parallel programming

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APA (6th Edition):

Gangwani, T. (2016). Breaking serialization in lock-free multicore synchronization. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/92858

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Gangwani, Tanmay. “Breaking serialization in lock-free multicore synchronization.” 2016. Thesis, University of Illinois – Urbana-Champaign. Accessed February 28, 2021. http://hdl.handle.net/2142/92858.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Gangwani, Tanmay. “Breaking serialization in lock-free multicore synchronization.” 2016. Web. 28 Feb 2021.

Vancouver:

Gangwani T. Breaking serialization in lock-free multicore synchronization. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2016. [cited 2021 Feb 28]. Available from: http://hdl.handle.net/2142/92858.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Gangwani T. Breaking serialization in lock-free multicore synchronization. [Thesis]. University of Illinois – Urbana-Champaign; 2016. Available from: http://hdl.handle.net/2142/92858

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

26. Fellows, Kurt. A comparative study of the effects of parallelization on ARM and Intel based platforms.

Degree: MS, 1200, 2014, University of Illinois – Urbana-Champaign

 With the enormous growth in popularity of mobile devices in the past decade, there has been a large push in industry for chip designers and… (more)

Subjects/Keywords: Single Instruction Multiple Data (SIMD); Thread Building Blocks; OpenMP; NEON; Streaming SIMD Extensions (SSE); Advanced Vector Extensions (AVX)

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APA (6th Edition):

Fellows, K. (2014). A comparative study of the effects of parallelization on ARM and Intel based platforms. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/50710

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Fellows, Kurt. “A comparative study of the effects of parallelization on ARM and Intel based platforms.” 2014. Thesis, University of Illinois – Urbana-Champaign. Accessed February 28, 2021. http://hdl.handle.net/2142/50710.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Fellows, Kurt. “A comparative study of the effects of parallelization on ARM and Intel based platforms.” 2014. Web. 28 Feb 2021.

Vancouver:

Fellows K. A comparative study of the effects of parallelization on ARM and Intel based platforms. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2014. [cited 2021 Feb 28]. Available from: http://hdl.handle.net/2142/50710.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Fellows K. A comparative study of the effects of parallelization on ARM and Intel based platforms. [Thesis]. University of Illinois – Urbana-Champaign; 2014. Available from: http://hdl.handle.net/2142/50710

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

27. Choi, Jiho. HW-SW co-design techniques for modern programming languages.

Degree: PhD, Computer Science, 2018, University of Illinois – Urbana-Champaign

 Modern programming languages raise the level of abstraction, hide the details of computer systems from programmers, and provide many convenient features. Such strong abstraction from… (more)

Subjects/Keywords: Computer Architecture; Compiler; Inline Caching; Garbage Collection

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APA (6th Edition):

Choi, J. (2018). HW-SW co-design techniques for modern programming languages. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/102482

Chicago Manual of Style (16th Edition):

Choi, Jiho. “HW-SW co-design techniques for modern programming languages.” 2018. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed February 28, 2021. http://hdl.handle.net/2142/102482.

MLA Handbook (7th Edition):

Choi, Jiho. “HW-SW co-design techniques for modern programming languages.” 2018. Web. 28 Feb 2021.

Vancouver:

Choi J. HW-SW co-design techniques for modern programming languages. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2018. [cited 2021 Feb 28]. Available from: http://hdl.handle.net/2142/102482.

Council of Science Editors:

Choi J. HW-SW co-design techniques for modern programming languages. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2018. Available from: http://hdl.handle.net/2142/102482


University of Illinois – Urbana-Champaign

28. Karpuzcu, Rahmet U. Managing Many-Core Aging.

Degree: MS, 1200, 2010, University of Illinois – Urbana-Champaign

 Many-core scaling now faces a power wall. The gap between the number of cores that fit on a die and the number that can operate… (more)

Subjects/Keywords: Processor Aging; Voltage Scaling; Process Scaling; Power Wall.

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APA (6th Edition):

Karpuzcu, R. U. (2010). Managing Many-Core Aging. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/14617

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Karpuzcu, Rahmet U. “Managing Many-Core Aging.” 2010. Thesis, University of Illinois – Urbana-Champaign. Accessed February 28, 2021. http://hdl.handle.net/2142/14617.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Karpuzcu, Rahmet U. “Managing Many-Core Aging.” 2010. Web. 28 Feb 2021.

Vancouver:

Karpuzcu RU. Managing Many-Core Aging. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2010. [cited 2021 Feb 28]. Available from: http://hdl.handle.net/2142/14617.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Karpuzcu RU. Managing Many-Core Aging. [Thesis]. University of Illinois – Urbana-Champaign; 2010. Available from: http://hdl.handle.net/2142/14617

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

29. Duan, Yue Lu. Techniques for low overhead fences and sequential consistency violation recording.

Degree: PhD, 0112, 2015, University of Illinois – Urbana-Champaign

 Fences are instructions that programmers or compilers insert in the code to prevent the compiler or the hardware from reordering memory accesses [20, 43]. Fences… (more)

Subjects/Keywords: Fence; Sequential Consistency Violation

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APA (6th Edition):

Duan, Y. L. (2015). Techniques for low overhead fences and sequential consistency violation recording. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/72747

Chicago Manual of Style (16th Edition):

Duan, Yue Lu. “Techniques for low overhead fences and sequential consistency violation recording.” 2015. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed February 28, 2021. http://hdl.handle.net/2142/72747.

MLA Handbook (7th Edition):

Duan, Yue Lu. “Techniques for low overhead fences and sequential consistency violation recording.” 2015. Web. 28 Feb 2021.

Vancouver:

Duan YL. Techniques for low overhead fences and sequential consistency violation recording. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2015. [cited 2021 Feb 28]. Available from: http://hdl.handle.net/2142/72747.

Council of Science Editors:

Duan YL. Techniques for low overhead fences and sequential consistency violation recording. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/72747


University of Illinois – Urbana-Champaign

30. Qi, Shanxiang. Tolerating asymmetric data races with minimal hardware support.

Degree: MS, 0112, 2010, University of Illinois – Urbana-Champaign

 Data races are a common type of concurrency bug in parallel programs. An important type of race that has not received much attention is Asymmetric… (more)

Subjects/Keywords: computer architecture; software reliability; concurrency bugs

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Qi, S. (2010). Tolerating asymmetric data races with minimal hardware support. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/15995

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Qi, Shanxiang. “Tolerating asymmetric data races with minimal hardware support.” 2010. Thesis, University of Illinois – Urbana-Champaign. Accessed February 28, 2021. http://hdl.handle.net/2142/15995.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Qi, Shanxiang. “Tolerating asymmetric data races with minimal hardware support.” 2010. Web. 28 Feb 2021.

Vancouver:

Qi S. Tolerating asymmetric data races with minimal hardware support. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2010. [cited 2021 Feb 28]. Available from: http://hdl.handle.net/2142/15995.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Qi S. Tolerating asymmetric data races with minimal hardware support. [Thesis]. University of Illinois – Urbana-Champaign; 2010. Available from: http://hdl.handle.net/2142/15995

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

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