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You searched for +publisher:"University of Illinois – Urbana-Champaign" +contributor:("Snir, Marc"). Showing records 1 – 27 of 27 total matches.

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University of Illinois – Urbana-Champaign

1. Behzad, Babak. Auto-tuned optimized parallel I/O for GIScience and spatial applications.

Degree: MS, 0112, 2013, University of Illinois – Urbana-Champaign

 Reading and writing big data is increasingly becoming a major bottleneck of using high-performance computing systems as we are heading towards the Exascale era. An… (more)

Subjects/Keywords: Parallel I/O; GIScience; High Performance Computing (HPC); Spatial Applications; Auto-Tuning

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Behzad, B. (2013). Auto-tuned optimized parallel I/O for GIScience and spatial applications. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/44414

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Behzad, Babak. “Auto-tuned optimized parallel I/O for GIScience and spatial applications.” 2013. Thesis, University of Illinois – Urbana-Champaign. Accessed September 15, 2019. http://hdl.handle.net/2142/44414.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Behzad, Babak. “Auto-tuned optimized parallel I/O for GIScience and spatial applications.” 2013. Web. 15 Sep 2019.

Vancouver:

Behzad B. Auto-tuned optimized parallel I/O for GIScience and spatial applications. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2013. [cited 2019 Sep 15]. Available from: http://hdl.handle.net/2142/44414.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Behzad B. Auto-tuned optimized parallel I/O for GIScience and spatial applications. [Thesis]. University of Illinois – Urbana-Champaign; 2013. Available from: http://hdl.handle.net/2142/44414

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

2. Gainaru, Ana. Failure avoidance techniques for HPC systems based on failure prediction.

Degree: PhD, Computer Science, 2015, University of Illinois – Urbana-Champaign

 A increasingly larger percentage of computing capacity in today's large high-performance computing systems is wasted due to failures and recoveries. Moreover, it is expected that… (more)

Subjects/Keywords: High Performance Computing (HPC); fault tolerance; resiliency; failure prediction; performance degradation

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APA (6th Edition):

Gainaru, A. (2015). Failure avoidance techniques for HPC systems based on failure prediction. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/88016

Chicago Manual of Style (16th Edition):

Gainaru, Ana. “Failure avoidance techniques for HPC systems based on failure prediction.” 2015. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed September 15, 2019. http://hdl.handle.net/2142/88016.

MLA Handbook (7th Edition):

Gainaru, Ana. “Failure avoidance techniques for HPC systems based on failure prediction.” 2015. Web. 15 Sep 2019.

Vancouver:

Gainaru A. Failure avoidance techniques for HPC systems based on failure prediction. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2015. [cited 2019 Sep 15]. Available from: http://hdl.handle.net/2142/88016.

Council of Science Editors:

Gainaru A. Failure avoidance techniques for HPC systems based on failure prediction. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/88016


University of Illinois – Urbana-Champaign

3. Behzad, Babak. Optimizing parallel I/O performance of HPC applications.

Degree: PhD, Computer Science, 2015, University of Illinois – Urbana-Champaign

 Parallel I/O is an essential component of modern High Performance Computing (HPC). Obtaining good I/O performance for a broad range of applications on diverse HPC… (more)

Subjects/Keywords: High Performance Computing (HPC); Parallel Computing; Parallel I/O; Big Data; Storage Performance Tuning; Autotuning

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APA (6th Edition):

Behzad, B. (2015). Optimizing parallel I/O performance of HPC applications. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/89120

Chicago Manual of Style (16th Edition):

Behzad, Babak. “Optimizing parallel I/O performance of HPC applications.” 2015. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed September 15, 2019. http://hdl.handle.net/2142/89120.

MLA Handbook (7th Edition):

Behzad, Babak. “Optimizing parallel I/O performance of HPC applications.” 2015. Web. 15 Sep 2019.

Vancouver:

Behzad B. Optimizing parallel I/O performance of HPC applications. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2015. [cited 2019 Sep 15]. Available from: http://hdl.handle.net/2142/89120.

Council of Science Editors:

Behzad B. Optimizing parallel I/O performance of HPC applications. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/89120


University of Illinois – Urbana-Champaign

4. Luu, Huong Vu Thanh. Optimizing I/O performance for high performance computing applications: from auto-tuning to a feedback-driven approach.

Degree: PhD, Computer Science, 2015, University of Illinois – Urbana-Champaign

 The 2014 TOP500 supercomputer list includes over 40 deployed petascale systems, and the high performance computing (HPC) community is working toward developing the first exaflop… (more)

Subjects/Keywords: High Performance Computing (HPC); Input/Output (I/O); Parallel I/O; Performance Analysis

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APA (6th Edition):

Luu, H. V. T. (2015). Optimizing I/O performance for high performance computing applications: from auto-tuning to a feedback-driven approach. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/78421

Chicago Manual of Style (16th Edition):

Luu, Huong Vu Thanh. “Optimizing I/O performance for high performance computing applications: from auto-tuning to a feedback-driven approach.” 2015. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed September 15, 2019. http://hdl.handle.net/2142/78421.

MLA Handbook (7th Edition):

Luu, Huong Vu Thanh. “Optimizing I/O performance for high performance computing applications: from auto-tuning to a feedback-driven approach.” 2015. Web. 15 Sep 2019.

Vancouver:

Luu HVT. Optimizing I/O performance for high performance computing applications: from auto-tuning to a feedback-driven approach. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2015. [cited 2019 Sep 15]. Available from: http://hdl.handle.net/2142/78421.

Council of Science Editors:

Luu HVT. Optimizing I/O performance for high performance computing applications: from auto-tuning to a feedback-driven approach. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/78421


University of Illinois – Urbana-Champaign

5. Kim, Wooil. Architecting, programming, and evaluating an on-chip incoherent multi-processor memory hierarchy.

Degree: PhD, Computer Science, 2015, University of Illinois – Urbana-Champaign

 New architectures for extreme-scale computing need to be designed for higher energy efficiency than current systems. The DOE-funded Traleika Glacier architecture is a recently-proposed extreme-scale… (more)

Subjects/Keywords: incoherent cache hierarchy; scratchpad hierarchy; compiler-directed coherence; Runnemede architecture

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APA (6th Edition):

Kim, W. (2015). Architecting, programming, and evaluating an on-chip incoherent multi-processor memory hierarchy. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/89128

Chicago Manual of Style (16th Edition):

Kim, Wooil. “Architecting, programming, and evaluating an on-chip incoherent multi-processor memory hierarchy.” 2015. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed September 15, 2019. http://hdl.handle.net/2142/89128.

MLA Handbook (7th Edition):

Kim, Wooil. “Architecting, programming, and evaluating an on-chip incoherent multi-processor memory hierarchy.” 2015. Web. 15 Sep 2019.

Vancouver:

Kim W. Architecting, programming, and evaluating an on-chip incoherent multi-processor memory hierarchy. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2015. [cited 2019 Sep 15]. Available from: http://hdl.handle.net/2142/89128.

Council of Science Editors:

Kim W. Architecting, programming, and evaluating an on-chip incoherent multi-processor memory hierarchy. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/89128


University of Illinois – Urbana-Champaign

6. Lee, Chee Wai. Techniques in scalable and effective parallel performance analysis.

Degree: PhD, 0112, 2010, University of Illinois – Urbana-Champaign

 Performance analysis tools are essential to the maintenance of efficient parallel execution of scientific applications. As scientific applications are executed on larger and larger parallel… (more)

Subjects/Keywords: Parallel Performance Tools; Scalability; Performance Analysis; High Performance Computing (HPC)

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APA (6th Edition):

Lee, C. W. (2010). Techniques in scalable and effective parallel performance analysis. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/14568

Chicago Manual of Style (16th Edition):

Lee, Chee Wai. “Techniques in scalable and effective parallel performance analysis.” 2010. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed September 15, 2019. http://hdl.handle.net/2142/14568.

MLA Handbook (7th Edition):

Lee, Chee Wai. “Techniques in scalable and effective parallel performance analysis.” 2010. Web. 15 Sep 2019.

Vancouver:

Lee CW. Techniques in scalable and effective parallel performance analysis. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2010. [cited 2019 Sep 15]. Available from: http://hdl.handle.net/2142/14568.

Council of Science Editors:

Lee CW. Techniques in scalable and effective parallel performance analysis. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2010. Available from: http://hdl.handle.net/2142/14568


University of Illinois – Urbana-Champaign

7. Zhao, Xin. Runtime support for irregular computation in MPI-based applications.

Degree: PhD, Computer Science, 2016, University of Illinois – Urbana-Champaign

 In recent years there are increasing number of applications that have been using irregular computation models in various domains, such as computational chemistry, bioinformatics, nuclear… (more)

Subjects/Keywords: Message Passing Interface (MPI); One-sided communication; Scalability; Active Messages, Irregular application

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APA (6th Edition):

Zhao, X. (2016). Runtime support for irregular computation in MPI-based applications. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/90933

Chicago Manual of Style (16th Edition):

Zhao, Xin. “Runtime support for irregular computation in MPI-based applications.” 2016. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed September 15, 2019. http://hdl.handle.net/2142/90933.

MLA Handbook (7th Edition):

Zhao, Xin. “Runtime support for irregular computation in MPI-based applications.” 2016. Web. 15 Sep 2019.

Vancouver:

Zhao X. Runtime support for irregular computation in MPI-based applications. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2016. [cited 2019 Sep 15]. Available from: http://hdl.handle.net/2142/90933.

Council of Science Editors:

Zhao X. Runtime support for irregular computation in MPI-based applications. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2016. Available from: http://hdl.handle.net/2142/90933


University of Illinois – Urbana-Champaign

8. Mikida, Eric P. Adaptive techniques for scalable optimistic parallel discrete event simulation.

Degree: PhD, Computer Science, 2019, University of Illinois – Urbana-Champaign

 Discrete Event Simulation (DES) can be an important tool across various domains such as Engineering, Military, Biology, High Performance Computing, and many others. Interacting systems… (more)

Subjects/Keywords: Parallel Computing; PDES; Simulation; Adaptive; GVT; Load Balancing

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APA (6th Edition):

Mikida, E. P. (2019). Adaptive techniques for scalable optimistic parallel discrete event simulation. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/104831

Chicago Manual of Style (16th Edition):

Mikida, Eric P. “Adaptive techniques for scalable optimistic parallel discrete event simulation.” 2019. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed September 15, 2019. http://hdl.handle.net/2142/104831.

MLA Handbook (7th Edition):

Mikida, Eric P. “Adaptive techniques for scalable optimistic parallel discrete event simulation.” 2019. Web. 15 Sep 2019.

Vancouver:

Mikida EP. Adaptive techniques for scalable optimistic parallel discrete event simulation. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2019. [cited 2019 Sep 15]. Available from: http://hdl.handle.net/2142/104831.

Council of Science Editors:

Mikida EP. Adaptive techniques for scalable optimistic parallel discrete event simulation. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2019. Available from: http://hdl.handle.net/2142/104831


University of Illinois – Urbana-Champaign

9. Alsop, Johnathan R. Specialization without complexity in heterogeneous memory systems.

Degree: PhD, Electrical & Computer Engr, 2018, University of Illinois – Urbana-Champaign

 The end of Dennard scaling and Moore's law has motivated a rise in the use of parallelism and hardware specialization in computer system design. Across… (more)

Subjects/Keywords: heterogeneous computing; coherence; consistency; memory systems; GPU

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APA (6th Edition):

Alsop, J. R. (2018). Specialization without complexity in heterogeneous memory systems. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/102480

Chicago Manual of Style (16th Edition):

Alsop, Johnathan R. “Specialization without complexity in heterogeneous memory systems.” 2018. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed September 15, 2019. http://hdl.handle.net/2142/102480.

MLA Handbook (7th Edition):

Alsop, Johnathan R. “Specialization without complexity in heterogeneous memory systems.” 2018. Web. 15 Sep 2019.

Vancouver:

Alsop JR. Specialization without complexity in heterogeneous memory systems. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2018. [cited 2019 Sep 15]. Available from: http://hdl.handle.net/2142/102480.

Council of Science Editors:

Alsop JR. Specialization without complexity in heterogeneous memory systems. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2018. Available from: http://hdl.handle.net/2142/102480


University of Illinois – Urbana-Champaign

10. Lifflander, Jonathan Josiah. Optimizing work stealing algorithms with scheduling constraints.

Degree: PhD, Computer Science, 2016, University of Illinois – Urbana-Champaign

 The fork-join paradigm of concurrent expression has gained popularity in conjunction with work-stealing schedulers. Random work-stealing schedulers have been shown to effectively perform dynamic load… (more)

Subjects/Keywords: concurrency; work-stealing; fork-join; scheduling; locality

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APA (6th Edition):

Lifflander, J. J. (2016). Optimizing work stealing algorithms with scheduling constraints. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/90511

Chicago Manual of Style (16th Edition):

Lifflander, Jonathan Josiah. “Optimizing work stealing algorithms with scheduling constraints.” 2016. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed September 15, 2019. http://hdl.handle.net/2142/90511.

MLA Handbook (7th Edition):

Lifflander, Jonathan Josiah. “Optimizing work stealing algorithms with scheduling constraints.” 2016. Web. 15 Sep 2019.

Vancouver:

Lifflander JJ. Optimizing work stealing algorithms with scheduling constraints. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2016. [cited 2019 Sep 15]. Available from: http://hdl.handle.net/2142/90511.

Council of Science Editors:

Lifflander JJ. Optimizing work stealing algorithms with scheduling constraints. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2016. Available from: http://hdl.handle.net/2142/90511


University of Illinois – Urbana-Champaign

11. Sinclair, Matthew David. Efficient coherence and consistency for specialized memory hierarchies.

Degree: PhD, Computer Science, 2017, University of Illinois – Urbana-Champaign

 As the benefits from transistor scaling slow down, specialization is becoming increasingly important for a wide range of applications. Although traditional heterogeneous systems work well… (more)

Subjects/Keywords: Shared memory; Heterogeneous systems; General purpose graphics processing unit (GPGPU); Caches memories; Cache coherence; Memory consistency; Scratchpads; Fine-grained synchronization

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APA (6th Edition):

Sinclair, M. D. (2017). Efficient coherence and consistency for specialized memory hierarchies. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/99316

Chicago Manual of Style (16th Edition):

Sinclair, Matthew David. “Efficient coherence and consistency for specialized memory hierarchies.” 2017. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed September 15, 2019. http://hdl.handle.net/2142/99316.

MLA Handbook (7th Edition):

Sinclair, Matthew David. “Efficient coherence and consistency for specialized memory hierarchies.” 2017. Web. 15 Sep 2019.

Vancouver:

Sinclair MD. Efficient coherence and consistency for specialized memory hierarchies. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2017. [cited 2019 Sep 15]. Available from: http://hdl.handle.net/2142/99316.

Council of Science Editors:

Sinclair MD. Efficient coherence and consistency for specialized memory hierarchies. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/99316


University of Illinois – Urbana-Champaign

12. Montesinos Ortego, Pablo. Practical Time Travel of Multiprocessor Systems.

Degree: PhD, Computer Science, 2009, University of Illinois – Urbana-Champaign

 With the arrival of multicore chips as the commodity architecture for a wide range of platforms, there is a growing pressure to make parallel programming… (more)

Subjects/Keywords: Deterministic Replay; Determinism; Time Travel; Multiprocessors; Debuggability; Programmability; Chunk-based Execution and Replay

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APA (6th Edition):

Montesinos Ortego, P. (2009). Practical Time Travel of Multiprocessor Systems. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/13395

Chicago Manual of Style (16th Edition):

Montesinos Ortego, Pablo. “Practical Time Travel of Multiprocessor Systems.” 2009. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed September 15, 2019. http://hdl.handle.net/2142/13395.

MLA Handbook (7th Edition):

Montesinos Ortego, Pablo. “Practical Time Travel of Multiprocessor Systems.” 2009. Web. 15 Sep 2019.

Vancouver:

Montesinos Ortego P. Practical Time Travel of Multiprocessor Systems. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2009. [cited 2019 Sep 15]. Available from: http://hdl.handle.net/2142/13395.

Council of Science Editors:

Montesinos Ortego P. Practical Time Travel of Multiprocessor Systems. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2009. Available from: http://hdl.handle.net/2142/13395


University of Illinois – Urbana-Champaign

13. Muzahid, Abdullah. Effective architectural support for detecting concurrency bugs.

Degree: PhD, 0112, 2012, University of Illinois – Urbana-Champaign

 Multicore machines have become pervasive and, as a result, parallel programming has received renewed interest. Unfortunately, writing correct parallel programs is notoriously hard. Therefore, it… (more)

Subjects/Keywords: Debugging; Concurrency Bugs; Multithreaded Programs; Multicore

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APA (6th Edition):

Muzahid, A. (2012). Effective architectural support for detecting concurrency bugs. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/34513

Chicago Manual of Style (16th Edition):

Muzahid, Abdullah. “Effective architectural support for detecting concurrency bugs.” 2012. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed September 15, 2019. http://hdl.handle.net/2142/34513.

MLA Handbook (7th Edition):

Muzahid, Abdullah. “Effective architectural support for detecting concurrency bugs.” 2012. Web. 15 Sep 2019.

Vancouver:

Muzahid A. Effective architectural support for detecting concurrency bugs. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2012. [cited 2019 Sep 15]. Available from: http://hdl.handle.net/2142/34513.

Council of Science Editors:

Muzahid A. Effective architectural support for detecting concurrency bugs. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2012. Available from: http://hdl.handle.net/2142/34513


University of Illinois – Urbana-Champaign

14. Bocchino, Robert L., Jr. An effect system and language for deterministic-by-default parallel programming.

Degree: PhD, 0112, 2011, University of Illinois – Urbana-Champaign

 This thesis presents a new, Java-based object-oriented parallel language called Deterministic Parallel Java (DPJ). DPJ uses a novel effect system to guarantee determinism by default.… (more)

Subjects/Keywords: parallel; parallelism; fork-join; programming languages; determinism; nondeterminism; regions; effects; effect systems; effect checking; strong isolation; atomicity; transactional memory; atomic sections; data race freedom; frameworks

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APA (6th Edition):

Bocchino, Robert L., J. (2011). An effect system and language for deterministic-by-default parallel programming. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/18416

Chicago Manual of Style (16th Edition):

Bocchino, Robert L., Jr. “An effect system and language for deterministic-by-default parallel programming.” 2011. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed September 15, 2019. http://hdl.handle.net/2142/18416.

MLA Handbook (7th Edition):

Bocchino, Robert L., Jr. “An effect system and language for deterministic-by-default parallel programming.” 2011. Web. 15 Sep 2019.

Vancouver:

Bocchino, Robert L. J. An effect system and language for deterministic-by-default parallel programming. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2011. [cited 2019 Sep 15]. Available from: http://hdl.handle.net/2142/18416.

Council of Science Editors:

Bocchino, Robert L. J. An effect system and language for deterministic-by-default parallel programming. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2011. Available from: http://hdl.handle.net/2142/18416

15. Nusbaum, Kurtis. Optimizing Barnes-Hut simulations for many-core super computers using the scalable parallel runtime.

Degree: MS, 0112, 2013, University of Illinois – Urbana-Champaign

 It is now generally accepted that the road to Exascale Super Computing will no doubt include increasing core counts on individual compute nodes. The Scalable… (more)

Subjects/Keywords: Barnes-Hut; Scalable Parallel Runtime (SPR); Qthreads; Parallel Programming Language (PPL); Many-Core; Exascale

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APA (6th Edition):

Nusbaum, K. (2013). Optimizing Barnes-Hut simulations for many-core super computers using the scalable parallel runtime. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/44186

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Nusbaum, Kurtis. “Optimizing Barnes-Hut simulations for many-core super computers using the scalable parallel runtime.” 2013. Thesis, University of Illinois – Urbana-Champaign. Accessed September 15, 2019. http://hdl.handle.net/2142/44186.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Nusbaum, Kurtis. “Optimizing Barnes-Hut simulations for many-core super computers using the scalable parallel runtime.” 2013. Web. 15 Sep 2019.

Vancouver:

Nusbaum K. Optimizing Barnes-Hut simulations for many-core super computers using the scalable parallel runtime. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2013. [cited 2019 Sep 15]. Available from: http://hdl.handle.net/2142/44186.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Nusbaum K. Optimizing Barnes-Hut simulations for many-core super computers using the scalable parallel runtime. [Thesis]. University of Illinois – Urbana-Champaign; 2013. Available from: http://hdl.handle.net/2142/44186

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

16. Yee, Alexander. A faster FFT in the Mid-West.

Degree: MS, 0112, 2013, University of Illinois – Urbana-Champaign

 FFT implementations today generally fall into two categories: Library generators (such as FFTW and Spiral) and specialized FFTs (such as prime95). Specialized FFTs have the… (more)

Subjects/Keywords: High Performance Computing (HPC); Fast Fourier Transform (FFT); Libraries

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APA (6th Edition):

Yee, A. (2013). A faster FFT in the Mid-West. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/44116

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yee, Alexander. “A faster FFT in the Mid-West.” 2013. Thesis, University of Illinois – Urbana-Champaign. Accessed September 15, 2019. http://hdl.handle.net/2142/44116.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yee, Alexander. “A faster FFT in the Mid-West.” 2013. Web. 15 Sep 2019.

Vancouver:

Yee A. A faster FFT in the Mid-West. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2013. [cited 2019 Sep 15]. Available from: http://hdl.handle.net/2142/44116.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yee A. A faster FFT in the Mid-West. [Thesis]. University of Illinois – Urbana-Champaign; 2013. Available from: http://hdl.handle.net/2142/44116

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

17. Kjolstad, Fredrik Berg. Refactoring transformations for maintainable, scalable and efficient parallelism.

Degree: MS, 0112, 2011, University of Illinois – Urbana-Champaign

 Computing is everywhere and our society depends on it. Increased performance over the last decades has allowed us to solve ever more interesting problems. We… (more)

Subjects/Keywords: Refactoring; Program Transformation; Parallelism; High Performance Computing (HPC); Immutability; Datatypes

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kjolstad, F. B. (2011). Refactoring transformations for maintainable, scalable and efficient parallelism. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/26124

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kjolstad, Fredrik Berg. “Refactoring transformations for maintainable, scalable and efficient parallelism.” 2011. Thesis, University of Illinois – Urbana-Champaign. Accessed September 15, 2019. http://hdl.handle.net/2142/26124.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kjolstad, Fredrik Berg. “Refactoring transformations for maintainable, scalable and efficient parallelism.” 2011. Web. 15 Sep 2019.

Vancouver:

Kjolstad FB. Refactoring transformations for maintainable, scalable and efficient parallelism. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2011. [cited 2019 Sep 15]. Available from: http://hdl.handle.net/2142/26124.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kjolstad FB. Refactoring transformations for maintainable, scalable and efficient parallelism. [Thesis]. University of Illinois – Urbana-Champaign; 2011. Available from: http://hdl.handle.net/2142/26124

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

18. Sasidharan, Aparna. A distributed multi-threaded data partitioner with space-filling curve orders.

Degree: PhD, Computer Science, 2018, University of Illinois – Urbana-Champaign

 The problem discussed in this thesis is distributed data partitioning and data re-ordering on many-core architectures. We present extensive literature survey, with examples from various… (more)

Subjects/Keywords: Shared Memory; Pthreads; Distributed Memory; MPI; Adaptive Mesh Refinement; Space-filling Curves; Load Balancing; Kd-trees; Intel KNL Performance

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APA (6th Edition):

Sasidharan, A. (2018). A distributed multi-threaded data partitioner with space-filling curve orders. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/101580

Chicago Manual of Style (16th Edition):

Sasidharan, Aparna. “A distributed multi-threaded data partitioner with space-filling curve orders.” 2018. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed September 15, 2019. http://hdl.handle.net/2142/101580.

MLA Handbook (7th Edition):

Sasidharan, Aparna. “A distributed multi-threaded data partitioner with space-filling curve orders.” 2018. Web. 15 Sep 2019.

Vancouver:

Sasidharan A. A distributed multi-threaded data partitioner with space-filling curve orders. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2018. [cited 2019 Sep 15]. Available from: http://hdl.handle.net/2142/101580.

Council of Science Editors:

Sasidharan A. A distributed multi-threaded data partitioner with space-filling curve orders. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2018. Available from: http://hdl.handle.net/2142/101580

19. Calhoun, Jon Cameron. From detection to optimization: impact of soft errors on high-performance computing applications.

Degree: PhD, Computer Science, 2017, University of Illinois – Urbana-Champaign

 As high-performance computing (HPC) continues to progress, constraints on HPC system design forces the handling of errors to higher levels in the software stack. Of… (more)

Subjects/Keywords: High-performance computing; Fault tolerance; Silent data corruption; Soft errors; Error detection; Error recovery; Fault injection; Error propagation; Lossy compression; Checkpoint-restart

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APA (6th Edition):

Calhoun, J. C. (2017). From detection to optimization: impact of soft errors on high-performance computing applications. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/98379

Chicago Manual of Style (16th Edition):

Calhoun, Jon Cameron. “From detection to optimization: impact of soft errors on high-performance computing applications.” 2017. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed September 15, 2019. http://hdl.handle.net/2142/98379.

MLA Handbook (7th Edition):

Calhoun, Jon Cameron. “From detection to optimization: impact of soft errors on high-performance computing applications.” 2017. Web. 15 Sep 2019.

Vancouver:

Calhoun JC. From detection to optimization: impact of soft errors on high-performance computing applications. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2017. [cited 2019 Sep 15]. Available from: http://hdl.handle.net/2142/98379.

Council of Science Editors:

Calhoun JC. From detection to optimization: impact of soft errors on high-performance computing applications. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/98379

20. Sack, Paul. Scalable collective message-passing algorithms.

Degree: PhD, 0112, 2012, University of Illinois – Urbana-Champaign

 Governments, universities, and companies expend vast resources building the top supercomputers. The processors and interconnect networks become faster, while the number of nodes grows exponentially.… (more)

Subjects/Keywords: Supercomputing; Message-passing; collective algorithms

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APA (6th Edition):

Sack, P. (2012). Scalable collective message-passing algorithms. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/29839

Chicago Manual of Style (16th Edition):

Sack, Paul. “Scalable collective message-passing algorithms.” 2012. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed September 15, 2019. http://hdl.handle.net/2142/29839.

MLA Handbook (7th Edition):

Sack, Paul. “Scalable collective message-passing algorithms.” 2012. Web. 15 Sep 2019.

Vancouver:

Sack P. Scalable collective message-passing algorithms. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2012. [cited 2019 Sep 15]. Available from: http://hdl.handle.net/2142/29839.

Council of Science Editors:

Sack P. Scalable collective message-passing algorithms. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2012. Available from: http://hdl.handle.net/2142/29839

21. Hoque, Imranul. Storage and processing systems for power-law graphs.

Degree: PhD, 0112, 2014, University of Illinois – Urbana-Champaign

 Large graphs abound around us - online social networks, Web graphs, the Internet, citation networks, protein interaction networks, telephone call graphs, peer-to-peer overlay networks, electric… (more)

Subjects/Keywords: Graph; Storage; Analytics; Distributed System; Power-Law

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hoque, I. (2014). Storage and processing systems for power-law graphs. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/46650

Chicago Manual of Style (16th Edition):

Hoque, Imranul. “Storage and processing systems for power-law graphs.” 2014. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed September 15, 2019. http://hdl.handle.net/2142/46650.

MLA Handbook (7th Edition):

Hoque, Imranul. “Storage and processing systems for power-law graphs.” 2014. Web. 15 Sep 2019.

Vancouver:

Hoque I. Storage and processing systems for power-law graphs. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2014. [cited 2019 Sep 15]. Available from: http://hdl.handle.net/2142/46650.

Council of Science Editors:

Hoque I. Storage and processing systems for power-law graphs. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2014. Available from: http://hdl.handle.net/2142/46650

22. Ramachandran, Pradeep. Detecting and Recovering from In-Core Hardware Faults Through Software Anomaly Treatment.

Degree: PhD, 0112, 2011, University of Illinois – Urbana-Champaign

 Aggressive scaling of CMOS transistors has enabled extensive system integration and building faster and more e???cient systems. On the ???ip side, this has resulted in… (more)

Subjects/Keywords: Fault tolerance; Computer architecture; symptom detection

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APA (6th Edition):

Ramachandran, P. (2011). Detecting and Recovering from In-Core Hardware Faults Through Software Anomaly Treatment. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/24127

Chicago Manual of Style (16th Edition):

Ramachandran, Pradeep. “Detecting and Recovering from In-Core Hardware Faults Through Software Anomaly Treatment.” 2011. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed September 15, 2019. http://hdl.handle.net/2142/24127.

MLA Handbook (7th Edition):

Ramachandran, Pradeep. “Detecting and Recovering from In-Core Hardware Faults Through Software Anomaly Treatment.” 2011. Web. 15 Sep 2019.

Vancouver:

Ramachandran P. Detecting and Recovering from In-Core Hardware Faults Through Software Anomaly Treatment. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2011. [cited 2019 Sep 15]. Available from: http://hdl.handle.net/2142/24127.

Council of Science Editors:

Ramachandran P. Detecting and Recovering from In-Core Hardware Faults Through Software Anomaly Treatment. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2011. Available from: http://hdl.handle.net/2142/24127

23. Neelakantam, Naveen. Hardware atomicity for compiler-directed control speculation.

Degree: PhD, 0112, 2012, University of Illinois – Urbana-Champaign

 This dissertation introduces the atomic region as a novel compiler abstraction which eases the development of speculative compiler optimizations. As this dissertation will show, speculation… (more)

Subjects/Keywords: Hardware Atomicity; Speculative Compiler Optimization; Control Speculation; Hardware/Software Co-design; Dynamic Optimization; Computer Architecture

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Neelakantam, N. (2012). Hardware atomicity for compiler-directed control speculation. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/29658

Chicago Manual of Style (16th Edition):

Neelakantam, Naveen. “Hardware atomicity for compiler-directed control speculation.” 2012. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed September 15, 2019. http://hdl.handle.net/2142/29658.

MLA Handbook (7th Edition):

Neelakantam, Naveen. “Hardware atomicity for compiler-directed control speculation.” 2012. Web. 15 Sep 2019.

Vancouver:

Neelakantam N. Hardware atomicity for compiler-directed control speculation. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2012. [cited 2019 Sep 15]. Available from: http://hdl.handle.net/2142/29658.

Council of Science Editors:

Neelakantam N. Hardware atomicity for compiler-directed control speculation. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2012. Available from: http://hdl.handle.net/2142/29658

24. Duan, Yue Lu. Techniques for low overhead fences and sequential consistency violation recording.

Degree: PhD, 0112, 2015, University of Illinois – Urbana-Champaign

 Fences are instructions that programmers or compilers insert in the code to prevent the compiler or the hardware from reordering memory accesses [20, 43]. Fences… (more)

Subjects/Keywords: Fence; Sequential Consistency Violation

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APA (6th Edition):

Duan, Y. L. (2015). Techniques for low overhead fences and sequential consistency violation recording. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/72747

Chicago Manual of Style (16th Edition):

Duan, Yue Lu. “Techniques for low overhead fences and sequential consistency violation recording.” 2015. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed September 15, 2019. http://hdl.handle.net/2142/72747.

MLA Handbook (7th Edition):

Duan, Yue Lu. “Techniques for low overhead fences and sequential consistency violation recording.” 2015. Web. 15 Sep 2019.

Vancouver:

Duan YL. Techniques for low overhead fences and sequential consistency violation recording. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2015. [cited 2019 Sep 15]. Available from: http://hdl.handle.net/2142/72747.

Council of Science Editors:

Duan YL. Techniques for low overhead fences and sequential consistency violation recording. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/72747

25. Sung, Hyojin. DeNovo: rethinking the memory hierarchy for disciplined parallelism.

Degree: PhD, Computer Science, 2015, University of Illinois – Urbana-Champaign

 As multicore systems become widespread, both software and hardware face a major challenge in efficiently exploiting and implementing parallelism. While shared–memory remains a popular programming… (more)

Subjects/Keywords: shared memory; cache coherence; memory consistency; disciplined parallelism

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APA (6th Edition):

Sung, H. (2015). DeNovo: rethinking the memory hierarchy for disciplined parallelism. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/88059

Chicago Manual of Style (16th Edition):

Sung, Hyojin. “DeNovo: rethinking the memory hierarchy for disciplined parallelism.” 2015. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed September 15, 2019. http://hdl.handle.net/2142/88059.

MLA Handbook (7th Edition):

Sung, Hyojin. “DeNovo: rethinking the memory hierarchy for disciplined parallelism.” 2015. Web. 15 Sep 2019.

Vancouver:

Sung H. DeNovo: rethinking the memory hierarchy for disciplined parallelism. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2015. [cited 2019 Sep 15]. Available from: http://hdl.handle.net/2142/88059.

Council of Science Editors:

Sung H. DeNovo: rethinking the memory hierarchy for disciplined parallelism. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/88059

26. Qian, Xuehai. Scalable and flexible bulk architecture.

Degree: PhD, 0112, 2013, University of Illinois – Urbana-Champaign

 Multicore machines have become pervasive and, as a result, parallel programming has received renewed interest. Unfortunately, writing correct parallel programs is notoriously hard. Looking ahead,… (more)

Subjects/Keywords: Memory consistency model; Chunk-based Architecture; Cache Coherence

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APA (6th Edition):

Qian, X. (2013). Scalable and flexible bulk architecture. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/45472

Chicago Manual of Style (16th Edition):

Qian, Xuehai. “Scalable and flexible bulk architecture.” 2013. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed September 15, 2019. http://hdl.handle.net/2142/45472.

MLA Handbook (7th Edition):

Qian, Xuehai. “Scalable and flexible bulk architecture.” 2013. Web. 15 Sep 2019.

Vancouver:

Qian X. Scalable and flexible bulk architecture. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2013. [cited 2019 Sep 15]. Available from: http://hdl.handle.net/2142/45472.

Council of Science Editors:

Qian X. Scalable and flexible bulk architecture. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2013. Available from: http://hdl.handle.net/2142/45472

27. Komuravelli, Rakesh. Exploiting software information for an efficient memory hierarchy.

Degree: PhD, 0112, 2015, University of Illinois – Urbana-Champaign

 Power consumption is one of the most important factors in the design of today’s processor chips. Multicore and heterogeneous systems have emerged to address the… (more)

Subjects/Keywords: Computer architecture; cache coherence; multicores; heterogeneous systems; protocol verification; memory hierarchy

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Komuravelli, R. (2015). Exploiting software information for an efficient memory hierarchy. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/72791

Chicago Manual of Style (16th Edition):

Komuravelli, Rakesh. “Exploiting software information for an efficient memory hierarchy.” 2015. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed September 15, 2019. http://hdl.handle.net/2142/72791.

MLA Handbook (7th Edition):

Komuravelli, Rakesh. “Exploiting software information for an efficient memory hierarchy.” 2015. Web. 15 Sep 2019.

Vancouver:

Komuravelli R. Exploiting software information for an efficient memory hierarchy. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2015. [cited 2019 Sep 15]. Available from: http://hdl.handle.net/2142/72791.

Council of Science Editors:

Komuravelli R. Exploiting software information for an efficient memory hierarchy. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/72791

.