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You searched for +publisher:"University of Illinois – Urbana-Champaign" +contributor:("Rosenbaum, Elyse"). Showing records 1 – 30 of 45 total matches.

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University of Illinois – Urbana-Champaign

1. Xiu, Yang. Logic upset induced by substrate current during power-on ESD.

Degree: MS, 1200, 2015, University of Illinois – Urbana-Champaign

 In this thesis, we will describe an experimental study of one possible soft failure mechanism during power-on electrostatic discharge (ESD). For contact discharge into a… (more)

Subjects/Keywords: power-on electrostatic discharge (ESD); soft failure; substrate current; system-level electrostatic discharge (ESD)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Xiu, Y. (2015). Logic upset induced by substrate current during power-on ESD. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/73003

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Xiu, Yang. “Logic upset induced by substrate current during power-on ESD.” 2015. Thesis, University of Illinois – Urbana-Champaign. Accessed October 31, 2020. http://hdl.handle.net/2142/73003.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Xiu, Yang. “Logic upset induced by substrate current during power-on ESD.” 2015. Web. 31 Oct 2020.

Vancouver:

Xiu Y. Logic upset induced by substrate current during power-on ESD. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2015. [cited 2020 Oct 31]. Available from: http://hdl.handle.net/2142/73003.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Xiu Y. Logic upset induced by substrate current during power-on ESD. [Thesis]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/73003

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

2. Reiman, Collin Michael. Evaluation of the practicality of system efficient ESD design.

Degree: MS, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign

 A custom test board facilitates transmission line pulse (TLP) characterization of the external pins of an integrated circuit. Models extracted from the data are used… (more)

Subjects/Keywords: System-efficient electrostatic discharge (ESD) design (SEED); System; Efficient; Design; Electrostatic discharge (ESD); Electrostatic; Discharge; Transmission line pulse (TLP); Transmission; Line; Pulse

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APA (6th Edition):

Reiman, C. M. (2017). Evaluation of the practicality of system efficient ESD design. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/99289

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Reiman, Collin Michael. “Evaluation of the practicality of system efficient ESD design.” 2017. Thesis, University of Illinois – Urbana-Champaign. Accessed October 31, 2020. http://hdl.handle.net/2142/99289.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Reiman, Collin Michael. “Evaluation of the practicality of system efficient ESD design.” 2017. Web. 31 Oct 2020.

Vancouver:

Reiman CM. Evaluation of the practicality of system efficient ESD design. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2017. [cited 2020 Oct 31]. Available from: http://hdl.handle.net/2142/99289.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Reiman CM. Evaluation of the practicality of system efficient ESD design. [Thesis]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/99289

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

3. Xiong, Jie. Enhanced modeling methodology for system-level electrostatic discharge simulation.

Degree: MS, Electrical & Computer Engr, 2019, University of Illinois – Urbana-Champaign

 To enable accurate system-level electrostatic discharge (ESD) simulation, models for the equipment under test, the ESD source, and the environment are required. This work presents… (more)

Subjects/Keywords: Electrostatic discharge; System-efficient ESD design; IEC 61000-4-2 discharge; TLP characterization

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APA (6th Edition):

Xiong, J. (2019). Enhanced modeling methodology for system-level electrostatic discharge simulation. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/104725

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Xiong, Jie. “Enhanced modeling methodology for system-level electrostatic discharge simulation.” 2019. Thesis, University of Illinois – Urbana-Champaign. Accessed October 31, 2020. http://hdl.handle.net/2142/104725.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Xiong, Jie. “Enhanced modeling methodology for system-level electrostatic discharge simulation.” 2019. Web. 31 Oct 2020.

Vancouver:

Xiong J. Enhanced modeling methodology for system-level electrostatic discharge simulation. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2019. [cited 2020 Oct 31]. Available from: http://hdl.handle.net/2142/104725.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Xiong J. Enhanced modeling methodology for system-level electrostatic discharge simulation. [Thesis]. University of Illinois – Urbana-Champaign; 2019. Available from: http://hdl.handle.net/2142/104725

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

4. Chen, Xiangyu. Modeling trustworthy opinion using an uncertainty-aware approach.

Degree: MS, Computer Science, 2016, University of Illinois – Urbana-Champaign

 In this era of information explosion, conflicts are often encountered when information is provided by multiple sources. Traditional truth discovery task aims to identify the… (more)

Subjects/Keywords: trustworthy opinion; truth discovery

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APA (6th Edition):

Chen, X. (2016). Modeling trustworthy opinion using an uncertainty-aware approach. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/90794

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chen, Xiangyu. “Modeling trustworthy opinion using an uncertainty-aware approach.” 2016. Thesis, University of Illinois – Urbana-Champaign. Accessed October 31, 2020. http://hdl.handle.net/2142/90794.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chen, Xiangyu. “Modeling trustworthy opinion using an uncertainty-aware approach.” 2016. Web. 31 Oct 2020.

Vancouver:

Chen X. Modeling trustworthy opinion using an uncertainty-aware approach. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2016. [cited 2020 Oct 31]. Available from: http://hdl.handle.net/2142/90794.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen X. Modeling trustworthy opinion using an uncertainty-aware approach. [Thesis]. University of Illinois – Urbana-Champaign; 2016. Available from: http://hdl.handle.net/2142/90794

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

5. Xiu, Yang. Failures caused by supply fluctuations during system-level ESD.

Degree: PhD, Electrical & Computer Engr, 2018, University of Illinois – Urbana-Champaign

 It is necessary to design robust electronic systems against system-level electrostatic discharge (ESD). In additional to withstanding ESD without hard failures (permanent damage), it is… (more)

Subjects/Keywords: System-level ESD; supply noise; IEC 61000-4-2

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APA (6th Edition):

Xiu, Y. (2018). Failures caused by supply fluctuations during system-level ESD. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/100889

Chicago Manual of Style (16th Edition):

Xiu, Yang. “Failures caused by supply fluctuations during system-level ESD.” 2018. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed October 31, 2020. http://hdl.handle.net/2142/100889.

MLA Handbook (7th Edition):

Xiu, Yang. “Failures caused by supply fluctuations during system-level ESD.” 2018. Web. 31 Oct 2020.

Vancouver:

Xiu Y. Failures caused by supply fluctuations during system-level ESD. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2018. [cited 2020 Oct 31]. Available from: http://hdl.handle.net/2142/100889.

Council of Science Editors:

Xiu Y. Failures caused by supply fluctuations during system-level ESD. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2018. Available from: http://hdl.handle.net/2142/100889


University of Illinois – Urbana-Champaign

6. Keel, Min-Sun. Design of reliable and energy-efficient high-speed interface circuits.

Degree: PhD, Electrical & Computer Engineering, 2015, University of Illinois – Urbana-Champaign

 The data-rate demand in high-speed interface circuits increases exponentially every year. High-speed I/Os are better implemented in advanced process technologies for lower-power systems, with the… (more)

Subjects/Keywords: Electrostatic discharge (ESD); Charged device model (CDM); High-speed I/O; wireline communication; transmitter; receiver; ADC-based receiver; Stub Series Terminated Logic (SSTL)

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APA (6th Edition):

Keel, M. (2015). Design of reliable and energy-efficient high-speed interface circuits. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/88932

Chicago Manual of Style (16th Edition):

Keel, Min-Sun. “Design of reliable and energy-efficient high-speed interface circuits.” 2015. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed October 31, 2020. http://hdl.handle.net/2142/88932.

MLA Handbook (7th Edition):

Keel, Min-Sun. “Design of reliable and energy-efficient high-speed interface circuits.” 2015. Web. 31 Oct 2020.

Vancouver:

Keel M. Design of reliable and energy-efficient high-speed interface circuits. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2015. [cited 2020 Oct 31]. Available from: http://hdl.handle.net/2142/88932.

Council of Science Editors:

Keel M. Design of reliable and energy-efficient high-speed interface circuits. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/88932


University of Illinois – Urbana-Champaign

7. Lee, Hsuan-Ping. Atomic layer deposition Al2O3-passivated AlGaN/GaN high-electron-mobility transistors on Si(111) towards reliable high-speed electronics.

Degree: PhD, Electrical & Computer Engr, 2020, University of Illinois – Urbana-Champaign

 (Al)GaN-based transistors are the backbones of next-generation high power/frequency electronics. However, various challenges with this exciting technology still necessitate more comprehensive investigations. In particular, epitaxially… (more)

Subjects/Keywords: AlGaN/GaN HEMT; Si(111); high-speed electronics

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APA (6th Edition):

Lee, H. (2020). Atomic layer deposition Al2O3-passivated AlGaN/GaN high-electron-mobility transistors on Si(111) towards reliable high-speed electronics. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/107848

Chicago Manual of Style (16th Edition):

Lee, Hsuan-Ping. “Atomic layer deposition Al2O3-passivated AlGaN/GaN high-electron-mobility transistors on Si(111) towards reliable high-speed electronics.” 2020. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed October 31, 2020. http://hdl.handle.net/2142/107848.

MLA Handbook (7th Edition):

Lee, Hsuan-Ping. “Atomic layer deposition Al2O3-passivated AlGaN/GaN high-electron-mobility transistors on Si(111) towards reliable high-speed electronics.” 2020. Web. 31 Oct 2020.

Vancouver:

Lee H. Atomic layer deposition Al2O3-passivated AlGaN/GaN high-electron-mobility transistors on Si(111) towards reliable high-speed electronics. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2020. [cited 2020 Oct 31]. Available from: http://hdl.handle.net/2142/107848.

Council of Science Editors:

Lee H. Atomic layer deposition Al2O3-passivated AlGaN/GaN high-electron-mobility transistors on Si(111) towards reliable high-speed electronics. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2020. Available from: http://hdl.handle.net/2142/107848


University of Illinois – Urbana-Champaign

8. Ma, Xiao. Inference of electromagnetic system behavior in the presence of variability.

Degree: PhD, Electrical & Computer Engr, 2020, University of Illinois – Urbana-Champaign

 This thesis contributes to and advances the state-of-the-art of the analysis of stochastic electromagnetic-circuit systems by applying novel statistical inference and generative modeling techniques to… (more)

Subjects/Keywords: Stochastic electromagnetic-circuit analysis; Statistical inference; Generative modeling; S-parameters; Variational autoencoder; Physical constraints; Passivity; Dependency between subsystems; Conditional variational autoencoder; Universal statistics; Random coupling model; Wave chaos

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APA (6th Edition):

Ma, X. (2020). Inference of electromagnetic system behavior in the presence of variability. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/107854

Chicago Manual of Style (16th Edition):

Ma, Xiao. “Inference of electromagnetic system behavior in the presence of variability.” 2020. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed October 31, 2020. http://hdl.handle.net/2142/107854.

MLA Handbook (7th Edition):

Ma, Xiao. “Inference of electromagnetic system behavior in the presence of variability.” 2020. Web. 31 Oct 2020.

Vancouver:

Ma X. Inference of electromagnetic system behavior in the presence of variability. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2020. [cited 2020 Oct 31]. Available from: http://hdl.handle.net/2142/107854.

Council of Science Editors:

Ma X. Inference of electromagnetic system behavior in the presence of variability. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2020. Available from: http://hdl.handle.net/2142/107854


University of Illinois – Urbana-Champaign

9. Liu, Wenbo. Low-power high-performance SAR ADC design with digital calibration techniques.

Degree: PhD, 1200, 2011, University of Illinois – Urbana-Champaign

 This dissertation presents the design of three high-performance successive-approximation-register (SAR) analog-to-digital converters (ADCs) using distinct digital background calibration techniques under the framework of a generalized… (more)

Subjects/Keywords: successive-approximation-register (SAR) analog-to-digital converters (ADC); redundancy; sub-radix-2; Nonlinearity; digital calibration; linear equalizer; generalized linear equalizer; perturbation; bit-wise correlation; channel mismatch; time-interleaved analog-to-digital converters (ADC)

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APA (6th Edition):

Liu, W. (2011). Low-power high-performance SAR ADC design with digital calibration techniques. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/18623

Chicago Manual of Style (16th Edition):

Liu, Wenbo. “Low-power high-performance SAR ADC design with digital calibration techniques.” 2011. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed October 31, 2020. http://hdl.handle.net/2142/18623.

MLA Handbook (7th Edition):

Liu, Wenbo. “Low-power high-performance SAR ADC design with digital calibration techniques.” 2011. Web. 31 Oct 2020.

Vancouver:

Liu W. Low-power high-performance SAR ADC design with digital calibration techniques. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2011. [cited 2020 Oct 31]. Available from: http://hdl.handle.net/2142/18623.

Council of Science Editors:

Liu W. Low-power high-performance SAR ADC design with digital calibration techniques. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2011. Available from: http://hdl.handle.net/2142/18623


University of Illinois – Urbana-Champaign

10. Chan, Doris A. CMOS Power Device Modeling and Amplifier Circuits.

Degree: PhD, 1200, 2011, University of Illinois – Urbana-Champaign

 A power amplifier (PA) is a key part of the RF front-end in transmitters for a local broadband network. Today, commercial PAs are made of… (more)

Subjects/Keywords: Complementary Metal Oxide Semiconductor (CMOS); millimeter-wave; coplanar waveguide; Worldwide Interoperability for Microwave Access (WiMAX); power divider/combiner; power amplifier

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APA (6th Edition):

Chan, D. A. (2011). CMOS Power Device Modeling and Amplifier Circuits. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/18249

Chicago Manual of Style (16th Edition):

Chan, Doris A. “CMOS Power Device Modeling and Amplifier Circuits.” 2011. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed October 31, 2020. http://hdl.handle.net/2142/18249.

MLA Handbook (7th Edition):

Chan, Doris A. “CMOS Power Device Modeling and Amplifier Circuits.” 2011. Web. 31 Oct 2020.

Vancouver:

Chan DA. CMOS Power Device Modeling and Amplifier Circuits. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2011. [cited 2020 Oct 31]. Available from: http://hdl.handle.net/2142/18249.

Council of Science Editors:

Chan DA. CMOS Power Device Modeling and Amplifier Circuits. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2011. Available from: http://hdl.handle.net/2142/18249


University of Illinois – Urbana-Champaign

11. Klokotov, Dmitri. Application of the latency insertion method (LIM) to the analysis of large circuit interconnect networks.

Degree: PhD, 1200, 2012, University of Illinois – Urbana-Champaign

 The focus of this research is to explore the applications of the finite difference formulation based on the latency insertion method (LIM) to the analysis… (more)

Subjects/Keywords: circuit simulation; latency insertion; power integrity; power distribution network analysis; electrothermal analysis; IR drop; Latency insertion method (LIM)

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APA (6th Edition):

Klokotov, D. (2012). Application of the latency insertion method (LIM) to the analysis of large circuit interconnect networks. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/29639

Chicago Manual of Style (16th Edition):

Klokotov, Dmitri. “Application of the latency insertion method (LIM) to the analysis of large circuit interconnect networks.” 2012. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed October 31, 2020. http://hdl.handle.net/2142/29639.

MLA Handbook (7th Edition):

Klokotov, Dmitri. “Application of the latency insertion method (LIM) to the analysis of large circuit interconnect networks.” 2012. Web. 31 Oct 2020.

Vancouver:

Klokotov D. Application of the latency insertion method (LIM) to the analysis of large circuit interconnect networks. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2012. [cited 2020 Oct 31]. Available from: http://hdl.handle.net/2142/29639.

Council of Science Editors:

Klokotov D. Application of the latency insertion method (LIM) to the analysis of large circuit interconnect networks. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2012. Available from: http://hdl.handle.net/2142/29639


University of Illinois – Urbana-Champaign

12. Chen, Ying-Yu. Graphene nano-ribbon and transition metal dichalcogenide field-effect transistor modeling and circuit simulation.

Degree: PhD, Electrical & Computer Engr, 2015, University of Illinois – Urbana-Champaign

 This dissertation presents a modeling and simulation study of graphene nano-ribbon and transition metal dichalcogenide field-effect transistors. Through compact modeling, SPICE implementation of the transistors… (more)

Subjects/Keywords: graphene; transition metal dichalcogenide; transistor; flexible transistor; modeling; simulation

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APA (6th Edition):

Chen, Y. (2015). Graphene nano-ribbon and transition metal dichalcogenide field-effect transistor modeling and circuit simulation. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/88212

Chicago Manual of Style (16th Edition):

Chen, Ying-Yu. “Graphene nano-ribbon and transition metal dichalcogenide field-effect transistor modeling and circuit simulation.” 2015. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed October 31, 2020. http://hdl.handle.net/2142/88212.

MLA Handbook (7th Edition):

Chen, Ying-Yu. “Graphene nano-ribbon and transition metal dichalcogenide field-effect transistor modeling and circuit simulation.” 2015. Web. 31 Oct 2020.

Vancouver:

Chen Y. Graphene nano-ribbon and transition metal dichalcogenide field-effect transistor modeling and circuit simulation. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2015. [cited 2020 Oct 31]. Available from: http://hdl.handle.net/2142/88212.

Council of Science Editors:

Chen Y. Graphene nano-ribbon and transition metal dichalcogenide field-effect transistor modeling and circuit simulation. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/88212


University of Illinois – Urbana-Champaign

13. Anand, Tejasvi. Toward realizing power scalable and energy proportional high-speed wireline links.

Degree: PhD, Electrical & Computer Engineering, 2015, University of Illinois – Urbana-Champaign

 Growing computational demand and proliferation of cloud computing has placed high-speed serial links at the center stage. Due to saturating energy efficiency improvements over the… (more)

Subjects/Keywords: energy proportional; rapid-on/off; Phase locked loops (PLLs); multiplying delay locked loop (MDLL); delay locked loop; transceiver; Input/Output (I/O); serial link; temperature sensor; LC oscillator; LC oscillator

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APA (6th Edition):

Anand, T. (2015). Toward realizing power scalable and energy proportional high-speed wireline links. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/89205

Chicago Manual of Style (16th Edition):

Anand, Tejasvi. “Toward realizing power scalable and energy proportional high-speed wireline links.” 2015. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed October 31, 2020. http://hdl.handle.net/2142/89205.

MLA Handbook (7th Edition):

Anand, Tejasvi. “Toward realizing power scalable and energy proportional high-speed wireline links.” 2015. Web. 31 Oct 2020.

Vancouver:

Anand T. Toward realizing power scalable and energy proportional high-speed wireline links. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2015. [cited 2020 Oct 31]. Available from: http://hdl.handle.net/2142/89205.

Council of Science Editors:

Anand T. Toward realizing power scalable and energy proportional high-speed wireline links. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/89205


University of Illinois – Urbana-Champaign

14. Talegaonkar, Mrunmay Vyankatesh. Design of energy efficient high speed I/O interfaces.

Degree: PhD, Electrical & Computer Engr, 2016, University of Illinois – Urbana-Champaign

 Energy efficiency has become a key performance metric for wireline high speed I/O interfaces. Consequently, design of low power I/O interfaces has garnered large interest… (more)

Subjects/Keywords: digital multiplying delay-locked loop (MDLL); digitally-controlled ring oscillator (DCO); bit error rate; rapid on-off bias; fast turn-on clock multiplier; energy-proportional operation; current mode logic output driver; clock and data recovery (CDR), Mueller-Muller CDR; baud-rate; burst-mode; channel pulse response; channel estimation; phase-locked loop (PLL); fractional-N PLL; frequency-to-digital converter; phase interpolator

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APA (6th Edition):

Talegaonkar, M. V. (2016). Design of energy efficient high speed I/O interfaces. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/90871

Chicago Manual of Style (16th Edition):

Talegaonkar, Mrunmay Vyankatesh. “Design of energy efficient high speed I/O interfaces.” 2016. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed October 31, 2020. http://hdl.handle.net/2142/90871.

MLA Handbook (7th Edition):

Talegaonkar, Mrunmay Vyankatesh. “Design of energy efficient high speed I/O interfaces.” 2016. Web. 31 Oct 2020.

Vancouver:

Talegaonkar MV. Design of energy efficient high speed I/O interfaces. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2016. [cited 2020 Oct 31]. Available from: http://hdl.handle.net/2142/90871.

Council of Science Editors:

Talegaonkar MV. Design of energy efficient high speed I/O interfaces. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2016. Available from: http://hdl.handle.net/2142/90871


University of Illinois – Urbana-Champaign

15. Elkholy, Ahmed Mostafa Mohamed Attia. Digital enhancement techniques for fractional-N frequency synthesizers.

Degree: PhD, Electrical & Computer Engr, 2016, University of Illinois – Urbana-Champaign

 Meeting the demand for unprecedented connectivity in the era of internet-of-things (IoT) requires extremely energy efficient operation of IoT nodes to extend battery life. Managing… (more)

Subjects/Keywords: Phase-locked loops (PLLs); digital PLL; All-digital phase locked loop (ADPLL); fractional-N; Fractional divider, frequency synthesizer; Wide bandwidth; Bang-bang phase detector (BBPD); Digital-to-time converter (DTC); Least-mean square (LMS); Time-to-digtial converter (TDC); Time amplifier; Jitter; Digitally controlled oscillator (DCO); Frequency multiplier; Frequency tracking; Impulse sensitivity function (ISF); Injection locking; Multiplying injection-locked oscillator (MILO); Phase domain response (PDR); Phase noise; Pulse; Reference spur; Root mean square (rms) jitter; Sub-harmonic locking; Sub-sampling (SS)

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APA (6th Edition):

Elkholy, A. M. M. A. (2016). Digital enhancement techniques for fractional-N frequency synthesizers. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/95573

Chicago Manual of Style (16th Edition):

Elkholy, Ahmed Mostafa Mohamed Attia. “Digital enhancement techniques for fractional-N frequency synthesizers.” 2016. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed October 31, 2020. http://hdl.handle.net/2142/95573.

MLA Handbook (7th Edition):

Elkholy, Ahmed Mostafa Mohamed Attia. “Digital enhancement techniques for fractional-N frequency synthesizers.” 2016. Web. 31 Oct 2020.

Vancouver:

Elkholy AMMA. Digital enhancement techniques for fractional-N frequency synthesizers. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2016. [cited 2020 Oct 31]. Available from: http://hdl.handle.net/2142/95573.

Council of Science Editors:

Elkholy AMMA. Digital enhancement techniques for fractional-N frequency synthesizers. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2016. Available from: http://hdl.handle.net/2142/95573


University of Illinois – Urbana-Champaign

16. Lin, Yingyan. Energy-efficient systems for information transfer and processing.

Degree: PhD, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign

 Machine learning (ML) systems are finding excellent utility in tackling the data deluge of the big data era thanks to the exponential increase in computing… (more)

Subjects/Keywords: Machine learning; Energy efficiency; Analog-to-digital converter; Bit-error-rate optimal analog-to-digital converter (ADC); Convolutional neural networks; Sparsity; Statistical error compensation; Near threshold computing

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APA (6th Edition):

Lin, Y. (2017). Energy-efficient systems for information transfer and processing. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/98139

Chicago Manual of Style (16th Edition):

Lin, Yingyan. “Energy-efficient systems for information transfer and processing.” 2017. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed October 31, 2020. http://hdl.handle.net/2142/98139.

MLA Handbook (7th Edition):

Lin, Yingyan. “Energy-efficient systems for information transfer and processing.” 2017. Web. 31 Oct 2020.

Vancouver:

Lin Y. Energy-efficient systems for information transfer and processing. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2017. [cited 2020 Oct 31]. Available from: http://hdl.handle.net/2142/98139.

Council of Science Editors:

Lin Y. Energy-efficient systems for information transfer and processing. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/98139


University of Illinois – Urbana-Champaign

17. Yu, Ting. Power grid verification and optimization.

Degree: PhD, 1200, 2014, University of Illinois – Urbana-Champaign

 IR-drop is the voltage drop that is caused by the impedance of power grid and devices' switchings. It is important to verify voltage values of… (more)

Subjects/Keywords: power grid; IR-drop; parallel

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APA (6th Edition):

Yu, T. (2014). Power grid verification and optimization. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/50738

Chicago Manual of Style (16th Edition):

Yu, Ting. “Power grid verification and optimization.” 2014. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed October 31, 2020. http://hdl.handle.net/2142/50738.

MLA Handbook (7th Edition):

Yu, Ting. “Power grid verification and optimization.” 2014. Web. 31 Oct 2020.

Vancouver:

Yu T. Power grid verification and optimization. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2014. [cited 2020 Oct 31]. Available from: http://hdl.handle.net/2142/50738.

Council of Science Editors:

Yu T. Power grid verification and optimization. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2014. Available from: http://hdl.handle.net/2142/50738


University of Illinois – Urbana-Champaign

18. Dias, Neville L. Patterned zero-dimensional nanostructures: fabrication and characterization.

Degree: PhD, 1200, 2012, University of Illinois – Urbana-Champaign

 Due to the advantages arising from low-dimensional electronic systems, considerable effort has been put into the use of quantum dots and wires as the active… (more)

Subjects/Keywords: quantum dots; nanopores

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APA (6th Edition):

Dias, N. L. (2012). Patterned zero-dimensional nanostructures: fabrication and characterization. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/29771

Chicago Manual of Style (16th Edition):

Dias, Neville L. “Patterned zero-dimensional nanostructures: fabrication and characterization.” 2012. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed October 31, 2020. http://hdl.handle.net/2142/29771.

MLA Handbook (7th Edition):

Dias, Neville L. “Patterned zero-dimensional nanostructures: fabrication and characterization.” 2012. Web. 31 Oct 2020.

Vancouver:

Dias NL. Patterned zero-dimensional nanostructures: fabrication and characterization. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2012. [cited 2020 Oct 31]. Available from: http://hdl.handle.net/2142/29771.

Council of Science Editors:

Dias NL. Patterned zero-dimensional nanostructures: fabrication and characterization. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2012. Available from: http://hdl.handle.net/2142/29771

19. Vora, Sandeep Gautam. Investigating soft failures induced by system-level ESD.

Degree: MS, Electrical & Computer Engr, 2018, University of Illinois – Urbana-Champaign

 Hardware and application-level manifestations of ESD soft failures were characterized for three single-board computers. ESD events were generated following the system-level ESD standard (IEC 61000-4-2),… (more)

Subjects/Keywords: ESD; Soft Failures; System-Level ESD; IEC 61000-4-2; Soft Failure

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APA (6th Edition):

Vora, S. G. (2018). Investigating soft failures induced by system-level ESD. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/102509

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Vora, Sandeep Gautam. “Investigating soft failures induced by system-level ESD.” 2018. Thesis, University of Illinois – Urbana-Champaign. Accessed October 31, 2020. http://hdl.handle.net/2142/102509.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Vora, Sandeep Gautam. “Investigating soft failures induced by system-level ESD.” 2018. Web. 31 Oct 2020.

Vancouver:

Vora SG. Investigating soft failures induced by system-level ESD. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2018. [cited 2020 Oct 31]. Available from: http://hdl.handle.net/2142/102509.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Vora SG. Investigating soft failures induced by system-level ESD. [Thesis]. University of Illinois – Urbana-Champaign; 2018. Available from: http://hdl.handle.net/2142/102509

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

20. Mysore Vijayaraj, Prajwal. Detection of ESD-induced soft errors.

Degree: MS, Electrical & Computer Engr, 2018, University of Illinois – Urbana-Champaign

 IEC-61000-4-2 compliant ESD discharges are performed on a microcontroller. The effect of ESD-induced noise on a digital system having a workload is examined. UART interface… (more)

Subjects/Keywords: Bit flips; ESD; microcontroller; soft errors; Rail clamp; Phase margin

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APA (6th Edition):

Mysore Vijayaraj, P. (2018). Detection of ESD-induced soft errors. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/101631

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mysore Vijayaraj, Prajwal. “Detection of ESD-induced soft errors.” 2018. Thesis, University of Illinois – Urbana-Champaign. Accessed October 31, 2020. http://hdl.handle.net/2142/101631.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mysore Vijayaraj, Prajwal. “Detection of ESD-induced soft errors.” 2018. Web. 31 Oct 2020.

Vancouver:

Mysore Vijayaraj P. Detection of ESD-induced soft errors. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2018. [cited 2020 Oct 31]. Available from: http://hdl.handle.net/2142/101631.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mysore Vijayaraj P. Detection of ESD-induced soft errors. [Thesis]. University of Illinois – Urbana-Champaign; 2018. Available from: http://hdl.handle.net/2142/101631

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

21. Mertens, Robert. A compact model for silicon controlled rectifiers in low voltage CMOS processes.

Degree: MS, 1200, 2014, University of Illinois – Urbana-Champaign

 This thesis presents an SCR compact model for simulating ESD protection circuits. The aspects of the compact model that are necessary to reproduce measurement data,… (more)

Subjects/Keywords: Complementary metal–oxide–semiconductor (CMOS); integrated circuits; silicon; silicon controlled rectifiers (SCR); Electrostatic discharge (ESD)

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APA (6th Edition):

Mertens, R. (2014). A compact model for silicon controlled rectifiers in low voltage CMOS processes. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/49624

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mertens, Robert. “A compact model for silicon controlled rectifiers in low voltage CMOS processes.” 2014. Thesis, University of Illinois – Urbana-Champaign. Accessed October 31, 2020. http://hdl.handle.net/2142/49624.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mertens, Robert. “A compact model for silicon controlled rectifiers in low voltage CMOS processes.” 2014. Web. 31 Oct 2020.

Vancouver:

Mertens R. A compact model for silicon controlled rectifiers in low voltage CMOS processes. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2014. [cited 2020 Oct 31]. Available from: http://hdl.handle.net/2142/49624.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mertens R. A compact model for silicon controlled rectifiers in low voltage CMOS processes. [Thesis]. University of Illinois – Urbana-Champaign; 2014. Available from: http://hdl.handle.net/2142/49624

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

22. Shukla, Vrashank G. Full chip modeling for predictive simulation of charged device model electrostatic discharge events.

Degree: MS, 1200, 2010, University of Illinois – Urbana-Champaign

 With downscaling of device dimensions in integrated circuits (ICs), the risk of circuit failure due to electrostatic discharge (ESD) is increasing. In particular, the increased… (more)

Subjects/Keywords: Internal I/O; Electrostatic discharge (ESD); Charged device model (CDM); Transient Simulation; Anti-parallel diodes

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APA (6th Edition):

Shukla, V. G. (2010). Full chip modeling for predictive simulation of charged device model electrostatic discharge events. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/16496

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Shukla, Vrashank G. “Full chip modeling for predictive simulation of charged device model electrostatic discharge events.” 2010. Thesis, University of Illinois – Urbana-Champaign. Accessed October 31, 2020. http://hdl.handle.net/2142/16496.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Shukla, Vrashank G. “Full chip modeling for predictive simulation of charged device model electrostatic discharge events.” 2010. Web. 31 Oct 2020.

Vancouver:

Shukla VG. Full chip modeling for predictive simulation of charged device model electrostatic discharge events. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2010. [cited 2020 Oct 31]. Available from: http://hdl.handle.net/2142/16496.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Shukla VG. Full chip modeling for predictive simulation of charged device model electrostatic discharge events. [Thesis]. University of Illinois – Urbana-Champaign; 2010. Available from: http://hdl.handle.net/2142/16496

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

23. Sagan, Sam. Automated testing and machine-learning-based modeling of air discharge ESD.

Degree: MS, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign

 An IEC 16000-4-2 compliant, high-accuracy air-discharge automation system is used to study the properties of air discharge electrostatic discharge (ESD). This work corroborates conclusions of… (more)

Subjects/Keywords: Air discharge; Electrostatic discharge (ESD); Machine learning

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APA (6th Edition):

Sagan, S. (2017). Automated testing and machine-learning-based modeling of air discharge ESD. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/98434

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sagan, Sam. “Automated testing and machine-learning-based modeling of air discharge ESD.” 2017. Thesis, University of Illinois – Urbana-Champaign. Accessed October 31, 2020. http://hdl.handle.net/2142/98434.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sagan, Sam. “Automated testing and machine-learning-based modeling of air discharge ESD.” 2017. Web. 31 Oct 2020.

Vancouver:

Sagan S. Automated testing and machine-learning-based modeling of air discharge ESD. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2017. [cited 2020 Oct 31]. Available from: http://hdl.handle.net/2142/98434.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sagan S. Automated testing and machine-learning-based modeling of air discharge ESD. [Thesis]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/98434

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

24. Thomson, Nicholas A. High current pulse characterization of semiconductor devices.

Degree: MS, Electrical & Computer Engineering, 2015, University of Illinois – Urbana-Champaign

 A new ESD testing system, the exponential-edge transmission line pulse system (EETLP), is presented. EETLP generates 100 ns square pulses with a variable, exponentially decaying… (more)

Subjects/Keywords: Electrostatic Discharge (ESD); Transmission Line-Pulse (TLP)

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APA (6th Edition):

Thomson, N. A. (2015). High current pulse characterization of semiconductor devices. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/89078

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Thomson, Nicholas A. “High current pulse characterization of semiconductor devices.” 2015. Thesis, University of Illinois – Urbana-Champaign. Accessed October 31, 2020. http://hdl.handle.net/2142/89078.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Thomson, Nicholas A. “High current pulse characterization of semiconductor devices.” 2015. Web. 31 Oct 2020.

Vancouver:

Thomson NA. High current pulse characterization of semiconductor devices. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2015. [cited 2020 Oct 31]. Available from: http://hdl.handle.net/2142/89078.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Thomson NA. High current pulse characterization of semiconductor devices. [Thesis]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/89078

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

25. Kripanidhi, Arjun. Investigation of the hazards of substrate current injection: transient external latchup and substrate noise coupling.

Degree: MS, 1200, 2011, University of Illinois – Urbana-Champaign

 Substrate current injection is the origin of external latchup and substrate noise coupling. The trigger current for external latchup depends on the duration of the… (more)

Subjects/Keywords: Latchup; Complementary metal–oxide–semiconductor (CMOS); Positive-Negative-Positive-Negative (PNPN); transient external latchup; substrate noise coupling

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APA (6th Edition):

Kripanidhi, A. (2011). Investigation of the hazards of substrate current injection: transient external latchup and substrate noise coupling. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/26209

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kripanidhi, Arjun. “Investigation of the hazards of substrate current injection: transient external latchup and substrate noise coupling.” 2011. Thesis, University of Illinois – Urbana-Champaign. Accessed October 31, 2020. http://hdl.handle.net/2142/26209.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kripanidhi, Arjun. “Investigation of the hazards of substrate current injection: transient external latchup and substrate noise coupling.” 2011. Web. 31 Oct 2020.

Vancouver:

Kripanidhi A. Investigation of the hazards of substrate current injection: transient external latchup and substrate noise coupling. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2011. [cited 2020 Oct 31]. Available from: http://hdl.handle.net/2142/26209.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kripanidhi A. Investigation of the hazards of substrate current injection: transient external latchup and substrate noise coupling. [Thesis]. University of Illinois – Urbana-Champaign; 2011. Available from: http://hdl.handle.net/2142/26209

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

26. Faust, Adam. The effect of on-chip ESD protection on reliable high-speed I/O link equalization power consumption.

Degree: MS, 1200, 2011, University of Illinois – Urbana-Champaign

 For signal integrity reasons, the magnitude of the parasitics generated by electrostatic discharge (ESD) protection devices has become budgeted. Such budgets restrict the protection level… (more)

Subjects/Keywords: Electrostatic Discharge (ESD); Serial I/O; Signal Integrity; Equalization

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APA (6th Edition):

Faust, A. (2011). The effect of on-chip ESD protection on reliable high-speed I/O link equalization power consumption. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/26032

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Faust, Adam. “The effect of on-chip ESD protection on reliable high-speed I/O link equalization power consumption.” 2011. Thesis, University of Illinois – Urbana-Champaign. Accessed October 31, 2020. http://hdl.handle.net/2142/26032.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Faust, Adam. “The effect of on-chip ESD protection on reliable high-speed I/O link equalization power consumption.” 2011. Web. 31 Oct 2020.

Vancouver:

Faust A. The effect of on-chip ESD protection on reliable high-speed I/O link equalization power consumption. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2011. [cited 2020 Oct 31]. Available from: http://hdl.handle.net/2142/26032.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Faust A. The effect of on-chip ESD protection on reliable high-speed I/O link equalization power consumption. [Thesis]. University of Illinois – Urbana-Champaign; 2011. Available from: http://hdl.handle.net/2142/26032

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

27. Ayling, Alex Eben. ESD circuit design and measurement techniques.

Degree: MS, Electrical & Computer Engr, 2020, University of Illinois – Urbana-Champaign

 Part 1 of this thesis presents a method to measure sub-nanosecond reverse recovery in wafer-level test structures. The setup uses a transmission line pulse generator… (more)

Subjects/Keywords: Electrostatic Discharge; Integrated Circuits

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APA (6th Edition):

Ayling, A. E. (2020). ESD circuit design and measurement techniques. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/108033

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ayling, Alex Eben. “ESD circuit design and measurement techniques.” 2020. Thesis, University of Illinois – Urbana-Champaign. Accessed October 31, 2020. http://hdl.handle.net/2142/108033.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ayling, Alex Eben. “ESD circuit design and measurement techniques.” 2020. Web. 31 Oct 2020.

Vancouver:

Ayling AE. ESD circuit design and measurement techniques. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2020. [cited 2020 Oct 31]. Available from: http://hdl.handle.net/2142/108033.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ayling AE. ESD circuit design and measurement techniques. [Thesis]. University of Illinois – Urbana-Champaign; 2020. Available from: http://hdl.handle.net/2142/108033

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

28. Reiman, Collin Michael. Modeling and numerical methods for power electronic devices.

Degree: PhD, Electrical & Computer Engr, 2019, University of Illinois – Urbana-Champaign

 A scalable I-V model for latch-up in non-collinear PNPN devices is adapted from a previous model for collinear SCR devices. The model is applied to… (more)

Subjects/Keywords: silicon controlled rectifier; SCR; PNPN; latch-up; 14-nm; switched-mode power supply; SMPS; flyback; boost; state vector simulation; event detection

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APA (6th Edition):

Reiman, C. M. (2019). Modeling and numerical methods for power electronic devices. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/105674

Chicago Manual of Style (16th Edition):

Reiman, Collin Michael. “Modeling and numerical methods for power electronic devices.” 2019. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed October 31, 2020. http://hdl.handle.net/2142/105674.

MLA Handbook (7th Edition):

Reiman, Collin Michael. “Modeling and numerical methods for power electronic devices.” 2019. Web. 31 Oct 2020.

Vancouver:

Reiman CM. Modeling and numerical methods for power electronic devices. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2019. [cited 2020 Oct 31]. Available from: http://hdl.handle.net/2142/105674.

Council of Science Editors:

Reiman CM. Modeling and numerical methods for power electronic devices. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2019. Available from: http://hdl.handle.net/2142/105674

29. Thomson, Nicholas Adam. Investigation of system-level ESD induced soft failures.

Degree: PhD, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign

 Electrostatic discharge (ESD) is a common phenomenon that can have negative implications for the performance of systems during operation. ESD is a brief, high-current stress… (more)

Subjects/Keywords: Electrostatic discharge (ESD); System-level; Soft failures

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Thomson, N. A. (2017). Investigation of system-level ESD induced soft failures. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/97379

Chicago Manual of Style (16th Edition):

Thomson, Nicholas Adam. “Investigation of system-level ESD induced soft failures.” 2017. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed October 31, 2020. http://hdl.handle.net/2142/97379.

MLA Handbook (7th Edition):

Thomson, Nicholas Adam. “Investigation of system-level ESD induced soft failures.” 2017. Web. 31 Oct 2020.

Vancouver:

Thomson NA. Investigation of system-level ESD induced soft failures. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2017. [cited 2020 Oct 31]. Available from: http://hdl.handle.net/2142/97379.

Council of Science Editors:

Thomson NA. Investigation of system-level ESD induced soft failures. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/97379

30. Olson, Nicholas A. Charged device model electrostatic discharge failures in system on a chip and system in a package designs.

Degree: PhD, 1200, 2011, University of Illinois – Urbana-Champaign

 Advances in integrated circuit design and packaging techniques have introduced new ESD-susceptible (Electrostatic Discharge) circuit interfaces. This document will introduce these interfaces and the methods… (more)

Subjects/Keywords: Charged Device Model; Charged Device Model (CDM); Electrostatic Discharge (ESD); Electrostatic Discharge; System on a Chip; System in a Package

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Olson, N. A. (2011). Charged device model electrostatic discharge failures in system on a chip and system in a package designs. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/24101

Chicago Manual of Style (16th Edition):

Olson, Nicholas A. “Charged device model electrostatic discharge failures in system on a chip and system in a package designs.” 2011. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed October 31, 2020. http://hdl.handle.net/2142/24101.

MLA Handbook (7th Edition):

Olson, Nicholas A. “Charged device model electrostatic discharge failures in system on a chip and system in a package designs.” 2011. Web. 31 Oct 2020.

Vancouver:

Olson NA. Charged device model electrostatic discharge failures in system on a chip and system in a package designs. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2011. [cited 2020 Oct 31]. Available from: http://hdl.handle.net/2142/24101.

Council of Science Editors:

Olson NA. Charged device model electrostatic discharge failures in system on a chip and system in a package designs. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2011. Available from: http://hdl.handle.net/2142/24101

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