+publisher:"University of Illinois – Urbana-Champaign" +contributor:("Kim, Nam Sung")

University of Illinois – Urbana-Champaign

1. Tseng, Yu-Hsuan. Inference neural network hardware acceleration techniques.

Degree: MS, Electrical & Computer Engr, 2018, University of Illinois – Urbana-Champaign

► A number of recent researches focus on designing accelerators for popular deep learning algorithms. Most of these algorithms heavily involve matrix multiplication. As a result,… (more)

Subjects/Keywords: architecture; acceleration; neural network; analog; hash table

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APA (6^th Edition):

Tseng, Y. (2018). Inference neural network hardware acceleration techniques. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/101021

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Tseng, Yu-Hsuan. “Inference neural network hardware acceleration techniques.” 2018. Thesis, University of Illinois – Urbana-Champaign. Accessed December 12, 2019. http://hdl.handle.net/2142/101021.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Tseng, Yu-Hsuan. “Inference neural network hardware acceleration techniques.” 2018. Web. 12 Dec 2019.

Vancouver:

Tseng Y. Inference neural network hardware acceleration techniques. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2018. [cited 2019 Dec 12]. Available from: http://hdl.handle.net/2142/101021.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tseng Y. Inference neural network hardware acceleration techniques. [Thesis]. University of Illinois – Urbana-Champaign; 2018. Available from: http://hdl.handle.net/2142/101021

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of Illinois – Urbana-Champaign

2. Min, David. Synthesis constraint optimization for near-threshold voltage design.

Degree: MS, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign

URL: http://hdl.handle.net/2142/97551

► Near-threshold voltage (NTV) design is a viable solution to many embedded systems which require high energy efficiencies and low performances, but it makes them vulnerable… (more)

Subjects/Keywords: Near-threshold voltage; Low-energy; Embedded systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Min, D. (2017). Synthesis constraint optimization for near-threshold voltage design. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/97551

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Min, David. “Synthesis constraint optimization for near-threshold voltage design.” 2017. Thesis, University of Illinois – Urbana-Champaign. Accessed December 12, 2019. http://hdl.handle.net/2142/97551.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Min, David. “Synthesis constraint optimization for near-threshold voltage design.” 2017. Web. 12 Dec 2019.

Vancouver:

Min D. Synthesis constraint optimization for near-threshold voltage design. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2017. [cited 2019 Dec 12]. Available from: http://hdl.handle.net/2142/97551.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Min D. Synthesis constraint optimization for near-threshold voltage design. [Thesis]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/97551

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of Illinois – Urbana-Champaign

3. Duwe III, Henry John. Dependable design for low-cost ultra-low-power processors.

Degree: PhD, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign

URL: http://hdl.handle.net/2142/99273

► Emerging applications in the Internet of Things (IoT) domain, such as wearables, implantables, smart tags, and wireless sensor networks put severe power, cost, reliability, and… (more)

▼ Emerging applications in the Internet of Things (IoT) domain, such as wearables, implantables, smart tags, and wireless sensor networks put severe power, cost, reliability, and security constraints on hardware system design. This dissertation focuses on the architecture and design of dependable ultra-low power computing systems. Specifically, it proposes architecture and design techniques that exploit the unique application and usage characteristics of future computing systems to deliver low power, while meeting the reliability and security constraints of these systems. First, this dissertation considers the challenge of achieving both low power and high reliability in SRAM memories. It proposes both an architectural technique to reduce the overheads of error correction and a technique that uses the nature of error correcting codes to allow lower voltage operation without sacrificing reliability. Next, this dissertation considers low power and low cost. By leveraging the fact that many IoT systems are embedded in nature and will run the same application for their entire lifetime, fine-grained usage characteristics of the hardware-software system can be determined at design time. This dissertation presents a novel hardware-software co-analysis based on symbolic simulation that can determine the possible states of the processor throughout any execution of a specific application. This enables power-gating where more gates are turned off for longer, bespoke processors customized to specific applications, and stricter determination of peak power bounds. Finally, this dissertation considers achieving secure IoT systems at low cost and power overhead. By leveraging the hardware-software co-analysis, this dissertation shows that gate-level information flow security guarantees can be provided without hardware overheads. Advisors/Committee Members: Champaign%22%20%2Bcontributor%3A%28%22Kumar%2C%20Rakesh%22%29&pagesize-30">Kumar, Rakesh (advisor), Champaign%22%20%2Bcontributor%3A%28%22Kumar%2C%20Rakesh%22%29&pagesize-30">Kumar, Rakesh (Committee Chair), Champaign%22%20%2Bcontributor%3A%28%22Chen%2C%20Deming%22%29&pagesize-30">Chen, Deming (committee member), Champaign%22%20%2Bcontributor%3A%28%22Dolecek%2C%20Lara%22%29&pagesize-30">Dolecek, Lara (committee member), Champaign%22%20%2Bcontributor%3A%28%22Kim%2C%20Nam%20Sung%22%29&pagesize-30">Kim, Nam Sung (committee member).

Subjects/Keywords: Computer architecture; Low-power; Reliability; Security; Symbolic simulation; Co-analysis

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Duwe III, H. J. (2017). Dependable design for low-cost ultra-low-power processors. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/99273

Chicago Manual of Style (16^th Edition):

Duwe III, Henry John. “Dependable design for low-cost ultra-low-power processors.” 2017. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed December 12, 2019. http://hdl.handle.net/2142/99273.

MLA Handbook (7^th Edition):

Duwe III, Henry John. “Dependable design for low-cost ultra-low-power processors.” 2017. Web. 12 Dec 2019.

Vancouver:

Duwe III HJ. Dependable design for low-cost ultra-low-power processors. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2017. [cited 2019 Dec 12]. Available from: http://hdl.handle.net/2142/99273.

Council of Science Editors:

Duwe III HJ. Dependable design for low-cost ultra-low-power processors. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/99273

University of Illinois – Urbana-Champaign

4. Chang, Li-Wen. Toward performance portability for CPUS and GPUS through algorithmic compositions.

Degree: PhD, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign

URL: http://hdl.handle.net/2142/98331

► The diversity of microarchitecture designs in heterogeneous computing systems allows programs to achieve high performance and energy efficiency, but results in substantial software redevelopment cost… (more)

Subjects/Keywords: Performance portability; Algorithmic composition; Parallel programming; TANGRAM; Programming language; Compiler; Graphics processing units (GPUs); Central processing units (CPUs); Open Computing Language (OpenCL); Open Multi-Processing (OpenMP); Open Accelerators (OpenACC); C++ Accelerated Massive Parallelism (C++AMP)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Chang, L. (2017). Toward performance portability for CPUS and GPUS through algorithmic compositions. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/98331

Chicago Manual of Style (16^th Edition):

Chang, Li-Wen. “Toward performance portability for CPUS and GPUS through algorithmic compositions.” 2017. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed December 12, 2019. http://hdl.handle.net/2142/98331.

MLA Handbook (7^th Edition):

Chang, Li-Wen. “Toward performance portability for CPUS and GPUS through algorithmic compositions.” 2017. Web. 12 Dec 2019.

Vancouver:

Chang L. Toward performance portability for CPUS and GPUS through algorithmic compositions. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2017. [cited 2019 Dec 12]. Available from: http://hdl.handle.net/2142/98331.

Council of Science Editors:

Chang L. Toward performance portability for CPUS and GPUS through algorithmic compositions. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/98331

University of Illinois – Urbana-Champaign

5. Campbell, Keith A. Robust and reliable hardware accelerator design through high-level synthesis.

Degree: PhD, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign

URL: http://hdl.handle.net/2142/99294

► System-on-chip design is becoming increasingly complex as technology scaling enables more and more functionality on a chip. This scaling-driven complexity has resulted in a variety… (more)

▼ System-on-chip design is becoming increasingly complex as technology scaling enables more and more functionality on a chip. This scaling-driven complexity has resulted in a variety of reliability and validation challenges including logic bugs, hot spots, wear-out, and soft errors. To make matters worse, as we reach the limits of Dennard scaling, efforts to improve system performance and energy efficiency have resulted in the integration of a wide variety of complex hardware accelerators in SoCs. Thus the challenge is to design complex, custom hardware that is efficient, but also correct and reliable. High-level synthesis shows promise to address the problem of complex hardware design by providing a bridge from the high-productivity software domain to the hardware design process. Much research has been done on high-level synthesis efficiency optimizations. This dissertation shows that high-level synthesis also has the power to address validation and reliability challenges through three automated solutions targeting three key stages in the hardware design and use cycle: pre-silicon debugging, post-silicon validation, and post-deployment error detection. Our solution for rapid pre-silicon debugging of accelerator designs is hybrid tracing: comparing a datapath-level trace of hardware execution with a reference software implementation at a fine temporal and spatial granularity to detect logic bugs. An integrated backtrace process delivers source-code meaning to the hardware designer, pinpointing the location of bug activation and providing a strong hint for potential bug fixes. Experimental results show that we are able to detect and aid in localization of logic bugs from both C/C++ specifications as well as the high-level synthesis engine itself. A variation of this solution tailored for rapid post-silicon validation of accelerator designs is hybrid hashing: inserting signature generation logic in a hardware design to create a heavily compressed signature stream that captures the internal behavior of the design at a fine temporal and spatial granularity for comparison with a reference set of signatures generated by high-level simulation to detect bugs. Using hybrid hashing, we demonstrate an improvement in error detection latency (time elapsed from when a bug is activated to when it manifests as an observable failure) of two orders of magnitude and a threefold improvement in bug coverage compared to traditional post-silicon validation techniques. Hybrid hashing also uncovered previously unknown bugs in the CHStone benchmark suite, which is widely used by the HLS community. Hybrid hashing incurs less than 10% area overhead for the accelerator it validates with negligible performance impact, and we also introduce techniques to minimize any possible intrusiveness introduced by hybrid hashing. Finally, our solution for post-deployment error detection is modulo-3 shadow datapaths: performing lightweight shadow computations in modulo-3 space for each main computation. We leverage the binding and scheduling… Advisors/Committee Members: Champaign%22%20%2Bcontributor%3A%28%22Chen%2C%20Deming%22%29&pagesize-30">Chen, Deming (advisor), Champaign%22%20%2Bcontributor%3A%28%22Chen%2C%20Deming%22%29&pagesize-30">Chen, Deming (Committee Chair), Champaign%22%20%2Bcontributor%3A%28%22Hwu%2C%20Wen-Mei%20W%22%29&pagesize-30">Hwu, Wen-Mei W (committee member), Champaign%22%20%2Bcontributor%3A%28%22Wong%2C%20Martin%20D%20F%22%29&pagesize-30">Wong, Martin D F (committee member), Champaign%22%20%2Bcontributor%3A%28%22Kim%2C%20Nam%20Sung%22%29&pagesize-30">Kim, Nam Sung (committee member).

Subjects/Keywords: High-level synthesis (HLS); Automation; Error detection; Scheduling; Binding; Compiler transformation; Compiler optimization; Pipelining; Modulo arithmetic; Modulo-3; Logic optimization; State machine; Datapath; Control logic; Shadow datapath; Modulo datapath; Low cost; High performance; Electrical bug; Aliasing; Stuck-at fault; Soft error; Timing error; Checkpointing; Rollback; Recovery; Pre-silicon validation; Post-silicon validation; Pre-silicon debug; Post-silicon debug; Accelerator; System on a chip; Signature generation; Execution signature; Execution hash; Logic bug; Nondeterministic bug; Masked error; Circuit reliability; Hot spot; Wear out; Silent data corruption; Observability; Detection latency; Mixed datapath; Diversity; Checkpoint corruption; Error injection; Error removal; Quick Error Detection (QED); Hybrid Quick Error Detection (H-QED); Instrumentation; Hybrid co-simulation; Hardware/software; Integration testing; Hybrid tracing; Hybrid hashing; Source-code localization; Software debugging tool; Valgrind; Clang sanitizer; Clang static analyzer; Cppcheck; Root cause analysis; Execution tracing; Realtime error detection; Simulation trigger; Nonintrusive; Address conversion; Undefined behavior; High-level synthesis (HLS) bug; Detection coverage; Gate-level architecture; Mersenne modulus; Full adder; Half adder; Quarter adder; Wraparound; Modulo reducer; Modulo adder; Modulo multiplier; Modulo comparator; Cross-layer; Algorithm; Instruction; Architecture; Logic synthesis; Physical design; Algorithm-based fault tolerance (ABFT); Error detection by duplicated instructions (EDDI); Parity; Flip-flop hardening; Layout design through error-aware transistor positioning dual interlocked storage cell (LEAP-DICE); Cost-effective; Place-and-route; Field programmable gate array (FPGA) emulation; Application specific integrated circuit (ASIC); Field programmable gate array (FPGA); Energy; Area; Latency

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Campbell, K. A. (2017). Robust and reliable hardware accelerator design through high-level synthesis. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/99294

Chicago Manual of Style (16^th Edition):

Campbell, Keith A. “Robust and reliable hardware accelerator design through high-level synthesis.” 2017. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed December 12, 2019. http://hdl.handle.net/2142/99294.

MLA Handbook (7^th Edition):

Campbell, Keith A. “Robust and reliable hardware accelerator design through high-level synthesis.” 2017. Web. 12 Dec 2019.

Vancouver:

Campbell KA. Robust and reliable hardware accelerator design through high-level synthesis. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2017. [cited 2019 Dec 12]. Available from: http://hdl.handle.net/2142/99294.

Council of Science Editors:

Campbell KA. Robust and reliable hardware accelerator design through high-level synthesis. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/99294

University of Illinois – Urbana-Champaign

6. Karpuzcu, Rahmet. Novel many-core architectures for energy-efficiency.

Degree: PhD, 1200, 2012, University of Illinois – Urbana-Champaign

URL: http://hdl.handle.net/2142/34560

► Ideal CMOS device scaling relies on scaling voltages down with lithographic dimensions at every technology generation. This gives rise to faster circuits due to higher… (more)

▼ Ideal CMOS device scaling relies on scaling voltages down with lithographic dimensions at every technology generation. This gives rise to faster circuits due to higher frequency and smaller silicon area for the same functionality. The dynamic power density - equivalently, dynamic power, if the chip area is fixed - stays constant. Static power density, on the other hand, increases. In early generations, however, since the share of static power was practically negligible, dynamic power density staying constant translated to total power density staying constant. This picture has changed recently. To keep the growth of the static power under control, the decrease in the threshold voltage has practically stopped. This, in turn, has prevented the supply voltage from scaling. The end effect is an increasing power density over generations, giving rise to the power wall: Processor chips can include more cores and accelerators than can be active at any given time - and the situation is getting worse. This effect, utilization wall or dark silicon, as induced by the power wall, presents a fundamental challenge that is transforming the many-core architecture landscape. This dissertation attempts to address the key implication of the power wall problem, dark silicon, in two novel and promising ways: By (1) trading off the processor service life for power and performance - the BubbleWrap many-core, and (2) exploring near-threshold voltage operation from an architectural perspective - the Polyomino many-core. The BubbleWrap many-core assumes as many cores on chip as CMOS transistor density scaling trends suggest, and exploits the resulting implicit redundancy - as not all of the cores can be powered on simultaneously - to extract maximum performance by trading off power and service life on a per-core basis. To achieve this, BubbleWrap continuously tunes the supply voltage within the course of each core's service life, leveraging any aging-induced guard-band instantaneously left, rendering one of the following regimes of operation: Minimize power at the same performance level and processor service life; attain the highest performance for the same service life while respecting the given power budget; or attain even higher performance for a shorter service life while respecting the given power budget. Effectively, BubbleWrap runs each core at a closer-to-optimal operating point by always aggressively using up all the aging-induced guard-band that the designers have included - preventing any waste of it. Another way to dim dark silicon is reducing the supply voltage to a value only slightly higher than the threshold voltage. This regime is called near-threshold voltage (NTV) computing (NTC), as opposed to conventional super-threshold voltage (STV) computing (STC). A major drawback of NTC is the higher susceptibility to parametric variations, namely the deviation of device parameters from their nominal values. To address parametric variations in present and future NTV designs,… Advisors/Committee Members: Champaign%22%20%2Bcontributor%3A%28%22Torrellas%2C%20Josep%22%29&pagesize-30">Torrellas, Josep (advisor), Champaign%22%20%2Bcontributor%3A%28%22Torrellas%2C%20Josep%22%29&pagesize-30">Torrellas, Josep (Committee Chair), Champaign%22%20%2Bcontributor%3A%28%22Hwu%2C%20Wen-Mei%20W.%22%29&pagesize-30">Hwu, Wen-Mei W. (committee member), Champaign%22%20%2Bcontributor%3A%28%22Patel%2C%20Sanjay%20J.%22%29&pagesize-30">Patel, Sanjay J. (committee member), Champaign%22%20%2Bcontributor%3A%28%22Shanbhag%2C%20Naresh%20R.%22%29&pagesize-30">Shanbhag, Naresh R. (committee member), Champaign%22%20%2Bcontributor%3A%28%22Kim%2C%20Nam%20Sung%22%29&pagesize-30">Kim, Nam Sung (committee member), Champaign%22%20%2Bcontributor%3A%28%22Wilkerson%2C%20Chris%22%29&pagesize-30">Wilkerson, Chris (committee member).

Subjects/Keywords: Power constraints; Dark silicon; Near-threshold voltage; Many-core architectures; Process variations; Static random-access memory (SRAM) fault models; Wear-Out

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Karpuzcu, R. (2012). Novel many-core architectures for energy-efficiency. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/34560

Chicago Manual of Style (16^th Edition):

Karpuzcu, Rahmet. “Novel many-core architectures for energy-efficiency.” 2012. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed December 12, 2019. http://hdl.handle.net/2142/34560.

MLA Handbook (7^th Edition):

Karpuzcu, Rahmet. “Novel many-core architectures for energy-efficiency.” 2012. Web. 12 Dec 2019.

Vancouver:

Karpuzcu R. Novel many-core architectures for energy-efficiency. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2012. [cited 2019 Dec 12]. Available from: http://hdl.handle.net/2142/34560.

Council of Science Editors:

Karpuzcu R. Novel many-core architectures for energy-efficiency. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2012. Available from: http://hdl.handle.net/2142/34560

University of Illinois – Urbana-Champaign

7. Choi, Wooseok. Design of energy-efficient high-speed wireline transceiver.

Degree: PhD, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign

URL: http://hdl.handle.net/2142/97564

► Energy efficiency has become the most important performance metric of integrated circuits used in many applications ranging from mobile devices to high-performance processors. The power… (more)

▼ Energy efficiency has become the most important performance metric of integrated circuits used in many applications ranging from mobile devices to high-performance processors. The power problem permeates both computing and communication systems alike. Especially in the era of Big Data, continuously growing demand for higher communication bandwidth is driving the need for energy-efficient high-speed I/O serial links. However, the rate at which the energy efficiency of serial links is improving is much slower than the rate at which the required data transfer bandwidth is increasing. This dissertation explores two design approaches for energy-efficient communication systems. The first design approach maximizes the energy efficiency of a transceiver without any performance loss, and as a prototype, a source-synchronous multi-Gb/s transceiver that achieves excellent energy efficiency lower than 0.3pJ/bit is presented. To this end, the proposed transceiver employs aggressive supply voltage scaling, and multiplexed transmitter and receiver synchronized by low-rate multi-phase clocks are adopted to achieve high data rate even at a supply voltage close to the device threshold voltage. Phase spacing errors resulting from device mismatches are corrected using a self-calibration scheme. The proposed phase calibration method uses a single digital delay-locked loop (DLL) for calibrating all the phases, which makes the calibration process insensitive to the supply voltage level. Thanks to this technique, the proposed multi-Gb/s transceiver operates robustly and energy-efficiently at a very low supply voltage. Fabricated in a 65nm CMOS process, the energy efficiency and data rate of the prototype transceiver vary from 0.29pJ/bit to 0.58pJ/bit and 1Gb/s to 6Gb/s, respectively, as the supply voltage is varied from 0.45V to 0.7V. In the second approach, observing that the data traffic in a real system is bursty, a full-rate burst-mode transceiver that achieves rapid on/off operation needed for energy-proportional systems is presented. By injecting input data edges into the oscillator embedded in a classical type-II digital clock and data recovery (CDR) circuit, the proposed receiver achieves instantaneous phase-locking and input jitter filtering simultaneously. In other words, the proposed CDR combines the advantages of conventional feed-forward and feedback architectures to achieve energy-proportional operation. By controlling the number of data edges injected into the oscillator, both the jitter transfer bandwidth and the jitter tolerance corner are accurately controlled. The feedback loop also corrects for any frequency error and helps improve the CDR's immunity to oscillator frequency drift during the power-on and -off states. This also improves the CDR's tolerance to consecutive identical digits present in the input data. Fabricated in a 90nm CMOS process, the prototype receiver instantaneously locks onto the very first data edge and consumes 6.1mW at 2.2Gb/s. Owing to its short power-on time, the overall transceiver's… Advisors/Committee Members: Champaign%22%20%2Bcontributor%3A%28%22Hanumolu%2C%20Pavan%20Kumar%22%29&pagesize-30">Hanumolu, Pavan Kumar (advisor), Champaign%22%20%2Bcontributor%3A%28%22Hanumolu%2C%20Pavan%20Kumar%22%29&pagesize-30">Hanumolu, Pavan Kumar (Committee Chair), Champaign%22%20%2Bcontributor%3A%28%22Kim%2C%20Nam%20Sung%22%29&pagesize-30">Kim, Nam Sung (committee member), Champaign%22%20%2Bcontributor%3A%28%22Schutt-Aine%2C%20Jose%20E%22%29&pagesize-30">Schutt-Aine, Jose E (committee member), Champaign%22%20%2Bcontributor%3A%28%22Srikant%2C%20Rayadurgam%22%29&pagesize-30">Srikant, Rayadurgam (committee member).

Subjects/Keywords: Energy efficiency; Serial link; High-speed input/output (I/O); Wireline transceiver; Near-threshold voltage design; Burst-mode clock and data recovery (CDR); Rapid on/off link

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Choi, W. (2017). Design of energy-efficient high-speed wireline transceiver. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/97564

Chicago Manual of Style (16^th Edition):

Choi, Wooseok. “Design of energy-efficient high-speed wireline transceiver.” 2017. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed December 12, 2019. http://hdl.handle.net/2142/97564.

MLA Handbook (7^th Edition):

Choi, Wooseok. “Design of energy-efficient high-speed wireline transceiver.” 2017. Web. 12 Dec 2019.

Vancouver:

Choi W. Design of energy-efficient high-speed wireline transceiver. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2017. [cited 2019 Dec 12]. Available from: http://hdl.handle.net/2142/97564.

Council of Science Editors:

Choi W. Design of energy-efficient high-speed wireline transceiver. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/97564

University of Illinois – Urbana-Champaign

8. Gopi Reddy, Bhargava Reddy. Energy efficient core designs for upcoming process technologies.

Degree: PhD, Computer Science, 2019, University of Illinois – Urbana-Champaign

URL: http://hdl.handle.net/2142/104832

► Energy efficiency has been a first order constraint in the design of micro processors for the last decade. As Moore's law sunsets, new technologies are… (more)

▼ Energy efficiency has been a first order constraint in the design of micro processors for the last decade. As Moore's law sunsets, new technologies are being actively explored to extend the march in increasing the computational power and efficiency. It is essential for computer architects to understand the opportunities and challenges in utilizing the upcoming process technology trends in order to design the most efficient processors. In this work, we consider three process technology trends and propose core designs that are best suited for each of the technologies. The process technologies are expected to be viable over a span of timelines. We first consider the most popular method currently available to improve the energy efficiency, i.e. by lowering the operating voltage. We make key observations regarding the limiting factors in scaling down the operating voltage for general purpose high performance processors. Later, we propose our novel core design, ScalCore, one that can work in high performance mode at nominal Vdd, and in a very energy-efficient mode at low Vdd. The resulting core design can operate at much lower voltages providing higher parallel performance while consuming lower energy. While lowering Vdd improves the energy efficiency, CMOS devices are fundamentally limited in their low voltage operation. Therefore, we next consider an upcoming device technology – Tunneling Field-Effect Transistors (TFETs), that is expected to supplement CMOS device technology in the near future. TFETs can attain much higher energy efficiency than CMOS at low voltages. However, their performance saturates at high voltages and, therefore, cannot entirely replace CMOS when high performance is needed. Ideally, we desire a core that is as energy-efficient as TFET and provides as much performance as CMOS. To reach this goal, we characterize the TFET device behavior for core design and judiciously integrate TFET units, CMOS units in a single core. The resulting core, called HetCore, can provide very high energy efficiency while limiting the slowdown when compared to a CMOS core. Finally, we analyze Monolithic 3D (M3D) integration technology that is widely considered to be the only way to integrate more transistors on a chip. We present the first analysis of the architectural implications of using M3D for core design and show how to partition the core across different layers. We also address one of the key challenges in realizing the technology, namely, the top layer performance degradation. We propose a critical path based partitioning for logic stages and asymmetric bit/port partitioning for storage stages. The result is a core that performs nearly as well as a core without any top layer slowdown. When compared to a 2D baseline design, an M3D core not only provides much higher performance, it also reduces the energy consumption at the same time. In summary, this thesis addresses one of the fundamental challenges in computer architecture – overcoming the fact that CMOS is not scaling anymore. As we increase the computing… Advisors/Committee Members: Champaign%22%20%2Bcontributor%3A%28%22Torrellas%2C%20Josep%22%29&pagesize-30">Torrellas, Josep (advisor), Champaign%22%20%2Bcontributor%3A%28%22Torrellas%2C%20Josep%22%29&pagesize-30">Torrellas, Josep (Committee Chair), Champaign%22%20%2Bcontributor%3A%28%22Hwu%2C%20Wen-Mei%22%29&pagesize-30">Hwu, Wen-Mei (committee member), Champaign%22%20%2Bcontributor%3A%28%22Kim%2C%20Nam%20Sung%22%29&pagesize-30">Kim, Nam Sung (committee member), Champaign%22%20%2Bcontributor%3A%28%22Fletcher%2C%20Christopher%22%29&pagesize-30">Fletcher, Christopher (committee member), Champaign%22%20%2Bcontributor%3A%28%22Mishra%2C%20Asit%22%29&pagesize-30">Mishra, Asit (committee member).

Subjects/Keywords: Energy efficient architecture; TFET; Monolithic 3D; ScalCore; HetCore; Microarchitecture; Processor; CPU; Low Voltage

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APA (6^th Edition):

Gopi Reddy, B. R. (2019). Energy efficient core designs for upcoming process technologies. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/104832

Chicago Manual of Style (16^th Edition):

Gopi Reddy, Bhargava Reddy. “Energy efficient core designs for upcoming process technologies.” 2019. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed December 12, 2019. http://hdl.handle.net/2142/104832.

MLA Handbook (7^th Edition):

Gopi Reddy, Bhargava Reddy. “Energy efficient core designs for upcoming process technologies.” 2019. Web. 12 Dec 2019.

Vancouver:

Gopi Reddy BR. Energy efficient core designs for upcoming process technologies. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2019. [cited 2019 Dec 12]. Available from: http://hdl.handle.net/2142/104832.

Council of Science Editors:

Gopi Reddy BR. Energy efficient core designs for upcoming process technologies. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2019. Available from: http://hdl.handle.net/2142/104832

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