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You searched for +publisher:"University of Illinois – Urbana-Champaign" +contributor:("Kim, Nam Sung"). Showing records 1 – 8 of 8 total matches.

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University of Illinois – Urbana-Champaign

1. Tseng, Yu-Hsuan. Inference neural network hardware acceleration techniques.

Degree: MS, Electrical & Computer Engr, 2018, University of Illinois – Urbana-Champaign

 A number of recent researches focus on designing accelerators for popular deep learning algorithms. Most of these algorithms heavily involve matrix multiplication. As a result,… (more)

Subjects/Keywords: architecture; acceleration; neural network; analog; hash table

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Tseng, Y. (2018). Inference neural network hardware acceleration techniques. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/101021

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Tseng, Yu-Hsuan. “Inference neural network hardware acceleration techniques.” 2018. Thesis, University of Illinois – Urbana-Champaign. Accessed December 12, 2019. http://hdl.handle.net/2142/101021.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Tseng, Yu-Hsuan. “Inference neural network hardware acceleration techniques.” 2018. Web. 12 Dec 2019.

Vancouver:

Tseng Y. Inference neural network hardware acceleration techniques. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2018. [cited 2019 Dec 12]. Available from: http://hdl.handle.net/2142/101021.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tseng Y. Inference neural network hardware acceleration techniques. [Thesis]. University of Illinois – Urbana-Champaign; 2018. Available from: http://hdl.handle.net/2142/101021

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

2. Min, David. Synthesis constraint optimization for near-threshold voltage design.

Degree: MS, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign

 Near-threshold voltage (NTV) design is a viable solution to many embedded systems which require high energy efficiencies and low performances, but it makes them vulnerable… (more)

Subjects/Keywords: Near-threshold voltage; Low-energy; Embedded systems

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APA (6th Edition):

Min, D. (2017). Synthesis constraint optimization for near-threshold voltage design. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/97551

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Min, David. “Synthesis constraint optimization for near-threshold voltage design.” 2017. Thesis, University of Illinois – Urbana-Champaign. Accessed December 12, 2019. http://hdl.handle.net/2142/97551.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Min, David. “Synthesis constraint optimization for near-threshold voltage design.” 2017. Web. 12 Dec 2019.

Vancouver:

Min D. Synthesis constraint optimization for near-threshold voltage design. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2017. [cited 2019 Dec 12]. Available from: http://hdl.handle.net/2142/97551.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Min D. Synthesis constraint optimization for near-threshold voltage design. [Thesis]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/97551

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

3. Duwe III, Henry John. Dependable design for low-cost ultra-low-power processors.

Degree: PhD, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign

 Emerging applications in the Internet of Things (IoT) domain, such as wearables, implantables, smart tags, and wireless sensor networks put severe power, cost, reliability, and… (more)

Subjects/Keywords: Computer architecture; Low-power; Reliability; Security; Symbolic simulation; Co-analysis

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APA (6th Edition):

Duwe III, H. J. (2017). Dependable design for low-cost ultra-low-power processors. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/99273

Chicago Manual of Style (16th Edition):

Duwe III, Henry John. “Dependable design for low-cost ultra-low-power processors.” 2017. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed December 12, 2019. http://hdl.handle.net/2142/99273.

MLA Handbook (7th Edition):

Duwe III, Henry John. “Dependable design for low-cost ultra-low-power processors.” 2017. Web. 12 Dec 2019.

Vancouver:

Duwe III HJ. Dependable design for low-cost ultra-low-power processors. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2017. [cited 2019 Dec 12]. Available from: http://hdl.handle.net/2142/99273.

Council of Science Editors:

Duwe III HJ. Dependable design for low-cost ultra-low-power processors. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/99273


University of Illinois – Urbana-Champaign

4. Chang, Li-Wen. Toward performance portability for CPUS and GPUS through algorithmic compositions.

Degree: PhD, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign

 The diversity of microarchitecture designs in heterogeneous computing systems allows programs to achieve high performance and energy efficiency, but results in substantial software redevelopment cost… (more)

Subjects/Keywords: Performance portability; Algorithmic composition; Parallel programming; TANGRAM; Programming language; Compiler; Graphics processing units (GPUs); Central processing units (CPUs); Open Computing Language (OpenCL); Open Multi-Processing (OpenMP); Open Accelerators (OpenACC); C++ Accelerated Massive Parallelism (C++AMP)

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APA (6th Edition):

Chang, L. (2017). Toward performance portability for CPUS and GPUS through algorithmic compositions. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/98331

Chicago Manual of Style (16th Edition):

Chang, Li-Wen. “Toward performance portability for CPUS and GPUS through algorithmic compositions.” 2017. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed December 12, 2019. http://hdl.handle.net/2142/98331.

MLA Handbook (7th Edition):

Chang, Li-Wen. “Toward performance portability for CPUS and GPUS through algorithmic compositions.” 2017. Web. 12 Dec 2019.

Vancouver:

Chang L. Toward performance portability for CPUS and GPUS through algorithmic compositions. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2017. [cited 2019 Dec 12]. Available from: http://hdl.handle.net/2142/98331.

Council of Science Editors:

Chang L. Toward performance portability for CPUS and GPUS through algorithmic compositions. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/98331


University of Illinois – Urbana-Champaign

5. Campbell, Keith A. Robust and reliable hardware accelerator design through high-level synthesis.

Degree: PhD, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign

 System-on-chip design is becoming increasingly complex as technology scaling enables more and more functionality on a chip. This scaling-driven complexity has resulted in a variety… (more)

Subjects/Keywords: High-level synthesis (HLS); Automation; Error detection; Scheduling; Binding; Compiler transformation; Compiler optimization; Pipelining; Modulo arithmetic; Modulo-3; Logic optimization; State machine; Datapath; Control logic; Shadow datapath; Modulo datapath; Low cost; High performance; Electrical bug; Aliasing; Stuck-at fault; Soft error; Timing error; Checkpointing; Rollback; Recovery; Pre-silicon validation; Post-silicon validation; Pre-silicon debug; Post-silicon debug; Accelerator; System on a chip; Signature generation; Execution signature; Execution hash; Logic bug; Nondeterministic bug; Masked error; Circuit reliability; Hot spot; Wear out; Silent data corruption; Observability; Detection latency; Mixed datapath; Diversity; Checkpoint corruption; Error injection; Error removal; Quick Error Detection (QED); Hybrid Quick Error Detection (H-QED); Instrumentation; Hybrid co-simulation; Hardware/software; Integration testing; Hybrid tracing; Hybrid hashing; Source-code localization; Software debugging tool; Valgrind; Clang sanitizer; Clang static analyzer; Cppcheck; Root cause analysis; Execution tracing; Realtime error detection; Simulation trigger; Nonintrusive; Address conversion; Undefined behavior; High-level synthesis (HLS) bug; Detection coverage; Gate-level architecture; Mersenne modulus; Full adder; Half adder; Quarter adder; Wraparound; Modulo reducer; Modulo adder; Modulo multiplier; Modulo comparator; Cross-layer; Algorithm; Instruction; Architecture; Logic synthesis; Physical design; Algorithm-based fault tolerance (ABFT); Error detection by duplicated instructions (EDDI); Parity; Flip-flop hardening; Layout design through error-aware transistor positioning dual interlocked storage cell (LEAP-DICE); Cost-effective; Place-and-route; Field programmable gate array (FPGA) emulation; Application specific integrated circuit (ASIC); Field programmable gate array (FPGA); Energy; Area; Latency

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Campbell, K. A. (2017). Robust and reliable hardware accelerator design through high-level synthesis. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/99294

Chicago Manual of Style (16th Edition):

Campbell, Keith A. “Robust and reliable hardware accelerator design through high-level synthesis.” 2017. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed December 12, 2019. http://hdl.handle.net/2142/99294.

MLA Handbook (7th Edition):

Campbell, Keith A. “Robust and reliable hardware accelerator design through high-level synthesis.” 2017. Web. 12 Dec 2019.

Vancouver:

Campbell KA. Robust and reliable hardware accelerator design through high-level synthesis. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2017. [cited 2019 Dec 12]. Available from: http://hdl.handle.net/2142/99294.

Council of Science Editors:

Campbell KA. Robust and reliable hardware accelerator design through high-level synthesis. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/99294


University of Illinois – Urbana-Champaign

6. Karpuzcu, Rahmet. Novel many-core architectures for energy-efficiency.

Degree: PhD, 1200, 2012, University of Illinois – Urbana-Champaign

 Ideal CMOS device scaling relies on scaling voltages down with lithographic dimensions at every technology generation. This gives rise to faster circuits due to higher… (more)

Subjects/Keywords: Power constraints; Dark silicon; Near-threshold voltage; Many-core architectures; Process variations; Static random-access memory (SRAM) fault models; Wear-Out

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Karpuzcu, R. (2012). Novel many-core architectures for energy-efficiency. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/34560

Chicago Manual of Style (16th Edition):

Karpuzcu, Rahmet. “Novel many-core architectures for energy-efficiency.” 2012. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed December 12, 2019. http://hdl.handle.net/2142/34560.

MLA Handbook (7th Edition):

Karpuzcu, Rahmet. “Novel many-core architectures for energy-efficiency.” 2012. Web. 12 Dec 2019.

Vancouver:

Karpuzcu R. Novel many-core architectures for energy-efficiency. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2012. [cited 2019 Dec 12]. Available from: http://hdl.handle.net/2142/34560.

Council of Science Editors:

Karpuzcu R. Novel many-core architectures for energy-efficiency. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2012. Available from: http://hdl.handle.net/2142/34560


University of Illinois – Urbana-Champaign

7. Choi, Wooseok. Design of energy-efficient high-speed wireline transceiver.

Degree: PhD, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign

 Energy efficiency has become the most important performance metric of integrated circuits used in many applications ranging from mobile devices to high-performance processors. The power… (more)

Subjects/Keywords: Energy efficiency; Serial link; High-speed input/output (I/O); Wireline transceiver; Near-threshold voltage design; Burst-mode clock and data recovery (CDR); Rapid on/off link

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Choi, W. (2017). Design of energy-efficient high-speed wireline transceiver. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/97564

Chicago Manual of Style (16th Edition):

Choi, Wooseok. “Design of energy-efficient high-speed wireline transceiver.” 2017. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed December 12, 2019. http://hdl.handle.net/2142/97564.

MLA Handbook (7th Edition):

Choi, Wooseok. “Design of energy-efficient high-speed wireline transceiver.” 2017. Web. 12 Dec 2019.

Vancouver:

Choi W. Design of energy-efficient high-speed wireline transceiver. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2017. [cited 2019 Dec 12]. Available from: http://hdl.handle.net/2142/97564.

Council of Science Editors:

Choi W. Design of energy-efficient high-speed wireline transceiver. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/97564


University of Illinois – Urbana-Champaign

8. Gopi Reddy, Bhargava Reddy. Energy efficient core designs for upcoming process technologies.

Degree: PhD, Computer Science, 2019, University of Illinois – Urbana-Champaign

 Energy efficiency has been a first order constraint in the design of micro processors for the last decade. As Moore's law sunsets, new technologies are… (more)

Subjects/Keywords: Energy efficient architecture; TFET; Monolithic 3D; ScalCore; HetCore; Microarchitecture; Processor; CPU; Low Voltage

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Gopi Reddy, B. R. (2019). Energy efficient core designs for upcoming process technologies. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/104832

Chicago Manual of Style (16th Edition):

Gopi Reddy, Bhargava Reddy. “Energy efficient core designs for upcoming process technologies.” 2019. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed December 12, 2019. http://hdl.handle.net/2142/104832.

MLA Handbook (7th Edition):

Gopi Reddy, Bhargava Reddy. “Energy efficient core designs for upcoming process technologies.” 2019. Web. 12 Dec 2019.

Vancouver:

Gopi Reddy BR. Energy efficient core designs for upcoming process technologies. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2019. [cited 2019 Dec 12]. Available from: http://hdl.handle.net/2142/104832.

Council of Science Editors:

Gopi Reddy BR. Energy efficient core designs for upcoming process technologies. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2019. Available from: http://hdl.handle.net/2142/104832

.