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You searched for +publisher:"University of Illinois – Urbana-Champaign" +contributor:("Hwu, Wen-Mei"). Showing records 1 – 30 of 61 total matches.

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University of Illinois – Urbana-Champaign

1. Ross, Gregory. High performance histogramming on massively parallel processors.

Degree: MS, 1200, 2014, University of Illinois – Urbana-Champaign

 Histogramming is a technique by which input datasets are mined to extract features and patterns. Histograms have wide range of uses in computer vision, machine… (more)

Subjects/Keywords: General Purpose Computing on Graphics Processing Units (GPGPU); Compute Unified Device Architecture (CUDA); Histogram; Image Processing; Parallelism

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ross, G. (2014). High performance histogramming on massively parallel processors. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/50625

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ross, Gregory. “High performance histogramming on massively parallel processors.” 2014. Thesis, University of Illinois – Urbana-Champaign. Accessed April 13, 2021. http://hdl.handle.net/2142/50625.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ross, Gregory. “High performance histogramming on massively parallel processors.” 2014. Web. 13 Apr 2021.

Vancouver:

Ross G. High performance histogramming on massively parallel processors. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2014. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/2142/50625.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ross G. High performance histogramming on massively parallel processors. [Thesis]. University of Illinois – Urbana-Champaign; 2014. Available from: http://hdl.handle.net/2142/50625

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

2. Obeid, Nady M. Compact binning for parallel processing of limited-range functions.

Degree: MS, 1200, 2011, University of Illinois – Urbana-Champaign

 Limited-range functions are domain-level optimizations to a class of applications where all input elements contribute to all output elements, based on the distance between two… (more)

Subjects/Keywords: irregular binning; compact binning; graphics processing units (GPUs); graphics processors; parallel processing; limited-range functions; gridding; cutoff distance

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APA (6th Edition):

Obeid, N. M. (2011). Compact binning for parallel processing of limited-range functions. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/18310

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Obeid, Nady M. “Compact binning for parallel processing of limited-range functions.” 2011. Thesis, University of Illinois – Urbana-Champaign. Accessed April 13, 2021. http://hdl.handle.net/2142/18310.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Obeid, Nady M. “Compact binning for parallel processing of limited-range functions.” 2011. Web. 13 Apr 2021.

Vancouver:

Obeid NM. Compact binning for parallel processing of limited-range functions. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2011. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/2142/18310.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Obeid NM. Compact binning for parallel processing of limited-range functions. [Thesis]. University of Illinois – Urbana-Champaign; 2011. Available from: http://hdl.handle.net/2142/18310

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

3. Chang, Li-Wen. Scalable parallel tridiagonal algorithms with diagonal pivoting and their optimization for many-core architectures.

Degree: MS, 1200, 2014, University of Illinois – Urbana-Champaign

 Tridiagonal solvers are important building blocks for a wide range of scientific applications that are commonly performance-sensitive. Recently, many-core architectures, such as GPUs, have become… (more)

Subjects/Keywords: Tridiagonal Solver; SPIKE algorithm; Linear Recurrence; Cyclic Reduction; Diagonal Pivoting; Graphics Processing Unit (GPU) Computing; General Purpose computation on Graphics Processing Units (GPGPU); Many-core

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APA (6th Edition):

Chang, L. (2014). Scalable parallel tridiagonal algorithms with diagonal pivoting and their optimization for many-core architectures. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/50588

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chang, Li-Wen. “Scalable parallel tridiagonal algorithms with diagonal pivoting and their optimization for many-core architectures.” 2014. Thesis, University of Illinois – Urbana-Champaign. Accessed April 13, 2021. http://hdl.handle.net/2142/50588.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chang, Li-Wen. “Scalable parallel tridiagonal algorithms with diagonal pivoting and their optimization for many-core architectures.” 2014. Web. 13 Apr 2021.

Vancouver:

Chang L. Scalable parallel tridiagonal algorithms with diagonal pivoting and their optimization for many-core architectures. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2014. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/2142/50588.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chang L. Scalable parallel tridiagonal algorithms with diagonal pivoting and their optimization for many-core architectures. [Thesis]. University of Illinois – Urbana-Champaign; 2014. Available from: http://hdl.handle.net/2142/50588

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

4. Lv, Jie. Parallel merge for many-core architectures.

Degree: MS, Electrical & Computer Engr, 2016, University of Illinois – Urbana-Champaign

 This thesis proposes a novel GPU implementation for merging two sorted arrays. We consider the problem of merging two arrays A and B into a… (more)

Subjects/Keywords: Graphics processing unit (GPU); Parallel Merge

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APA (6th Edition):

Lv, J. (2016). Parallel merge for many-core architectures. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/90824

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lv, Jie. “Parallel merge for many-core architectures.” 2016. Thesis, University of Illinois – Urbana-Champaign. Accessed April 13, 2021. http://hdl.handle.net/2142/90824.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lv, Jie. “Parallel merge for many-core architectures.” 2016. Web. 13 Apr 2021.

Vancouver:

Lv J. Parallel merge for many-core architectures. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2016. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/2142/90824.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lv J. Parallel merge for many-core architectures. [Thesis]. University of Illinois – Urbana-Champaign; 2016. Available from: http://hdl.handle.net/2142/90824

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

5. Huang, Sitao. Hardware acceleration of the pair HMM algorithm for DNA variant calling.

Degree: MS, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign

 With the advent of several accurate and sophisticated statistical algorithms and pipelines for DNA sequence analysis, it is becoming increasingly possible to translate raw sequencing… (more)

Subjects/Keywords: Hardware acceleration; Field-programmable gate array (FPGA); Forward algorithm; Pair hidden Markov model (HMM); Computational genomics; Processing element (PE) ring

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APA (6th Edition):

Huang, S. (2017). Hardware acceleration of the pair HMM algorithm for DNA variant calling. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/97496

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Huang, Sitao. “Hardware acceleration of the pair HMM algorithm for DNA variant calling.” 2017. Thesis, University of Illinois – Urbana-Champaign. Accessed April 13, 2021. http://hdl.handle.net/2142/97496.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Huang, Sitao. “Hardware acceleration of the pair HMM algorithm for DNA variant calling.” 2017. Web. 13 Apr 2021.

Vancouver:

Huang S. Hardware acceleration of the pair HMM algorithm for DNA variant calling. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2017. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/2142/97496.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Huang S. Hardware acceleration of the pair HMM algorithm for DNA variant calling. [Thesis]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/97496

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

6. AlMasri, Mohammad. On implementing sparse matrix-vector multiplication on intel platform.

Degree: MS, Electrical & Computer Engr, 2018, University of Illinois – Urbana-Champaign

 Sparse matrix-vector multiplication, SpMV, can be a performance bottle-neck in iterative solvers and algebraic eigenvalue problems. In this thesis, we present our sparse matrix compressed… (more)

Subjects/Keywords: SpMV; SIMD; CCF; CSR; I-e; MKL; OpenMP; Skylake; KNL

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APA (6th Edition):

AlMasri, M. (2018). On implementing sparse matrix-vector multiplication on intel platform. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/101729

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

AlMasri, Mohammad. “On implementing sparse matrix-vector multiplication on intel platform.” 2018. Thesis, University of Illinois – Urbana-Champaign. Accessed April 13, 2021. http://hdl.handle.net/2142/101729.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

AlMasri, Mohammad. “On implementing sparse matrix-vector multiplication on intel platform.” 2018. Web. 13 Apr 2021.

Vancouver:

AlMasri M. On implementing sparse matrix-vector multiplication on intel platform. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2018. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/2142/101729.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

AlMasri M. On implementing sparse matrix-vector multiplication on intel platform. [Thesis]. University of Illinois – Urbana-Champaign; 2018. Available from: http://hdl.handle.net/2142/101729

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

7. Li, Cheng. Performance benchmarking, analysis, and optimization of deep learning inference.

Degree: PhD, Computer Science, 2020, University of Illinois – Urbana-Champaign

 The world sees a proliferation of deep learning (DL) models and their wide adoption in different application domains. This has made the performance benchmarking, understanding,… (more)

Subjects/Keywords: deep learning; machine learning; performance analysis; benchmarking; optimization

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Li, C. (2020). Performance benchmarking, analysis, and optimization of deep learning inference. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/108505

Chicago Manual of Style (16th Edition):

Li, Cheng. “Performance benchmarking, analysis, and optimization of deep learning inference.” 2020. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed April 13, 2021. http://hdl.handle.net/2142/108505.

MLA Handbook (7th Edition):

Li, Cheng. “Performance benchmarking, analysis, and optimization of deep learning inference.” 2020. Web. 13 Apr 2021.

Vancouver:

Li C. Performance benchmarking, analysis, and optimization of deep learning inference. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2020. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/2142/108505.

Council of Science Editors:

Li C. Performance benchmarking, analysis, and optimization of deep learning inference. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2020. Available from: http://hdl.handle.net/2142/108505


University of Illinois – Urbana-Champaign

8. Kim, Hee-Seok. Compiler and runtime techniques for bulk-synchronous programming models on CPU architectures.

Degree: PhD, Electrical & Computer Engineering, 2015, University of Illinois – Urbana-Champaign

 The rising pressure to simultaneously improve performance and reduce power consumption is driving more heterogeneity into all aspects of computing devices. However, wide adoption of… (more)

Subjects/Keywords: OpenCL; compiler; Central Processing Unit (CPU); performance portability; data locality

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APA (6th Edition):

Kim, H. (2015). Compiler and runtime techniques for bulk-synchronous programming models on CPU architectures. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/88987

Chicago Manual of Style (16th Edition):

Kim, Hee-Seok. “Compiler and runtime techniques for bulk-synchronous programming models on CPU architectures.” 2015. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed April 13, 2021. http://hdl.handle.net/2142/88987.

MLA Handbook (7th Edition):

Kim, Hee-Seok. “Compiler and runtime techniques for bulk-synchronous programming models on CPU architectures.” 2015. Web. 13 Apr 2021.

Vancouver:

Kim H. Compiler and runtime techniques for bulk-synchronous programming models on CPU architectures. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2015. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/2142/88987.

Council of Science Editors:

Kim H. Compiler and runtime techniques for bulk-synchronous programming models on CPU architectures. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/88987

9. Pearson, Carl. Heterogeneous system and application communication modeling.

Degree: MS, Electrical & Computer Engr, 2018, University of Illinois – Urbana-Champaign

 With the end of Dennard scaling, high-performance computing increasingly relies on heterogeneous systems with specialized hardware to improve application performance. This trend has driven up… (more)

Subjects/Keywords: GPGPU; CUDA; NVLink; Benchmark; PCIe; NUMA

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APA (6th Edition):

Pearson, C. (2018). Heterogeneous system and application communication modeling. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/101501

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Pearson, Carl. “Heterogeneous system and application communication modeling.” 2018. Thesis, University of Illinois – Urbana-Champaign. Accessed April 13, 2021. http://hdl.handle.net/2142/101501.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Pearson, Carl. “Heterogeneous system and application communication modeling.” 2018. Web. 13 Apr 2021.

Vancouver:

Pearson C. Heterogeneous system and application communication modeling. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2018. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/2142/101501.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Pearson C. Heterogeneous system and application communication modeling. [Thesis]. University of Illinois – Urbana-Champaign; 2018. Available from: http://hdl.handle.net/2142/101501

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

10. Zhu, Xinrui. MLModelScope website development with react.

Degree: MS, Electrical & Computer Engr, 2019, University of Illinois – Urbana-Champaign

 With the rapid growth of the MLModelScope project, there is an urgent need for a user interface to show users the available resources, functionalities, and… (more)

Subjects/Keywords: React; User Interface; Machine Learning; MLModelScope

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APA (6th Edition):

Zhu, X. (2019). MLModelScope website development with react. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/105716

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Zhu, Xinrui. “MLModelScope website development with react.” 2019. Thesis, University of Illinois – Urbana-Champaign. Accessed April 13, 2021. http://hdl.handle.net/2142/105716.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Zhu, Xinrui. “MLModelScope website development with react.” 2019. Web. 13 Apr 2021.

Vancouver:

Zhu X. MLModelScope website development with react. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2019. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/2142/105716.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zhu X. MLModelScope website development with react. [Thesis]. University of Illinois – Urbana-Champaign; 2019. Available from: http://hdl.handle.net/2142/105716

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

11. Srivastava, Abhishek. Performance evaluation of deep learning on smartphones.

Degree: MS, Computer Science, 2019, University of Illinois – Urbana-Champaign

 Deep Learning powers a variety of applications from self driving cars and autonomous robotics to web search and voice assistants. It is fair to say… (more)

Subjects/Keywords: Deep Learning; Benchmarking; Performance Evaluation; Mobile Devices

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Srivastava, A. (2019). Performance evaluation of deep learning on smartphones. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/106260

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Srivastava, Abhishek. “Performance evaluation of deep learning on smartphones.” 2019. Thesis, University of Illinois – Urbana-Champaign. Accessed April 13, 2021. http://hdl.handle.net/2142/106260.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Srivastava, Abhishek. “Performance evaluation of deep learning on smartphones.” 2019. Web. 13 Apr 2021.

Vancouver:

Srivastava A. Performance evaluation of deep learning on smartphones. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2019. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/2142/106260.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Srivastava A. Performance evaluation of deep learning on smartphones. [Thesis]. University of Illinois – Urbana-Champaign; 2019. Available from: http://hdl.handle.net/2142/106260

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

12. Wu, Xiao-Long. Tiger: tiled iterative genome assembler and approximate multi-genome aligner.

Degree: PhD, 1200, 2013, University of Illinois – Urbana-Champaign

 Sequence assembly and alignments are two important stepping stones for comparative genomics. With the fast adoption of the next-generation sequencing (NGS) technologies and the coming… (more)

Subjects/Keywords: De novo genome assembly; next-generation sequencing; third-generation sequencing; iterative genome assembler; read partitioning; Multiple sequence alignment; multiple genome alignment

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APA (6th Edition):

Wu, X. (2013). Tiger: tiled iterative genome assembler and approximate multi-genome aligner. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/45618

Chicago Manual of Style (16th Edition):

Wu, Xiao-Long. “Tiger: tiled iterative genome assembler and approximate multi-genome aligner.” 2013. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed April 13, 2021. http://hdl.handle.net/2142/45618.

MLA Handbook (7th Edition):

Wu, Xiao-Long. “Tiger: tiled iterative genome assembler and approximate multi-genome aligner.” 2013. Web. 13 Apr 2021.

Vancouver:

Wu X. Tiger: tiled iterative genome assembler and approximate multi-genome aligner. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2013. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/2142/45618.

Council of Science Editors:

Wu X. Tiger: tiled iterative genome assembler and approximate multi-genome aligner. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2013. Available from: http://hdl.handle.net/2142/45618


University of Illinois – Urbana-Champaign

13. Chang, Li-Wen. Toward performance portability for CPUS and GPUS through algorithmic compositions.

Degree: PhD, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign

 The diversity of microarchitecture designs in heterogeneous computing systems allows programs to achieve high performance and energy efficiency, but results in substantial software redevelopment cost… (more)

Subjects/Keywords: Performance portability; Algorithmic composition; Parallel programming; TANGRAM; Programming language; Compiler; Graphics processing units (GPUs); Central processing units (CPUs); Open Computing Language (OpenCL); Open Multi-Processing (OpenMP); Open Accelerators (OpenACC); C++ Accelerated Massive Parallelism (C++AMP)

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APA (6th Edition):

Chang, L. (2017). Toward performance portability for CPUS and GPUS through algorithmic compositions. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/98331

Chicago Manual of Style (16th Edition):

Chang, Li-Wen. “Toward performance portability for CPUS and GPUS through algorithmic compositions.” 2017. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed April 13, 2021. http://hdl.handle.net/2142/98331.

MLA Handbook (7th Edition):

Chang, Li-Wen. “Toward performance portability for CPUS and GPUS through algorithmic compositions.” 2017. Web. 13 Apr 2021.

Vancouver:

Chang L. Toward performance portability for CPUS and GPUS through algorithmic compositions. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2017. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/2142/98331.

Council of Science Editors:

Chang L. Toward performance portability for CPUS and GPUS through algorithmic compositions. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/98331


University of Illinois – Urbana-Champaign

14. Yu, Jiahui. Towards efficient, on-demand and automated deep learning.

Degree: PhD, Electrical & Computer Engr, 2020, University of Illinois – Urbana-Champaign

 In the past decade, deep learning has achieved great breakthroughs on tasks of computer vision, speech, language, control and many others. The advanced and dedicated… (more)

Subjects/Keywords: efficient; on-demand; automated; deep learning; automl

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APA (6th Edition):

Yu, J. (2020). Towards efficient, on-demand and automated deep learning. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/107845

Chicago Manual of Style (16th Edition):

Yu, Jiahui. “Towards efficient, on-demand and automated deep learning.” 2020. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed April 13, 2021. http://hdl.handle.net/2142/107845.

MLA Handbook (7th Edition):

Yu, Jiahui. “Towards efficient, on-demand and automated deep learning.” 2020. Web. 13 Apr 2021.

Vancouver:

Yu J. Towards efficient, on-demand and automated deep learning. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2020. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/2142/107845.

Council of Science Editors:

Yu J. Towards efficient, on-demand and automated deep learning. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2020. Available from: http://hdl.handle.net/2142/107845


University of Illinois – Urbana-Champaign

15. Papakonstantinou, Alexandros. High-level automation of custom hardware design for high-performance computing.

Degree: PhD, 1200, 2013, University of Illinois – Urbana-Champaign

 This dissertation focuses on efficient generation of custom processors from high-level language descriptions. Our work exploits compiler-based optimizations and transformations in tandem with high-level synthesis… (more)

Subjects/Keywords: High-level synthesis; Field-Programmable Gate Array (FPGA); CUDA; parallel programming; High Performance Computing (HPC)

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APA (6th Edition):

Papakonstantinou, A. (2013). High-level automation of custom hardware design for high-performance computing. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/42137

Chicago Manual of Style (16th Edition):

Papakonstantinou, Alexandros. “High-level automation of custom hardware design for high-performance computing.” 2013. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed April 13, 2021. http://hdl.handle.net/2142/42137.

MLA Handbook (7th Edition):

Papakonstantinou, Alexandros. “High-level automation of custom hardware design for high-performance computing.” 2013. Web. 13 Apr 2021.

Vancouver:

Papakonstantinou A. High-level automation of custom hardware design for high-performance computing. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2013. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/2142/42137.

Council of Science Editors:

Papakonstantinou A. High-level automation of custom hardware design for high-performance computing. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2013. Available from: http://hdl.handle.net/2142/42137


University of Illinois – Urbana-Champaign

16. Lin, Chen-Hsuan. Design automation for circuit reliability and energy efficiency.

Degree: PhD, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign

 This dissertation presents approaches to improve circuit reliability and energy efficiency from different angles, such as verification, logic synthesis, and functional unit design. A variety… (more)

Subjects/Keywords: Electronic design automation; Reliability; Energy efficiency; Data mining; Satisfiability (SAT) solving; Logic restructuring; Assertion; Negative bias temperature instability (NBTI) effect; Modulo arithmetic; Shadow datapath

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APA (6th Edition):

Lin, C. (2017). Design automation for circuit reliability and energy efficiency. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/99237

Chicago Manual of Style (16th Edition):

Lin, Chen-Hsuan. “Design automation for circuit reliability and energy efficiency.” 2017. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed April 13, 2021. http://hdl.handle.net/2142/99237.

MLA Handbook (7th Edition):

Lin, Chen-Hsuan. “Design automation for circuit reliability and energy efficiency.” 2017. Web. 13 Apr 2021.

Vancouver:

Lin C. Design automation for circuit reliability and energy efficiency. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2017. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/2142/99237.

Council of Science Editors:

Lin C. Design automation for circuit reliability and energy efficiency. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/99237


University of Illinois – Urbana-Champaign

17. Hwang, Leslie K. Thermal designs, models and optimization for three-dimensional integrated circuits.

Degree: PhD, Electrical & Computer Engr, 2018, University of Illinois – Urbana-Champaign

 Three-dimensional integrated circuits (3D ICs), a novel packaging technology, are heavily studied to enable improved performance with denser packaging and reduced interconnects. Despite numerous advantages,… (more)

Subjects/Keywords: 3D IC; thermal design; TTSV; thermal fin; microchannel; optimization

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APA (6th Edition):

Hwang, L. K. (2018). Thermal designs, models and optimization for three-dimensional integrated circuits. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/102951

Chicago Manual of Style (16th Edition):

Hwang, Leslie K. “Thermal designs, models and optimization for three-dimensional integrated circuits.” 2018. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed April 13, 2021. http://hdl.handle.net/2142/102951.

MLA Handbook (7th Edition):

Hwang, Leslie K. “Thermal designs, models and optimization for three-dimensional integrated circuits.” 2018. Web. 13 Apr 2021.

Vancouver:

Hwang LK. Thermal designs, models and optimization for three-dimensional integrated circuits. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2018. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/2142/102951.

Council of Science Editors:

Hwang LK. Thermal designs, models and optimization for three-dimensional integrated circuits. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2018. Available from: http://hdl.handle.net/2142/102951


University of Illinois – Urbana-Champaign

18. Lin, Chun-Xun. Advances in parallel programming for electronic design automation.

Degree: PhD, Electrical & Computer Engr, 2020, University of Illinois – Urbana-Champaign

 The continued miniaturization of the technology node increases not only the chip capacity but also the circuit design complexity. How does one efficiently design a… (more)

Subjects/Keywords: Electronic design automation; Parallel programming

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APA (6th Edition):

Lin, C. (2020). Advances in parallel programming for electronic design automation. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/108425

Chicago Manual of Style (16th Edition):

Lin, Chun-Xun. “Advances in parallel programming for electronic design automation.” 2020. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed April 13, 2021. http://hdl.handle.net/2142/108425.

MLA Handbook (7th Edition):

Lin, Chun-Xun. “Advances in parallel programming for electronic design automation.” 2020. Web. 13 Apr 2021.

Vancouver:

Lin C. Advances in parallel programming for electronic design automation. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2020. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/2142/108425.

Council of Science Editors:

Lin C. Advances in parallel programming for electronic design automation. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2020. Available from: http://hdl.handle.net/2142/108425


University of Illinois – Urbana-Champaign

19. Alian, Mohammad. A cross-stack, network-centric architectural design for next-generation datacenters.

Degree: PhD, Electrical & Computer Engr, 2020, University of Illinois – Urbana-Champaign

 This thesis proposes a full-stack, cross-layer datacenter architecture based on in-network computing and near-memory processing paradigms. The proposed datacenter architecture is built atop two principles:… (more)

Subjects/Keywords: datacenter architecture; near-data processing; near-memory processing; in-network computing; distributed simulation; datacenter network architecture; scale-out processing

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APA (6th Edition):

Alian, M. (2020). A cross-stack, network-centric architectural design for next-generation datacenters. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/108449

Chicago Manual of Style (16th Edition):

Alian, Mohammad. “A cross-stack, network-centric architectural design for next-generation datacenters.” 2020. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed April 13, 2021. http://hdl.handle.net/2142/108449.

MLA Handbook (7th Edition):

Alian, Mohammad. “A cross-stack, network-centric architectural design for next-generation datacenters.” 2020. Web. 13 Apr 2021.

Vancouver:

Alian M. A cross-stack, network-centric architectural design for next-generation datacenters. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2020. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/2142/108449.

Council of Science Editors:

Alian M. A cross-stack, network-centric architectural design for next-generation datacenters. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2020. Available from: http://hdl.handle.net/2142/108449


University of Illinois – Urbana-Champaign

20. Karpuzcu, Rahmet. Novel many-core architectures for energy-efficiency.

Degree: PhD, 1200, 2012, University of Illinois – Urbana-Champaign

 Ideal CMOS device scaling relies on scaling voltages down with lithographic dimensions at every technology generation. This gives rise to faster circuits due to higher… (more)

Subjects/Keywords: Power constraints; Dark silicon; Near-threshold voltage; Many-core architectures; Process variations; Static random-access memory (SRAM) fault models; Wear-Out

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APA (6th Edition):

Karpuzcu, R. (2012). Novel many-core architectures for energy-efficiency. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/34560

Chicago Manual of Style (16th Edition):

Karpuzcu, Rahmet. “Novel many-core architectures for energy-efficiency.” 2012. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed April 13, 2021. http://hdl.handle.net/2142/34560.

MLA Handbook (7th Edition):

Karpuzcu, Rahmet. “Novel many-core architectures for energy-efficiency.” 2012. Web. 13 Apr 2021.

Vancouver:

Karpuzcu R. Novel many-core architectures for energy-efficiency. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2012. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/2142/34560.

Council of Science Editors:

Karpuzcu R. Novel many-core architectures for energy-efficiency. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2012. Available from: http://hdl.handle.net/2142/34560


University of Illinois – Urbana-Champaign

21. Crago, Neal. Energy-efficient latency tolerance for 1000-core data parallel processors with decoupled strands.

Degree: PhD, 1200, 2012, University of Illinois – Urbana-Champaign

 This dissertation presents a novel decoupled latency tolerance technique for 1000-core data parallel processors. The approach focuses on developing instruction latency tolerance to improve performance… (more)

Subjects/Keywords: Parallel Processing; Data-parallel; Graphics processing unit (GPU); General-purpose computing on graphics processing units (GPGPU); manycore; latency tolerance; decoupled architecture; compiler technique; energy-efficiency; power-efficiency; high-performance; low power; low energy

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APA (6th Edition):

Crago, N. (2012). Energy-efficient latency tolerance for 1000-core data parallel processors with decoupled strands. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/34589

Chicago Manual of Style (16th Edition):

Crago, Neal. “Energy-efficient latency tolerance for 1000-core data parallel processors with decoupled strands.” 2012. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed April 13, 2021. http://hdl.handle.net/2142/34589.

MLA Handbook (7th Edition):

Crago, Neal. “Energy-efficient latency tolerance for 1000-core data parallel processors with decoupled strands.” 2012. Web. 13 Apr 2021.

Vancouver:

Crago N. Energy-efficient latency tolerance for 1000-core data parallel processors with decoupled strands. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2012. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/2142/34589.

Council of Science Editors:

Crago N. Energy-efficient latency tolerance for 1000-core data parallel processors with decoupled strands. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2012. Available from: http://hdl.handle.net/2142/34589


University of Illinois – Urbana-Champaign

22. Johnson, Daniel. Multithreaded architectures for manycore throughput processors.

Degree: PhD, 1200, 2013, University of Illinois – Urbana-Champaign

 This dissertation describes work on the architecture of throughput-oriented accelerator processors. First, we examine the limitations of current accelerator processors and identify an opportunity to… (more)

Subjects/Keywords: Processors; Multiprocessors; Computer Architecture; Parallel processing; Multithreading; High Performance Computing (HPC); visual computing; Accelerator processor; coprocessor; cache coherence; parallel computing; computer systems; graphics processors

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APA (6th Edition):

Johnson, D. (2013). Multithreaded architectures for manycore throughput processors. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/44751

Chicago Manual of Style (16th Edition):

Johnson, Daniel. “Multithreaded architectures for manycore throughput processors.” 2013. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed April 13, 2021. http://hdl.handle.net/2142/44751.

MLA Handbook (7th Edition):

Johnson, Daniel. “Multithreaded architectures for manycore throughput processors.” 2013. Web. 13 Apr 2021.

Vancouver:

Johnson D. Multithreaded architectures for manycore throughput processors. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2013. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/2142/44751.

Council of Science Editors:

Johnson D. Multithreaded architectures for manycore throughput processors. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2013. Available from: http://hdl.handle.net/2142/44751


University of Illinois – Urbana-Champaign

23. Wu, Pei-Ci. New methods for electronic design automation problems.

Degree: PhD, Electrical & Computer Engr, 2015, University of Illinois – Urbana-Champaign

 As the semiconductor technology marches towards the 14nm node and beyond, EDA (electronic design automation) has rapidly increased in importance with ever more complicated modern… (more)

Subjects/Keywords: Electronic Design Automation (EDA); Timing Closure; Buffer Insertion; Aerial Image Simulation; Escape Routing; Bus Planner

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APA (6th Edition):

Wu, P. (2015). New methods for electronic design automation problems. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/78447

Chicago Manual of Style (16th Edition):

Wu, Pei-Ci. “New methods for electronic design automation problems.” 2015. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed April 13, 2021. http://hdl.handle.net/2142/78447.

MLA Handbook (7th Edition):

Wu, Pei-Ci. “New methods for electronic design automation problems.” 2015. Web. 13 Apr 2021.

Vancouver:

Wu P. New methods for electronic design automation problems. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2015. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/2142/78447.

Council of Science Editors:

Wu P. New methods for electronic design automation problems. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/78447


University of Illinois – Urbana-Champaign

24. Wang, Haichuan. Compiler and runtime techniques for optimizing dynamic scripting languages.

Degree: PhD, Computer Science, 2015, University of Illinois – Urbana-Champaign

 This thesis studies the compilation and runtime techniques to improve the performance of dynamic scripting languages using R programming language as a test case. The… (more)

Subjects/Keywords: R Programming Language; Dynamic Scripting Language; Compiler; Performance; Specialization; Vectorization

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APA (6th Edition):

Wang, H. (2015). Compiler and runtime techniques for optimizing dynamic scripting languages. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/78638

Chicago Manual of Style (16th Edition):

Wang, Haichuan. “Compiler and runtime techniques for optimizing dynamic scripting languages.” 2015. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed April 13, 2021. http://hdl.handle.net/2142/78638.

MLA Handbook (7th Edition):

Wang, Haichuan. “Compiler and runtime techniques for optimizing dynamic scripting languages.” 2015. Web. 13 Apr 2021.

Vancouver:

Wang H. Compiler and runtime techniques for optimizing dynamic scripting languages. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2015. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/2142/78638.

Council of Science Editors:

Wang H. Compiler and runtime techniques for optimizing dynamic scripting languages. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/78638


University of Illinois – Urbana-Champaign

25. Ahn, Daniel. Software and architecture support for the bulk multicore.

Degree: PhD, 0112, 2012, University of Illinois – Urbana-Champaign

 Research on transactional memory began as a tool to improve the experience of programmers working on parallel code. Just as transactions in databases, it was… (more)

Subjects/Keywords: Computer Architecture; Compiler; Transactional Memory; Transactional Execution; Speculative Optimization; Bloomfilter; Signature; Memory Model; Sequential Consistency; Function Memoization; Alias Analysis

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APA (6th Edition):

Ahn, D. (2012). Software and architecture support for the bulk multicore. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/32076

Chicago Manual of Style (16th Edition):

Ahn, Daniel. “Software and architecture support for the bulk multicore.” 2012. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed April 13, 2021. http://hdl.handle.net/2142/32076.

MLA Handbook (7th Edition):

Ahn, Daniel. “Software and architecture support for the bulk multicore.” 2012. Web. 13 Apr 2021.

Vancouver:

Ahn D. Software and architecture support for the bulk multicore. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2012. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/2142/32076.

Council of Science Editors:

Ahn D. Software and architecture support for the bulk multicore. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2012. Available from: http://hdl.handle.net/2142/32076


University of Illinois – Urbana-Champaign

26. Huang, Tsung-Wei. Distributed timing analysis.

Degree: PhD, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign

 As design complexities continue to grow larger, the need to efficiently analyze circuit timing with billions of transistors across multiple modes and corners is quickly… (more)

Subjects/Keywords: Distributed systems; Timing analysis

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APA (6th Edition):

Huang, T. (2017). Distributed timing analysis. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/99302

Chicago Manual of Style (16th Edition):

Huang, Tsung-Wei. “Distributed timing analysis.” 2017. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed April 13, 2021. http://hdl.handle.net/2142/99302.

MLA Handbook (7th Edition):

Huang, Tsung-Wei. “Distributed timing analysis.” 2017. Web. 13 Apr 2021.

Vancouver:

Huang T. Distributed timing analysis. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2017. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/2142/99302.

Council of Science Editors:

Huang T. Distributed timing analysis. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/99302


University of Illinois – Urbana-Champaign

27. Estrada, Zachary. Dynamic reliability and security monitoring: a virtual machine approach.

Degree: PhD, Electrical & Computer Engr, 2016, University of Illinois – Urbana-Champaign

 While one always works to prevent attacks and failures, they are inevitable and situational awareness is key to taking appropriate action. Monitoring plays an integral… (more)

Subjects/Keywords: virtualization; emulation; security; reliability; hprobes; cloud; hardware-asssisted virtualization; dynamic analysis

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APA (6th Edition):

Estrada, Z. (2016). Dynamic reliability and security monitoring: a virtual machine approach. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/95458

Chicago Manual of Style (16th Edition):

Estrada, Zachary. “Dynamic reliability and security monitoring: a virtual machine approach.” 2016. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed April 13, 2021. http://hdl.handle.net/2142/95458.

MLA Handbook (7th Edition):

Estrada, Zachary. “Dynamic reliability and security monitoring: a virtual machine approach.” 2016. Web. 13 Apr 2021.

Vancouver:

Estrada Z. Dynamic reliability and security monitoring: a virtual machine approach. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2016. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/2142/95458.

Council of Science Editors:

Estrada Z. Dynamic reliability and security monitoring: a virtual machine approach. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2016. Available from: http://hdl.handle.net/2142/95458


University of Illinois – Urbana-Champaign

28. Jambunathan, Revathi. CHAOS: A multi-GPU PIC-DSMC solver for modeling gas and plasma flows.

Degree: PhD, Aerospace Engineering, 2019, University of Illinois – Urbana-Champaign

 Numerical modeling of gas and plasma-surface interactions is critical to understanding the complex kinetic processes that dominate the extreme environments of planetary entry and in-space… (more)

Subjects/Keywords: PIC; DSMC; Forest of Octree; GPU; CUDA; MPI; Morton encoding; linearization; permeability; porous media; plasma plume; neutralization; electron kinetics; charge-exchange collisions; ion backflow

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APA (6th Edition):

Jambunathan, R. (2019). CHAOS: A multi-GPU PIC-DSMC solver for modeling gas and plasma flows. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/104740

Chicago Manual of Style (16th Edition):

Jambunathan, Revathi. “CHAOS: A multi-GPU PIC-DSMC solver for modeling gas and plasma flows.” 2019. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed April 13, 2021. http://hdl.handle.net/2142/104740.

MLA Handbook (7th Edition):

Jambunathan, Revathi. “CHAOS: A multi-GPU PIC-DSMC solver for modeling gas and plasma flows.” 2019. Web. 13 Apr 2021.

Vancouver:

Jambunathan R. CHAOS: A multi-GPU PIC-DSMC solver for modeling gas and plasma flows. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2019. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/2142/104740.

Council of Science Editors:

Jambunathan R. CHAOS: A multi-GPU PIC-DSMC solver for modeling gas and plasma flows. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2019. Available from: http://hdl.handle.net/2142/104740


University of Illinois – Urbana-Champaign

29. Gopi Reddy, Bhargava Reddy. Energy efficient core designs for upcoming process technologies.

Degree: PhD, Computer Science, 2019, University of Illinois – Urbana-Champaign

 Energy efficiency has been a first order constraint in the design of micro processors for the last decade. As Moore's law sunsets, new technologies are… (more)

Subjects/Keywords: Energy efficient architecture; TFET; Monolithic 3D; ScalCore; HetCore; Microarchitecture; Processor; CPU; Low Voltage

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APA (6th Edition):

Gopi Reddy, B. R. (2019). Energy efficient core designs for upcoming process technologies. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/104832

Chicago Manual of Style (16th Edition):

Gopi Reddy, Bhargava Reddy. “Energy efficient core designs for upcoming process technologies.” 2019. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed April 13, 2021. http://hdl.handle.net/2142/104832.

MLA Handbook (7th Edition):

Gopi Reddy, Bhargava Reddy. “Energy efficient core designs for upcoming process technologies.” 2019. Web. 13 Apr 2021.

Vancouver:

Gopi Reddy BR. Energy efficient core designs for upcoming process technologies. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2019. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/2142/104832.

Council of Science Editors:

Gopi Reddy BR. Energy efficient core designs for upcoming process technologies. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2019. Available from: http://hdl.handle.net/2142/104832

30. Agarwal, Ayush. Memory access patterns and page promotion in hybrid memory systems.

Degree: MS, Electrical & Computer Engr, 2020, University of Illinois – Urbana-Champaign

 Hybrid heterogeneous memory systems are becoming increasingly popular as traditional memory systems are hitting performance and energy walls in processing data-intensive applications, which are becoming… (more)

Subjects/Keywords: memory system; data-intensive; prefetching; hybrid memory system; page promotion; page migration

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APA (6th Edition):

Agarwal, A. (2020). Memory access patterns and page promotion in hybrid memory systems. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/108002

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Agarwal, Ayush. “Memory access patterns and page promotion in hybrid memory systems.” 2020. Thesis, University of Illinois – Urbana-Champaign. Accessed April 13, 2021. http://hdl.handle.net/2142/108002.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Agarwal, Ayush. “Memory access patterns and page promotion in hybrid memory systems.” 2020. Web. 13 Apr 2021.

Vancouver:

Agarwal A. Memory access patterns and page promotion in hybrid memory systems. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2020. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/2142/108002.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Agarwal A. Memory access patterns and page promotion in hybrid memory systems. [Thesis]. University of Illinois – Urbana-Champaign; 2020. Available from: http://hdl.handle.net/2142/108002

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

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