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You searched for +publisher:"University of Illinois – Urbana-Champaign" +contributor:("Chen, Deming"). Showing records 1 – 30 of 78 total matches.

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University of Illinois – Urbana-Champaign

1. Tolar, Jacob. A directory enhanced network on chip for FPGA.

Degree: MS, 1200, 2013, University of Illinois – Urbana-Champaign

 This thesis presents and evaluates a directory enhanced network on chip for FPGA, with the goal of improving the performance of cores generated by FCUDA,… (more)

Subjects/Keywords: Network on Chip; Field-Programmable Gate Array (FPGA); FCUDA

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APA (6th Edition):

Tolar, J. (2013). A directory enhanced network on chip for FPGA. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/44439

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Tolar, Jacob. “A directory enhanced network on chip for FPGA.” 2013. Thesis, University of Illinois – Urbana-Champaign. Accessed April 07, 2020. http://hdl.handle.net/2142/44439.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Tolar, Jacob. “A directory enhanced network on chip for FPGA.” 2013. Web. 07 Apr 2020.

Vancouver:

Tolar J. A directory enhanced network on chip for FPGA. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2013. [cited 2020 Apr 07]. Available from: http://hdl.handle.net/2142/44439.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tolar J. A directory enhanced network on chip for FPGA. [Thesis]. University of Illinois – Urbana-Champaign; 2013. Available from: http://hdl.handle.net/2142/44439

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

2. Sangai, Amit. Circuit level delay and power analysis of graphene nano-ribbon field-effect transistors using monte carlo simulations and standard cell library characterization.

Degree: MS, 1200, 2014, University of Illinois – Urbana-Champaign

 Graphene nano-ribbon (GNR) transistors have emerged as a promising candidate to replace traditional silicon transistors in future scaled technologies. Since these devices are very small,… (more)

Subjects/Keywords: Graphene; Monte Carlo; Graphene nanoribbon field-effect transistor (GNRFET); Graphene nano-ribbon

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APA (6th Edition):

Sangai, A. (2014). Circuit level delay and power analysis of graphene nano-ribbon field-effect transistors using monte carlo simulations and standard cell library characterization. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/46893

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sangai, Amit. “Circuit level delay and power analysis of graphene nano-ribbon field-effect transistors using monte carlo simulations and standard cell library characterization.” 2014. Thesis, University of Illinois – Urbana-Champaign. Accessed April 07, 2020. http://hdl.handle.net/2142/46893.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sangai, Amit. “Circuit level delay and power analysis of graphene nano-ribbon field-effect transistors using monte carlo simulations and standard cell library characterization.” 2014. Web. 07 Apr 2020.

Vancouver:

Sangai A. Circuit level delay and power analysis of graphene nano-ribbon field-effect transistors using monte carlo simulations and standard cell library characterization. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2014. [cited 2020 Apr 07]. Available from: http://hdl.handle.net/2142/46893.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sangai A. Circuit level delay and power analysis of graphene nano-ribbon field-effect transistors using monte carlo simulations and standard cell library characterization. [Thesis]. University of Illinois – Urbana-Champaign; 2014. Available from: http://hdl.handle.net/2142/46893

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

3. Liang, Yi. Fast optimal power flow analysis for large-scale smart grid.

Degree: MS, 1200, 2014, University of Illinois – Urbana-Champaign

 Optimal power flow OPF plays an important role in power system operation. The emerging smart grid aims to create an automated energy delivery system that… (more)

Subjects/Keywords: Smart Grid; Power System; Network Reduction; Optimal Power Flow

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APA (6th Edition):

Liang, Y. (2014). Fast optimal power flow analysis for large-scale smart grid. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/46937

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Liang, Yi. “Fast optimal power flow analysis for large-scale smart grid.” 2014. Thesis, University of Illinois – Urbana-Champaign. Accessed April 07, 2020. http://hdl.handle.net/2142/46937.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Liang, Yi. “Fast optimal power flow analysis for large-scale smart grid.” 2014. Web. 07 Apr 2020.

Vancouver:

Liang Y. Fast optimal power flow analysis for large-scale smart grid. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2014. [cited 2020 Apr 07]. Available from: http://hdl.handle.net/2142/46937.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Liang Y. Fast optimal power flow analysis for large-scale smart grid. [Thesis]. University of Illinois – Urbana-Champaign; 2014. Available from: http://hdl.handle.net/2142/46937

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

4. He, Di. Accelerating lattice scoring of automatic speech recognition through acoustic pre-pruning on GPU.

Degree: MS, 1200, 2015, University of Illinois – Urbana-Champaign

 This thesis introduces an acoustic pre-pruning algorithm that speeds up lattice scoring for GMM based ASR systems, and a constrained agglomerative clustering algorithm that makes… (more)

Subjects/Keywords: acoustic pre-pruning; lattice scoring; Gaussian mixture model (GMM); graphic processing unit (GPU)

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APA (6th Edition):

He, D. (2015). Accelerating lattice scoring of automatic speech recognition through acoustic pre-pruning on GPU. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/73019

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

He, Di. “Accelerating lattice scoring of automatic speech recognition through acoustic pre-pruning on GPU.” 2015. Thesis, University of Illinois – Urbana-Champaign. Accessed April 07, 2020. http://hdl.handle.net/2142/73019.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

He, Di. “Accelerating lattice scoring of automatic speech recognition through acoustic pre-pruning on GPU.” 2015. Web. 07 Apr 2020.

Vancouver:

He D. Accelerating lattice scoring of automatic speech recognition through acoustic pre-pruning on GPU. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2015. [cited 2020 Apr 07]. Available from: http://hdl.handle.net/2142/73019.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

He D. Accelerating lattice scoring of automatic speech recognition through acoustic pre-pruning on GPU. [Thesis]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/73019

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

5. Dhar, Ashutosh. The case for reconfigurable general purpose GPU computing.

Degree: MS, 1200, 2015, University of Illinois – Urbana-Champaign

 General purpose graphics processing unit (GPU) computing (GPGPU) has emerged as a new paradigm for programmers to exploit massive amounts of parallelism for relatively low… (more)

Subjects/Keywords: Graphics Processing Unit (GPU); General Purpose Graphics Processing Unit (GPGPU); Reconfigurable Computing; Architecture; Compute Unified Device Architecture (CUDA)

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APA (6th Edition):

Dhar, A. (2015). The case for reconfigurable general purpose GPU computing. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/73103

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Dhar, Ashutosh. “The case for reconfigurable general purpose GPU computing.” 2015. Thesis, University of Illinois – Urbana-Champaign. Accessed April 07, 2020. http://hdl.handle.net/2142/73103.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Dhar, Ashutosh. “The case for reconfigurable general purpose GPU computing.” 2015. Web. 07 Apr 2020.

Vancouver:

Dhar A. The case for reconfigurable general purpose GPU computing. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2015. [cited 2020 Apr 07]. Available from: http://hdl.handle.net/2142/73103.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Dhar A. The case for reconfigurable general purpose GPU computing. [Thesis]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/73103

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

6. Wei, Chunan. New PCM based FPGA architecture and graphene memory cell design.

Degree: MS, 1200, 2014, University of Illinois – Urbana-Champaign

 In this work, we introduce a new look-up table (LUT) implementation using phase change memory (PCM) cells. Utilizing the fact that PCM cells store data… (more)

Subjects/Keywords: Phase change memory (PCM); Graphene; Field-Programmable Gate Array (FPGA); Memory; Lookup table (LUT)

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APA (6th Edition):

Wei, C. (2014). New PCM based FPGA architecture and graphene memory cell design. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/49715

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wei, Chunan. “New PCM based FPGA architecture and graphene memory cell design.” 2014. Thesis, University of Illinois – Urbana-Champaign. Accessed April 07, 2020. http://hdl.handle.net/2142/49715.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wei, Chunan. “New PCM based FPGA architecture and graphene memory cell design.” 2014. Web. 07 Apr 2020.

Vancouver:

Wei C. New PCM based FPGA architecture and graphene memory cell design. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2014. [cited 2020 Apr 07]. Available from: http://hdl.handle.net/2142/49715.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wei C. New PCM based FPGA architecture and graphene memory cell design. [Thesis]. University of Illinois – Urbana-Champaign; 2014. Available from: http://hdl.handle.net/2142/49715

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

7. Sun, Zelei. VAST-LP: clock gating in high-level synthesis.

Degree: MS, Electrical & Computer Engr, 2016, University of Illinois – Urbana-Champaign

 High-level synthesis (HLS) promises high-quality hardware with minimal develop- ment e ort. In this thesis, we evaluate the current state-of-the-art HLS engine VAST and propose… (more)

Subjects/Keywords: low power; high level synthesis

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APA (6th Edition):

Sun, Z. (2016). VAST-LP: clock gating in high-level synthesis. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/90970

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sun, Zelei. “VAST-LP: clock gating in high-level synthesis.” 2016. Thesis, University of Illinois – Urbana-Champaign. Accessed April 07, 2020. http://hdl.handle.net/2142/90970.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sun, Zelei. “VAST-LP: clock gating in high-level synthesis.” 2016. Web. 07 Apr 2020.

Vancouver:

Sun Z. VAST-LP: clock gating in high-level synthesis. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2016. [cited 2020 Apr 07]. Available from: http://hdl.handle.net/2142/90970.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sun Z. VAST-LP: clock gating in high-level synthesis. [Thesis]. University of Illinois – Urbana-Champaign; 2016. Available from: http://hdl.handle.net/2142/90970

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

8. Yan, Yan. Efficient parallelization of Bowtie 2 with OpenCL on GPU.

Degree: MS, Electrical & Computer Engr, 2016, University of Illinois – Urbana-Champaign

 As a crucial and computation-intensive aspect in bioinformatics, sequence alignment has gained considerable attention from researchers and developers. Among all the sequence aligners, Bowtie 2… (more)

Subjects/Keywords: OpenCL; Bowtie 2; Sequence Aligner; Smith-Waterman

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APA (6th Edition):

Yan, Y. (2016). Efficient parallelization of Bowtie 2 with OpenCL on GPU. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/92977

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yan, Yan. “Efficient parallelization of Bowtie 2 with OpenCL on GPU.” 2016. Thesis, University of Illinois – Urbana-Champaign. Accessed April 07, 2020. http://hdl.handle.net/2142/92977.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yan, Yan. “Efficient parallelization of Bowtie 2 with OpenCL on GPU.” 2016. Web. 07 Apr 2020.

Vancouver:

Yan Y. Efficient parallelization of Bowtie 2 with OpenCL on GPU. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2016. [cited 2020 Apr 07]. Available from: http://hdl.handle.net/2142/92977.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yan Y. Efficient parallelization of Bowtie 2 with OpenCL on GPU. [Thesis]. University of Illinois – Urbana-Champaign; 2016. Available from: http://hdl.handle.net/2142/92977

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

9. Zuo, Wei. A polyhedral-based systemc modeling and generation framework for effective low-power design space exploration.

Degree: MS, Electrical & Computer Engr, 2016, University of Illinois – Urbana-Champaign

 With the prevalence of systems-on-chips there is a growing need for automation and acceleration of the design process. A classical approach is to take a… (more)

Subjects/Keywords: SoC design space exploration; polyhedral model

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APA (6th Edition):

Zuo, W. (2016). A polyhedral-based systemc modeling and generation framework for effective low-power design space exploration. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/95498

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Zuo, Wei. “A polyhedral-based systemc modeling and generation framework for effective low-power design space exploration.” 2016. Thesis, University of Illinois – Urbana-Champaign. Accessed April 07, 2020. http://hdl.handle.net/2142/95498.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Zuo, Wei. “A polyhedral-based systemc modeling and generation framework for effective low-power design space exploration.” 2016. Web. 07 Apr 2020.

Vancouver:

Zuo W. A polyhedral-based systemc modeling and generation framework for effective low-power design space exploration. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2016. [cited 2020 Apr 07]. Available from: http://hdl.handle.net/2142/95498.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zuo W. A polyhedral-based systemc modeling and generation framework for effective low-power design space exploration. [Thesis]. University of Illinois – Urbana-Champaign; 2016. Available from: http://hdl.handle.net/2142/95498

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

10. Chen, Daniel E. FPGA acceleration of short read alignment with high-level synthesis.

Degree: MS, Electrical and Computer Engineering, 2017, University of Illinois – Urbana-Champaign

 With the introduction of next-generation sequencing (NGS) technologies, DNA sequencing is becoming an increasingly widespread process. When performed on human patients, it can allow for… (more)

Subjects/Keywords: Field-programmable gate array (FPGA); Hardware acceleration; High-level synthesis; OpenCL; Short read alignment

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APA (6th Edition):

Chen, D. E. (2017). FPGA acceleration of short read alignment with high-level synthesis. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/97641

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chen, Daniel E. “FPGA acceleration of short read alignment with high-level synthesis.” 2017. Thesis, University of Illinois – Urbana-Champaign. Accessed April 07, 2020. http://hdl.handle.net/2142/97641.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chen, Daniel E. “FPGA acceleration of short read alignment with high-level synthesis.” 2017. Web. 07 Apr 2020.

Vancouver:

Chen DE. FPGA acceleration of short read alignment with high-level synthesis. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2017. [cited 2020 Apr 07]. Available from: http://hdl.handle.net/2142/97641.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen DE. FPGA acceleration of short read alignment with high-level synthesis. [Thesis]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/97641

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

11. Manikandan, Gowthami Jayashri. Comprehensive evaluation of error correction methods for high-throughput sequencing data.

Degree: MS, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign

 The advent of DNA and RNA sequencing has significantly revolutionized the study of genomics and molecular biology. Development of high-throughput sequencing technologies have brought about… (more)

Subjects/Keywords: Computational genomics; Algorithms; Parallel computing

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APA (6th Edition):

Manikandan, G. J. (2017). Comprehensive evaluation of error correction methods for high-throughput sequencing data. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/97787

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Manikandan, Gowthami Jayashri. “Comprehensive evaluation of error correction methods for high-throughput sequencing data.” 2017. Thesis, University of Illinois – Urbana-Champaign. Accessed April 07, 2020. http://hdl.handle.net/2142/97787.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Manikandan, Gowthami Jayashri. “Comprehensive evaluation of error correction methods for high-throughput sequencing data.” 2017. Web. 07 Apr 2020.

Vancouver:

Manikandan GJ. Comprehensive evaluation of error correction methods for high-throughput sequencing data. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2017. [cited 2020 Apr 07]. Available from: http://hdl.handle.net/2142/97787.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Manikandan GJ. Comprehensive evaluation of error correction methods for high-throughput sequencing data. [Thesis]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/97787

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

12. Xu, Zhangqi. FCUDA: Efficient high-level automation CUDA-to-FPGA compilation.

Degree: MS, Electrical and Computer Engineering, 2017, University of Illinois – Urbana-Champaign

 The demand for high-performance computing has been growing significantly in the past decade. The bottleneck of Moore's law and the increasing power consumption in the… (more)

Subjects/Keywords: Field programmable gate array (FPGA); High-level synthesis (HLS); Compute unified device architecture (CUDA)

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APA (6th Edition):

Xu, Z. (2017). FCUDA: Efficient high-level automation CUDA-to-FPGA compilation. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/99536

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Xu, Zhangqi. “FCUDA: Efficient high-level automation CUDA-to-FPGA compilation.” 2017. Thesis, University of Illinois – Urbana-Champaign. Accessed April 07, 2020. http://hdl.handle.net/2142/99536.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Xu, Zhangqi. “FCUDA: Efficient high-level automation CUDA-to-FPGA compilation.” 2017. Web. 07 Apr 2020.

Vancouver:

Xu Z. FCUDA: Efficient high-level automation CUDA-to-FPGA compilation. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2017. [cited 2020 Apr 07]. Available from: http://hdl.handle.net/2142/99536.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Xu Z. FCUDA: Efficient high-level automation CUDA-to-FPGA compilation. [Thesis]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/99536

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

13. Konigsmark, Sven Tenzing Choden. A system for multi-level authentication with physically unclonable functions.

Degree: MS, 1200, 2014, University of Illinois – Urbana-Champaign

 We analyze deficiencies in existing Physically Unclonable Function (PUF) systems and protocols, and propose a new system of PUFs (SoP) that is numerically secure under… (more)

Subjects/Keywords: Physically Unclonable Functions; Hardware Security

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APA (6th Edition):

Konigsmark, S. T. C. (2014). A system for multi-level authentication with physically unclonable functions. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/46931

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Konigsmark, Sven Tenzing Choden. “A system for multi-level authentication with physically unclonable functions.” 2014. Thesis, University of Illinois – Urbana-Champaign. Accessed April 07, 2020. http://hdl.handle.net/2142/46931.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Konigsmark, Sven Tenzing Choden. “A system for multi-level authentication with physically unclonable functions.” 2014. Web. 07 Apr 2020.

Vancouver:

Konigsmark STC. A system for multi-level authentication with physically unclonable functions. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2014. [cited 2020 Apr 07]. Available from: http://hdl.handle.net/2142/46931.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Konigsmark STC. A system for multi-level authentication with physically unclonable functions. [Thesis]. University of Illinois – Urbana-Champaign; 2014. Available from: http://hdl.handle.net/2142/46931

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

14. Huang, Sitao. Hardware acceleration of the pair HMM algorithm for DNA variant calling.

Degree: MS, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign

 With the advent of several accurate and sophisticated statistical algorithms and pipelines for DNA sequence analysis, it is becoming increasingly possible to translate raw sequencing… (more)

Subjects/Keywords: Hardware acceleration; Field-programmable gate array (FPGA); Forward algorithm; Pair hidden Markov model (HMM); Computational genomics; Processing element (PE) ring

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APA (6th Edition):

Huang, S. (2017). Hardware acceleration of the pair HMM algorithm for DNA variant calling. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/97496

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Huang, Sitao. “Hardware acceleration of the pair HMM algorithm for DNA variant calling.” 2017. Thesis, University of Illinois – Urbana-Champaign. Accessed April 07, 2020. http://hdl.handle.net/2142/97496.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Huang, Sitao. “Hardware acceleration of the pair HMM algorithm for DNA variant calling.” 2017. Web. 07 Apr 2020.

Vancouver:

Huang S. Hardware acceleration of the pair HMM algorithm for DNA variant calling. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2017. [cited 2020 Apr 07]. Available from: http://hdl.handle.net/2142/97496.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Huang S. Hardware acceleration of the pair HMM algorithm for DNA variant calling. [Thesis]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/97496

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

15. Papakonstantinou, Alexandros. High-level automation of custom hardware design for high-performance computing.

Degree: PhD, 1200, 2013, University of Illinois – Urbana-Champaign

 This dissertation focuses on efficient generation of custom processors from high-level language descriptions. Our work exploits compiler-based optimizations and transformations in tandem with high-level synthesis… (more)

Subjects/Keywords: High-level synthesis; Field-Programmable Gate Array (FPGA); CUDA; parallel programming; High Performance Computing (HPC)

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APA (6th Edition):

Papakonstantinou, A. (2013). High-level automation of custom hardware design for high-performance computing. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/42137

Chicago Manual of Style (16th Edition):

Papakonstantinou, Alexandros. “High-level automation of custom hardware design for high-performance computing.” 2013. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed April 07, 2020. http://hdl.handle.net/2142/42137.

MLA Handbook (7th Edition):

Papakonstantinou, Alexandros. “High-level automation of custom hardware design for high-performance computing.” 2013. Web. 07 Apr 2020.

Vancouver:

Papakonstantinou A. High-level automation of custom hardware design for high-performance computing. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2013. [cited 2020 Apr 07]. Available from: http://hdl.handle.net/2142/42137.

Council of Science Editors:

Papakonstantinou A. High-level automation of custom hardware design for high-performance computing. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2013. Available from: http://hdl.handle.net/2142/42137


University of Illinois – Urbana-Champaign

16. Dong, Chen. Architecture and CAD for nanoscale and 3d FPGA.

Degree: PhD, 1200, 2011, University of Illinois – Urbana-Champaign

 FPGAs (field programmable gate arrays) are attractive alternatives compared to ASICs (application-specific integrated circuits) for significantly lowering amortized manufacturing costs and dramatically improving design productivity.… (more)

Subjects/Keywords: Field-Programmable Gate Array (FPGA); Carbon Nanotube; 3D Integration; Computer-aided design (CAD); Physical Design

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APA (6th Edition):

Dong, C. (2011). Architecture and CAD for nanoscale and 3d FPGA. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/18492

Chicago Manual of Style (16th Edition):

Dong, Chen. “Architecture and CAD for nanoscale and 3d FPGA.” 2011. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed April 07, 2020. http://hdl.handle.net/2142/18492.

MLA Handbook (7th Edition):

Dong, Chen. “Architecture and CAD for nanoscale and 3d FPGA.” 2011. Web. 07 Apr 2020.

Vancouver:

Dong C. Architecture and CAD for nanoscale and 3d FPGA. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2011. [cited 2020 Apr 07]. Available from: http://hdl.handle.net/2142/18492.

Council of Science Editors:

Dong C. Architecture and CAD for nanoscale and 3d FPGA. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2011. Available from: http://hdl.handle.net/2142/18492


University of Illinois – Urbana-Champaign

17. Chen, Ying-Yu. Graphene nano-ribbon and transition metal dichalcogenide field-effect transistor modeling and circuit simulation.

Degree: PhD, Electrical & Computer Engr, 2015, University of Illinois – Urbana-Champaign

 This dissertation presents a modeling and simulation study of graphene nano-ribbon and transition metal dichalcogenide field-effect transistors. Through compact modeling, SPICE implementation of the transistors… (more)

Subjects/Keywords: graphene; transition metal dichalcogenide; transistor; flexible transistor; modeling; simulation

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APA (6th Edition):

Chen, Y. (2015). Graphene nano-ribbon and transition metal dichalcogenide field-effect transistor modeling and circuit simulation. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/88212

Chicago Manual of Style (16th Edition):

Chen, Ying-Yu. “Graphene nano-ribbon and transition metal dichalcogenide field-effect transistor modeling and circuit simulation.” 2015. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed April 07, 2020. http://hdl.handle.net/2142/88212.

MLA Handbook (7th Edition):

Chen, Ying-Yu. “Graphene nano-ribbon and transition metal dichalcogenide field-effect transistor modeling and circuit simulation.” 2015. Web. 07 Apr 2020.

Vancouver:

Chen Y. Graphene nano-ribbon and transition metal dichalcogenide field-effect transistor modeling and circuit simulation. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2015. [cited 2020 Apr 07]. Available from: http://hdl.handle.net/2142/88212.

Council of Science Editors:

Chen Y. Graphene nano-ribbon and transition metal dichalcogenide field-effect transistor modeling and circuit simulation. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/88212


University of Illinois – Urbana-Champaign

18. Lin, Chen-Hsuan. Design automation for circuit reliability and energy efficiency.

Degree: PhD, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign

 This dissertation presents approaches to improve circuit reliability and energy efficiency from different angles, such as verification, logic synthesis, and functional unit design. A variety… (more)

Subjects/Keywords: Electronic design automation; Reliability; Energy efficiency; Data mining; Satisfiability (SAT) solving; Logic restructuring; Assertion; Negative bias temperature instability (NBTI) effect; Modulo arithmetic; Shadow datapath

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APA (6th Edition):

Lin, C. (2017). Design automation for circuit reliability and energy efficiency. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/99237

Chicago Manual of Style (16th Edition):

Lin, Chen-Hsuan. “Design automation for circuit reliability and energy efficiency.” 2017. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed April 07, 2020. http://hdl.handle.net/2142/99237.

MLA Handbook (7th Edition):

Lin, Chen-Hsuan. “Design automation for circuit reliability and energy efficiency.” 2017. Web. 07 Apr 2020.

Vancouver:

Lin C. Design automation for circuit reliability and energy efficiency. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2017. [cited 2020 Apr 07]. Available from: http://hdl.handle.net/2142/99237.

Council of Science Editors:

Lin C. Design automation for circuit reliability and energy efficiency. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/99237


University of Illinois – Urbana-Champaign

19. Lee, Seungchul. Digital calibration of nonlinear memory errors in sigma-delta ADCs.

Degree: PhD, 1200, 2012, University of Illinois – Urbana-Champaign

 Background digital calibration techniques based on an output-referred error model are proposed to linearize sigma-delta (ΣΔ) modulators. A sequential power series (a special form of… (more)

Subjects/Keywords: Analog-to-digital converter; ΣΔ modulator; low gain amplifier; nonlinear distortion; memory error; quantization noise leakage; digital calibration; correlation; test signal; digital-to-analog converter; capacitor mismatch; piecewise linear model; independent component analysis; multi-stage delta-sigma (MASH) structure

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APA (6th Edition):

Lee, S. (2012). Digital calibration of nonlinear memory errors in sigma-delta ADCs. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/34543

Chicago Manual of Style (16th Edition):

Lee, Seungchul. “Digital calibration of nonlinear memory errors in sigma-delta ADCs.” 2012. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed April 07, 2020. http://hdl.handle.net/2142/34543.

MLA Handbook (7th Edition):

Lee, Seungchul. “Digital calibration of nonlinear memory errors in sigma-delta ADCs.” 2012. Web. 07 Apr 2020.

Vancouver:

Lee S. Digital calibration of nonlinear memory errors in sigma-delta ADCs. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2012. [cited 2020 Apr 07]. Available from: http://hdl.handle.net/2142/34543.

Council of Science Editors:

Lee S. Digital calibration of nonlinear memory errors in sigma-delta ADCs. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2012. Available from: http://hdl.handle.net/2142/34543


University of Illinois – Urbana-Champaign

20. Ma, Qiang. Routing algorithms for electronic design automation.

Degree: PhD, 1200, 2013, University of Illinois – Urbana-Champaign

 In electronic design automation (EDA), routing is one of the most important tasks for both printed circuit boards (PCB) and integration circuits (IC). After placement,… (more)

Subjects/Keywords: Routing; Algorithm; Electronic Design Automation

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APA (6th Edition):

Ma, Q. (2013). Routing algorithms for electronic design automation. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/42184

Chicago Manual of Style (16th Edition):

Ma, Qiang. “Routing algorithms for electronic design automation.” 2013. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed April 07, 2020. http://hdl.handle.net/2142/42184.

MLA Handbook (7th Edition):

Ma, Qiang. “Routing algorithms for electronic design automation.” 2013. Web. 07 Apr 2020.

Vancouver:

Ma Q. Routing algorithms for electronic design automation. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2013. [cited 2020 Apr 07]. Available from: http://hdl.handle.net/2142/42184.

Council of Science Editors:

Ma Q. Routing algorithms for electronic design automation. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2013. Available from: http://hdl.handle.net/2142/42184


University of Illinois – Urbana-Champaign

21. Kelm, John H. Hybrid coherence for scalable multicore architectures.

Degree: PhD, 1200, 2011, University of Illinois – Urbana-Champaign

 This work describes a cache architecture and memory model for 1000+ core microprocessors. Our approach exploits workload characteristics and programming model assumptions to build a… (more)

Subjects/Keywords: Accelerator architecture; hybrid architectures; memory model; cache coherence

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APA (6th Edition):

Kelm, J. H. (2011). Hybrid coherence for scalable multicore architectures. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/18272

Chicago Manual of Style (16th Edition):

Kelm, John H. “Hybrid coherence for scalable multicore architectures.” 2011. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed April 07, 2020. http://hdl.handle.net/2142/18272.

MLA Handbook (7th Edition):

Kelm, John H. “Hybrid coherence for scalable multicore architectures.” 2011. Web. 07 Apr 2020.

Vancouver:

Kelm JH. Hybrid coherence for scalable multicore architectures. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2011. [cited 2020 Apr 07]. Available from: http://hdl.handle.net/2142/18272.

Council of Science Editors:

Kelm JH. Hybrid coherence for scalable multicore architectures. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2011. Available from: http://hdl.handle.net/2142/18272


University of Illinois – Urbana-Champaign

22. Kim, Eric. Statistical error compensation for robust digital signal processing and machine learning.

Degree: PhD, 1200, 2015, University of Illinois – Urbana-Champaign

 Machine learning (ML) based inference has recently gained importance as a key kernel in processing massive data in digital signal processing (DSP) systems. Due to… (more)

Subjects/Keywords: statistical error compensation; low power design; error resiliency; machine learning; digital signal processing

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APA (6th Edition):

Kim, E. (2015). Statistical error compensation for robust digital signal processing and machine learning. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/72955

Chicago Manual of Style (16th Edition):

Kim, Eric. “Statistical error compensation for robust digital signal processing and machine learning.” 2015. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed April 07, 2020. http://hdl.handle.net/2142/72955.

MLA Handbook (7th Edition):

Kim, Eric. “Statistical error compensation for robust digital signal processing and machine learning.” 2015. Web. 07 Apr 2020.

Vancouver:

Kim E. Statistical error compensation for robust digital signal processing and machine learning. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2015. [cited 2020 Apr 07]. Available from: http://hdl.handle.net/2142/72955.

Council of Science Editors:

Kim E. Statistical error compensation for robust digital signal processing and machine learning. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/72955


University of Illinois – Urbana-Champaign

23. Johnson, Matthew Robert. Fast, accurate power measurement and optimization for microprocessor platforms.

Degree: PhD, Electrical & Computer Engr, 2015, University of Illinois – Urbana-Champaign

 Power and energy consumption have become important for all computers, but the tools used to measure and optimize power on physical hardware lag far behind… (more)

Subjects/Keywords: Power measurement; Current measurement; Energy efficiency; Software optimization; Field-Programmable Gate Array (FPGA); Power optimization

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APA (6th Edition):

Johnson, M. R. (2015). Fast, accurate power measurement and optimization for microprocessor platforms. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/78785

Chicago Manual of Style (16th Edition):

Johnson, Matthew Robert. “Fast, accurate power measurement and optimization for microprocessor platforms.” 2015. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed April 07, 2020. http://hdl.handle.net/2142/78785.

MLA Handbook (7th Edition):

Johnson, Matthew Robert. “Fast, accurate power measurement and optimization for microprocessor platforms.” 2015. Web. 07 Apr 2020.

Vancouver:

Johnson MR. Fast, accurate power measurement and optimization for microprocessor platforms. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2015. [cited 2020 Apr 07]. Available from: http://hdl.handle.net/2142/78785.

Council of Science Editors:

Johnson MR. Fast, accurate power measurement and optimization for microprocessor platforms. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/78785


University of Illinois – Urbana-Champaign

24. Xiong, Feng. Scaling study of phase change memory using carbon nanotube electrodes.

Degree: PhD, 1200, 2014, University of Illinois – Urbana-Champaign

 Demands for data storage and computer memory are growing exponentially. It is thus essential to find a new scalable, energy-efficient memory technology. We have been… (more)

Subjects/Keywords: Phase change material (PCM); Phase Change Memory; Carbon Nanotube (CNT); Finite Element Model; Resistive Memory; Resistive random access memory (RRAM); Crossbar

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APA (6th Edition):

Xiong, F. (2014). Scaling study of phase change memory using carbon nanotube electrodes. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/49709

Chicago Manual of Style (16th Edition):

Xiong, Feng. “Scaling study of phase change memory using carbon nanotube electrodes.” 2014. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed April 07, 2020. http://hdl.handle.net/2142/49709.

MLA Handbook (7th Edition):

Xiong, Feng. “Scaling study of phase change memory using carbon nanotube electrodes.” 2014. Web. 07 Apr 2020.

Vancouver:

Xiong F. Scaling study of phase change memory using carbon nanotube electrodes. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2014. [cited 2020 Apr 07]. Available from: http://hdl.handle.net/2142/49709.

Council of Science Editors:

Xiong F. Scaling study of phase change memory using carbon nanotube electrodes. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2014. Available from: http://hdl.handle.net/2142/49709


University of Illinois – Urbana-Champaign

25. Choi, Jungwook. High performance and error resilient probabilistic inference system for machine learning.

Degree: PhD, Electrical & Computer Engr, 2015, University of Illinois – Urbana-Champaign

 Many real-world machine learning applications can be considered as inferring the best label assignment of maximum a posteriori probability (MAP) problems. Since these MAP problems… (more)

Subjects/Keywords: Belief Propagation (BP); Field-Programmable Gate Array (FPGA); hybrid-core computing platform; Markov Random Field (MRF); sequential tree-reweighted message passing (TRW-S); stereo matching; Error resilience; message passing; algorithmic noise tolerance

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APA (6th Edition):

Choi, J. (2015). High performance and error resilient probabilistic inference system for machine learning. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/88204

Chicago Manual of Style (16th Edition):

Choi, Jungwook. “High performance and error resilient probabilistic inference system for machine learning.” 2015. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed April 07, 2020. http://hdl.handle.net/2142/88204.

MLA Handbook (7th Edition):

Choi, Jungwook. “High performance and error resilient probabilistic inference system for machine learning.” 2015. Web. 07 Apr 2020.

Vancouver:

Choi J. High performance and error resilient probabilistic inference system for machine learning. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2015. [cited 2020 Apr 07]. Available from: http://hdl.handle.net/2142/88204.

Council of Science Editors:

Choi J. High performance and error resilient probabilistic inference system for machine learning. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/88204


University of Illinois – Urbana-Champaign

26. Kim, Hee-Seok. Compiler and runtime techniques for bulk-synchronous programming models on CPU architectures.

Degree: PhD, Electrical & Computer Engineering, 2015, University of Illinois – Urbana-Champaign

 The rising pressure to simultaneously improve performance and reduce power consumption is driving more heterogeneity into all aspects of computing devices. However, wide adoption of… (more)

Subjects/Keywords: OpenCL; compiler; Central Processing Unit (CPU); performance portability; data locality

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APA (6th Edition):

Kim, H. (2015). Compiler and runtime techniques for bulk-synchronous programming models on CPU architectures. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/88987

Chicago Manual of Style (16th Edition):

Kim, Hee-Seok. “Compiler and runtime techniques for bulk-synchronous programming models on CPU architectures.” 2015. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed April 07, 2020. http://hdl.handle.net/2142/88987.

MLA Handbook (7th Edition):

Kim, Hee-Seok. “Compiler and runtime techniques for bulk-synchronous programming models on CPU architectures.” 2015. Web. 07 Apr 2020.

Vancouver:

Kim H. Compiler and runtime techniques for bulk-synchronous programming models on CPU architectures. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2015. [cited 2020 Apr 07]. Available from: http://hdl.handle.net/2142/88987.

Council of Science Editors:

Kim H. Compiler and runtime techniques for bulk-synchronous programming models on CPU architectures. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/88987


University of Illinois – Urbana-Champaign

27. Xiao, Zigang. Design automation algorithms for advanced lithography.

Degree: PhD, Electrical & Computer Engr, 2015, University of Illinois – Urbana-Champaign

 In circuit manufacturing, as the technology nodes keep shrinking, conventional 193 nm immersion lithography (193i) has reached its printability limit. To continue the scaling with… (more)

Subjects/Keywords: Electronic Design Automation; Compute-aided Design; Lithography; Self-aligned Double Patterning; Directed Self-Assembly; Machine Learning; Design-Technology Co-optimization

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APA (6th Edition):

Xiao, Z. (2015). Design automation algorithms for advanced lithography. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/88991

Chicago Manual of Style (16th Edition):

Xiao, Zigang. “Design automation algorithms for advanced lithography.” 2015. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed April 07, 2020. http://hdl.handle.net/2142/88991.

MLA Handbook (7th Edition):

Xiao, Zigang. “Design automation algorithms for advanced lithography.” 2015. Web. 07 Apr 2020.

Vancouver:

Xiao Z. Design automation algorithms for advanced lithography. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2015. [cited 2020 Apr 07]. Available from: http://hdl.handle.net/2142/88991.

Council of Science Editors:

Xiao Z. Design automation algorithms for advanced lithography. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/88991


University of Illinois – Urbana-Champaign

28. Guo, Daifeng. Algorithms for DFM in electronic design automation.

Degree: PhD, Electrical & Computer Engr, 2019, University of Illinois – Urbana-Champaign

 As the dimension of features in integrated circuits (IC) keeps shrinking to fulfill Moore’s law, the manufacturing process has no choice but confronting the limit… (more)

Subjects/Keywords: Algorithm; Optimization; Design for Manufacturing; Electronic Design Automation; Computer-Aided Design

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APA (6th Edition):

Guo, D. (2019). Algorithms for DFM in electronic design automation. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/104852

Chicago Manual of Style (16th Edition):

Guo, Daifeng. “Algorithms for DFM in electronic design automation.” 2019. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed April 07, 2020. http://hdl.handle.net/2142/104852.

MLA Handbook (7th Edition):

Guo, Daifeng. “Algorithms for DFM in electronic design automation.” 2019. Web. 07 Apr 2020.

Vancouver:

Guo D. Algorithms for DFM in electronic design automation. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2019. [cited 2020 Apr 07]. Available from: http://hdl.handle.net/2142/104852.

Council of Science Editors:

Guo D. Algorithms for DFM in electronic design automation. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2019. Available from: http://hdl.handle.net/2142/104852


University of Illinois – Urbana-Champaign

29. Xu, Ti. Valuing of inertia and fast-acting storage devices in interconnected power grids.

Degree: PhD, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign

 As power systems evolve, integration of renewable energy, lightweight-turbine generators and other electronic devices result in: 1) less inertia and maybe worse primary frequency responses… (more)

Subjects/Keywords: Inertia; Fast-acting storage

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APA (6th Edition):

Xu, T. (2017). Valuing of inertia and fast-acting storage devices in interconnected power grids. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/99176

Chicago Manual of Style (16th Edition):

Xu, Ti. “Valuing of inertia and fast-acting storage devices in interconnected power grids.” 2017. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed April 07, 2020. http://hdl.handle.net/2142/99176.

MLA Handbook (7th Edition):

Xu, Ti. “Valuing of inertia and fast-acting storage devices in interconnected power grids.” 2017. Web. 07 Apr 2020.

Vancouver:

Xu T. Valuing of inertia and fast-acting storage devices in interconnected power grids. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2017. [cited 2020 Apr 07]. Available from: http://hdl.handle.net/2142/99176.

Council of Science Editors:

Xu T. Valuing of inertia and fast-acting storage devices in interconnected power grids. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/99176


University of Illinois – Urbana-Champaign

30. Crago, Neal. Energy-efficient latency tolerance for 1000-core data parallel processors with decoupled strands.

Degree: PhD, 1200, 2012, University of Illinois – Urbana-Champaign

 This dissertation presents a novel decoupled latency tolerance technique for 1000-core data parallel processors. The approach focuses on developing instruction latency tolerance to improve performance… (more)

Subjects/Keywords: Parallel Processing; Data-parallel; Graphics processing unit (GPU); General-purpose computing on graphics processing units (GPGPU); manycore; latency tolerance; decoupled architecture; compiler technique; energy-efficiency; power-efficiency; high-performance; low power; low energy

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Crago, N. (2012). Energy-efficient latency tolerance for 1000-core data parallel processors with decoupled strands. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/34589

Chicago Manual of Style (16th Edition):

Crago, Neal. “Energy-efficient latency tolerance for 1000-core data parallel processors with decoupled strands.” 2012. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed April 07, 2020. http://hdl.handle.net/2142/34589.

MLA Handbook (7th Edition):

Crago, Neal. “Energy-efficient latency tolerance for 1000-core data parallel processors with decoupled strands.” 2012. Web. 07 Apr 2020.

Vancouver:

Crago N. Energy-efficient latency tolerance for 1000-core data parallel processors with decoupled strands. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2012. [cited 2020 Apr 07]. Available from: http://hdl.handle.net/2142/34589.

Council of Science Editors:

Crago N. Energy-efficient latency tolerance for 1000-core data parallel processors with decoupled strands. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2012. Available from: http://hdl.handle.net/2142/34589

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