+publisher:"University of Cincinnati" +contributor:("Vemuri, Dr. Ranga")

University of Cincinnati

1. DASASATHYAN, SRINIVASAN. SYNTHESIS OF VIRTUAL PIPELINES ON VIRTEX-BASED FPGAs.

Degree: MS, Engineering : Computer Engineering, 2001, University of Cincinnati

URL: http://rave.ohiolink.edu/etdc/view?acc_num=ucin990618529

► Partially reconfigurable devices have the ability to configure a portion of the device while the remaining portion of the device is still operational. This feature… (more)

▼ Partially reconfigurable devices have the ability to configure a portion of the device while the remaining portion of the device is still operational. This feature can be used to improve the performance of a pipelined design by overlapping the reconfiguration of a stage with the execution of previous stages. The above technique is called pipeline reconfiguration. By configuring pipeline stages one every clock cycle the constraint on the design size can be eliminated.This technique virtualizes the hardware and allows designs of any size to execute on finite sized devices. Virtual Pipelining uses pipeline reconfiguration and hardware virtualization to improve the performance of the design. This thesis presents a design flow for automatically synthesizing Virtual Pipelines on Virtex based FPGAs in order to improve the performance of a pipelined design. The input specification is a data flow graph with various arithmetic and logic operations. The input pipelined specification is split into a number of partial designs, each representing the status of the device during every clock cycle. While generating the partial designs, placement and mapping constraints are inserted into the design so that the design is placed column wise on the Virtex chip. The placement of the design is done so that it aids in the generation of partial bit-streams. In order to configure an individual pipeline stages, we developed a flow to generate partial bit-streams for pipeline stages. The flow uses guided place and route along with the JBits API to generate partial bit-streams. To control the flow of data, in and out of the pipeline stages, we presented a data flow controller that routes the data to and from the memory. And finally, to synchronize the reconfiguration and execution of the design, we presented a host controller to synchronize reconfiguration and execution of pipeline stages. To show the effectiveness of Virtual Pipelining, we executed our designs on the SLAAC-1V board. The results of our experiments indicated that there is a gain in throughput when a design is Virtually Pipelined when compared to the non-pipelined version. The gain in throughput is due to partial reconfiguration and pipelining. When the number of stages in the design is less than the number of stages that a device can fit, reconfiguration is not needed every clock cycle and hence the throughput gain is only due to increase in clock frequency because of pipelining. Advisors/Committee Members: Vemuri, Dr. Ranga (Advisor).

Subjects/Keywords: partial reconfiguration; virtex based board; virtual pipeline; JHDL; SBLOX (serial blocks)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

DASASATHYAN, S. (2001). SYNTHESIS OF VIRTUAL PIPELINES ON VIRTEX-BASED FPGAs. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin990618529

Chicago Manual of Style (16^th Edition):

DASASATHYAN, SRINIVASAN. “SYNTHESIS OF VIRTUAL PIPELINES ON VIRTEX-BASED FPGAs.” 2001. Masters Thesis, University of Cincinnati. Accessed January 27, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin990618529.

MLA Handbook (7^th Edition):

DASASATHYAN, SRINIVASAN. “SYNTHESIS OF VIRTUAL PIPELINES ON VIRTEX-BASED FPGAs.” 2001. Web. 27 Jan 2021.

Vancouver:

DASASATHYAN S. SYNTHESIS OF VIRTUAL PIPELINES ON VIRTEX-BASED FPGAs. [Internet] [Masters thesis]. University of Cincinnati; 2001. [cited 2021 Jan 27]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin990618529.

Council of Science Editors:

DASASATHYAN S. SYNTHESIS OF VIRTUAL PIPELINES ON VIRTEX-BASED FPGAs. [Masters Thesis]. University of Cincinnati; 2001. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin990618529

University of Cincinnati

2. YELAMANCHILI, VEENA RAO. A SIMULATION AND PERFORMANCE ESTIMATION SYSTEM FOR ANALOG AND MIXED SIGNAL SYSTEMS.

Degree: MS, Engineering : Computer Engineering, 2003, University of Cincinnati

URL: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1068671449

► High performance analog/mixed signal systems play a wide role in signal acquisition and conditioning for front and back end designs. Circuit designers have been developing… (more)

▼ High performance analog/mixed signal systems play a wide role in signal acquisition and conditioning for front and back end designs. Circuit designers have been developing many such systems using various synthesis flows. The ultimate goal of any synthesis flow is to determine the optimal design implementation that can satisfy the system behavior and constraints. To achieve this objective, components of a circuit are assigned dimensions and, tested for ambiance dependent conditions. The quality of mixed signal systems is quantified by performance parameters like gain, cmrr, unitygain etc. Most of the evaluation strategies depend on the results produced by simulators. Hence, one approach for validation for performance parameters is to repeat the testing procedure across multiple simulators. However, due to the differences among simulators and their data representation, the user needs to develop simulator specific evaluation techniques. This process is time consuming and redundant. An attempt to minimize the issues of multiple simulators and create a unified approach to develop evaluation techniques is the primary objective in design of Performance Analysis System (PAS). PAS is developed to analyze and evaluate various performance parameters of analog and mixed-signal circuits. A Circuit Definition file is defined in VS format and contains details about circuit components. A Parameter file, also written in VS format, contains the analysis conditoins needed to obtain simulation data for the evaluation of the performance parameters. The Circuit Definition file and Parameter file are inputs to a Virtual Simulator which is an abstract simulation tool that maps into one of the four simulators, Ngspice, Spectre, Hspice or Macro modeler, and outputs the post analysis simulation data. The raw simulation data that is obtained is given as input to a three layered data storage system. To access this data, a set of Access functions are developed and made available to the user. These functions aid a designer in obtaining any information needed from the simulation data. Using the Access functions, a analog model library is developed that includes models for performance parameters. PAS is further extended to include a layout generator to generate circuit with parasitics prior to simulations. PAS handles circuits of all sizes and evaluates any number of performance parameters at once. PAS is tested extensively on a set of benchmarks using each of the integrated simulators and the results indicate that the performance models developed are accurate and are evaluated with less execution time. Advisors/Committee Members: Vemuri, Dr. Ranga (Advisor).

Subjects/Keywords: simulations; performance parameters; analog; circuits; analysis &; testing

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

YELAMANCHILI, V. R. (2003). A SIMULATION AND PERFORMANCE ESTIMATION SYSTEM FOR ANALOG AND MIXED SIGNAL SYSTEMS. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1068671449

Chicago Manual of Style (16^th Edition):

YELAMANCHILI, VEENA RAO. “A SIMULATION AND PERFORMANCE ESTIMATION SYSTEM FOR ANALOG AND MIXED SIGNAL SYSTEMS.” 2003. Masters Thesis, University of Cincinnati. Accessed January 27, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1068671449.

MLA Handbook (7^th Edition):

YELAMANCHILI, VEENA RAO. “A SIMULATION AND PERFORMANCE ESTIMATION SYSTEM FOR ANALOG AND MIXED SIGNAL SYSTEMS.” 2003. Web. 27 Jan 2021.

Vancouver:

YELAMANCHILI VR. A SIMULATION AND PERFORMANCE ESTIMATION SYSTEM FOR ANALOG AND MIXED SIGNAL SYSTEMS. [Internet] [Masters thesis]. University of Cincinnati; 2003. [cited 2021 Jan 27]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1068671449.

Council of Science Editors:

YELAMANCHILI VR. A SIMULATION AND PERFORMANCE ESTIMATION SYSTEM FOR ANALOG AND MIXED SIGNAL SYSTEMS. [Masters Thesis]. University of Cincinnati; 2003. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1068671449

University of Cincinnati

3. BHADURI, AMITAVA. INDUCTIVE AND CAPACITIVE AWARE METHODOLOGIES FOR PHYSICAL AND CIRCUIT SYNTHESIS OF HIGH-SPEED DIGITAL AND RF CIRCUITS.

Degree: PhD, Engineering : Computer Science and Engineering, 2005, University of Cincinnati

URL: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1129580425

► Computer-aided design in VLSI is a continuously evolving subject, with new algorithms and solutions constantly modifying the established norms in order to accommodate efficient strategies… (more)

▼ Computer-aided design in VLSI is a continuously evolving subject, with new algorithms and solutions constantly modifying the established norms in order to accommodate efficient strategies to make CAD principles strong at an early phase of design abstraction. The same principle also applies to the routing phase in the physical design of VLSI circuits. There have been several attempts to innovate novel routing methodologies and make it parasitic aware. This awareness in the routing paradigm is important in high-frequency designs, since inductive and capacitive crosstalk that often proved to be crucial in the performance of digital and analog circuits were ignored in previous design attempts. We added an important flavor to make the interconnect-centric routing more meaningful. Realizing the importance of self and mutual inductance and coupling capacitance between neighboring wires, we introduced a routing approach based on higher order moment metrics, which captures the inductive and capacitive parasitics to form a cost function comprising of a mathematical expression. Minimizing the cost allowed us not only to obtain routes that are inductive and capacitive aware but also that produced the least ringing and delay during signal propagation. To make the route cost function even more robust and efficient, we introduced a concept of parasitic transformation on the universal RLC template required by the moment-driven cost function. Besides making the routing technique parasitic-aware, we also made the routing methodology suited towards faster convergence, in line with the requirement of an efficient CAD tool. A constraint-driven non-linear algorithm that satisfies the design rule requirements in addition to minimizing the moment-driven cost function using non-linear algorithm, has been developed to serve this purpose. Layout inclusive synthesis strategies have been present in the domain of Analog and RF synthesis for quite some time. Introducing capacitive and on-chip inductor parasitics helped to bring the parasitic awareness during synthesis and prevented the expensive re-design loop between fabrication and design specification from happening. In order to give the synthesis technique a new dimension and a more refined approach, we implemented a quasi-static extraction strategy in order to extract the resistive, self and mutual inductive parasitics of on-chip inductors and interconnects, within the synthesis flow. Previous attempts, which were ignorant of complete self and mutual inductive and capacitive parasitics of on-chip inductors and interconnects, benefited from this full parasitic extraction technique, thereby giving a fruitful closure to RF circuit synthesis by making the design layout-aware. We also extended the moment-driven routing methodology to the RF circuit synthesis domain, in order to make the routing process at the layout inclusion stage intelligent in terms of parasitic awareness, and efficient, by not transferring the burden of bad routing decisions to the synthesis engine. Coupled with this idea… Advisors/Committee Members: VEMURI, Dr. RANGA (Advisor).

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

BHADURI, A. (2005). INDUCTIVE AND CAPACITIVE AWARE METHODOLOGIES FOR PHYSICAL AND CIRCUIT SYNTHESIS OF HIGH-SPEED DIGITAL AND RF CIRCUITS. (Doctoral Dissertation). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1129580425

Chicago Manual of Style (16^th Edition):

BHADURI, AMITAVA. “INDUCTIVE AND CAPACITIVE AWARE METHODOLOGIES FOR PHYSICAL AND CIRCUIT SYNTHESIS OF HIGH-SPEED DIGITAL AND RF CIRCUITS.” 2005. Doctoral Dissertation, University of Cincinnati. Accessed January 27, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1129580425.

MLA Handbook (7^th Edition):

BHADURI, AMITAVA. “INDUCTIVE AND CAPACITIVE AWARE METHODOLOGIES FOR PHYSICAL AND CIRCUIT SYNTHESIS OF HIGH-SPEED DIGITAL AND RF CIRCUITS.” 2005. Web. 27 Jan 2021.

Vancouver:

BHADURI A. INDUCTIVE AND CAPACITIVE AWARE METHODOLOGIES FOR PHYSICAL AND CIRCUIT SYNTHESIS OF HIGH-SPEED DIGITAL AND RF CIRCUITS. [Internet] [Doctoral dissertation]. University of Cincinnati; 2005. [cited 2021 Jan 27]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1129580425.

Council of Science Editors:

BHADURI A. INDUCTIVE AND CAPACITIVE AWARE METHODOLOGIES FOR PHYSICAL AND CIRCUIT SYNTHESIS OF HIGH-SPEED DIGITAL AND RF CIRCUITS. [Doctoral Dissertation]. University of Cincinnati; 2005. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1129580425

University of Cincinnati

4. RANJAN, MUKESH. AUTOMATED LAYOUT-INCLUSIVE SYNTHESIS OF ANALOG CIRCUITS USING SYMBOLIC PERFORMANCE MODELS.

Degree: PhD, Engineering : Computer Science and Engineering, 2005, University of Cincinnati

URL: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1129922496

► A key task in the automated design of analog/RF circuits is circuit sizing, a process that involves assigning numerical values to unknown circuit parameters of… (more)

▼ A key task in the automated design of analog/RF circuits is circuit sizing, a process that involves assigning numerical values to unknown circuit parameters of a fixed topology, while being subjected to a set of performance constraints. Over the years, the terms sizing and synthesis have been used interchangeably, and have become synonymous in the analog domain. Mature tools for the synthesis of digital circuits are abundant, but the market for analog synthesis tools is still growing and very few commercial products exist. Several techniques have been developed in the past for analog synthesis, ranging from knowledge-based methods to techniques using numerical simulation. A frequently used technique involves an iterative stochastic search, which uses numerical simulations at every probable design point, in order to obtain the performance metrics. Expensive computations and parasitics unawareness of this traditional method necessitates a scheme which can produce fast layout aware designs. In this dissertation a new synthesis methodology, which uses parameterized layout generators and symbolic performance models (SPMs) inside the synthesis loop, has been developed to overcome the deficiencies of the previous circuit sizing method. This layout-inclusive (layout-in-loop) approach uses efficient parameterized procedural layout generators, obtained using the module specification language (MSL) system, for speedy layout instantiation. Fast performance estimation is achieved by using pre-compiled SPMs, which are symbolic representation of circuit performances, obtained using symbolic analysis. The transfer functions of SPMs are stored as efficient symbolic graphs called element-coefficient diagrams (ECDs). Techniques to include layout geometry effects in the SPMs have also been developed. This method is used for the synthesis of op-amps and filters. The method proposed above for analog circuits is then applied to the synthesis of an RF low-noise amplifier (LNA). This method also uses symbolic performance models (SPMs), and parameterized layout generator along with high-frequency extraction techniques in the synthesis loop. SPMs for noise figure and distortion parameters are developed using repetitive and weakly nonlinear symbolic analysis and are stored as pre-compiled ECDs. Full parasitic extraction is done by using multiple extractors. Quasi-static extraction is used to obtain the critical parasitic effects of interconnects and on-chip inductors. Further in the dissertation, efforts are made to overcome the shortcomings of the proposed method. The first limitation is the size of circuits that can be synthesized. It arises because of the limit on the size of ECD-code that can be compiled by a standard GNU C++ compiler. To overcome this bottleneck, a new comprehensive method and framework for exact symbolic analysis of large analog circuits is developed. The method is based on the concepts of hierarchical circuit decomposition, subcircuit symbolic analysis and transfer function synthesis. Node tearing methods have been used… Advisors/Committee Members: Vemuri, Dr. Ranga (Advisor).

Subjects/Keywords: Computer Science; Analog Circuit Synthesis; Symbolic Analysis; Layout-Aware; Parasitic-Aware; Analog Design

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

RANJAN, M. (2005). AUTOMATED LAYOUT-INCLUSIVE SYNTHESIS OF ANALOG CIRCUITS USING SYMBOLIC PERFORMANCE MODELS. (Doctoral Dissertation). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1129922496

Chicago Manual of Style (16^th Edition):

RANJAN, MUKESH. “AUTOMATED LAYOUT-INCLUSIVE SYNTHESIS OF ANALOG CIRCUITS USING SYMBOLIC PERFORMANCE MODELS.” 2005. Doctoral Dissertation, University of Cincinnati. Accessed January 27, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1129922496.

MLA Handbook (7^th Edition):

RANJAN, MUKESH. “AUTOMATED LAYOUT-INCLUSIVE SYNTHESIS OF ANALOG CIRCUITS USING SYMBOLIC PERFORMANCE MODELS.” 2005. Web. 27 Jan 2021.

Vancouver:

RANJAN M. AUTOMATED LAYOUT-INCLUSIVE SYNTHESIS OF ANALOG CIRCUITS USING SYMBOLIC PERFORMANCE MODELS. [Internet] [Doctoral dissertation]. University of Cincinnati; 2005. [cited 2021 Jan 27]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1129922496.

Council of Science Editors:

RANJAN M. AUTOMATED LAYOUT-INCLUSIVE SYNTHESIS OF ANALOG CIRCUITS USING SYMBOLIC PERFORMANCE MODELS. [Doctoral Dissertation]. University of Cincinnati; 2005. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1129922496

University of Cincinnati

5. BADAOUI, RAOUL. APPROACHES FOR PARASITIC-INCLUSIVE SYMBOLIC CIRCUIT REPRESENTATION AND EXTRACTION FOR SYNTHESIS.

Degree: PhD, Engineering : Computer Science and Engineering, 2005, University of Cincinnati

URL: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1132193275

► Layout-induced parasitics have significant effects on the behavior of circuits in general and the performance of high-frequency analog ones in particular. To achieve parasite-inclusive performance-closure,… (more)

▼ Layout-induced parasitics have significant effects on the behavior of circuits in general and the performance of high-frequency analog ones in particular. To achieve parasite-inclusive performance-closure, layout-aware circuit synthesis methodologies are beginning to emerge. In layout-in-the-loop synthesis methodologies, performance analysis is based on the generation of a concrete layout for the explored circuit sizes. A parasite-inclusive circuit is extracted from the layout using a standard extractor and is analyzed using a simulator to determine whether the required constraints are met. The purpose of layout generation during the synthesis process is solely to determine the layout-induced effects in terms of device and interconnect parasites in the extracted circuit in order to perform accurate, layout-aware performance analysis. If the parasites could be estimated or determined otherwise, there would be no need for layout generation. Various approaches of estimating parasitics lack the correctness that would only come from examining the layout itself. The proposed approach tries to include the exactness of the layout to be generated without actually generating it. It relies on using pre-generated structures for the specified un-sized circuit; these structures are generated before synthesis, they contain the information that a layout would have provided to a synthesis process if it was to be generated. This information contains extraction specifics for modules, location of modules and routing characteristics. Pre-Layout Extraction: The concept of Pre-Layout Extraction shall be used to cover the extraction specific information of modules present in the circuit. It is achieved using a high-level language MSL (Module Specification Language) for the specification of parameterized, topology-specific circuit extractors. Upon compilation, the MSL program yields an executable module which generates the extracted circuit containing parasitics, passive and active devices when given specific sizes. This is done without ever generating a layout. Multi-Placement Structures: For the placement specification of the layout, Multi-Placement Structures shall be used. The proposed approach aims at retaining the benefits of both optimization-based techniques and layout templates techniques: a fast instantiation time of layout for layout-inclusive synthesis and various placement possibilities for various input sizes. ( No restriction to a single, pre-defined template ). It consists of a one-time generation of a multi-placement structure for a specific unsized circuit. The obtained structure would be used in a layout-inclusive synthesis process in the following manner: It is provided with numerical sizes from a sizing algorithm tool and returns a specific floor-plan for the circuit. For different sizes given, the aim is to have the best floor-plan returned depending on the specified sizes. Multi-Variant Routing: The remaining part of a layout description known as routing shall be handled using the proposed idea of Multi-Variant… Advisors/Committee Members: Vemuri, Dr. Ranga (Advisor).

Subjects/Keywords: vlsi; analog vlsi; routing; placement; extraction; pre-layout extraction

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

BADAOUI, R. (2005). APPROACHES FOR PARASITIC-INCLUSIVE SYMBOLIC CIRCUIT REPRESENTATION AND EXTRACTION FOR SYNTHESIS. (Doctoral Dissertation). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1132193275

Chicago Manual of Style (16^th Edition):

BADAOUI, RAOUL. “APPROACHES FOR PARASITIC-INCLUSIVE SYMBOLIC CIRCUIT REPRESENTATION AND EXTRACTION FOR SYNTHESIS.” 2005. Doctoral Dissertation, University of Cincinnati. Accessed January 27, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1132193275.

MLA Handbook (7^th Edition):

BADAOUI, RAOUL. “APPROACHES FOR PARASITIC-INCLUSIVE SYMBOLIC CIRCUIT REPRESENTATION AND EXTRACTION FOR SYNTHESIS.” 2005. Web. 27 Jan 2021.

Vancouver:

BADAOUI R. APPROACHES FOR PARASITIC-INCLUSIVE SYMBOLIC CIRCUIT REPRESENTATION AND EXTRACTION FOR SYNTHESIS. [Internet] [Doctoral dissertation]. University of Cincinnati; 2005. [cited 2021 Jan 27]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1132193275.

Council of Science Editors:

BADAOUI R. APPROACHES FOR PARASITIC-INCLUSIVE SYMBOLIC CIRCUIT REPRESENTATION AND EXTRACTION FOR SYNTHESIS. [Doctoral Dissertation]. University of Cincinnati; 2005. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1132193275

University of Cincinnati

6. AGARWAL, ANURADHA. ALGORITHMS FOR LAYOUT-AWARE AND PERFORMANCE MODEL DRIVEN SYNTHESIS OF ANALOG CIRCUITS.

Degree: PhD, Engineering : Computer Science and Engineering, 2005, University of Cincinnati

URL: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1132259454

► With the ever increasing complexity of integrated circuits and constantly shrinking device sizes, the need to develop entire dystems on chip (SoC) has received a… (more)

▼ With the ever increasing complexity of integrated circuits and constantly shrinking device sizes, the need to develop entire dystems on chip (SoC) has received a significant momentum. With this need,comes the responsibility of bringing about mature computer-aided design (CAD) techniques to handle the complexity of designing such systems. Although mature commercial techniques exist for designing the digital components in a system, design automation for the irreplaceable analog and radio-frequency (RF) circuits in a system remains incipient. Circuit sizing is one of the most important and challenging constituents of any analog design process. Given a set of high-level specifications and a circuit topology, sizing aims to determine the device dimensions and biasing information in order to meet the desired specifications. In this dissertation, we address two major problems ailing the sizing process. One of the most important challenges in analog synthesis is to design a circuit which meets the input specifications at the post-layout stage. The other problem we seek to address in this dissertation is the enormous time spent in sizing due to the overhead of running thousands of simulations for performance estimation. Analog and RF circuits are extremely sensitive to layout parasitics. This extreme dependence of the behavior of analog circuits, on layout-induced parasitics, is responsible for several silicon runs before a functional chip can be designed. We propose two techniques to introduce layout awareness during circuit sizing. The first approach is based on developing fast and accurate models of the layout parasitics. The parasitic capacitance models are used inside a circuit sizing framework to estimate the layout parasitics and account for them in the performance evaluation process. This approach relies on procedural layout generators (PLGs) for developing the parasitic models. The second approach proposed for layout-aware design draws a similarity between layout parasitics and process variables in a yield optimization problem. A two-step approach is proposed for identifying the worst case parasitic corners and for sizing in presence of these parasitics. A parasitic robust design is sought for which passes the post-layout validation test. Circuit sizing primarily comprises of two components: a search engine and a performance estimator. Stochastic combinatorial optimization techniques are used for exploring the design space. For each candidate design explored by the search engine, the circuit performance is estimated. Typically, the performance estimation time dominates the overall synthesis time. Most commercial approaches deploy a simulator-in-loop approach to the sizing problem due to the high accuracy desired from the estimation process. We propose two techniques for replacing the simulator with accurate and efficient performance models. Since the performance models allow a very quick evaluation of the circuit performance, their use helps in drastically reducing the time complexity of sizing. Unlike the existing… Advisors/Committee Members: Vemuri, Dr. Ranga (Advisor).

Subjects/Keywords: Analog; Radio-frequency; Circuit Synthesis; Layout Parasitics; Performance Modeling; Parasitic Estimation and Modeling; Layout-Aware Synthesis; Circuit sizing; Parasitic Corners; Yield Optimization; Parasitic Capacitances; Dynamic Performance Macromodel

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

AGARWAL, A. (2005). ALGORITHMS FOR LAYOUT-AWARE AND PERFORMANCE MODEL DRIVEN SYNTHESIS OF ANALOG CIRCUITS. (Doctoral Dissertation). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1132259454

Chicago Manual of Style (16^th Edition):

AGARWAL, ANURADHA. “ALGORITHMS FOR LAYOUT-AWARE AND PERFORMANCE MODEL DRIVEN SYNTHESIS OF ANALOG CIRCUITS.” 2005. Doctoral Dissertation, University of Cincinnati. Accessed January 27, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1132259454.

MLA Handbook (7^th Edition):

AGARWAL, ANURADHA. “ALGORITHMS FOR LAYOUT-AWARE AND PERFORMANCE MODEL DRIVEN SYNTHESIS OF ANALOG CIRCUITS.” 2005. Web. 27 Jan 2021.

Vancouver:

AGARWAL A. ALGORITHMS FOR LAYOUT-AWARE AND PERFORMANCE MODEL DRIVEN SYNTHESIS OF ANALOG CIRCUITS. [Internet] [Doctoral dissertation]. University of Cincinnati; 2005. [cited 2021 Jan 27]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1132259454.

Council of Science Editors:

AGARWAL A. ALGORITHMS FOR LAYOUT-AWARE AND PERFORMANCE MODEL DRIVEN SYNTHESIS OF ANALOG CIRCUITS. [Doctoral Dissertation]. University of Cincinnati; 2005. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1132259454

University of Cincinnati

7. KRISHNAN, AKHIL. HARDWARE IMPLEMENTATION OF A NOVEL ENCRYPTION ALGORITHM.

Degree: MS, Engineering : Computer Engineering, 2006, University of Cincinnati

URL: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1139462392

► Multivariate cryptosystem is a novel cryptographic system which can offer very high security even for small key sizes. This particular feature makes this scheme very… (more)

Subjects/Keywords: cryptography; FPGA; multivariate cryptosystem; encryption hardware

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

KRISHNAN, A. (2006). HARDWARE IMPLEMENTATION OF A NOVEL ENCRYPTION ALGORITHM. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1139462392

Chicago Manual of Style (16^th Edition):

KRISHNAN, AKHIL. “HARDWARE IMPLEMENTATION OF A NOVEL ENCRYPTION ALGORITHM.” 2006. Masters Thesis, University of Cincinnati. Accessed January 27, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1139462392.

MLA Handbook (7^th Edition):

KRISHNAN, AKHIL. “HARDWARE IMPLEMENTATION OF A NOVEL ENCRYPTION ALGORITHM.” 2006. Web. 27 Jan 2021.

Vancouver:

KRISHNAN A. HARDWARE IMPLEMENTATION OF A NOVEL ENCRYPTION ALGORITHM. [Internet] [Masters thesis]. University of Cincinnati; 2006. [cited 2021 Jan 27]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1139462392.

Council of Science Editors:

KRISHNAN A. HARDWARE IMPLEMENTATION OF A NOVEL ENCRYPTION ALGORITHM. [Masters Thesis]. University of Cincinnati; 2006. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1139462392

University of Cincinnati

8. BHATTACHARYA, PRASUN. COMPARISON OF SINGLE-PORT AND MULTI-PORT NoCs WITH CONTEMPORARY BUSES ON FPGAs.

Degree: MS, Engineering : Computer Engineering, 2006, University of Cincinnati

URL: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1142842819

► Systems-on-chip brought several cores onto a single chip. But, as more cores are being put onto a single chip, the on-chip communication resource, which is… (more)

Subjects/Keywords: NoC; Routers; SoC; FPGA

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

BHATTACHARYA, P. (2006). COMPARISON OF SINGLE-PORT AND MULTI-PORT NoCs WITH CONTEMPORARY BUSES ON FPGAs. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1142842819

Chicago Manual of Style (16^th Edition):

BHATTACHARYA, PRASUN. “COMPARISON OF SINGLE-PORT AND MULTI-PORT NoCs WITH CONTEMPORARY BUSES ON FPGAs.” 2006. Masters Thesis, University of Cincinnati. Accessed January 27, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1142842819.

MLA Handbook (7^th Edition):

BHATTACHARYA, PRASUN. “COMPARISON OF SINGLE-PORT AND MULTI-PORT NoCs WITH CONTEMPORARY BUSES ON FPGAs.” 2006. Web. 27 Jan 2021.

Vancouver:

BHATTACHARYA P. COMPARISON OF SINGLE-PORT AND MULTI-PORT NoCs WITH CONTEMPORARY BUSES ON FPGAs. [Internet] [Masters thesis]. University of Cincinnati; 2006. [cited 2021 Jan 27]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1142842819.

Council of Science Editors:

BHATTACHARYA P. COMPARISON OF SINGLE-PORT AND MULTI-PORT NoCs WITH CONTEMPORARY BUSES ON FPGAs. [Masters Thesis]. University of Cincinnati; 2006. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1142842819

University of Cincinnati

9. CHAKRABORTY, RITOCHIT. SYMBOLIC TIME DOMAIN BEHAVIOR AND PERFORMANCE ANALYSIS OF LINEAR ANALOG CIRCUITS.

Degree: MS, Engineering : Computer Engineering, 2006, University of Cincinnati

URL: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1145990101

► Automated design of analog circuits involves circuit sizing, a process of assigning numerical values to unknown parameters of a fixed circuit topology. With the advent… (more)

Subjects/Keywords: Analog Circuit Synthesis; Symbolic Analysis; Symbolic Newton-Iteration; Pole Extraction

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APA (6^th Edition):

CHAKRABORTY, R. (2006). SYMBOLIC TIME DOMAIN BEHAVIOR AND PERFORMANCE ANALYSIS OF LINEAR ANALOG CIRCUITS. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1145990101

Chicago Manual of Style (16^th Edition):

CHAKRABORTY, RITOCHIT. “SYMBOLIC TIME DOMAIN BEHAVIOR AND PERFORMANCE ANALYSIS OF LINEAR ANALOG CIRCUITS.” 2006. Masters Thesis, University of Cincinnati. Accessed January 27, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1145990101.

MLA Handbook (7^th Edition):

CHAKRABORTY, RITOCHIT. “SYMBOLIC TIME DOMAIN BEHAVIOR AND PERFORMANCE ANALYSIS OF LINEAR ANALOG CIRCUITS.” 2006. Web. 27 Jan 2021.

Vancouver:

CHAKRABORTY R. SYMBOLIC TIME DOMAIN BEHAVIOR AND PERFORMANCE ANALYSIS OF LINEAR ANALOG CIRCUITS. [Internet] [Masters thesis]. University of Cincinnati; 2006. [cited 2021 Jan 27]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1145990101.

Council of Science Editors:

CHAKRABORTY R. SYMBOLIC TIME DOMAIN BEHAVIOR AND PERFORMANCE ANALYSIS OF LINEAR ANALOG CIRCUITS. [Masters Thesis]. University of Cincinnati; 2006. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1145990101

University of Cincinnati

10. DING, MENGMENG. REGRESSION BASED ANALOG PERFORMANCE MACROMODELING: TECHNIQUES AND APPLICATIONS.

Degree: PhD, Engineering : Computer Science and Engineering, 2006, University of Cincinnati

URL: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1146145102

► Optimization based analog circuit sizing opens a new page for computer aided design of analog integrated circuits. While differing in implementation details, the sizing tools… (more)

▼ Optimization based analog circuit sizing opens a new page for computer aided design of analog integrated circuits. While differing in implementation details, the sizing tools usually include two main modules: an optimization engine and a module for performance parameter evaluation. The latter often contributes to the bulk of total computational time when a transistor level circuit simulator is used to obtain performance parameters. This motivates us to develop fast performance macromodels.Regression based techniques, when applied to performance macromodeling, have obvious advantages over other approaches: higher degree of automation, no need for simulator whatsoever, applicable to any performance parameter and topology. On the other hand, regression techniques usually suffer from “the curse of dimensionality”, which refers to the phenomenon that the sample size needed to cover a high dimensional space grows exponentially with the dimension. This thesis provides a few novel techniques to cope with this problem based on the specific needs by analog performance macromodeling, falling into two categories: adaptive sampling and design space reduction. Initial effort has been dedicated to developing an adaptive sampling algorithm to reduce training set size while maintaining high model accuracy. The proposed adaptive sampling algorithm is called adaptive grid refinement algorithm. The algorithm first constructs a regression model in the entire design space, a hypercube, using training data set generated from a two level full factorial design. The hypercube is then split into equal-sized smaller hypercubes if the model has error exceeding user defined bound. Within each smaller hypercube a local regression model is constructed and validated. Splitting stops only if all the local models have validation errors within the error bound. The final model is a set of local regression models. Although it is desirable to model the entire design space accurately, only part of the design space called the feasible design space is worth exploring by an analog sizing tool. A feasibility model is needed to identify the feasible design space. Feasibility modeling is treated as a two-class classification problem in our case. The small size of the feasible design space, however, challenges the state-of-the-art classification techniques such as Support Vector Machines when uniform randomly distributed instances are used for model training. We thus propose an active learning scheme to improve the feasibility classifier’s accuracy more efficiently. The performance regression macromodels are built and validated within the feasible design space. Experiments show that they are more accurate compared to those valid within the entire design space when equal sized training sets are used. The resulting performance macromodel is essentially a combined model: a feasibility classifier and a set of performance regression models. The third technique is designed to further reduce modeling cost of the combined model. More efficient feasibility model… Advisors/Committee Members: Vemuri, Dr. Ranga (Advisor).

Subjects/Keywords: analog performance macromodeling; analog circuit sizing; adaptive sampling; active learning; regression; classification

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APA (6^th Edition):

DING, M. (2006). REGRESSION BASED ANALOG PERFORMANCE MACROMODELING: TECHNIQUES AND APPLICATIONS. (Doctoral Dissertation). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1146145102

Chicago Manual of Style (16^th Edition):

DING, MENGMENG. “REGRESSION BASED ANALOG PERFORMANCE MACROMODELING: TECHNIQUES AND APPLICATIONS.” 2006. Doctoral Dissertation, University of Cincinnati. Accessed January 27, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1146145102.

MLA Handbook (7^th Edition):

DING, MENGMENG. “REGRESSION BASED ANALOG PERFORMANCE MACROMODELING: TECHNIQUES AND APPLICATIONS.” 2006. Web. 27 Jan 2021.

Vancouver:

DING M. REGRESSION BASED ANALOG PERFORMANCE MACROMODELING: TECHNIQUES AND APPLICATIONS. [Internet] [Doctoral dissertation]. University of Cincinnati; 2006. [cited 2021 Jan 27]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1146145102.

Council of Science Editors:

DING M. REGRESSION BASED ANALOG PERFORMANCE MACROMODELING: TECHNIQUES AND APPLICATIONS. [Doctoral Dissertation]. University of Cincinnati; 2006. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1146145102

University of Cincinnati

11. PATEL, VIPUL J. BEHAVIORAL SIMULATION AND SYNTHESIS ENVIRONMENT FOR CONTINUOUS-TIME SINGLE-LOOP SINGLE-BIT BASEBAND DELTA-SIGMA ANALOG-TO-DIGITAL MODULATORS.

Degree: MS, Engineering : Computer Engineering, 2006, University of Cincinnati

URL: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1147473065

► For the past few decades, research and design of CAD tools have focused on developing a set of tools that will guarantee designers first-pass fabrication… (more)

▼ For the past few decades, research and design of CAD tools have focused on developing a set of tools that will guarantee designers first-pass fabrication success. There have been many variations of digital design “suites” that make this claim. With the increase in integrated circuit complexity and the drive for systems-on-a-chip (SoC), companies and universities are now focusing their efforts on creating design tools addressing the analog and RF domains. System-level design is one of the most important and challenging elements in the mixed-signal design process. Currently, many system designs are approached from a bottom-up perspective where components are designed individually and then assembled at the system-level. Concepts such as analog and digital interfacing, defining component specifications, and system verification are typically lacking or are addressed too late. Rapid modeling and component-level trade-offs are important in the design of systems. Many of these integration issues can be addressed early in the design phase by having the capability to predict and model component-level effects. In order to address these issues of system design and synthesis, four primary tools have been developed. These tools include (1) a continuous-time delta-sigma system modeler and designer, (2) a circuit sizer, (3) a performance analysis system, and (4) a parameterized module layout generator. Various analog synthesis flows have been developed using these tools. The first goal of this thesis is to provide the design community with a behavioral environment that will model and aid in the creation of continuous-time single-loop single-bit baseband delta-sigma analog-to-digital modulators using MATLAB and Simulink. The second goal is to use the designs from the delta-sigma toolbox to produce component-level specifications derived from system-level requirements. In this thesis, the developed tools were used in a synthesis loop to design, implement, and verify two continuous-time delta-sigma modulators and their respective components. A third order modulator was designed with 1 MHz instantaneous bandwidth and a sampling rate of 64 MSps using the top-down design methodology. The modulator performed with an SNR of 60 dB and ENOB of 9.7 bits. A fourth order modulator with a sample rate of 50 MSps was designed with a bandwidth of 390 kHz, and the bottom-up design methodology was used. This design performed with an SNR of 74.2 dB and ENOB of 12.0 bits. Advisors/Committee Members: Vemuri, Dr. Ranga (Advisor).

Subjects/Keywords: Delta-Sigma; Sigma-Delta; Top-Down; Bottom-Up; Modulator; Methodology; Analog; RF; Digital; Synthesis; Analog Synthesis; Layout; Parasitics; Behavioral Modeling; Layout-Aware; MATLAB; Simulink

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

PATEL, V. J. (2006). BEHAVIORAL SIMULATION AND SYNTHESIS ENVIRONMENT FOR CONTINUOUS-TIME SINGLE-LOOP SINGLE-BIT BASEBAND DELTA-SIGMA ANALOG-TO-DIGITAL MODULATORS. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1147473065

Chicago Manual of Style (16^th Edition):

PATEL, VIPUL J. “BEHAVIORAL SIMULATION AND SYNTHESIS ENVIRONMENT FOR CONTINUOUS-TIME SINGLE-LOOP SINGLE-BIT BASEBAND DELTA-SIGMA ANALOG-TO-DIGITAL MODULATORS.” 2006. Masters Thesis, University of Cincinnati. Accessed January 27, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1147473065.

MLA Handbook (7^th Edition):

PATEL, VIPUL J. “BEHAVIORAL SIMULATION AND SYNTHESIS ENVIRONMENT FOR CONTINUOUS-TIME SINGLE-LOOP SINGLE-BIT BASEBAND DELTA-SIGMA ANALOG-TO-DIGITAL MODULATORS.” 2006. Web. 27 Jan 2021.

Vancouver:

PATEL VJ. BEHAVIORAL SIMULATION AND SYNTHESIS ENVIRONMENT FOR CONTINUOUS-TIME SINGLE-LOOP SINGLE-BIT BASEBAND DELTA-SIGMA ANALOG-TO-DIGITAL MODULATORS. [Internet] [Masters thesis]. University of Cincinnati; 2006. [cited 2021 Jan 27]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1147473065.

Council of Science Editors:

PATEL VJ. BEHAVIORAL SIMULATION AND SYNTHESIS ENVIRONMENT FOR CONTINUOUS-TIME SINGLE-LOOP SINGLE-BIT BASEBAND DELTA-SIGMA ANALOG-TO-DIGITAL MODULATORS. [Masters Thesis]. University of Cincinnati; 2006. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1147473065

University of Cincinnati

12. HUANG, RENQIU. PHYSICAL AWARE HIGH LEVEL SYNTHESIS AND INTERCONNECT FOR FPGAs.

Degree: PhD, Engineering : Computer Science and Engineering, 2006, University of Cincinnati

URL: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1147616884

► Reconfigurable computing (RC) is going mainstream where FPGA plays an essential role. Synthesizing the application from concept and prototyping onto reconfigurable FPGAs has emerged as… (more)

▼ Reconfigurable computing (RC) is going mainstream where FPGA plays an essential role. Synthesizing the application from concept and prototyping onto reconfigurable FPGAs has emerged as one of the main challenges in design automation area. A large number of new applications show the huge potentials of synthesis strategy and architecture development for FPGAs. The work presented in this dissertation deals with the synthesis and novel architecture of FPGAs. In particular, it tries to address physical aware high level synthesis (PAHLS) methodology to ensure the synthesis integrity for FPGAs. Motivated by the study of PAHLS, a hybrid interconnect structure is proposed to increase the performance and reconfigurability for FPGAs or FPGA-like reconfigurable platforms. We first present a performance-driven PAHLS where relational placement is combined with the macro generation strategy during high level synthesis. Second, we present an automated framework to integrate physical placement information into high-level synthesis that is believed to be the first on-line synthesis methodology for partially reconfigurable FPGAs. The presented synthesizer allocates the FPGA resources adaptively and is incremental in nature. The algorithm is designed to be linear in terms of the number of operations to ensure its on-line usage. We then present a transformation mechanism to extend the synthesis frontier to heterogeneous configurable architectures. We develop an automatic synthesis methodology which attacks both memory and logic assignments by interacting with behavioral synthesis. Next, we present a hybrid interconnect structure which takes advantages of both mesh and tree interconnect topologies. The presented architecture is investigated with a combinatorial analysis which examines the number of switches needed. Our evaluation demonstrates that the presented model has less switch accrued effects due to the introduction of tree networks. Finally we extend that hybrid interconnect structure to support multi-granular configuration. We also develop a fast evaluation tool to simulate on-line placement and routing effects by applying that interconnect on a run-time reconfigurable platform. The studies show the efficiency of the extended model in overcoming the fragmentation problem with a penalty of modest increase in the number of switches for the construction of that interconnect. Advisors/Committee Members: Vemuri, Dr. Ranga (Advisor).

Subjects/Keywords: Computer Science; High level synthesis; system synthesis; algorithm; architecture; performance; interconnect; analysis; evaluation

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

HUANG, R. (2006). PHYSICAL AWARE HIGH LEVEL SYNTHESIS AND INTERCONNECT FOR FPGAs. (Doctoral Dissertation). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1147616884

Chicago Manual of Style (16^th Edition):

HUANG, RENQIU. “PHYSICAL AWARE HIGH LEVEL SYNTHESIS AND INTERCONNECT FOR FPGAs.” 2006. Doctoral Dissertation, University of Cincinnati. Accessed January 27, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1147616884.

MLA Handbook (7^th Edition):

HUANG, RENQIU. “PHYSICAL AWARE HIGH LEVEL SYNTHESIS AND INTERCONNECT FOR FPGAs.” 2006. Web. 27 Jan 2021.

Vancouver:

HUANG R. PHYSICAL AWARE HIGH LEVEL SYNTHESIS AND INTERCONNECT FOR FPGAs. [Internet] [Doctoral dissertation]. University of Cincinnati; 2006. [cited 2021 Jan 27]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1147616884.

Council of Science Editors:

HUANG R. PHYSICAL AWARE HIGH LEVEL SYNTHESIS AND INTERCONNECT FOR FPGAs. [Doctoral Dissertation]. University of Cincinnati; 2006. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1147616884

University of Cincinnati

13. YAN, JIANPING. A TILED FPGA ARCHITECTURE FOR POWER-AWARE COMPUTATIONS.

Degree: MS, Engineering : Computer Engineering, 2006, University of Cincinnati

URL: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1150126839

► Current SRAM FPGAs have reached high gate densities which make them suitable for portable reconfigurable systems and data intensive applications. However, some challenges need to… (more)

▼ Current SRAM FPGAs have reached high gate densities which make them suitable for portable reconfigurable systems and data intensive applications. However, some challenges need to be faced to make this become a reality. First, due to a large number of transistors for field programmability and low utilization rate of FPGA resources, existing FPGAs are highly power hungry compared to ASICs. As chip technology progresses to 90 nm and below, this situation becomes worse and static current plays a major role in the total power. Second, the present column-based configuration structure is not flexible enough for applications with multiple reconfigurations. Unnecessary memory bits have to be configured if the layout of the module does not fully occupy the height of the device and, consequently, introduces wastage of time and energy. Third, the global clock distribution over the whole chip results in a very high power consumption. Even when some parts of the hardware resources are not used, the whole clock line must be switched at every clock cycle. Finally, current FPGAs can not support bus routing structure. The implementation of data intensive applications using traditional bit-based routing tracks will require more routing resource and produce higher power consumption. A lot of previous efforts have been made on FPGA power modeling and power reduction. In the work of power modeling and estimation for SRAM FPGAs, none of them has considered the impact of inrush current and configuration current, which can not be neglected for low-power applications that need multiple reconfigurations. For the previous power reduction architectures, some of them considered either one of dynamic power reduction or static power reduction. The other architectures such as dual-Vdd FPGA architecture considered both dynamic power and static power reduction. But their implementations produce significant area and configuration time overheads and the power management strategy is very inefficient since it is based on fine grained logic blocks or routing switches. The complex power management makes these architectures not practical for the real time applications that need multiple dynamic reconfigurations. This thesis proposes a battery-aware tiled FPGA architecture for data intensive computations. The architecture is globally coarse-grained in terms of FPGA tiles and locally fine-grained in terms of configurable logic blocks within each FPGA tile. The main feature of the architecture is that the power supply to each tile can be turned on/off depending on the computational requirements and system load. The static control strategy is fairly simple, which makes the area and configuration time overheads relatively small. The architecture adopts a two-level configuration structure, column-based programming and fully random access programming, which can efficiently reduce the configuration time and energy, while keeping the overheads of pin count and area relatively small. This combined configuration architecture enables the easy task relocation from one… Advisors/Committee Members: Vemuri, Dr. Ranga (Advisor).

Subjects/Keywords: FPGA; Power Consumption; Architecture; Simulation

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

YAN, J. (2006). A TILED FPGA ARCHITECTURE FOR POWER-AWARE COMPUTATIONS. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1150126839

Chicago Manual of Style (16^th Edition):

YAN, JIANPING. “A TILED FPGA ARCHITECTURE FOR POWER-AWARE COMPUTATIONS.” 2006. Masters Thesis, University of Cincinnati. Accessed January 27, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1150126839.

MLA Handbook (7^th Edition):

YAN, JIANPING. “A TILED FPGA ARCHITECTURE FOR POWER-AWARE COMPUTATIONS.” 2006. Web. 27 Jan 2021.

Vancouver:

YAN J. A TILED FPGA ARCHITECTURE FOR POWER-AWARE COMPUTATIONS. [Internet] [Masters thesis]. University of Cincinnati; 2006. [cited 2021 Jan 27]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1150126839.

Council of Science Editors:

YAN J. A TILED FPGA ARCHITECTURE FOR POWER-AWARE COMPUTATIONS. [Masters Thesis]. University of Cincinnati; 2006. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1150126839

University of Cincinnati

14. MASSARINI, RENO. POWER - AWARE MOBILE SENSOR NETWORKS WITH RECONFIGURABLE COMPUTING NODES.

Degree: MS, Engineering : Computer Engineering, 2006, University of Cincinnati

URL: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1159198177

► Portable electronic devices like laptops, PDAs, and cell phones are finding their way into more and more homes, offices, and classrooms. They typically come with… (more)

Subjects/Keywords: Agriculture; Forestry and Wildlife

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

MASSARINI, R. (2006). POWER - AWARE MOBILE SENSOR NETWORKS WITH RECONFIGURABLE COMPUTING NODES. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1159198177

Chicago Manual of Style (16^th Edition):

MASSARINI, RENO. “POWER - AWARE MOBILE SENSOR NETWORKS WITH RECONFIGURABLE COMPUTING NODES.” 2006. Masters Thesis, University of Cincinnati. Accessed January 27, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1159198177.

MLA Handbook (7^th Edition):

MASSARINI, RENO. “POWER - AWARE MOBILE SENSOR NETWORKS WITH RECONFIGURABLE COMPUTING NODES.” 2006. Web. 27 Jan 2021.

Vancouver:

MASSARINI R. POWER - AWARE MOBILE SENSOR NETWORKS WITH RECONFIGURABLE COMPUTING NODES. [Internet] [Masters thesis]. University of Cincinnati; 2006. [cited 2021 Jan 27]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1159198177.

Council of Science Editors:

MASSARINI R. POWER - AWARE MOBILE SENSOR NETWORKS WITH RECONFIGURABLE COMPUTING NODES. [Masters Thesis]. University of Cincinnati; 2006. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1159198177

University of Cincinnati

15. JIA, XIN. GAPLA: A GLOBALLY ASYNCHRONOUS LOCALLY SYNCHRONOUS FPGA ARCHITECTURE.

Degree: PhD, Engineering : Computer Engineering, 2007, University of Cincinnati

URL: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1164589281

► Conventional FPGAs, designed to implement synchronous circuits and systems, are facing some challenges. (1) The delays of the long interconnect wires can easily dominate all… (more)

▼ Conventional FPGAs, designed to implement synchronous circuits and systems, are facing some challenges. (1) The delays of the long interconnect wires can easily dominate all other delays and severely reduce the application clock rates. For example, the corner-to-corner interconnect delay of a xc2v8000 FPGA is about 14.9ns. A synchronous design using such an interconnection can run under the clock speed of no more than 67MHz. (2) A multitude of modules running at different clock frequencies are likely to be integrated on a single FPGA to form a single-chip solution since FPGAs have grown to sufficient sizes. Data communication between modules means to move data across different clock domains. Therefore, the data signals appear to be asynchronous in the new clock domain. Current FPGA architectures and CAD tools provide very few or even no support for asynchronous communications. Therefore, it is up to the designer to build reliable circuits for communications across clock domains, which is tedious and error-prone. (3) Clock distribution network is complicated and power consuming. (4) Dynamically partial reconfigurability is becoming crucial to FPGAs. But current FPGA support for dynamically partial reconfiguration is at best tedious since changing of one part might violate the global clock restriction in a monotonic clock realm. Introducing asynchronous concept into the FPGA architecture is a possible solution to the named challenges. Asynchronous designs provide average-case performance instead of the worst-case performance provided by the synchronous designs. In terms of interconnect delays, performance is dictated by the average of the interconnect delays rather than the worst-case delay. Hence use of long wires does not necessarily lead to a significant performance penalty. By adopting asynchronous design, FPGAs then an provide architectural supports for communications across different clock domains. Different modules running at different clock frequencies can be easily glued together. Also, since the speed independent property of asynchronous designs, modifying one part will not affect the correctness of other parts. Therefore, dynamically partial reconfiguration can be easily realized. Clock distribution is no longer a problem since the global clock signals are removed. Furthermore, unused modules in an asynchronous design could be automatically shut down to save the total power consumption. In this dissertation, the GAPLA: a GALS Programmable Logic Array architecture is presented. GALS stands for Globally Asynchronous Locally Synchronous. A GALS system consists of synchronous logic blocks operating independently under locally generated clocks and communicating with each other through handshaking asynchronous interfaces. In GAPLA, the FPGA area is divided into locally synchronous programmable logic blocks wrapped with programmable asynchronous I/O interfaces which are then connected by the routing network. Interconnect inside each synchronous block is local and fast. The long interconnects between synchronous… Advisors/Committee Members: Vemuri, Dr. Ranga (Advisor).

Subjects/Keywords: FPGA Architecture; Globally Asynchronous Locally Synchronous

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

JIA, X. (2007). GAPLA: A GLOBALLY ASYNCHRONOUS LOCALLY SYNCHRONOUS FPGA ARCHITECTURE. (Doctoral Dissertation). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1164589281

Chicago Manual of Style (16^th Edition):

JIA, XIN. “GAPLA: A GLOBALLY ASYNCHRONOUS LOCALLY SYNCHRONOUS FPGA ARCHITECTURE.” 2007. Doctoral Dissertation, University of Cincinnati. Accessed January 27, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1164589281.

MLA Handbook (7^th Edition):

JIA, XIN. “GAPLA: A GLOBALLY ASYNCHRONOUS LOCALLY SYNCHRONOUS FPGA ARCHITECTURE.” 2007. Web. 27 Jan 2021.

Vancouver:

JIA X. GAPLA: A GLOBALLY ASYNCHRONOUS LOCALLY SYNCHRONOUS FPGA ARCHITECTURE. [Internet] [Doctoral dissertation]. University of Cincinnati; 2007. [cited 2021 Jan 27]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1164589281.

Council of Science Editors:

JIA X. GAPLA: A GLOBALLY ASYNCHRONOUS LOCALLY SYNCHRONOUS FPGA ARCHITECTURE. [Doctoral Dissertation]. University of Cincinnati; 2007. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1164589281

University of Cincinnati

16. YANG, HUIYING. SYMBOLIC SENSITIVITY ANALYSIS TECHNIQUES AND APPLICATIONS IN ANALOG CIRCUIT SYNTHESIS.

Degree: PhD, Engineering : Computer Engineering, 2007, University of Cincinnati

URL: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1167665537

► With increasing complexity of integrated circuits and decreasing time-to-market constraints, there was remarkable success in automation of the digital circuit design, but it exposes the… (more)

▼ With increasing complexity of integrated circuits and decreasing time-to-market constraints, there was remarkable success in automation of the digital circuit design, but it exposes the lack of comparable analog design automation tools. Although analog components typically constitute only a small portion of the integrated circuits and emerging systems-on-chip (SoC) designs, they are indispensable in all electronic applications that interface with the outside world. Due to the complexity of analog and radio-frequency (RF) circuits, analog circuit design time dominates and becomes a bottleneck in ICs. There is a growing need for analog design automation tools. One of the main challenges in analog design is sizing. Given an analog topology and a set of high-level design specifications, the size of all components in the circuit must be appropriately determined in order to meet all design target specifications. There are many ways to approach the sizing problem, from manual design and knowledge-based strategies to global optimization engines utilizing a detailed circuit simulator like SPICE. Typically, most commercial approaches use simulation-in-loop to tackle analog sizing problem due to the high accuracy desired from the estimation process which introduce commercial simulators, like SPICE, to numerically estimate circuit performance and identify critical parameters. Choosing appropriate parameter for sizing in each loop is very critical during the whole sizing process. Sensitivity of an analog circuit is the mathematical measure of variations in the performance metrics due to infinitesimally small perturbations of circuit parameter values which can determine the critical design variables in analog circuit synthesis and can be used repetitively to identify critical parasitics that severely hamper the circuit performance. In this dissertation, we focus on the development of accurate and efficient symbolic sensitivity analysis for use in the synthesis of analog circuits. We build the sensitivity analysis model and propose the methodologies for performance sensitivity calculations with respect to transistors, capacitors and MOSFETs. We apply different sensitivity analysis techniques to improve the efficiency and accuracy of analog circuit synthesis. In our approach, the parameters chosen for sizing are determined by their sensitivities instead of randomly choosing the parameters to be perturbed. This reduces the iteration time and hence the overall synthesis time considerably. We also build the parasitic estimation model and optimize the parasitics by applying symbolic sensitivity techniques. Advisors/Committee Members: Vemuri, Dr. Ranga (Advisor).

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APA (6^th Edition):

YANG, H. (2007). SYMBOLIC SENSITIVITY ANALYSIS TECHNIQUES AND APPLICATIONS IN ANALOG CIRCUIT SYNTHESIS. (Doctoral Dissertation). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1167665537

Chicago Manual of Style (16^th Edition):

YANG, HUIYING. “SYMBOLIC SENSITIVITY ANALYSIS TECHNIQUES AND APPLICATIONS IN ANALOG CIRCUIT SYNTHESIS.” 2007. Doctoral Dissertation, University of Cincinnati. Accessed January 27, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1167665537.

MLA Handbook (7^th Edition):

YANG, HUIYING. “SYMBOLIC SENSITIVITY ANALYSIS TECHNIQUES AND APPLICATIONS IN ANALOG CIRCUIT SYNTHESIS.” 2007. Web. 27 Jan 2021.

Vancouver:

YANG H. SYMBOLIC SENSITIVITY ANALYSIS TECHNIQUES AND APPLICATIONS IN ANALOG CIRCUIT SYNTHESIS. [Internet] [Doctoral dissertation]. University of Cincinnati; 2007. [cited 2021 Jan 27]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1167665537.

Council of Science Editors:

YANG H. SYMBOLIC SENSITIVITY ANALYSIS TECHNIQUES AND APPLICATIONS IN ANALOG CIRCUIT SYNTHESIS. [Doctoral Dissertation]. University of Cincinnati; 2007. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1167665537

University of Cincinnati

17. THAKORE, PRIYANKA. DEVELOPMENT OF PROCESS VARIATION TOLERANT STANDARD CELLS.

Degree: MS, Engineering : Electrical Engineering, 2007, University of Cincinnati

URL: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1176841201

► ASIC design using standard cell library cells is the most widespread design method. Lower process technologies drive a need to incorporate Design for Manufacturability technique… (more)

Subjects/Keywords: DFM; DFY; Standard Cell; Process Variation; library characterization

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APA (6^th Edition):

THAKORE, P. (2007). DEVELOPMENT OF PROCESS VARIATION TOLERANT STANDARD CELLS. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1176841201

Chicago Manual of Style (16^th Edition):

THAKORE, PRIYANKA. “DEVELOPMENT OF PROCESS VARIATION TOLERANT STANDARD CELLS.” 2007. Masters Thesis, University of Cincinnati. Accessed January 27, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1176841201.

MLA Handbook (7^th Edition):

THAKORE, PRIYANKA. “DEVELOPMENT OF PROCESS VARIATION TOLERANT STANDARD CELLS.” 2007. Web. 27 Jan 2021.

Vancouver:

THAKORE P. DEVELOPMENT OF PROCESS VARIATION TOLERANT STANDARD CELLS. [Internet] [Masters thesis]. University of Cincinnati; 2007. [cited 2021 Jan 27]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1176841201.

Council of Science Editors:

THAKORE P. DEVELOPMENT OF PROCESS VARIATION TOLERANT STANDARD CELLS. [Masters Thesis]. University of Cincinnati; 2007. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1176841201

University of Cincinnati

18. RAMMOHAN, SRIVIDHYA. REDUCED COMPLEMENTARY DYNAMIC AND DIFFERENTIAL CMOS LOGIC: A DESIGN METHODOLOGY FOR DPA RESISTANT CRYPTOGRAPHIC CIRCUITS.

Degree: MS, Engineering : Computer Engineering, 2007, University of Cincinnati

URL: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1179459225

► In recent times, many embedded applications such as mobile phones, smart-cards, etc. use cryptographic devices that use a secret key to encrypt sensitive data to… (more)

Subjects/Keywords: Differential Power Analysis (DPA) Attacks; Secret Key; Dynamic Differential Logic; Side-Channel Attacks

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APA (6^th Edition):

RAMMOHAN, S. (2007). REDUCED COMPLEMENTARY DYNAMIC AND DIFFERENTIAL CMOS LOGIC: A DESIGN METHODOLOGY FOR DPA RESISTANT CRYPTOGRAPHIC CIRCUITS. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1179459225

Chicago Manual of Style (16^th Edition):

RAMMOHAN, SRIVIDHYA. “REDUCED COMPLEMENTARY DYNAMIC AND DIFFERENTIAL CMOS LOGIC: A DESIGN METHODOLOGY FOR DPA RESISTANT CRYPTOGRAPHIC CIRCUITS.” 2007. Masters Thesis, University of Cincinnati. Accessed January 27, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1179459225.

MLA Handbook (7^th Edition):

RAMMOHAN, SRIVIDHYA. “REDUCED COMPLEMENTARY DYNAMIC AND DIFFERENTIAL CMOS LOGIC: A DESIGN METHODOLOGY FOR DPA RESISTANT CRYPTOGRAPHIC CIRCUITS.” 2007. Web. 27 Jan 2021.

Vancouver:

RAMMOHAN S. REDUCED COMPLEMENTARY DYNAMIC AND DIFFERENTIAL CMOS LOGIC: A DESIGN METHODOLOGY FOR DPA RESISTANT CRYPTOGRAPHIC CIRCUITS. [Internet] [Masters thesis]. University of Cincinnati; 2007. [cited 2021 Jan 27]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1179459225.

Council of Science Editors:

RAMMOHAN S. REDUCED COMPLEMENTARY DYNAMIC AND DIFFERENTIAL CMOS LOGIC: A DESIGN METHODOLOGY FOR DPA RESISTANT CRYPTOGRAPHIC CIRCUITS. [Masters Thesis]. University of Cincinnati; 2007. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1179459225

University of Cincinnati

19. KOMMINENI, BALAJI. SPLINE CENTER AND RANGE REGRESSION TECHNIQUE AND ITS APPLICATION TO VARIATION AWARE PERFORMANCE MACROMODELING OF ANALOG CIRCUITS.

Degree: MS, Engineering : Electrical Engineering, 2007, University of Cincinnati

URL: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1195585950

► Regression is an essential part of engineering methodologies. It plays a critical role in modeling unknown relationships among variables. However when measurement accuracy becomes very… (more)

▼ Regression is an essential part of engineering methodologies. It plays a critical role in modeling unknown relationships among variables. However when measurement accuracy becomes very important simple regression techniques fail to capture these relationships. This is due to the fact that measured data is prone to much variation due to noise which is unavoidable. Thus, a more robust regression technique is needed which can be used even in the presence of noise. This work is aimed at the development of such a regression technique. The technique is applied to the problem of analog circuit synthesis for generating process variation tolerant analog designs. Noisy data can be modeled as intervals. Interval data types represent a range of values which a variable can assume within a lower bound and an upper bound. Thus, the problem translates to modeling interval valued data. But, the regular real regression techniques cannot be extended to intervals due to the inherent problems of interval arithmetic. Performing real valued arithmetic on interval data and a regression technique which allows such a manipulation form a possible solution. Several such techniques have been proposed in literature which make use of the center and range information of the intervals. Spline Center and Range Regression is a new technique proposed in this work. The Spline Center And Range Regression technique is capable of interpolating the lower and upper bounds of interval valued data based on the center and range information of the intervals. The Spline Center and Range Regression approach interpolates on the center and range values of an interval independently which are then combined to obtain the interval bound. For interpolating the center and the range it uses spline regression which is a type of regression capable of working on highly non-linear data and at the same time provides excellent accuracy. Thus, combining splines with the above mentioned approach gives a highly accurate interval regression technique as compared to it’s linear counterparts. The Spline Center and Range Regression technique is applied to the VLSI design to tackle the effects of process variations on analog circuits. Process variations cause the performance parameters used for designing the circuit to vary from the intended value once the circuit is manufactured. Performance macromodels have been used extensively for the analog circuit sizing process. Conventional macromodels have failed to take into account the effects of process variations. To overcome this problem new variation aware performance macromodels are developed using SCRR. These macromodels are then used to synthesize process variation tolerant analog circuits. Advisors/Committee Members: Vemuri, Dr. Ranga (Advisor).

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

KOMMINENI, B. (2007). SPLINE CENTER AND RANGE REGRESSION TECHNIQUE AND ITS APPLICATION TO VARIATION AWARE PERFORMANCE MACROMODELING OF ANALOG CIRCUITS. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1195585950

Chicago Manual of Style (16^th Edition):

KOMMINENI, BALAJI. “SPLINE CENTER AND RANGE REGRESSION TECHNIQUE AND ITS APPLICATION TO VARIATION AWARE PERFORMANCE MACROMODELING OF ANALOG CIRCUITS.” 2007. Masters Thesis, University of Cincinnati. Accessed January 27, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1195585950.

MLA Handbook (7^th Edition):

KOMMINENI, BALAJI. “SPLINE CENTER AND RANGE REGRESSION TECHNIQUE AND ITS APPLICATION TO VARIATION AWARE PERFORMANCE MACROMODELING OF ANALOG CIRCUITS.” 2007. Web. 27 Jan 2021.

Vancouver:

KOMMINENI B. SPLINE CENTER AND RANGE REGRESSION TECHNIQUE AND ITS APPLICATION TO VARIATION AWARE PERFORMANCE MACROMODELING OF ANALOG CIRCUITS. [Internet] [Masters thesis]. University of Cincinnati; 2007. [cited 2021 Jan 27]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1195585950.

Council of Science Editors:

KOMMINENI B. SPLINE CENTER AND RANGE REGRESSION TECHNIQUE AND ITS APPLICATION TO VARIATION AWARE PERFORMANCE MACROMODELING OF ANALOG CIRCUITS. [Masters Thesis]. University of Cincinnati; 2007. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1195585950

University of Cincinnati

20. Sethuraman, Balasubramanian. Novel Methodologies for Efficient Networks-on-Chip Implementation on Reconfigurable Devices.

Degree: PhD, Engineering : Computer Science and Engineering, 2007, University of Cincinnati

URL: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1196043683

► International Technology Roadmap for Semiconductors (ITRS) project the latest trend moving towards a system-level and platform-based design, involving large percentage of design reuse. Different Intellectual… (more)

▼ International Technology Roadmap for Semiconductors (ITRS) project the latest trend moving towards a system-level and platform-based design, involving large percentage of design reuse. Different Intellectual Property (IP) cores, including processor and memory, are interconnected to build a typical System-on-Chip (SoC) architectures. Larger SoC designs dictate the data communication to happen over the global interconnects. At 45 nm and below, interconnects have profound impact on the performance (and power), due to increased delays and cross-coupling from multiple sources. Hence, attaining timing closure with reasonable performance and low power is increasingly becoming impractical. Also, the traditional bus based interconnection architectures present synchronization nightmare in a heterogenous System-on-Chip environment. At system level, the performance of the shared-bus start to deteriorate with increased number of cores. Networks-on-chip (NoC) has been proposed as a new design paradigm to solve the communication and performance bottlenecks in the modern System-on-Chip designs. Unlike the shared-bus approach, the central idea in an NoC is to implement interconnection of various IP cores using on-chip packet-switched networks. Due to reduced development costs and shorter design cycles and Time-To-Market, reconfigurable devices, especially, the FPGAs are increasingly being used in low/medium volume applications in place of their ASIC counterparts. Due to the scalability issues present in the use of shared-bus, NoC is gaining attention in the latest FPGA-based SoCs. In spite of the advantages, being a typical shared network, an NoC suffers from bottlenecks involving hop latency, congestion, bandwidth violations and increased area. In this thesis, we innovate and implement novelty to realize efficient Networks-on-Chip using commercial Xilinx FPGAs. We present tangible solutions for the issues that plague the efficient Networks-on-Chip implementation on the reconfigurable fabric. First, we concentrate this area overhead issue, the solutions to which actually resulted in many-fold advantages. Area is at a premium on an FPGA and therefore, the communication network should be as small as possible. The on-chip micro network area can be reduced by: (1) Using a simple router without sacrificing on the performance, and (2) Reducing the number of routers. Implementing the first idea, we develop a light weight parallel router (LiPaR), with multiple optimizations that resulted in a significant reduction logic area usage. The highlight of this dissertation remains in the translation of the second idea with the proposition of a novel router design that can handle multiple logic cores simultaneously, without any performance penalty. The new Multi Local Port Router (MLPR) provided many-fold advantages including reduction in area, power, transit time & congestion, and most importantly, bandwidth optimization, resulting in an efficient and high performance NoC design. Essentially, the MLPR is a marriage between switch-based and… Advisors/Committee Members: Vemuri, Dr. Ranga (Advisor).

Subjects/Keywords: Networks-on-Chip (NoC); System-on-Chip (SoC); FPGA; Reconfigurable and Platform-Based Design; Light Weight Router Design; Multi Local Port Router; Multicast Router; Low Power Topology Generation and Mapping; Power Issues and IR drop Analysis

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Sethuraman, B. (2007). Novel Methodologies for Efficient Networks-on-Chip Implementation on Reconfigurable Devices. (Doctoral Dissertation). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1196043683

Chicago Manual of Style (16^th Edition):

Sethuraman, Balasubramanian. “Novel Methodologies for Efficient Networks-on-Chip Implementation on Reconfigurable Devices.” 2007. Doctoral Dissertation, University of Cincinnati. Accessed January 27, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1196043683.

MLA Handbook (7^th Edition):

Sethuraman, Balasubramanian. “Novel Methodologies for Efficient Networks-on-Chip Implementation on Reconfigurable Devices.” 2007. Web. 27 Jan 2021.

Vancouver:

Sethuraman B. Novel Methodologies for Efficient Networks-on-Chip Implementation on Reconfigurable Devices. [Internet] [Doctoral dissertation]. University of Cincinnati; 2007. [cited 2021 Jan 27]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1196043683.

Council of Science Editors:

Sethuraman B. Novel Methodologies for Efficient Networks-on-Chip Implementation on Reconfigurable Devices. [Doctoral Dissertation]. University of Cincinnati; 2007. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1196043683

University of Cincinnati

21. RAGUPATHY, MANOJ KUMAR. SWITCH LEVEL SIMULATION IN THE PRESENCE OF UNCERTAINTIES.

Degree: MS, Engineering : Computer Engineering, 2008, University of Cincinnati

URL: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1201512323

► Process variation plays a critical role in the nanometer era. There has been an increasing trend to consider the effects of process variation during the… (more)

Subjects/Keywords: switch-level; IRSIM; interval arithmetic; affine arithmetic

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APA (6^th Edition):

RAGUPATHY, M. K. (2008). SWITCH LEVEL SIMULATION IN THE PRESENCE OF UNCERTAINTIES. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1201512323

Chicago Manual of Style (16^th Edition):

RAGUPATHY, MANOJ KUMAR. “SWITCH LEVEL SIMULATION IN THE PRESENCE OF UNCERTAINTIES.” 2008. Masters Thesis, University of Cincinnati. Accessed January 27, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1201512323.

MLA Handbook (7^th Edition):

RAGUPATHY, MANOJ KUMAR. “SWITCH LEVEL SIMULATION IN THE PRESENCE OF UNCERTAINTIES.” 2008. Web. 27 Jan 2021.

Vancouver:

RAGUPATHY MK. SWITCH LEVEL SIMULATION IN THE PRESENCE OF UNCERTAINTIES. [Internet] [Masters thesis]. University of Cincinnati; 2008. [cited 2021 Jan 27]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1201512323.

Council of Science Editors:

RAGUPATHY MK. SWITCH LEVEL SIMULATION IN THE PRESENCE OF UNCERTAINTIES. [Masters Thesis]. University of Cincinnati; 2008. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1201512323

University of Cincinnati

22. KASAM, SUMAN. FORMAL VERIFICATION OF TIME CONSTRAINED UAV TASK ALLOCATION USING MODEL-CHECKING.

Degree: MS, Engineering : Computer Engineering, 2008, University of Cincinnati

URL: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1201537607

► Real-time constrained systems are part of the everyday life. These are computer systems subjected to timing constraints along with non-timing constraints. They can be found… (more)

▼ Real-time constrained systems are part of the everyday life. These are computer systems subjected to timing constraints along with non-timing constraints. They can be found in cars, aeroplanes, washing machines, toasters, chemical plants, power stations; anywhere that systems are used to control or interact with an environment where time is important. Many of them are safety critical systems where failure is unacceptable. Clearly, the need for reliable systems is critical. This reliability can be improved by exhaustive verifcation of the systems. Formal verifcation of real-time constrained systems has gained attention in the last few decades because of their efficiency in unveiling design errors not found by humans. However, formal verifcation methods are limited by their inability to control the state space explosion problem. The problem of state space explosion gets even more complex with timed systems. Numerous methods have been proposed to address the state space explosion problems with timed systems. However, existing techniques do not eliminate the problem of state space explosion, but mitigate the problem of state space explosion. For arger systems, the problem still persists. These real-time constrained systems include real-time constrained task allocation systems. Most of these real-time constrained task allocation problems are solved by modeling them as constrained optimization problems which use a set of constraint variables, linear constraint equations, and an optimization function. The problem of state space explosion is very high in such systems because of the large number of constraint variables. Thus, verifcation of such real-time constrained task allocation systems is still harder. In this thesis, we present a novel method to verify such real-time constrained task allocation systems using formal methods. The method verifies the task allocation (result) from the LP solver instead of the algorithms involved in the solver or the constraints. We then proposed techniques to divide the huge state space into smaller state spaces to solve the problem of state space explosion with large problems. Advisors/Committee Members: Vemuri, Dr. Ranga (Advisor).

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APA (6^th Edition):

KASAM, S. (2008). FORMAL VERIFICATION OF TIME CONSTRAINED UAV TASK ALLOCATION USING MODEL-CHECKING. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1201537607

Chicago Manual of Style (16^th Edition):

KASAM, SUMAN. “FORMAL VERIFICATION OF TIME CONSTRAINED UAV TASK ALLOCATION USING MODEL-CHECKING.” 2008. Masters Thesis, University of Cincinnati. Accessed January 27, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1201537607.

MLA Handbook (7^th Edition):

KASAM, SUMAN. “FORMAL VERIFICATION OF TIME CONSTRAINED UAV TASK ALLOCATION USING MODEL-CHECKING.” 2008. Web. 27 Jan 2021.

Vancouver:

KASAM S. FORMAL VERIFICATION OF TIME CONSTRAINED UAV TASK ALLOCATION USING MODEL-CHECKING. [Internet] [Masters thesis]. University of Cincinnati; 2008. [cited 2021 Jan 27]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1201537607.

Council of Science Editors:

KASAM S. FORMAL VERIFICATION OF TIME CONSTRAINED UAV TASK ALLOCATION USING MODEL-CHECKING. [Masters Thesis]. University of Cincinnati; 2008. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1201537607

University of Cincinnati

23. MANSOURI, NAZANIN. AUTOMATED CORRECTNESS CONDITION GENERATION FOR FORMAL VERIFICATION OF SYNTHESIZED RTL DESIGNS.

Degree: PhD, Engineering : Computer Engineering, 2001, University of Cincinnati

URL: http://rave.ohiolink.edu/etdc/view?acc_num=ucin982064542

► This work presents a formal methodology for verifying the functional correctness of synthesized register transfer level designs (RTL) generated by a high-level synthesis system. The… (more)

▼ This work presents a formal methodology for verifying the functional correctness of synthesized register transfer level designs (RTL) generated by a high-level synthesis system. The verification is conducted by proving the observation equivalence of the RTL design with a description of its desired behavior. High-level synthesis tools generate register transfer level designs from algorithmic behavioral specifications. The high-level synthesis process consists of dependency graph scheduling,function unit allocation, register allocation, interconnect allocation and controller generation tasks. Widely used algorithms for these tasks retain the overall control flow structure of the behavioral specification allowing code motion only within basic blocks. Further, high-level synthesis algorithms are in general oblivious to the mathematical properties of arithmetic and logic operators, selecting and sharing RTL library modules solely based on matching uninterpreted function symbols and constants. Many researchers have noted that these features of high-level synthesis algorithms can be exploited to develop efficient verification strategies for synthesized designs. This dissertation reports a verification methodology that effectively exploits these features to achieve efficient and fully automated verification of synthesized designs. Contributions of this research include formalization and formulation in higher-order logic in a theorem proving environment mathematical models for the synthesized register transfer level designs and their behavioral specifications and a set of sufficient correctness conditions for these designs. It presents an in depth study of pipelining in design synthesis, and identifies the complete set of correctness conditions for RTL designs generated through the synthesis processes that employ pipelining techniques. This method has been implemented in a verification tool (the correctness condition generator, CCG) and is integrated with a high-level synthesis system. CCG generates (1) formal specifications of the behavior and the RTL design including the data path and the controller, (2) the correctness lemmas establishing equivalence between the synthesized RTL design and its behavioral specification, and (3) their proof scripts that can be submitted to a higher-order logic proof checker. The tool performs model extraction, correctness condition generation and proof generation automatically and without human interaction. This approach is based on the identification, by the synthesis tool during the synthesis process, of the binding between critical specification variables and criticalregisters in the RTL design and between the critical states in the behavior and the corresponding states in the RTL design. CCG is capable of handling a broad range of behavior constructs that may be used for specifying the behavior and a wide variety of algorithms that may be employed during the synthesis process. Also, the verification algorithms of CCG have the appealing feature of relying on symbolic analysis of the… Advisors/Committee Members: Vemuri, Dr. Ranga (Advisor).

Subjects/Keywords: formal verification; register transfer level (RTL); High-level synthesis; correctness conditions

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

MANSOURI, N. (2001). AUTOMATED CORRECTNESS CONDITION GENERATION FOR FORMAL VERIFICATION OF SYNTHESIZED RTL DESIGNS. (Doctoral Dissertation). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin982064542

Chicago Manual of Style (16^th Edition):

MANSOURI, NAZANIN. “AUTOMATED CORRECTNESS CONDITION GENERATION FOR FORMAL VERIFICATION OF SYNTHESIZED RTL DESIGNS.” 2001. Doctoral Dissertation, University of Cincinnati. Accessed January 27, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin982064542.

MLA Handbook (7^th Edition):

MANSOURI, NAZANIN. “AUTOMATED CORRECTNESS CONDITION GENERATION FOR FORMAL VERIFICATION OF SYNTHESIZED RTL DESIGNS.” 2001. Web. 27 Jan 2021.

Vancouver:

MANSOURI N. AUTOMATED CORRECTNESS CONDITION GENERATION FOR FORMAL VERIFICATION OF SYNTHESIZED RTL DESIGNS. [Internet] [Doctoral dissertation]. University of Cincinnati; 2001. [cited 2021 Jan 27]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin982064542.

Council of Science Editors:

MANSOURI N. AUTOMATED CORRECTNESS CONDITION GENERATION FOR FORMAL VERIFICATION OF SYNTHESIZED RTL DESIGNS. [Doctoral Dissertation]. University of Cincinnati; 2001. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin982064542

University of Cincinnati

24. KASAT, AMIT. MEMORY SYNTHESIS FOR FPGA-BASED RECONFIGURABLE COMPUTERS.

Degree: MS, Engineering : Computer Engineering, 2001, University of Cincinnati

URL: http://rave.ohiolink.edu/etdc/view?acc_num=ucin988222220

► A design executing on Reconfigurable Computer (RC) typically reads from and writes to physical memories on the RC. For data intensive applications like Digital Signal… (more)

▼ A design executing on Reconfigurable Computer (RC) typically reads from and writes to physical memories on the RC. For data intensive applications like Digital Signal Processing (DSP), Image Processing, Pattern Recognition, etc. memory reads and writes constitute a large portion of the total design execution time. With the advent of on-chip memories available on various FPGA devices, a complete hierarchy of physical memories is now available on a RC. Different types of memories provide different access latencies, storage capacities, multiple ports etc. An intelligent usage of these memories can lead to significant improvement in the read/write latency of the design. Most automated synthesis tools targeted for RCs do a trivial form of memory mapping, which does not make use of this memory hierarchy. In order to exploit the memory hierarchy, more sophisticated logic partitioning and memory mapping tools arerequired. This thesis presents an automated memory mapping methodology during high level synthesis flow. By memory mapping, we mean performing a detailed assignment of various data structures, which are part of thedesign, to the physical memories available on the RC. We use TabuSearch meta-heuristic to find a good mapping for various logical memories of the design onto physical memories available on the RC. We present a heuristic, called Rectangle Carving, to map a single logical memory onto the RC. Tabu search calls this heuristic at every iteration to get new solutions. To ensure correct functionality for the memory mapping, additional control logic is required. This logic is used to resolve potential memory access conflicts, and to make the details of memory mapping transparent to the accessing logic, thus keeping the implementation of the logic independent of memory mapping. Quality of memory mapping is closely related to the way logic partitioning is done on the board. We present an integrated methodology to perform both logic partitioning and memory mapping together. A tabu search formulation is used to do the task. This helps in getting good overall design mapping in very little time. The execution time of the tool on benchmark examples is found to be very small. For design containing 100 logical memories, the stand alone memory mapper took less than 150 seconds. The heuristic is produces results within 3.5 % of the near optimal results produced by the ILP-approach. The spatial partitioner took less than 800 seconds for designs having 100 compute tasks and 100 logical memories. Advisors/Committee Members: Vemuri, Dr. Ranga (Advisor).

Subjects/Keywords: FPGA; Memory Synthesis; On-chip RAM; Reconfigurable computers; Logic partitioning

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

KASAT, A. (2001). MEMORY SYNTHESIS FOR FPGA-BASED RECONFIGURABLE COMPUTERS. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin988222220

Chicago Manual of Style (16^th Edition):

KASAT, AMIT. “MEMORY SYNTHESIS FOR FPGA-BASED RECONFIGURABLE COMPUTERS.” 2001. Masters Thesis, University of Cincinnati. Accessed January 27, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin988222220.

MLA Handbook (7^th Edition):

KASAT, AMIT. “MEMORY SYNTHESIS FOR FPGA-BASED RECONFIGURABLE COMPUTERS.” 2001. Web. 27 Jan 2021.

Vancouver:

KASAT A. MEMORY SYNTHESIS FOR FPGA-BASED RECONFIGURABLE COMPUTERS. [Internet] [Masters thesis]. University of Cincinnati; 2001. [cited 2021 Jan 27]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin988222220.

Council of Science Editors:

KASAT A. MEMORY SYNTHESIS FOR FPGA-BASED RECONFIGURABLE COMPUTERS. [Masters Thesis]. University of Cincinnati; 2001. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin988222220

University of Cincinnati

25. MUKHERJEE, MADHUBANTI. ALGORITHMS FOR COUPLING CIRCUIT AND PHYSICAL SYNTHESIS WITH HIGH-LEVEL DESIGN-SPACE EXPLORATION FOR 2D AND 3D SYSTEMS.

Degree: PhD, Engineering : Computer Science and Engineering, 2004, University of Cincinnati

URL: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1112670784

► With increasing complexity and size of VLSI systems, RTL can no longer be a viable design entry point. On the other hand, higher levels of… (more)

▼ With increasing complexity and size of VLSI systems, RTL can no longer be a viable design entry point. On the other hand, higher levels of abstraction takes the design description farther away from the physical characteristics of the system, making valuable, and necessary information unavailable to the synthesis process leading to problems in achieving design convergence. This work addresses three significant problems in providing a direct link to circuit and physical synthesis during high level design space exploration. (1) Developing methodologies for coupling circuit synthesis with high level synthesis design-space exploration for the design of high performance DSP designs, (2) Developing algorithms to couple high level synthesis with physical synthesis by performing incremental placement during high level synthesis design-space exploration, (3) Developing algorithms to couple high level synthesis and physical synthesis for vertically integrated 3D systems by performing simultaneous scheduling, binding and layer assignment for resources; and finding the best possible methodology for the performance optimization in terms of interconnect lengths in the critical path and inter-layer vias. Unlike previous research efforts that concentrate on obtaining estimates, our work aims at directly coupling high level synthesis decisions with circuit and layout synthesis. The proposed approaches allow us to examine larger design spaces to synthesize better designs, which would otherwise be pruned by a top-down synthesis flow.To leverage circuit level optimizations during high level design space exploration, we propose a methodology for performing on-demand resource topology modification using partial evaluation for constant operands during synthesis of application specific DSP circuits. We also propose a methodology to perform on-demand resizing of resources for the generation of constraint satisfying RTL at the end of behavioral synthesis. In order to integrate physical synthesis during high level exploration, we propose a methodology to perform incremental global placement in a high level synthesis framework. The high level exploration system uses a delay budget driven incremental placement engine for the generation of constraint satisfying placed RTL structures. We also demonstrate the application of the placement methodology to account for resource resizing that changes resource dimensions impacting the physical RTL structure and associated interconnect characteristics. We extend the scope of our work to address behavioral synthesis for vertically integrated three-dimensional systems and propose a methodology to perform physical-aware synthesis for these systems. The emergence of three-dimensional systems has provided novel avenues for miniaturization; delay and power minimization. We propose a methodology to perform simultaneous scheduling, binding and layer assignment for vertically integrated three dimensional systems. By choosing judicious cost functions, both the inter-layer vias and the total length of interconnects in… Advisors/Committee Members: Vemuri, Dr. Ranga (Advisor).

Subjects/Keywords: Computer Science; Physical-aware High Level Synthesis; Design-space exploration; Vertically Integrated 3D Systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

MUKHERJEE, M. (2004). ALGORITHMS FOR COUPLING CIRCUIT AND PHYSICAL SYNTHESIS WITH HIGH-LEVEL DESIGN-SPACE EXPLORATION FOR 2D AND 3D SYSTEMS. (Doctoral Dissertation). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1112670784

Chicago Manual of Style (16^th Edition):

MUKHERJEE, MADHUBANTI. “ALGORITHMS FOR COUPLING CIRCUIT AND PHYSICAL SYNTHESIS WITH HIGH-LEVEL DESIGN-SPACE EXPLORATION FOR 2D AND 3D SYSTEMS.” 2004. Doctoral Dissertation, University of Cincinnati. Accessed January 27, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1112670784.

MLA Handbook (7^th Edition):

MUKHERJEE, MADHUBANTI. “ALGORITHMS FOR COUPLING CIRCUIT AND PHYSICAL SYNTHESIS WITH HIGH-LEVEL DESIGN-SPACE EXPLORATION FOR 2D AND 3D SYSTEMS.” 2004. Web. 27 Jan 2021.

Vancouver:

MUKHERJEE M. ALGORITHMS FOR COUPLING CIRCUIT AND PHYSICAL SYNTHESIS WITH HIGH-LEVEL DESIGN-SPACE EXPLORATION FOR 2D AND 3D SYSTEMS. [Internet] [Doctoral dissertation]. University of Cincinnati; 2004. [cited 2021 Jan 27]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1112670784.

Council of Science Editors:

MUKHERJEE M. ALGORITHMS FOR COUPLING CIRCUIT AND PHYSICAL SYNTHESIS WITH HIGH-LEVEL DESIGN-SPACE EXPLORATION FOR 2D AND 3D SYSTEMS. [Doctoral Dissertation]. University of Cincinnati; 2004. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1112670784

University of Cincinnati

26. GANESAN, SREELAKSHMI. SYNTHESIS OF MIXED-SIGNAL SYSTEMS BASED ON RAPID PROTOTYPING.

Degree: PhD, Engineering : Computer Engineering, 2001, University of Cincinnati

URL: http://rave.ohiolink.edu/etdc/view?acc_num=ucin988815041

► This dissertation presents a methodology for behavioral synthesis of analog and mixed signal systems based on rapid prototyping followed by technology retargeting. Rapid prototyping with… (more)

▼ This dissertation presents a methodology for behavioral synthesis of analog and mixed signal systems based on rapid prototyping followed by technology retargeting. Rapid prototyping with field-programmable devices enables fast implementation of a function-compliant hardware prototype, while technology retargeting converts the functional prototype to an ASIC. The synthesis environment comprises of field-programmable mixed-signal prototyping hardware integrated with the design tools for automated synthesis of mixed-signal systems from high-level behavioral specifications. The prototyping system is composed of field-programmable analog arrays (FPAAs) and field-programmable gate arrays (FPGAs) on which the synthesized designs are implemented and validated. Mixed-signal synthesis begins with an abstract specification of the desired behavior or functionality of the system. This is represented in an intermediate format suitable for synthesis. Identification of the portions to be implemented in analog and digital domains follows. The partitioned design must best satisfy the system's architectural and performance constraints. And finally, the analog and digital subsystems are synthesized for the target FPAA and FPGA technologies respectively. Synthesis of mixed-signal designs from behavioral specifications must address analog-digital partitioning. We begin with the system behavior specified based on signal-/data- flow. Our intermediate format for representation, called the Mixed Signal Flow Graph, is based on the time-amplitude characterization of signals: (1) continuous time, continuous amplitude, (2) continuous time, discrete amplitude, (3) discrete-time, continuous amplitude, and (4) discrete time, discrete amplitude. The behavior in each domain is represented by a connected network of behavioral blocks. In this signal-/data-flow graph representation, nodes are composed of transfer function blocks for linear operations and nonlinear function blocks for nonlinear operations, and edges represent the signal flow. Edges that cross the domain boundaries have interface attributes to denote signal conversion between domains. We investigate the issues and present a technique for mixed-signal behavioral partitioning of signal-processing systems. The partitioner searches the mixed-signal design space, and determines the design points that satisfy constraints imposed by the target field-programmable mixed-signal architecture on available configurable resources, available data-converters, their resolution and speed, and I/O pins. The quality of the solutions is then evaluated based on two metrics, namely feasibility and performance cost. The former is a measure of the validity of the solution with respect to the architectural constraints. The latter measures the performance of the system based on bandwidth and noise. The behavior of an analog system is represented as a signal flow graph (SFG), where nodes represent operations (transfer functions and non-linear functions) on signals and edges represent signal flow. Library binding or… Advisors/Committee Members: Vemuri, Dr. Ranga (Advisor).

Subjects/Keywords: mixed-signal; synthesis of analog and mixed signal systems; rapid prototyping; field-programmable analog array (FPAA)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

GANESAN, S. (2001). SYNTHESIS OF MIXED-SIGNAL SYSTEMS BASED ON RAPID PROTOTYPING. (Doctoral Dissertation). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin988815041

Chicago Manual of Style (16^th Edition):

GANESAN, SREELAKSHMI. “SYNTHESIS OF MIXED-SIGNAL SYSTEMS BASED ON RAPID PROTOTYPING.” 2001. Doctoral Dissertation, University of Cincinnati. Accessed January 27, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin988815041.

MLA Handbook (7^th Edition):

GANESAN, SREELAKSHMI. “SYNTHESIS OF MIXED-SIGNAL SYSTEMS BASED ON RAPID PROTOTYPING.” 2001. Web. 27 Jan 2021.

Vancouver:

GANESAN S. SYNTHESIS OF MIXED-SIGNAL SYSTEMS BASED ON RAPID PROTOTYPING. [Internet] [Doctoral dissertation]. University of Cincinnati; 2001. [cited 2021 Jan 27]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin988815041.

Council of Science Editors:

GANESAN S. SYNTHESIS OF MIXED-SIGNAL SYSTEMS BASED ON RAPID PROTOTYPING. [Doctoral Dissertation]. University of Cincinnati; 2001. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin988815041

University of Cincinnati

27. CHATHA, KARAMVIR SINGH. SYSTEM-LEVEL COSYNTHESIS OF TRANSFORMATIVE APPLICATIONS FOR HETEROGENEOUS HARDWARE-SOFTWARE ARCHITECTURES.

Degree: PhD, Engineering : Computer Science and Engineering, 2001, University of Cincinnati

URL: http://rave.ohiolink.edu/etdc/view?acc_num=ucin990822809

► Transformative applications are computationally intensive applications like image compression and decompression algorithms. Embedded system implementations of transformative applications typically consist of multiple hardware and software… (more)

▼ Transformative applications are computationally intensive applications like image compression and decompression algorithms. Embedded system implementations of transformative applications typically consist of multiple hardware and software processing elements. The objective of the research presented in this dissertation is to develop and implement innovative computer-aided design techniques for system-level cosynthesis of transformative applications for heterogeneous hardware-software architectures. As part of the research 1) a specification library, 2) an internal graph based format, and design tools for 3) latency minimization and 4) throughput maximization are developed. The specification library, graph format and optimization tools are encased in a system-level design environment called STELLAR. This dissertation presents the STELLAR environment for system-level hardware-software cosynthesis of transformative applications.The specification library called NOVA is based on an object-oriented approach and contains a collection of C++ classes.NOVA provides classes for specification of functionality, architecture and performance constraints. NOVA models the application functionality as a hierarchical, control and dataflow based task graph. It is an executable specification that can be functionally verified after compilation with the standard gcc compiler. NOVA provides constructs for specifying latency and throughput constraints on the application. It also provides constructs for specifying the system architecture that can include general purpose software processors, field programmable gate arrays, application specific integrated circuits and memory elements. The library supports specification of area constraints, reconfiguration times, memory sizes and memory widths of the various architecture elements. The internal graph format called NEBULA is derived from the NOVA specification. NEBULA captures the essential behavioral, structural and performance information of the application that is relevant for system-level optimization. The latency minimization tool called MAGELLAN and throughput maximization tool called ULYSSES are heuristic approaches for mapping the hierarchical control and dataflow based task graphs on heterogeneous architecture templates. MAGELLAN uses an iterative technique of closely linked hardware-software partitioning and scheduling. ULYSSES includes retiming transformation along with partitioning and scheduling. Both of them apply the partitioner and scheduler in a hierarchical top down manner. They optimize deterministic loop constructs by applying clustering, unrolling and pipelining. The number of actual hardware/software implementations of a function call in the task graph are optimized by resource sharing. MAGELLAN also considers speculative execution for conditional constructs. The techniques are validated by extensive experimentation with a realistic application. Additionally the quality of the results is evaluated by comparing with optimal approaches. Experiments are also conducted with… Advisors/Committee Members: Vemuri, Dr. Ranga (Advisor).

Subjects/Keywords: system-level design; hardware-software cosynthesis; hardware-software partitioning; pipelined scheduling; retiming transformation

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

CHATHA, K. S. (2001). SYSTEM-LEVEL COSYNTHESIS OF TRANSFORMATIVE APPLICATIONS FOR HETEROGENEOUS HARDWARE-SOFTWARE ARCHITECTURES. (Doctoral Dissertation). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin990822809

Chicago Manual of Style (16^th Edition):

CHATHA, KARAMVIR SINGH. “SYSTEM-LEVEL COSYNTHESIS OF TRANSFORMATIVE APPLICATIONS FOR HETEROGENEOUS HARDWARE-SOFTWARE ARCHITECTURES.” 2001. Doctoral Dissertation, University of Cincinnati. Accessed January 27, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin990822809.

MLA Handbook (7^th Edition):

CHATHA, KARAMVIR SINGH. “SYSTEM-LEVEL COSYNTHESIS OF TRANSFORMATIVE APPLICATIONS FOR HETEROGENEOUS HARDWARE-SOFTWARE ARCHITECTURES.” 2001. Web. 27 Jan 2021.

Vancouver:

CHATHA KS. SYSTEM-LEVEL COSYNTHESIS OF TRANSFORMATIVE APPLICATIONS FOR HETEROGENEOUS HARDWARE-SOFTWARE ARCHITECTURES. [Internet] [Doctoral dissertation]. University of Cincinnati; 2001. [cited 2021 Jan 27]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin990822809.

Council of Science Editors:

CHATHA KS. SYSTEM-LEVEL COSYNTHESIS OF TRANSFORMATIVE APPLICATIONS FOR HETEROGENEOUS HARDWARE-SOFTWARE ARCHITECTURES. [Doctoral Dissertation]. University of Cincinnati; 2001. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin990822809

University of Cincinnati

28. TEICA, ELENA. FORMAL CORRECTNESS AND COMPLETENESS FOR A SET OF UNINTERPRETED RTL TRANSFORMATIONS.

Degree: PhD, Engineering : Computer Science and Engineering, 2001, University of Cincinnati

URL: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1001432470

► The work presented in this thesis is concerned with the correctness of the high-level synthesis process. In particular, it addresses transformational derivation (TD) systems. TD… (more)

▼ The work presented in this thesis is concerned with the correctness of the high-level synthesis process. In particular, it addresses transformational derivation (TD) systems. TD denominates a class of synthesis techniques wherein a register transfer level (RTL) implementation is derived by applying a sequence of behavior-preserving transformations to an initial behavior representation. We present in this thesis a formal treatment of correctness and completeness for a set of ten uninterpreted register transfer level transformations on which a TD system can be based. The formal definitions for RTL transformations are based on an uninterpreted model for RTL designs corresponding to straight-line code behavior descriptions. Our model specifies an abstract RTL design as a set of properties asserted about abstract collections (sets) of components (operators and registers). RTL transformations are functions operating on elements of the set defined by these properties, and the completeness property is a higher-order predicate that defines a complete set of functions. The specification and proof exercise are conducted in the Prototype Verification System (PVS). The use of PVS for the formal treatment presented in this thesis is justified not only by the typed higher-order logic that underlies its specification and proving environment (required by the very nature of the problem we are dealing with), but also by its rich language constructs that allow expressive and efficient specifications. As an alternative to an error prone axiomatic approach, each transformation is specified in a definitional manner. The correctness of each transformation is defined as the behavior preserving property: a transformation is correct if the extracted computational behavior of the output registers is the same in the initial and in the transformed design. Each transformation is mechanically proved correct in PVS based on the assumption that a set of preconditions is satisfied. A finite set of correct RTL transformations is said to be complete if and only if for any two RTL designs that implement the same behavior description, one design can be derived from the other by applying a finite sequence of transformations contained in this set. In other words, any possible implementation of a given behavior can be synthesized by applying only certain transformations to an initial implementation. We formalized and mechanically proved in PVS the completeness property using a constructive approach. The proof is constructive in the sense that a finite sequence of ransformations (belonging to the complete set), that transforms a certain design implementation into another one having the same behavior, is algorithmically defined. Some of the practical uses of the theoretical results formally established are: 1. A transformational derivation synthesis system based on the core set of RTL transformations presented here will yield correct-by-construction designs (if correctly implemented). The completeness property of this set ensures a virtually exhaustive search… Advisors/Committee Members: Vemuri, Dr. Ranga (Advisor).

Subjects/Keywords: RTL Transformations; Formal Synthesis; Correctness Behavior Preserving Completeness; Mechanized in Higher-Order Logics of PVS

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

TEICA, E. (2001). FORMAL CORRECTNESS AND COMPLETENESS FOR A SET OF UNINTERPRETED RTL TRANSFORMATIONS. (Doctoral Dissertation). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1001432470

Chicago Manual of Style (16^th Edition):

TEICA, ELENA. “FORMAL CORRECTNESS AND COMPLETENESS FOR A SET OF UNINTERPRETED RTL TRANSFORMATIONS.” 2001. Doctoral Dissertation, University of Cincinnati. Accessed January 27, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1001432470.

MLA Handbook (7^th Edition):

TEICA, ELENA. “FORMAL CORRECTNESS AND COMPLETENESS FOR A SET OF UNINTERPRETED RTL TRANSFORMATIONS.” 2001. Web. 27 Jan 2021.

Vancouver:

TEICA E. FORMAL CORRECTNESS AND COMPLETENESS FOR A SET OF UNINTERPRETED RTL TRANSFORMATIONS. [Internet] [Doctoral dissertation]. University of Cincinnati; 2001. [cited 2021 Jan 27]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1001432470.

Council of Science Editors:

TEICA E. FORMAL CORRECTNESS AND COMPLETENESS FOR A SET OF UNINTERPRETED RTL TRANSFORMATIONS. [Doctoral Dissertation]. University of Cincinnati; 2001. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1001432470

University of Cincinnati

29. SIVA, SUBRAMANYAN D. APPLICATIONS OF SATISFIABILITY IN SYNTHESIS OF RECONFIGURABLE COMPUTERS.

Degree: MS, Engineering : Computer Engineering, 2002, University of Cincinnati

URL: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1022761893

► This thesis addresses applications of satisfiability techniques in a reconfigurable computer (RC) synthesis framework. The two areas explored are the interconnect synthesis problem and the… (more)

▼ This thesis addresses applications of satisfiability techniques in a reconfigurable computer (RC) synthesis framework. The two areas explored are the interconnect synthesis problem and the verification of synthesized register transfer level (RTL) designs. Traditionally, binary decision diagrams (BDD), an efficient canonical form for boolean expressions, have been applied to these problems. The disadvantage was the need of a good variable ordering to solve the problem efficiently. Most reconfigurable field programmable gate array (FPGA) architectures have programmable interconnection networks that can be reconfigured to implement various interconnection patterns among the FPGA's on the board. Partitioning tools for such architectures must produce the necessary interconnect configuration. This process is called Interconnect Synthesis. In our research, interconnect synthesis is based on a boolean satisfiability solver (SAT) using the Impulse Response technique. An appropriate methodology is needed to hierarchically specify the target interconnection network. An architecture description language called the Performance Description Language (PDL+), is used as the front end tool for modeling reconfigurable processors. These models are then elaborated in a symbolic environment called the Analyzer of Reconfigurable Computer (ARC). Boolean SAT solvers guarantee routing, if one exists. The results of SAT solvers are verified by feeding the obtained values back into the symbolic environment. Interconnect synthesis is performed on Wildforce and Corel RC processors. Grasp, Sato and Chaff solvers have been used. Experimental results show that large interconnect synthesis problems can be solved using SAT solvers and that Chaff has superior performance than the other solvers. In a high-level synthesis (HLS) flow, the behavioral specification in VHDL is subjected to scheduling, binding, interconnect and controller generation to obtain a register-transfer-level (RTL) design. In a successful design methodology, it is essential to verify the RTL design against its original specification. Traditionally, the task of verification is carried by simulation. This process is highly time intensive and it is not feasible to exhaustively simulate a design to guarantee its correctness. Formal verification attempts to establish universal properties about the design, independent of any particular set of inputs. In this thesis, synthesized RTL designs are verified using a SAT solver. This is to check whether the synthesis tool has generated a correct data path and controller. Data path verification is known as the combinational equivalence checking (CEC) problem. Experimental results show that as the bit size increase, the problem becomes hard and the SAT solver execution time is found to be large. It is observed that Chaff is the fastest of the three solvers. Also, the module concept is introduced for data-path verification. Controller verification is based on uninterpreted symbolic simulation procedure. The execution time on the benchmark examples… Advisors/Committee Members: Vemuri, Dr. Ranga (Advisor).

Subjects/Keywords: satisfiability; reconfigurable-computer; interconnect synthesis; high level synthesis; sat-solver

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

SIVA, S. D. (2002). APPLICATIONS OF SATISFIABILITY IN SYNTHESIS OF RECONFIGURABLE COMPUTERS. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1022761893

Chicago Manual of Style (16^th Edition):

SIVA, SUBRAMANYAN D. “APPLICATIONS OF SATISFIABILITY IN SYNTHESIS OF RECONFIGURABLE COMPUTERS.” 2002. Masters Thesis, University of Cincinnati. Accessed January 27, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1022761893.

MLA Handbook (7^th Edition):

SIVA, SUBRAMANYAN D. “APPLICATIONS OF SATISFIABILITY IN SYNTHESIS OF RECONFIGURABLE COMPUTERS.” 2002. Web. 27 Jan 2021.

Vancouver:

SIVA SD. APPLICATIONS OF SATISFIABILITY IN SYNTHESIS OF RECONFIGURABLE COMPUTERS. [Internet] [Masters thesis]. University of Cincinnati; 2002. [cited 2021 Jan 27]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1022761893.

Council of Science Editors:

SIVA SD. APPLICATIONS OF SATISFIABILITY IN SYNTHESIS OF RECONFIGURABLE COMPUTERS. [Masters Thesis]. University of Cincinnati; 2002. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1022761893

University of Cincinnati

30. KHAN, JAWAD BASIT. iPACE-V1: A PORTAABLE ADAPTIVE COMPUTING ENGINE.

Degree: MS, Engineering : Computer Engineering, 2002, University of Cincinnati

URL: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1025721991

► The iPACE-V1 (Image Processing Adaptive Computing Engine) is a portable, reconfigurable hardware platform, designed in the Digital Design Environments Laboratory at the University of Cincinnati.… (more)

▼ The iPACE-V1 (Image Processing Adaptive Computing Engine) is a portable, reconfigurable hardware platform, designed in the Digital Design Environments Laboratory at the University of Cincinnati. iPACE-V1 was specifically designed for real time, in-field image processing applications. Adaptive computing systems can be broadly defined as those systems which can modify their digital hardware to match the requirements of an application at hand. Field Programmable Gate Arrays (FPGA) are essential building blocks of such systems. iPACE-V1 has three Xilinx Virtex FPGAs: one houses the controller module, another acts as the main user programmable module and the data capture module is implemented in the last one. A maximum of 800,000 logic gates are available for computing in the form of FPGAs. Furthermore, 4 Mbytes of ZBT (Zero Bus turnaround) SRAM is interfaced. In addition to this, the board has a maximum of 1 Gigabytes SDRAM capacity. For non volatile data storage we have provided 4 Mbytes of FLASH ROM. Two serial ports along with a USB port are also provided. A camera is attached which provides video data and a small LCD is interfaced for image output. Every effort was made to incorporate as many debugging features, as possible: programmable clock, observable memories, partial reconfiguration and FPGA read-back are some features which top this list. Several controller cores have been written for various subsystems in iPACE-V1. These cores enable the user to efficiently exploit the available resources. This thesis discusses the hardware architecture of iPACE-V1 along with the VHDL controller cores. We also show the functional correctness and effectiveness of iPACE-V1. We have developed two demonstration examples for iPACE-V1: A frame grabber and a background elimination application. The frame grabber is implemented to demonstrate the functional correctness of the hardware. Whereas, the background elimination application is more performance oriented and is used to show the effectiveness of this architecture for realtime image processing. Advisors/Committee Members: Vemuri, Dr. Ranga (Advisor).

Subjects/Keywords: Computer Science; reconfigurable computing; adaptive computing; FPGAs; mobile computing; image processing

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

KHAN, J. B. (2002). iPACE-V1: A PORTAABLE ADAPTIVE COMPUTING ENGINE. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1025721991

Chicago Manual of Style (16^th Edition):

KHAN, JAWAD BASIT. “iPACE-V1: A PORTAABLE ADAPTIVE COMPUTING ENGINE.” 2002. Masters Thesis, University of Cincinnati. Accessed January 27, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1025721991.

MLA Handbook (7^th Edition):

KHAN, JAWAD BASIT. “iPACE-V1: A PORTAABLE ADAPTIVE COMPUTING ENGINE.” 2002. Web. 27 Jan 2021.

Vancouver:

KHAN JB. iPACE-V1: A PORTAABLE ADAPTIVE COMPUTING ENGINE. [Internet] [Masters thesis]. University of Cincinnati; 2002. [cited 2021 Jan 27]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1025721991.

Council of Science Editors:

KHAN JB. iPACE-V1: A PORTAABLE ADAPTIVE COMPUTING ENGINE. [Masters Thesis]. University of Cincinnati; 2002. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1025721991

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