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You searched for +publisher:"University of Cincinnati" +contributor:("Vemuri, Dr. Ranga"). Showing records 1 – 30 of 41 total matches.

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University of Cincinnati

1. DASASATHYAN, SRINIVASAN. SYNTHESIS OF VIRTUAL PIPELINES ON VIRTEX-BASED FPGAs.

Degree: MS, Engineering : Computer Engineering, 2001, University of Cincinnati

 Partially reconfigurable devices have the ability to configure a portion of the device while the remaining portion of the device is still operational. This feature… (more)

Subjects/Keywords: partial reconfiguration; virtex based board; virtual pipeline; JHDL; SBLOX (serial blocks)

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APA (6th Edition):

DASASATHYAN, S. (2001). SYNTHESIS OF VIRTUAL PIPELINES ON VIRTEX-BASED FPGAs. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin990618529

Chicago Manual of Style (16th Edition):

DASASATHYAN, SRINIVASAN. “SYNTHESIS OF VIRTUAL PIPELINES ON VIRTEX-BASED FPGAs.” 2001. Masters Thesis, University of Cincinnati. Accessed January 27, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin990618529.

MLA Handbook (7th Edition):

DASASATHYAN, SRINIVASAN. “SYNTHESIS OF VIRTUAL PIPELINES ON VIRTEX-BASED FPGAs.” 2001. Web. 27 Jan 2021.

Vancouver:

DASASATHYAN S. SYNTHESIS OF VIRTUAL PIPELINES ON VIRTEX-BASED FPGAs. [Internet] [Masters thesis]. University of Cincinnati; 2001. [cited 2021 Jan 27]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin990618529.

Council of Science Editors:

DASASATHYAN S. SYNTHESIS OF VIRTUAL PIPELINES ON VIRTEX-BASED FPGAs. [Masters Thesis]. University of Cincinnati; 2001. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin990618529


University of Cincinnati

2. YELAMANCHILI, VEENA RAO. A SIMULATION AND PERFORMANCE ESTIMATION SYSTEM FOR ANALOG AND MIXED SIGNAL SYSTEMS.

Degree: MS, Engineering : Computer Engineering, 2003, University of Cincinnati

 High performance analog/mixed signal systems play a wide role in signal acquisition and conditioning for front and back end designs. Circuit designers have been developing… (more)

Subjects/Keywords: simulations; performance parameters; analog; circuits; analysis &; testing

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APA (6th Edition):

YELAMANCHILI, V. R. (2003). A SIMULATION AND PERFORMANCE ESTIMATION SYSTEM FOR ANALOG AND MIXED SIGNAL SYSTEMS. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1068671449

Chicago Manual of Style (16th Edition):

YELAMANCHILI, VEENA RAO. “A SIMULATION AND PERFORMANCE ESTIMATION SYSTEM FOR ANALOG AND MIXED SIGNAL SYSTEMS.” 2003. Masters Thesis, University of Cincinnati. Accessed January 27, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1068671449.

MLA Handbook (7th Edition):

YELAMANCHILI, VEENA RAO. “A SIMULATION AND PERFORMANCE ESTIMATION SYSTEM FOR ANALOG AND MIXED SIGNAL SYSTEMS.” 2003. Web. 27 Jan 2021.

Vancouver:

YELAMANCHILI VR. A SIMULATION AND PERFORMANCE ESTIMATION SYSTEM FOR ANALOG AND MIXED SIGNAL SYSTEMS. [Internet] [Masters thesis]. University of Cincinnati; 2003. [cited 2021 Jan 27]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1068671449.

Council of Science Editors:

YELAMANCHILI VR. A SIMULATION AND PERFORMANCE ESTIMATION SYSTEM FOR ANALOG AND MIXED SIGNAL SYSTEMS. [Masters Thesis]. University of Cincinnati; 2003. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1068671449


University of Cincinnati

3. BHADURI, AMITAVA. INDUCTIVE AND CAPACITIVE AWARE METHODOLOGIES FOR PHYSICAL AND CIRCUIT SYNTHESIS OF HIGH-SPEED DIGITAL AND RF CIRCUITS.

Degree: PhD, Engineering : Computer Science and Engineering, 2005, University of Cincinnati

 Computer-aided design in VLSI is a continuously evolving subject, with new algorithms and solutions constantly modifying the established norms in order to accommodate efficient strategies… (more)

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APA (6th Edition):

BHADURI, A. (2005). INDUCTIVE AND CAPACITIVE AWARE METHODOLOGIES FOR PHYSICAL AND CIRCUIT SYNTHESIS OF HIGH-SPEED DIGITAL AND RF CIRCUITS. (Doctoral Dissertation). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1129580425

Chicago Manual of Style (16th Edition):

BHADURI, AMITAVA. “INDUCTIVE AND CAPACITIVE AWARE METHODOLOGIES FOR PHYSICAL AND CIRCUIT SYNTHESIS OF HIGH-SPEED DIGITAL AND RF CIRCUITS.” 2005. Doctoral Dissertation, University of Cincinnati. Accessed January 27, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1129580425.

MLA Handbook (7th Edition):

BHADURI, AMITAVA. “INDUCTIVE AND CAPACITIVE AWARE METHODOLOGIES FOR PHYSICAL AND CIRCUIT SYNTHESIS OF HIGH-SPEED DIGITAL AND RF CIRCUITS.” 2005. Web. 27 Jan 2021.

Vancouver:

BHADURI A. INDUCTIVE AND CAPACITIVE AWARE METHODOLOGIES FOR PHYSICAL AND CIRCUIT SYNTHESIS OF HIGH-SPEED DIGITAL AND RF CIRCUITS. [Internet] [Doctoral dissertation]. University of Cincinnati; 2005. [cited 2021 Jan 27]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1129580425.

Council of Science Editors:

BHADURI A. INDUCTIVE AND CAPACITIVE AWARE METHODOLOGIES FOR PHYSICAL AND CIRCUIT SYNTHESIS OF HIGH-SPEED DIGITAL AND RF CIRCUITS. [Doctoral Dissertation]. University of Cincinnati; 2005. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1129580425


University of Cincinnati

4. RANJAN, MUKESH. AUTOMATED LAYOUT-INCLUSIVE SYNTHESIS OF ANALOG CIRCUITS USING SYMBOLIC PERFORMANCE MODELS.

Degree: PhD, Engineering : Computer Science and Engineering, 2005, University of Cincinnati

 A key task in the automated design of analog/RF circuits is circuit sizing, a process that involves assigning numerical values to unknown circuit parameters of… (more)

Subjects/Keywords: Computer Science; Analog Circuit Synthesis; Symbolic Analysis; Layout-Aware; Parasitic-Aware; Analog Design

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APA (6th Edition):

RANJAN, M. (2005). AUTOMATED LAYOUT-INCLUSIVE SYNTHESIS OF ANALOG CIRCUITS USING SYMBOLIC PERFORMANCE MODELS. (Doctoral Dissertation). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1129922496

Chicago Manual of Style (16th Edition):

RANJAN, MUKESH. “AUTOMATED LAYOUT-INCLUSIVE SYNTHESIS OF ANALOG CIRCUITS USING SYMBOLIC PERFORMANCE MODELS.” 2005. Doctoral Dissertation, University of Cincinnati. Accessed January 27, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1129922496.

MLA Handbook (7th Edition):

RANJAN, MUKESH. “AUTOMATED LAYOUT-INCLUSIVE SYNTHESIS OF ANALOG CIRCUITS USING SYMBOLIC PERFORMANCE MODELS.” 2005. Web. 27 Jan 2021.

Vancouver:

RANJAN M. AUTOMATED LAYOUT-INCLUSIVE SYNTHESIS OF ANALOG CIRCUITS USING SYMBOLIC PERFORMANCE MODELS. [Internet] [Doctoral dissertation]. University of Cincinnati; 2005. [cited 2021 Jan 27]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1129922496.

Council of Science Editors:

RANJAN M. AUTOMATED LAYOUT-INCLUSIVE SYNTHESIS OF ANALOG CIRCUITS USING SYMBOLIC PERFORMANCE MODELS. [Doctoral Dissertation]. University of Cincinnati; 2005. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1129922496


University of Cincinnati

5. BADAOUI, RAOUL. APPROACHES FOR PARASITIC-INCLUSIVE SYMBOLIC CIRCUIT REPRESENTATION AND EXTRACTION FOR SYNTHESIS.

Degree: PhD, Engineering : Computer Science and Engineering, 2005, University of Cincinnati

 Layout-induced parasitics have significant effects on the behavior of circuits in general and the performance of high-frequency analog ones in particular. To achieve parasite-inclusive performance-closure,… (more)

Subjects/Keywords: vlsi; analog vlsi; routing; placement; extraction; pre-layout extraction

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APA (6th Edition):

BADAOUI, R. (2005). APPROACHES FOR PARASITIC-INCLUSIVE SYMBOLIC CIRCUIT REPRESENTATION AND EXTRACTION FOR SYNTHESIS. (Doctoral Dissertation). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1132193275

Chicago Manual of Style (16th Edition):

BADAOUI, RAOUL. “APPROACHES FOR PARASITIC-INCLUSIVE SYMBOLIC CIRCUIT REPRESENTATION AND EXTRACTION FOR SYNTHESIS.” 2005. Doctoral Dissertation, University of Cincinnati. Accessed January 27, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1132193275.

MLA Handbook (7th Edition):

BADAOUI, RAOUL. “APPROACHES FOR PARASITIC-INCLUSIVE SYMBOLIC CIRCUIT REPRESENTATION AND EXTRACTION FOR SYNTHESIS.” 2005. Web. 27 Jan 2021.

Vancouver:

BADAOUI R. APPROACHES FOR PARASITIC-INCLUSIVE SYMBOLIC CIRCUIT REPRESENTATION AND EXTRACTION FOR SYNTHESIS. [Internet] [Doctoral dissertation]. University of Cincinnati; 2005. [cited 2021 Jan 27]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1132193275.

Council of Science Editors:

BADAOUI R. APPROACHES FOR PARASITIC-INCLUSIVE SYMBOLIC CIRCUIT REPRESENTATION AND EXTRACTION FOR SYNTHESIS. [Doctoral Dissertation]. University of Cincinnati; 2005. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1132193275


University of Cincinnati

6. AGARWAL, ANURADHA. ALGORITHMS FOR LAYOUT-AWARE AND PERFORMANCE MODEL DRIVEN SYNTHESIS OF ANALOG CIRCUITS.

Degree: PhD, Engineering : Computer Science and Engineering, 2005, University of Cincinnati

 With the ever increasing complexity of integrated circuits and constantly shrinking device sizes, the need to develop entire dystems on chip (SoC) has received a… (more)

Subjects/Keywords: Analog; Radio-frequency; Circuit Synthesis; Layout Parasitics; Performance Modeling; Parasitic Estimation and Modeling; Layout-Aware Synthesis; Circuit sizing; Parasitic Corners; Yield Optimization; Parasitic Capacitances; Dynamic Performance Macromodel

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APA (6th Edition):

AGARWAL, A. (2005). ALGORITHMS FOR LAYOUT-AWARE AND PERFORMANCE MODEL DRIVEN SYNTHESIS OF ANALOG CIRCUITS. (Doctoral Dissertation). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1132259454

Chicago Manual of Style (16th Edition):

AGARWAL, ANURADHA. “ALGORITHMS FOR LAYOUT-AWARE AND PERFORMANCE MODEL DRIVEN SYNTHESIS OF ANALOG CIRCUITS.” 2005. Doctoral Dissertation, University of Cincinnati. Accessed January 27, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1132259454.

MLA Handbook (7th Edition):

AGARWAL, ANURADHA. “ALGORITHMS FOR LAYOUT-AWARE AND PERFORMANCE MODEL DRIVEN SYNTHESIS OF ANALOG CIRCUITS.” 2005. Web. 27 Jan 2021.

Vancouver:

AGARWAL A. ALGORITHMS FOR LAYOUT-AWARE AND PERFORMANCE MODEL DRIVEN SYNTHESIS OF ANALOG CIRCUITS. [Internet] [Doctoral dissertation]. University of Cincinnati; 2005. [cited 2021 Jan 27]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1132259454.

Council of Science Editors:

AGARWAL A. ALGORITHMS FOR LAYOUT-AWARE AND PERFORMANCE MODEL DRIVEN SYNTHESIS OF ANALOG CIRCUITS. [Doctoral Dissertation]. University of Cincinnati; 2005. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1132259454


University of Cincinnati

7. KRISHNAN, AKHIL. HARDWARE IMPLEMENTATION OF A NOVEL ENCRYPTION ALGORITHM.

Degree: MS, Engineering : Computer Engineering, 2006, University of Cincinnati

 Multivariate cryptosystem is a novel cryptographic system which can offer very high security even for small key sizes. This particular feature makes this scheme very… (more)

Subjects/Keywords: cryptography; FPGA; multivariate cryptosystem; encryption hardware

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APA (6th Edition):

KRISHNAN, A. (2006). HARDWARE IMPLEMENTATION OF A NOVEL ENCRYPTION ALGORITHM. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1139462392

Chicago Manual of Style (16th Edition):

KRISHNAN, AKHIL. “HARDWARE IMPLEMENTATION OF A NOVEL ENCRYPTION ALGORITHM.” 2006. Masters Thesis, University of Cincinnati. Accessed January 27, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1139462392.

MLA Handbook (7th Edition):

KRISHNAN, AKHIL. “HARDWARE IMPLEMENTATION OF A NOVEL ENCRYPTION ALGORITHM.” 2006. Web. 27 Jan 2021.

Vancouver:

KRISHNAN A. HARDWARE IMPLEMENTATION OF A NOVEL ENCRYPTION ALGORITHM. [Internet] [Masters thesis]. University of Cincinnati; 2006. [cited 2021 Jan 27]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1139462392.

Council of Science Editors:

KRISHNAN A. HARDWARE IMPLEMENTATION OF A NOVEL ENCRYPTION ALGORITHM. [Masters Thesis]. University of Cincinnati; 2006. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1139462392


University of Cincinnati

8. BHATTACHARYA, PRASUN. COMPARISON OF SINGLE-PORT AND MULTI-PORT NoCs WITH CONTEMPORARY BUSES ON FPGAs.

Degree: MS, Engineering : Computer Engineering, 2006, University of Cincinnati

 Systems-on-chip brought several cores onto a single chip. But, as more cores are being put onto a single chip, the on-chip communication resource, which is… (more)

Subjects/Keywords: NoC; Routers; SoC; FPGA

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APA (6th Edition):

BHATTACHARYA, P. (2006). COMPARISON OF SINGLE-PORT AND MULTI-PORT NoCs WITH CONTEMPORARY BUSES ON FPGAs. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1142842819

Chicago Manual of Style (16th Edition):

BHATTACHARYA, PRASUN. “COMPARISON OF SINGLE-PORT AND MULTI-PORT NoCs WITH CONTEMPORARY BUSES ON FPGAs.” 2006. Masters Thesis, University of Cincinnati. Accessed January 27, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1142842819.

MLA Handbook (7th Edition):

BHATTACHARYA, PRASUN. “COMPARISON OF SINGLE-PORT AND MULTI-PORT NoCs WITH CONTEMPORARY BUSES ON FPGAs.” 2006. Web. 27 Jan 2021.

Vancouver:

BHATTACHARYA P. COMPARISON OF SINGLE-PORT AND MULTI-PORT NoCs WITH CONTEMPORARY BUSES ON FPGAs. [Internet] [Masters thesis]. University of Cincinnati; 2006. [cited 2021 Jan 27]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1142842819.

Council of Science Editors:

BHATTACHARYA P. COMPARISON OF SINGLE-PORT AND MULTI-PORT NoCs WITH CONTEMPORARY BUSES ON FPGAs. [Masters Thesis]. University of Cincinnati; 2006. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1142842819


University of Cincinnati

9. CHAKRABORTY, RITOCHIT. SYMBOLIC TIME DOMAIN BEHAVIOR AND PERFORMANCE ANALYSIS OF LINEAR ANALOG CIRCUITS.

Degree: MS, Engineering : Computer Engineering, 2006, University of Cincinnati

 Automated design of analog circuits involves circuit sizing, a process of assigning numerical values to unknown parameters of a fixed circuit topology. With the advent… (more)

Subjects/Keywords: Analog Circuit Synthesis; Symbolic Analysis; Symbolic Newton-Iteration; Pole Extraction

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APA (6th Edition):

CHAKRABORTY, R. (2006). SYMBOLIC TIME DOMAIN BEHAVIOR AND PERFORMANCE ANALYSIS OF LINEAR ANALOG CIRCUITS. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1145990101

Chicago Manual of Style (16th Edition):

CHAKRABORTY, RITOCHIT. “SYMBOLIC TIME DOMAIN BEHAVIOR AND PERFORMANCE ANALYSIS OF LINEAR ANALOG CIRCUITS.” 2006. Masters Thesis, University of Cincinnati. Accessed January 27, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1145990101.

MLA Handbook (7th Edition):

CHAKRABORTY, RITOCHIT. “SYMBOLIC TIME DOMAIN BEHAVIOR AND PERFORMANCE ANALYSIS OF LINEAR ANALOG CIRCUITS.” 2006. Web. 27 Jan 2021.

Vancouver:

CHAKRABORTY R. SYMBOLIC TIME DOMAIN BEHAVIOR AND PERFORMANCE ANALYSIS OF LINEAR ANALOG CIRCUITS. [Internet] [Masters thesis]. University of Cincinnati; 2006. [cited 2021 Jan 27]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1145990101.

Council of Science Editors:

CHAKRABORTY R. SYMBOLIC TIME DOMAIN BEHAVIOR AND PERFORMANCE ANALYSIS OF LINEAR ANALOG CIRCUITS. [Masters Thesis]. University of Cincinnati; 2006. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1145990101


University of Cincinnati

10. DING, MENGMENG. REGRESSION BASED ANALOG PERFORMANCE MACROMODELING: TECHNIQUES AND APPLICATIONS.

Degree: PhD, Engineering : Computer Science and Engineering, 2006, University of Cincinnati

 Optimization based analog circuit sizing opens a new page for computer aided design of analog integrated circuits. While differing in implementation details, the sizing tools… (more)

Subjects/Keywords: analog performance macromodeling; analog circuit sizing; adaptive sampling; active learning; regression; classification

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APA (6th Edition):

DING, M. (2006). REGRESSION BASED ANALOG PERFORMANCE MACROMODELING: TECHNIQUES AND APPLICATIONS. (Doctoral Dissertation). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1146145102

Chicago Manual of Style (16th Edition):

DING, MENGMENG. “REGRESSION BASED ANALOG PERFORMANCE MACROMODELING: TECHNIQUES AND APPLICATIONS.” 2006. Doctoral Dissertation, University of Cincinnati. Accessed January 27, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1146145102.

MLA Handbook (7th Edition):

DING, MENGMENG. “REGRESSION BASED ANALOG PERFORMANCE MACROMODELING: TECHNIQUES AND APPLICATIONS.” 2006. Web. 27 Jan 2021.

Vancouver:

DING M. REGRESSION BASED ANALOG PERFORMANCE MACROMODELING: TECHNIQUES AND APPLICATIONS. [Internet] [Doctoral dissertation]. University of Cincinnati; 2006. [cited 2021 Jan 27]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1146145102.

Council of Science Editors:

DING M. REGRESSION BASED ANALOG PERFORMANCE MACROMODELING: TECHNIQUES AND APPLICATIONS. [Doctoral Dissertation]. University of Cincinnati; 2006. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1146145102


University of Cincinnati

11. PATEL, VIPUL J. BEHAVIORAL SIMULATION AND SYNTHESIS ENVIRONMENT FOR CONTINUOUS-TIME SINGLE-LOOP SINGLE-BIT BASEBAND DELTA-SIGMA ANALOG-TO-DIGITAL MODULATORS.

Degree: MS, Engineering : Computer Engineering, 2006, University of Cincinnati

 For the past few decades, research and design of CAD tools have focused on developing a set of tools that will guarantee designers first-pass fabrication… (more)

Subjects/Keywords: Delta-Sigma; Sigma-Delta; Top-Down; Bottom-Up; Modulator; Methodology; Analog; RF; Digital; Synthesis; Analog Synthesis; Layout; Parasitics; Behavioral Modeling; Layout-Aware; MATLAB; Simulink

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APA (6th Edition):

PATEL, V. J. (2006). BEHAVIORAL SIMULATION AND SYNTHESIS ENVIRONMENT FOR CONTINUOUS-TIME SINGLE-LOOP SINGLE-BIT BASEBAND DELTA-SIGMA ANALOG-TO-DIGITAL MODULATORS. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1147473065

Chicago Manual of Style (16th Edition):

PATEL, VIPUL J. “BEHAVIORAL SIMULATION AND SYNTHESIS ENVIRONMENT FOR CONTINUOUS-TIME SINGLE-LOOP SINGLE-BIT BASEBAND DELTA-SIGMA ANALOG-TO-DIGITAL MODULATORS.” 2006. Masters Thesis, University of Cincinnati. Accessed January 27, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1147473065.

MLA Handbook (7th Edition):

PATEL, VIPUL J. “BEHAVIORAL SIMULATION AND SYNTHESIS ENVIRONMENT FOR CONTINUOUS-TIME SINGLE-LOOP SINGLE-BIT BASEBAND DELTA-SIGMA ANALOG-TO-DIGITAL MODULATORS.” 2006. Web. 27 Jan 2021.

Vancouver:

PATEL VJ. BEHAVIORAL SIMULATION AND SYNTHESIS ENVIRONMENT FOR CONTINUOUS-TIME SINGLE-LOOP SINGLE-BIT BASEBAND DELTA-SIGMA ANALOG-TO-DIGITAL MODULATORS. [Internet] [Masters thesis]. University of Cincinnati; 2006. [cited 2021 Jan 27]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1147473065.

Council of Science Editors:

PATEL VJ. BEHAVIORAL SIMULATION AND SYNTHESIS ENVIRONMENT FOR CONTINUOUS-TIME SINGLE-LOOP SINGLE-BIT BASEBAND DELTA-SIGMA ANALOG-TO-DIGITAL MODULATORS. [Masters Thesis]. University of Cincinnati; 2006. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1147473065


University of Cincinnati

12. HUANG, RENQIU. PHYSICAL AWARE HIGH LEVEL SYNTHESIS AND INTERCONNECT FOR FPGAs.

Degree: PhD, Engineering : Computer Science and Engineering, 2006, University of Cincinnati

 Reconfigurable computing (RC) is going mainstream where FPGA plays an essential role. Synthesizing the application from concept and prototyping onto reconfigurable FPGAs has emerged as… (more)

Subjects/Keywords: Computer Science; High level synthesis; system synthesis; algorithm; architecture; performance; interconnect; analysis; evaluation

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APA (6th Edition):

HUANG, R. (2006). PHYSICAL AWARE HIGH LEVEL SYNTHESIS AND INTERCONNECT FOR FPGAs. (Doctoral Dissertation). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1147616884

Chicago Manual of Style (16th Edition):

HUANG, RENQIU. “PHYSICAL AWARE HIGH LEVEL SYNTHESIS AND INTERCONNECT FOR FPGAs.” 2006. Doctoral Dissertation, University of Cincinnati. Accessed January 27, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1147616884.

MLA Handbook (7th Edition):

HUANG, RENQIU. “PHYSICAL AWARE HIGH LEVEL SYNTHESIS AND INTERCONNECT FOR FPGAs.” 2006. Web. 27 Jan 2021.

Vancouver:

HUANG R. PHYSICAL AWARE HIGH LEVEL SYNTHESIS AND INTERCONNECT FOR FPGAs. [Internet] [Doctoral dissertation]. University of Cincinnati; 2006. [cited 2021 Jan 27]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1147616884.

Council of Science Editors:

HUANG R. PHYSICAL AWARE HIGH LEVEL SYNTHESIS AND INTERCONNECT FOR FPGAs. [Doctoral Dissertation]. University of Cincinnati; 2006. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1147616884


University of Cincinnati

13. YAN, JIANPING. A TILED FPGA ARCHITECTURE FOR POWER-AWARE COMPUTATIONS.

Degree: MS, Engineering : Computer Engineering, 2006, University of Cincinnati

 Current SRAM FPGAs have reached high gate densities which make them suitable for portable reconfigurable systems and data intensive applications. However, some challenges need to… (more)

Subjects/Keywords: FPGA; Power Consumption; Architecture; Simulation

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APA (6th Edition):

YAN, J. (2006). A TILED FPGA ARCHITECTURE FOR POWER-AWARE COMPUTATIONS. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1150126839

Chicago Manual of Style (16th Edition):

YAN, JIANPING. “A TILED FPGA ARCHITECTURE FOR POWER-AWARE COMPUTATIONS.” 2006. Masters Thesis, University of Cincinnati. Accessed January 27, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1150126839.

MLA Handbook (7th Edition):

YAN, JIANPING. “A TILED FPGA ARCHITECTURE FOR POWER-AWARE COMPUTATIONS.” 2006. Web. 27 Jan 2021.

Vancouver:

YAN J. A TILED FPGA ARCHITECTURE FOR POWER-AWARE COMPUTATIONS. [Internet] [Masters thesis]. University of Cincinnati; 2006. [cited 2021 Jan 27]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1150126839.

Council of Science Editors:

YAN J. A TILED FPGA ARCHITECTURE FOR POWER-AWARE COMPUTATIONS. [Masters Thesis]. University of Cincinnati; 2006. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1150126839


University of Cincinnati

14. MASSARINI, RENO. POWER - AWARE MOBILE SENSOR NETWORKS WITH RECONFIGURABLE COMPUTING NODES.

Degree: MS, Engineering : Computer Engineering, 2006, University of Cincinnati

 Portable electronic devices like laptops, PDAs, and cell phones are finding their way into more and more homes, offices, and classrooms. They typically come with… (more)

Subjects/Keywords: Agriculture; Forestry and Wildlife

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APA (6th Edition):

MASSARINI, R. (2006). POWER - AWARE MOBILE SENSOR NETWORKS WITH RECONFIGURABLE COMPUTING NODES. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1159198177

Chicago Manual of Style (16th Edition):

MASSARINI, RENO. “POWER - AWARE MOBILE SENSOR NETWORKS WITH RECONFIGURABLE COMPUTING NODES.” 2006. Masters Thesis, University of Cincinnati. Accessed January 27, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1159198177.

MLA Handbook (7th Edition):

MASSARINI, RENO. “POWER - AWARE MOBILE SENSOR NETWORKS WITH RECONFIGURABLE COMPUTING NODES.” 2006. Web. 27 Jan 2021.

Vancouver:

MASSARINI R. POWER - AWARE MOBILE SENSOR NETWORKS WITH RECONFIGURABLE COMPUTING NODES. [Internet] [Masters thesis]. University of Cincinnati; 2006. [cited 2021 Jan 27]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1159198177.

Council of Science Editors:

MASSARINI R. POWER - AWARE MOBILE SENSOR NETWORKS WITH RECONFIGURABLE COMPUTING NODES. [Masters Thesis]. University of Cincinnati; 2006. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1159198177


University of Cincinnati

15. JIA, XIN. GAPLA: A GLOBALLY ASYNCHRONOUS LOCALLY SYNCHRONOUS FPGA ARCHITECTURE.

Degree: PhD, Engineering : Computer Engineering, 2007, University of Cincinnati

 Conventional FPGAs, designed to implement synchronous circuits and systems, are facing some challenges. (1) The delays of the long interconnect wires can easily dominate all… (more)

Subjects/Keywords: FPGA Architecture; Globally Asynchronous Locally Synchronous

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APA (6th Edition):

JIA, X. (2007). GAPLA: A GLOBALLY ASYNCHRONOUS LOCALLY SYNCHRONOUS FPGA ARCHITECTURE. (Doctoral Dissertation). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1164589281

Chicago Manual of Style (16th Edition):

JIA, XIN. “GAPLA: A GLOBALLY ASYNCHRONOUS LOCALLY SYNCHRONOUS FPGA ARCHITECTURE.” 2007. Doctoral Dissertation, University of Cincinnati. Accessed January 27, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1164589281.

MLA Handbook (7th Edition):

JIA, XIN. “GAPLA: A GLOBALLY ASYNCHRONOUS LOCALLY SYNCHRONOUS FPGA ARCHITECTURE.” 2007. Web. 27 Jan 2021.

Vancouver:

JIA X. GAPLA: A GLOBALLY ASYNCHRONOUS LOCALLY SYNCHRONOUS FPGA ARCHITECTURE. [Internet] [Doctoral dissertation]. University of Cincinnati; 2007. [cited 2021 Jan 27]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1164589281.

Council of Science Editors:

JIA X. GAPLA: A GLOBALLY ASYNCHRONOUS LOCALLY SYNCHRONOUS FPGA ARCHITECTURE. [Doctoral Dissertation]. University of Cincinnati; 2007. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1164589281


University of Cincinnati

16. YANG, HUIYING. SYMBOLIC SENSITIVITY ANALYSIS TECHNIQUES AND APPLICATIONS IN ANALOG CIRCUIT SYNTHESIS.

Degree: PhD, Engineering : Computer Engineering, 2007, University of Cincinnati

 With increasing complexity of integrated circuits and decreasing time-to-market constraints, there was remarkable success in automation of the digital circuit design, but it exposes the… (more)

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APA (6th Edition):

YANG, H. (2007). SYMBOLIC SENSITIVITY ANALYSIS TECHNIQUES AND APPLICATIONS IN ANALOG CIRCUIT SYNTHESIS. (Doctoral Dissertation). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1167665537

Chicago Manual of Style (16th Edition):

YANG, HUIYING. “SYMBOLIC SENSITIVITY ANALYSIS TECHNIQUES AND APPLICATIONS IN ANALOG CIRCUIT SYNTHESIS.” 2007. Doctoral Dissertation, University of Cincinnati. Accessed January 27, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1167665537.

MLA Handbook (7th Edition):

YANG, HUIYING. “SYMBOLIC SENSITIVITY ANALYSIS TECHNIQUES AND APPLICATIONS IN ANALOG CIRCUIT SYNTHESIS.” 2007. Web. 27 Jan 2021.

Vancouver:

YANG H. SYMBOLIC SENSITIVITY ANALYSIS TECHNIQUES AND APPLICATIONS IN ANALOG CIRCUIT SYNTHESIS. [Internet] [Doctoral dissertation]. University of Cincinnati; 2007. [cited 2021 Jan 27]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1167665537.

Council of Science Editors:

YANG H. SYMBOLIC SENSITIVITY ANALYSIS TECHNIQUES AND APPLICATIONS IN ANALOG CIRCUIT SYNTHESIS. [Doctoral Dissertation]. University of Cincinnati; 2007. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1167665537


University of Cincinnati

17. THAKORE, PRIYANKA. DEVELOPMENT OF PROCESS VARIATION TOLERANT STANDARD CELLS.

Degree: MS, Engineering : Electrical Engineering, 2007, University of Cincinnati

 ASIC design using standard cell library cells is the most widespread design method. Lower process technologies drive a need to incorporate Design for Manufacturability technique… (more)

Subjects/Keywords: DFM; DFY; Standard Cell; Process Variation; library characterization

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APA (6th Edition):

THAKORE, P. (2007). DEVELOPMENT OF PROCESS VARIATION TOLERANT STANDARD CELLS. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1176841201

Chicago Manual of Style (16th Edition):

THAKORE, PRIYANKA. “DEVELOPMENT OF PROCESS VARIATION TOLERANT STANDARD CELLS.” 2007. Masters Thesis, University of Cincinnati. Accessed January 27, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1176841201.

MLA Handbook (7th Edition):

THAKORE, PRIYANKA. “DEVELOPMENT OF PROCESS VARIATION TOLERANT STANDARD CELLS.” 2007. Web. 27 Jan 2021.

Vancouver:

THAKORE P. DEVELOPMENT OF PROCESS VARIATION TOLERANT STANDARD CELLS. [Internet] [Masters thesis]. University of Cincinnati; 2007. [cited 2021 Jan 27]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1176841201.

Council of Science Editors:

THAKORE P. DEVELOPMENT OF PROCESS VARIATION TOLERANT STANDARD CELLS. [Masters Thesis]. University of Cincinnati; 2007. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1176841201


University of Cincinnati

18. RAMMOHAN, SRIVIDHYA. REDUCED COMPLEMENTARY DYNAMIC AND DIFFERENTIAL CMOS LOGIC: A DESIGN METHODOLOGY FOR DPA RESISTANT CRYPTOGRAPHIC CIRCUITS.

Degree: MS, Engineering : Computer Engineering, 2007, University of Cincinnati

 In recent times, many embedded applications such as mobile phones, smart-cards, etc. use cryptographic devices that use a secret key to encrypt sensitive data to… (more)

Subjects/Keywords: Differential Power Analysis (DPA) Attacks; Secret Key; Dynamic Differential Logic; Side-Channel Attacks

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APA (6th Edition):

RAMMOHAN, S. (2007). REDUCED COMPLEMENTARY DYNAMIC AND DIFFERENTIAL CMOS LOGIC: A DESIGN METHODOLOGY FOR DPA RESISTANT CRYPTOGRAPHIC CIRCUITS. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1179459225

Chicago Manual of Style (16th Edition):

RAMMOHAN, SRIVIDHYA. “REDUCED COMPLEMENTARY DYNAMIC AND DIFFERENTIAL CMOS LOGIC: A DESIGN METHODOLOGY FOR DPA RESISTANT CRYPTOGRAPHIC CIRCUITS.” 2007. Masters Thesis, University of Cincinnati. Accessed January 27, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1179459225.

MLA Handbook (7th Edition):

RAMMOHAN, SRIVIDHYA. “REDUCED COMPLEMENTARY DYNAMIC AND DIFFERENTIAL CMOS LOGIC: A DESIGN METHODOLOGY FOR DPA RESISTANT CRYPTOGRAPHIC CIRCUITS.” 2007. Web. 27 Jan 2021.

Vancouver:

RAMMOHAN S. REDUCED COMPLEMENTARY DYNAMIC AND DIFFERENTIAL CMOS LOGIC: A DESIGN METHODOLOGY FOR DPA RESISTANT CRYPTOGRAPHIC CIRCUITS. [Internet] [Masters thesis]. University of Cincinnati; 2007. [cited 2021 Jan 27]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1179459225.

Council of Science Editors:

RAMMOHAN S. REDUCED COMPLEMENTARY DYNAMIC AND DIFFERENTIAL CMOS LOGIC: A DESIGN METHODOLOGY FOR DPA RESISTANT CRYPTOGRAPHIC CIRCUITS. [Masters Thesis]. University of Cincinnati; 2007. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1179459225


University of Cincinnati

19. KOMMINENI, BALAJI. SPLINE CENTER AND RANGE REGRESSION TECHNIQUE AND ITS APPLICATION TO VARIATION AWARE PERFORMANCE MACROMODELING OF ANALOG CIRCUITS.

Degree: MS, Engineering : Electrical Engineering, 2007, University of Cincinnati

 Regression is an essential part of engineering methodologies. It plays a critical role in modeling unknown relationships among variables. However when measurement accuracy becomes very… (more)

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APA (6th Edition):

KOMMINENI, B. (2007). SPLINE CENTER AND RANGE REGRESSION TECHNIQUE AND ITS APPLICATION TO VARIATION AWARE PERFORMANCE MACROMODELING OF ANALOG CIRCUITS. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1195585950

Chicago Manual of Style (16th Edition):

KOMMINENI, BALAJI. “SPLINE CENTER AND RANGE REGRESSION TECHNIQUE AND ITS APPLICATION TO VARIATION AWARE PERFORMANCE MACROMODELING OF ANALOG CIRCUITS.” 2007. Masters Thesis, University of Cincinnati. Accessed January 27, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1195585950.

MLA Handbook (7th Edition):

KOMMINENI, BALAJI. “SPLINE CENTER AND RANGE REGRESSION TECHNIQUE AND ITS APPLICATION TO VARIATION AWARE PERFORMANCE MACROMODELING OF ANALOG CIRCUITS.” 2007. Web. 27 Jan 2021.

Vancouver:

KOMMINENI B. SPLINE CENTER AND RANGE REGRESSION TECHNIQUE AND ITS APPLICATION TO VARIATION AWARE PERFORMANCE MACROMODELING OF ANALOG CIRCUITS. [Internet] [Masters thesis]. University of Cincinnati; 2007. [cited 2021 Jan 27]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1195585950.

Council of Science Editors:

KOMMINENI B. SPLINE CENTER AND RANGE REGRESSION TECHNIQUE AND ITS APPLICATION TO VARIATION AWARE PERFORMANCE MACROMODELING OF ANALOG CIRCUITS. [Masters Thesis]. University of Cincinnati; 2007. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1195585950


University of Cincinnati

20. Sethuraman, Balasubramanian. Novel Methodologies for Efficient Networks-on-Chip Implementation on Reconfigurable Devices.

Degree: PhD, Engineering : Computer Science and Engineering, 2007, University of Cincinnati

 International Technology Roadmap for Semiconductors (ITRS) project the latest trend moving towards a system-level and platform-based design, involving large percentage of design reuse. Different Intellectual… (more)

Subjects/Keywords: Networks-on-Chip (NoC); System-on-Chip (SoC); FPGA; Reconfigurable and Platform-Based Design; Light Weight Router Design; Multi Local Port Router; Multicast Router; Low Power Topology Generation and Mapping; Power Issues and IR drop Analysis

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APA (6th Edition):

Sethuraman, B. (2007). Novel Methodologies for Efficient Networks-on-Chip Implementation on Reconfigurable Devices. (Doctoral Dissertation). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1196043683

Chicago Manual of Style (16th Edition):

Sethuraman, Balasubramanian. “Novel Methodologies for Efficient Networks-on-Chip Implementation on Reconfigurable Devices.” 2007. Doctoral Dissertation, University of Cincinnati. Accessed January 27, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1196043683.

MLA Handbook (7th Edition):

Sethuraman, Balasubramanian. “Novel Methodologies for Efficient Networks-on-Chip Implementation on Reconfigurable Devices.” 2007. Web. 27 Jan 2021.

Vancouver:

Sethuraman B. Novel Methodologies for Efficient Networks-on-Chip Implementation on Reconfigurable Devices. [Internet] [Doctoral dissertation]. University of Cincinnati; 2007. [cited 2021 Jan 27]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1196043683.

Council of Science Editors:

Sethuraman B. Novel Methodologies for Efficient Networks-on-Chip Implementation on Reconfigurable Devices. [Doctoral Dissertation]. University of Cincinnati; 2007. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1196043683


University of Cincinnati

21. RAGUPATHY, MANOJ KUMAR. SWITCH LEVEL SIMULATION IN THE PRESENCE OF UNCERTAINTIES.

Degree: MS, Engineering : Computer Engineering, 2008, University of Cincinnati

 Process variation plays a critical role in the nanometer era. There has been an increasing trend to consider the effects of process variation during the… (more)

Subjects/Keywords: switch-level; IRSIM; interval arithmetic; affine arithmetic

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APA (6th Edition):

RAGUPATHY, M. K. (2008). SWITCH LEVEL SIMULATION IN THE PRESENCE OF UNCERTAINTIES. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1201512323

Chicago Manual of Style (16th Edition):

RAGUPATHY, MANOJ KUMAR. “SWITCH LEVEL SIMULATION IN THE PRESENCE OF UNCERTAINTIES.” 2008. Masters Thesis, University of Cincinnati. Accessed January 27, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1201512323.

MLA Handbook (7th Edition):

RAGUPATHY, MANOJ KUMAR. “SWITCH LEVEL SIMULATION IN THE PRESENCE OF UNCERTAINTIES.” 2008. Web. 27 Jan 2021.

Vancouver:

RAGUPATHY MK. SWITCH LEVEL SIMULATION IN THE PRESENCE OF UNCERTAINTIES. [Internet] [Masters thesis]. University of Cincinnati; 2008. [cited 2021 Jan 27]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1201512323.

Council of Science Editors:

RAGUPATHY MK. SWITCH LEVEL SIMULATION IN THE PRESENCE OF UNCERTAINTIES. [Masters Thesis]. University of Cincinnati; 2008. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1201512323


University of Cincinnati

22. KASAM, SUMAN. FORMAL VERIFICATION OF TIME CONSTRAINED UAV TASK ALLOCATION USING MODEL-CHECKING.

Degree: MS, Engineering : Computer Engineering, 2008, University of Cincinnati

 Real-time constrained systems are part of the everyday life. These are computer systems subjected to timing constraints along with non-timing constraints. They can be found… (more)

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APA (6th Edition):

KASAM, S. (2008). FORMAL VERIFICATION OF TIME CONSTRAINED UAV TASK ALLOCATION USING MODEL-CHECKING. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1201537607

Chicago Manual of Style (16th Edition):

KASAM, SUMAN. “FORMAL VERIFICATION OF TIME CONSTRAINED UAV TASK ALLOCATION USING MODEL-CHECKING.” 2008. Masters Thesis, University of Cincinnati. Accessed January 27, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1201537607.

MLA Handbook (7th Edition):

KASAM, SUMAN. “FORMAL VERIFICATION OF TIME CONSTRAINED UAV TASK ALLOCATION USING MODEL-CHECKING.” 2008. Web. 27 Jan 2021.

Vancouver:

KASAM S. FORMAL VERIFICATION OF TIME CONSTRAINED UAV TASK ALLOCATION USING MODEL-CHECKING. [Internet] [Masters thesis]. University of Cincinnati; 2008. [cited 2021 Jan 27]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1201537607.

Council of Science Editors:

KASAM S. FORMAL VERIFICATION OF TIME CONSTRAINED UAV TASK ALLOCATION USING MODEL-CHECKING. [Masters Thesis]. University of Cincinnati; 2008. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1201537607


University of Cincinnati

23. MANSOURI, NAZANIN. AUTOMATED CORRECTNESS CONDITION GENERATION FOR FORMAL VERIFICATION OF SYNTHESIZED RTL DESIGNS.

Degree: PhD, Engineering : Computer Engineering, 2001, University of Cincinnati

 This work presents a formal methodology for verifying the functional correctness of synthesized register transfer level designs (RTL) generated by a high-level synthesis system. The… (more)

Subjects/Keywords: formal verification; register transfer level (RTL); High-level synthesis; correctness conditions

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APA (6th Edition):

MANSOURI, N. (2001). AUTOMATED CORRECTNESS CONDITION GENERATION FOR FORMAL VERIFICATION OF SYNTHESIZED RTL DESIGNS. (Doctoral Dissertation). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin982064542

Chicago Manual of Style (16th Edition):

MANSOURI, NAZANIN. “AUTOMATED CORRECTNESS CONDITION GENERATION FOR FORMAL VERIFICATION OF SYNTHESIZED RTL DESIGNS.” 2001. Doctoral Dissertation, University of Cincinnati. Accessed January 27, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin982064542.

MLA Handbook (7th Edition):

MANSOURI, NAZANIN. “AUTOMATED CORRECTNESS CONDITION GENERATION FOR FORMAL VERIFICATION OF SYNTHESIZED RTL DESIGNS.” 2001. Web. 27 Jan 2021.

Vancouver:

MANSOURI N. AUTOMATED CORRECTNESS CONDITION GENERATION FOR FORMAL VERIFICATION OF SYNTHESIZED RTL DESIGNS. [Internet] [Doctoral dissertation]. University of Cincinnati; 2001. [cited 2021 Jan 27]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin982064542.

Council of Science Editors:

MANSOURI N. AUTOMATED CORRECTNESS CONDITION GENERATION FOR FORMAL VERIFICATION OF SYNTHESIZED RTL DESIGNS. [Doctoral Dissertation]. University of Cincinnati; 2001. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin982064542


University of Cincinnati

24. KASAT, AMIT. MEMORY SYNTHESIS FOR FPGA-BASED RECONFIGURABLE COMPUTERS.

Degree: MS, Engineering : Computer Engineering, 2001, University of Cincinnati

 A design executing on Reconfigurable Computer (RC) typically reads from and writes to physical memories on the RC. For data intensive applications like Digital Signal… (more)

Subjects/Keywords: FPGA; Memory Synthesis; On-chip RAM; Reconfigurable computers; Logic partitioning

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APA (6th Edition):

KASAT, A. (2001). MEMORY SYNTHESIS FOR FPGA-BASED RECONFIGURABLE COMPUTERS. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin988222220

Chicago Manual of Style (16th Edition):

KASAT, AMIT. “MEMORY SYNTHESIS FOR FPGA-BASED RECONFIGURABLE COMPUTERS.” 2001. Masters Thesis, University of Cincinnati. Accessed January 27, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin988222220.

MLA Handbook (7th Edition):

KASAT, AMIT. “MEMORY SYNTHESIS FOR FPGA-BASED RECONFIGURABLE COMPUTERS.” 2001. Web. 27 Jan 2021.

Vancouver:

KASAT A. MEMORY SYNTHESIS FOR FPGA-BASED RECONFIGURABLE COMPUTERS. [Internet] [Masters thesis]. University of Cincinnati; 2001. [cited 2021 Jan 27]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin988222220.

Council of Science Editors:

KASAT A. MEMORY SYNTHESIS FOR FPGA-BASED RECONFIGURABLE COMPUTERS. [Masters Thesis]. University of Cincinnati; 2001. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin988222220


University of Cincinnati

25. MUKHERJEE, MADHUBANTI. ALGORITHMS FOR COUPLING CIRCUIT AND PHYSICAL SYNTHESIS WITH HIGH-LEVEL DESIGN-SPACE EXPLORATION FOR 2D AND 3D SYSTEMS.

Degree: PhD, Engineering : Computer Science and Engineering, 2004, University of Cincinnati

 With increasing complexity and size of VLSI systems, RTL can no longer be a viable design entry point. On the other hand, higher levels of… (more)

Subjects/Keywords: Computer Science; Physical-aware High Level Synthesis; Design-space exploration; Vertically Integrated 3D Systems

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APA (6th Edition):

MUKHERJEE, M. (2004). ALGORITHMS FOR COUPLING CIRCUIT AND PHYSICAL SYNTHESIS WITH HIGH-LEVEL DESIGN-SPACE EXPLORATION FOR 2D AND 3D SYSTEMS. (Doctoral Dissertation). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1112670784

Chicago Manual of Style (16th Edition):

MUKHERJEE, MADHUBANTI. “ALGORITHMS FOR COUPLING CIRCUIT AND PHYSICAL SYNTHESIS WITH HIGH-LEVEL DESIGN-SPACE EXPLORATION FOR 2D AND 3D SYSTEMS.” 2004. Doctoral Dissertation, University of Cincinnati. Accessed January 27, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1112670784.

MLA Handbook (7th Edition):

MUKHERJEE, MADHUBANTI. “ALGORITHMS FOR COUPLING CIRCUIT AND PHYSICAL SYNTHESIS WITH HIGH-LEVEL DESIGN-SPACE EXPLORATION FOR 2D AND 3D SYSTEMS.” 2004. Web. 27 Jan 2021.

Vancouver:

MUKHERJEE M. ALGORITHMS FOR COUPLING CIRCUIT AND PHYSICAL SYNTHESIS WITH HIGH-LEVEL DESIGN-SPACE EXPLORATION FOR 2D AND 3D SYSTEMS. [Internet] [Doctoral dissertation]. University of Cincinnati; 2004. [cited 2021 Jan 27]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1112670784.

Council of Science Editors:

MUKHERJEE M. ALGORITHMS FOR COUPLING CIRCUIT AND PHYSICAL SYNTHESIS WITH HIGH-LEVEL DESIGN-SPACE EXPLORATION FOR 2D AND 3D SYSTEMS. [Doctoral Dissertation]. University of Cincinnati; 2004. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1112670784


University of Cincinnati

26. GANESAN, SREELAKSHMI. SYNTHESIS OF MIXED-SIGNAL SYSTEMS BASED ON RAPID PROTOTYPING.

Degree: PhD, Engineering : Computer Engineering, 2001, University of Cincinnati

 This dissertation presents a methodology for behavioral synthesis of analog and mixed signal systems based on rapid prototyping followed by technology retargeting. Rapid prototyping with… (more)

Subjects/Keywords: mixed-signal; synthesis of analog and mixed signal systems; rapid prototyping; field-programmable analog array (FPAA)

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APA (6th Edition):

GANESAN, S. (2001). SYNTHESIS OF MIXED-SIGNAL SYSTEMS BASED ON RAPID PROTOTYPING. (Doctoral Dissertation). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin988815041

Chicago Manual of Style (16th Edition):

GANESAN, SREELAKSHMI. “SYNTHESIS OF MIXED-SIGNAL SYSTEMS BASED ON RAPID PROTOTYPING.” 2001. Doctoral Dissertation, University of Cincinnati. Accessed January 27, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin988815041.

MLA Handbook (7th Edition):

GANESAN, SREELAKSHMI. “SYNTHESIS OF MIXED-SIGNAL SYSTEMS BASED ON RAPID PROTOTYPING.” 2001. Web. 27 Jan 2021.

Vancouver:

GANESAN S. SYNTHESIS OF MIXED-SIGNAL SYSTEMS BASED ON RAPID PROTOTYPING. [Internet] [Doctoral dissertation]. University of Cincinnati; 2001. [cited 2021 Jan 27]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin988815041.

Council of Science Editors:

GANESAN S. SYNTHESIS OF MIXED-SIGNAL SYSTEMS BASED ON RAPID PROTOTYPING. [Doctoral Dissertation]. University of Cincinnati; 2001. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin988815041


University of Cincinnati

27. CHATHA, KARAMVIR SINGH. SYSTEM-LEVEL COSYNTHESIS OF TRANSFORMATIVE APPLICATIONS FOR HETEROGENEOUS HARDWARE-SOFTWARE ARCHITECTURES.

Degree: PhD, Engineering : Computer Science and Engineering, 2001, University of Cincinnati

 Transformative applications are computationally intensive applications like image compression and decompression algorithms. Embedded system implementations of transformative applications typically consist of multiple hardware and software… (more)

Subjects/Keywords: system-level design; hardware-software cosynthesis; hardware-software partitioning; pipelined scheduling; retiming transformation

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APA (6th Edition):

CHATHA, K. S. (2001). SYSTEM-LEVEL COSYNTHESIS OF TRANSFORMATIVE APPLICATIONS FOR HETEROGENEOUS HARDWARE-SOFTWARE ARCHITECTURES. (Doctoral Dissertation). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin990822809

Chicago Manual of Style (16th Edition):

CHATHA, KARAMVIR SINGH. “SYSTEM-LEVEL COSYNTHESIS OF TRANSFORMATIVE APPLICATIONS FOR HETEROGENEOUS HARDWARE-SOFTWARE ARCHITECTURES.” 2001. Doctoral Dissertation, University of Cincinnati. Accessed January 27, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin990822809.

MLA Handbook (7th Edition):

CHATHA, KARAMVIR SINGH. “SYSTEM-LEVEL COSYNTHESIS OF TRANSFORMATIVE APPLICATIONS FOR HETEROGENEOUS HARDWARE-SOFTWARE ARCHITECTURES.” 2001. Web. 27 Jan 2021.

Vancouver:

CHATHA KS. SYSTEM-LEVEL COSYNTHESIS OF TRANSFORMATIVE APPLICATIONS FOR HETEROGENEOUS HARDWARE-SOFTWARE ARCHITECTURES. [Internet] [Doctoral dissertation]. University of Cincinnati; 2001. [cited 2021 Jan 27]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin990822809.

Council of Science Editors:

CHATHA KS. SYSTEM-LEVEL COSYNTHESIS OF TRANSFORMATIVE APPLICATIONS FOR HETEROGENEOUS HARDWARE-SOFTWARE ARCHITECTURES. [Doctoral Dissertation]. University of Cincinnati; 2001. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin990822809


University of Cincinnati

28. TEICA, ELENA. FORMAL CORRECTNESS AND COMPLETENESS FOR A SET OF UNINTERPRETED RTL TRANSFORMATIONS.

Degree: PhD, Engineering : Computer Science and Engineering, 2001, University of Cincinnati

 The work presented in this thesis is concerned with the correctness of the high-level synthesis process. In particular, it addresses transformational derivation (TD) systems. TD… (more)

Subjects/Keywords: RTL Transformations; Formal Synthesis; Correctness Behavior Preserving Completeness; Mechanized in Higher-Order Logics of PVS

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

TEICA, E. (2001). FORMAL CORRECTNESS AND COMPLETENESS FOR A SET OF UNINTERPRETED RTL TRANSFORMATIONS. (Doctoral Dissertation). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1001432470

Chicago Manual of Style (16th Edition):

TEICA, ELENA. “FORMAL CORRECTNESS AND COMPLETENESS FOR A SET OF UNINTERPRETED RTL TRANSFORMATIONS.” 2001. Doctoral Dissertation, University of Cincinnati. Accessed January 27, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1001432470.

MLA Handbook (7th Edition):

TEICA, ELENA. “FORMAL CORRECTNESS AND COMPLETENESS FOR A SET OF UNINTERPRETED RTL TRANSFORMATIONS.” 2001. Web. 27 Jan 2021.

Vancouver:

TEICA E. FORMAL CORRECTNESS AND COMPLETENESS FOR A SET OF UNINTERPRETED RTL TRANSFORMATIONS. [Internet] [Doctoral dissertation]. University of Cincinnati; 2001. [cited 2021 Jan 27]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1001432470.

Council of Science Editors:

TEICA E. FORMAL CORRECTNESS AND COMPLETENESS FOR A SET OF UNINTERPRETED RTL TRANSFORMATIONS. [Doctoral Dissertation]. University of Cincinnati; 2001. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1001432470


University of Cincinnati

29. SIVA, SUBRAMANYAN D. APPLICATIONS OF SATISFIABILITY IN SYNTHESIS OF RECONFIGURABLE COMPUTERS.

Degree: MS, Engineering : Computer Engineering, 2002, University of Cincinnati

 This thesis addresses applications of satisfiability techniques in a reconfigurable computer (RC) synthesis framework. The two areas explored are the interconnect synthesis problem and the… (more)

Subjects/Keywords: satisfiability; reconfigurable-computer; interconnect synthesis; high level synthesis; sat-solver

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

SIVA, S. D. (2002). APPLICATIONS OF SATISFIABILITY IN SYNTHESIS OF RECONFIGURABLE COMPUTERS. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1022761893

Chicago Manual of Style (16th Edition):

SIVA, SUBRAMANYAN D. “APPLICATIONS OF SATISFIABILITY IN SYNTHESIS OF RECONFIGURABLE COMPUTERS.” 2002. Masters Thesis, University of Cincinnati. Accessed January 27, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1022761893.

MLA Handbook (7th Edition):

SIVA, SUBRAMANYAN D. “APPLICATIONS OF SATISFIABILITY IN SYNTHESIS OF RECONFIGURABLE COMPUTERS.” 2002. Web. 27 Jan 2021.

Vancouver:

SIVA SD. APPLICATIONS OF SATISFIABILITY IN SYNTHESIS OF RECONFIGURABLE COMPUTERS. [Internet] [Masters thesis]. University of Cincinnati; 2002. [cited 2021 Jan 27]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1022761893.

Council of Science Editors:

SIVA SD. APPLICATIONS OF SATISFIABILITY IN SYNTHESIS OF RECONFIGURABLE COMPUTERS. [Masters Thesis]. University of Cincinnati; 2002. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1022761893


University of Cincinnati

30. KHAN, JAWAD BASIT. iPACE-V1: A PORTAABLE ADAPTIVE COMPUTING ENGINE.

Degree: MS, Engineering : Computer Engineering, 2002, University of Cincinnati

 The iPACE-V1 (Image Processing Adaptive Computing Engine) is a portable, reconfigurable hardware platform, designed in the Digital Design Environments Laboratory at the University of Cincinnati.… (more)

Subjects/Keywords: Computer Science; reconfigurable computing; adaptive computing; FPGAs; mobile computing; image processing

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

KHAN, J. B. (2002). iPACE-V1: A PORTAABLE ADAPTIVE COMPUTING ENGINE. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1025721991

Chicago Manual of Style (16th Edition):

KHAN, JAWAD BASIT. “iPACE-V1: A PORTAABLE ADAPTIVE COMPUTING ENGINE.” 2002. Masters Thesis, University of Cincinnati. Accessed January 27, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1025721991.

MLA Handbook (7th Edition):

KHAN, JAWAD BASIT. “iPACE-V1: A PORTAABLE ADAPTIVE COMPUTING ENGINE.” 2002. Web. 27 Jan 2021.

Vancouver:

KHAN JB. iPACE-V1: A PORTAABLE ADAPTIVE COMPUTING ENGINE. [Internet] [Masters thesis]. University of Cincinnati; 2002. [cited 2021 Jan 27]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1025721991.

Council of Science Editors:

KHAN JB. iPACE-V1: A PORTAABLE ADAPTIVE COMPUTING ENGINE. [Masters Thesis]. University of Cincinnati; 2002. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1025721991

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