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University of Arkansas
1.
Lai, Chenggang.
Automatic Performance Optimization on Heterogeneous Computer Systems using Manycore Coprocessors.
Degree: PhD, 2018, University of Arkansas
URL: https://scholarworks.uark.edu/etd/3060 
► Emerging computer architectures and advanced computing technologies, such as Intel’s Many Integrated Core (MIC) Architecture and graphics processing units (GPU), provide a promising solution…
(more)
▼ Emerging computer architectures and advanced computing technologies, such as Intel’s Many Integrated Core (MIC) Architecture and graphics processing units (GPU), provide a promising solution to employ parallelism for achieving high performance, scalability and low power consumption. As a result, accelerators have become a crucial part in developing supercomputers. Accelerators usually equip with different types of cores and memory. It will compel application developers to reach challenging performance goals. The added complexity has led to the development of task-based runtime systems, which allow complex computations to be expressed as task graphs, and rely on scheduling algorithms to perform load balancing between all resources of the platforms. Developing good scheduling algorithms, even on a single node, and analyzing them can thus have a very high impact on the performance of current HPC systems. Load balancing strategies, at different levels, will be critical to obtain an effective usage of the heterogeneous hardware and to reduce the impact of communication on energy and performance. Implementing efficient load balancing algorithms, able to manage heterogeneous hardware, can be a challenging task, especially when a parallel programming model for distributed memory architecture.
In this paper, we presents several novel runtime approaches to determine the optimal data and task partition on heterogeneous platforms, targeting the Intel Xeon Phi accelerated heterogeneous systems.
Advisors/Committee Members: Miaoqing Huang, John M. Gauch, Xuan Shi.
Subjects/Keywords: Acceleration; Heterogeneous System; Manycore Coprocessor; Computer and Systems Architecture; Graphics and Human Computer Interfaces; OS and Networks; Power and Energy; Systems Architecture
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APA (6th Edition):
Lai, C. (2018). Automatic Performance Optimization on Heterogeneous Computer Systems using Manycore Coprocessors. (Doctoral Dissertation). University of Arkansas. Retrieved from https://scholarworks.uark.edu/etd/3060
Chicago Manual of Style (16th Edition):
Lai, Chenggang. “Automatic Performance Optimization on Heterogeneous Computer Systems using Manycore Coprocessors.” 2018. Doctoral Dissertation, University of Arkansas. Accessed November 14, 2019.
https://scholarworks.uark.edu/etd/3060.
MLA Handbook (7th Edition):
Lai, Chenggang. “Automatic Performance Optimization on Heterogeneous Computer Systems using Manycore Coprocessors.” 2018. Web. 14 Nov 2019.
Vancouver:
Lai C. Automatic Performance Optimization on Heterogeneous Computer Systems using Manycore Coprocessors. [Internet] [Doctoral dissertation]. University of Arkansas; 2018. [cited 2019 Nov 14].
Available from: https://scholarworks.uark.edu/etd/3060.
Council of Science Editors:
Lai C. Automatic Performance Optimization on Heterogeneous Computer Systems using Manycore Coprocessors. [Doctoral Dissertation]. University of Arkansas; 2018. Available from: https://scholarworks.uark.edu/etd/3060
University of Arkansas
2.
Sadeghian, Abazar.
Achieving a better balance between productivity and performance on FPGAs through Heterogeneous Extensible Multiprocessor Systems.
Degree: MSCmpE, 2016, University of Arkansas
URL: https://scholarworks.uark.edu/etd/1584
► Field Programmable Gate Arrays (FPGAs) were first introduced circa 1980, and they held the promise of delivering performance levels associated with customized circuits, but…
(more)
▼ Field Programmable Gate Arrays (FPGAs) were first introduced circa 1980, and they held the promise of delivering performance levels associated with customized circuits, but with productivity levels more closely associated with software development. Achieving both performance and productivity objectives has been a long standing challenge problem for the reconfigurable computing community and remains unsolved today. On one hand, Vendor supplied design flows have tended towards achieving the high levels of performance through gate level customization, but at the cost of very low productivity. On the other hand, FPGA densities are following Moore's law and and can now support complete multiprocessor system architectures. Thus FPGAs can be turned into an architecture with programmable processors which brings productivity but sacrifices the peak performance advantages of custom circuits. In this thesis we explore how the two use cases can be combined to achieve the best from both.
The flexibility of the FPGAs to host a heterogeneous multiprocessor system with different types of programmable processors and custom accelerators allows the software developers to design a platform that matches the unique performance needs of their application. However, currently no automated approaches are publicly available to create such heterogeneous architectures as well as the software support for these platforms. Creating base architectures, configuring multiple tool chains, and repetitive engineering design efforts can and should be automated. This thesis introduces Heterogeneous Extensible Multiprocessor System (HEMPS) template approach which allows an FPGA to be programmed with productivity levels close to those associated with parallel processing, and with performance levels close to those associated with customized circuits. The work in this thesis introduces an ArchGen script to automate the generation of HEMPS systems as well as a library of portable and self tuning polymorphic functions. These tools will abstract away the HW/SW co-design details and provide a transparent programming language to capture different levels of parallelisms, without sacrificing productivity or portability.
Advisors/Committee Members: David Andrews, Miaoqing Huang, Gordon Beavers.
Subjects/Keywords: Applied sciences; Accelerator; Custom hardware; Field Programmable gate arrays; Hardware/software co-design; Partial reconfiguration; System on chip; Digital Circuits; Other Electrical and Computer Engineering
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APA (6th Edition):
Sadeghian, A. (2016). Achieving a better balance between productivity and performance on FPGAs through Heterogeneous Extensible Multiprocessor Systems. (Masters Thesis). University of Arkansas. Retrieved from https://scholarworks.uark.edu/etd/1584
Chicago Manual of Style (16th Edition):
Sadeghian, Abazar. “Achieving a better balance between productivity and performance on FPGAs through Heterogeneous Extensible Multiprocessor Systems.” 2016. Masters Thesis, University of Arkansas. Accessed November 14, 2019.
https://scholarworks.uark.edu/etd/1584.
MLA Handbook (7th Edition):
Sadeghian, Abazar. “Achieving a better balance between productivity and performance on FPGAs through Heterogeneous Extensible Multiprocessor Systems.” 2016. Web. 14 Nov 2019.
Vancouver:
Sadeghian A. Achieving a better balance between productivity and performance on FPGAs through Heterogeneous Extensible Multiprocessor Systems. [Internet] [Masters thesis]. University of Arkansas; 2016. [cited 2019 Nov 14].
Available from: https://scholarworks.uark.edu/etd/1584.
Council of Science Editors:
Sadeghian A. Achieving a better balance between productivity and performance on FPGAs through Heterogeneous Extensible Multiprocessor Systems. [Masters Thesis]. University of Arkansas; 2016. Available from: https://scholarworks.uark.edu/etd/1584
University of Arkansas
3.
Ding, Hongyuan.
Exploiting Hardware Abstraction for Parallel Programming Framework: Platform and Multitasking.
Degree: PhD, 2017, University of Arkansas
URL: https://scholarworks.uark.edu/etd/1985
► With the help of the parallelism provided by the fine-grained architecture, hardware accelerators on Field Programmable Gate Arrays (FPGAs) can significantly improve the performance…
(more)
▼ With the help of the parallelism provided by the fine-grained architecture, hardware accelerators on Field Programmable Gate Arrays (FPGAs) can significantly improve the performance of many applications. However, designers are required to have excellent hardware programming skills and unique optimization techniques to explore the potential of FPGA resources fully. Intermediate frameworks above hardware circuits are proposed to improve either performance or productivity by leveraging parallel programming models beyond the multi-core era.
In this work, we propose the PolyPC (Polymorphic Parallel Computing) framework, which targets enhancing productivity without losing performance. It helps designers develop parallelized applications and implement them on FPGAs. The PolyPC framework implements a custom hardware platform, on which programs written in an OpenCL-like programming model can launch. Additionally, the PolyPC framework extends vendor-provided tools to provide a complete development environment including intermediate software framework, and automatic system builders. Designers' programs can be either synthesized as hardware processing elements (PEs) or compiled to executable files running on software PEs. Benefiting from nontrivial features of re-loadable PEs, and independent group-level schedulers, the multitasking is enabled for both software and hardware PEs to improve the efficiency of utilizing hardware resources.
The PolyPC framework is evaluated regarding performance, area efficiency, and multitasking. The results show a maximum 66 times speedup over a dual-core ARM processor and 1043 times speedup over a high-performance MicroBlaze with 125 times of area efficiency. It delivers a significant improvement in response time to high-priority tasks with the priority-aware scheduling. Overheads of multitasking are evaluated to analyze trade-offs. With the help of the design flow, the OpenCL application programs are converted into executables through the front-end source-to-source transformation and back-end synthesis/compilation to run on PEs, and the framework is generated from users' specifications.
Advisors/Committee Members: Miaoqing Huang, David Andrews, Wing Ning Li.
Subjects/Keywords: FPGA; Hardware Abstraction; Hardware Acceleration; Hardware Multitasking; MPSoC; OpenCL; Hardware Systems
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APA (6th Edition):
Ding, H. (2017). Exploiting Hardware Abstraction for Parallel Programming Framework: Platform and Multitasking. (Doctoral Dissertation). University of Arkansas. Retrieved from https://scholarworks.uark.edu/etd/1985
Chicago Manual of Style (16th Edition):
Ding, Hongyuan. “Exploiting Hardware Abstraction for Parallel Programming Framework: Platform and Multitasking.” 2017. Doctoral Dissertation, University of Arkansas. Accessed November 14, 2019.
https://scholarworks.uark.edu/etd/1985.
MLA Handbook (7th Edition):
Ding, Hongyuan. “Exploiting Hardware Abstraction for Parallel Programming Framework: Platform and Multitasking.” 2017. Web. 14 Nov 2019.
Vancouver:
Ding H. Exploiting Hardware Abstraction for Parallel Programming Framework: Platform and Multitasking. [Internet] [Doctoral dissertation]. University of Arkansas; 2017. [cited 2019 Nov 14].
Available from: https://scholarworks.uark.edu/etd/1985.
Council of Science Editors:
Ding H. Exploiting Hardware Abstraction for Parallel Programming Framework: Platform and Multitasking. [Doctoral Dissertation]. University of Arkansas; 2017. Available from: https://scholarworks.uark.edu/etd/1985
University of Arkansas
4.
Ding, Hongyuan.
Optimizing Performance and Scalability on Hybrid MPSoCs.
Degree: MSCmpE, 2014, University of Arkansas
URL: https://scholarworks.uark.edu/etd/2024
► Hardware accelerators are capable of achieving significant performance improvement. But design- ing hardware accelerators lacks the flexibility and the productivity. Combining hardware accelerators with…
(more)
▼ Hardware accelerators are capable of achieving significant performance improvement. But design- ing hardware accelerators lacks the flexibility and the productivity. Combining hardware accelerators with multiprocessor system-on-chip (MPSoC) is an alternative way to balance the flexibility, the productivity, and the performance. However, without appropriate programming model it is still a challenge to achieve parallelism on a hybrid (MPSoC) with with both general-purpose processors and dedicated accelerators. Besides, increasing computation demands with limited power budget require more energy-efficient design without performance degradation in embedded systems and mobile computing platforms. Reconfigurable computing with emerging storage technologies is an alternative to enable the optimization of both performance and power consumption.
In this work, we present a hybrid OpenCL-like (HOpenCL) parallel computing framework on FPGAs. The hybrid hardware platform as well as both the hardware and software kernels can be generated through this an automatic design flow. In addition, the OpenCL-like programming model is exploited to combine software and hardware kernels running on the unified hardware platform. By using the partial reconfiguration technique, a dynamic reconfiguration scheme is presented to optimize performance without losing the programmable flexibility.
Our results show that our automatic design flow can not only significantly minimize the development time, but also gain about 11 times speedup compared with pure software parallel implementation. When partial reconfiguration is enable to conduct dynamic scheduling, the overall performance speedup of our mixed micro benchmarks is around 5.2 times.
Advisors/Committee Members: Miaoqing Huang, David Andrews, Christophe Bobda.
Subjects/Keywords: Dynamic Scheduling; FPGA; High-level Synthesis; MPSoC; System Design; Hardware Systems; Systems and Communications
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APA (6th Edition):
Ding, H. (2014). Optimizing Performance and Scalability on Hybrid MPSoCs. (Masters Thesis). University of Arkansas. Retrieved from https://scholarworks.uark.edu/etd/2024
Chicago Manual of Style (16th Edition):
Ding, Hongyuan. “Optimizing Performance and Scalability on Hybrid MPSoCs.” 2014. Masters Thesis, University of Arkansas. Accessed November 14, 2019.
https://scholarworks.uark.edu/etd/2024.
MLA Handbook (7th Edition):
Ding, Hongyuan. “Optimizing Performance and Scalability on Hybrid MPSoCs.” 2014. Web. 14 Nov 2019.
Vancouver:
Ding H. Optimizing Performance and Scalability on Hybrid MPSoCs. [Internet] [Masters thesis]. University of Arkansas; 2014. [cited 2019 Nov 14].
Available from: https://scholarworks.uark.edu/etd/2024.
Council of Science Editors:
Ding H. Optimizing Performance and Scalability on Hybrid MPSoCs. [Masters Thesis]. University of Arkansas; 2014. Available from: https://scholarworks.uark.edu/etd/2024
University of Arkansas
5.
Lai, Chenggang.
Study of Parallel Programming Models on Computer Clusters with Accelerators.
Degree: MSCmpE, 2014, University of Arkansas
URL: https://scholarworks.uark.edu/etd/2046
► In order to reach exascale computing capability, accelerators have become a crucial part in developing supercomputers. This work examines the potential of two latest…
(more)
▼ In order to reach exascale computing capability, accelerators have become a crucial part in developing supercomputers. This work examines the potential of two latest acceleration technologies, Intel Many Integrated Core (MIC) Architecture and Graphics Processing Units (GPUs). This thesis applies three benchmarks under 3 different configurations, MPI+CPU, MPI+GPU, and MPI+MIC. The benchmarks include intensely communicating application, loosely communicating application, and embarrassingly parallel application. This thesis also carries out a detailed study on the scalability and performance of MIC processors under two programming models, i.e., offload model and native model, on the Beacon computer cluster.
According to different benchmarks, the results demonstrate different performance and scalability between GPU and MIC. (1) For embarrassingly parallel case, GPU-based parallel implementation on Keeneland computer cluster has a better performance than other accelerators. However, MIC-based parallel implementation shows a better scalability than the implementation on GPU. The performances of native model and offload model on MIC are very close. (2) For loosely communicating case, the performances on GPU and MIC are very close. The MIC-based parallel implementation still demonstrates a strong scalability when using 120 MIC processors in computation. (3) For the intensely communicating case, the MPI implementations on CPUs and GPUs both have a strong scalability. GPUs can consistently outperform other accelerators. However, the MIC-based implementation cannot scale quite well. The performance of different models on MIC is different from the performance of embarrassingly parallel case. Native model can consistently outperform the offload model by ~10 times. And there is not much performance gain when allocating more MIC processors. The increase of communication cost will offset the performance gain from the reduced workload on each MIC core. This work also tests the performance capabilities and scalability by changing the number of threads on each MIC card form 10 to 60. When using different number of threads for the intensely communicating case, it shows different capabilities of the MIC based offload model. The scalability can hold when the number of threads increases from 10 to 30, and the computation time reduces with a smaller rate from 30 threads to 50 threads. When using 60 threads, the computation time will increase. The reason is that the communication overhead will offset the performance gain when 60 threads are deployed on a single MIC card.
Advisors/Committee Members: Miaoqing Huang, John Gauch, Wing Ning Li.
Subjects/Keywords: Accelerators; Hybrid Architecture; Parallel Programming; Computer and Systems Architecture; Programming Languages and Compilers
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APA ·
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APA (6th Edition):
Lai, C. (2014). Study of Parallel Programming Models on Computer Clusters with Accelerators. (Masters Thesis). University of Arkansas. Retrieved from https://scholarworks.uark.edu/etd/2046
Chicago Manual of Style (16th Edition):
Lai, Chenggang. “Study of Parallel Programming Models on Computer Clusters with Accelerators.” 2014. Masters Thesis, University of Arkansas. Accessed November 14, 2019.
https://scholarworks.uark.edu/etd/2046.
MLA Handbook (7th Edition):
Lai, Chenggang. “Study of Parallel Programming Models on Computer Clusters with Accelerators.” 2014. Web. 14 Nov 2019.
Vancouver:
Lai C. Study of Parallel Programming Models on Computer Clusters with Accelerators. [Internet] [Masters thesis]. University of Arkansas; 2014. [cited 2019 Nov 14].
Available from: https://scholarworks.uark.edu/etd/2046.
Council of Science Editors:
Lai C. Study of Parallel Programming Models on Computer Clusters with Accelerators. [Masters Thesis]. University of Arkansas; 2014. Available from: https://scholarworks.uark.edu/etd/2046
University of Arkansas
6.
Warn, Seth.
High Performance Geospatial Analysis on Emerging Parallel Architectures.
Degree: PhD, 2011, University of Arkansas
URL: https://scholarworks.uark.edu/etd/156
► Geographic information systems (GIS) are performing increasingly sophisticated analyses on growing data sets. These analyses demand high performance. At the same time, modern computing…
(more)
▼ Geographic information systems (GIS) are performing increasingly sophisticated analyses on growing data sets. These analyses demand high performance. At the same time, modern computing platforms increasingly derive their performance from several forms of parallelism. This dissertation explores the available parallelism in several GIS-applied algorithms: viewshed calculation, image feature transform, and feature analysis. It presents implementations of these algorithms that exploit parallel processing to reduce execution time, and analyzes the effectiveness of the implementations in their use of parallel processing.
Advisors/Committee Members: Amy W. Apon, John Gauch, Miaoqing Huang.
Subjects/Keywords: Applied sciences; Geomatics; Geospatial analysis; Parallel architectures; Sift; Viewshed; Computer Sciences; Systems Architecture
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APA (6th Edition):
Warn, S. (2011). High Performance Geospatial Analysis on Emerging Parallel Architectures. (Doctoral Dissertation). University of Arkansas. Retrieved from https://scholarworks.uark.edu/etd/156
Chicago Manual of Style (16th Edition):
Warn, Seth. “High Performance Geospatial Analysis on Emerging Parallel Architectures.” 2011. Doctoral Dissertation, University of Arkansas. Accessed November 14, 2019.
https://scholarworks.uark.edu/etd/156.
MLA Handbook (7th Edition):
Warn, Seth. “High Performance Geospatial Analysis on Emerging Parallel Architectures.” 2011. Web. 14 Nov 2019.
Vancouver:
Warn S. High Performance Geospatial Analysis on Emerging Parallel Architectures. [Internet] [Doctoral dissertation]. University of Arkansas; 2011. [cited 2019 Nov 14].
Available from: https://scholarworks.uark.edu/etd/156.
Council of Science Editors:
Warn S. High Performance Geospatial Analysis on Emerging Parallel Architectures. [Doctoral Dissertation]. University of Arkansas; 2011. Available from: https://scholarworks.uark.edu/etd/156
University of Arkansas
7.
Cartwright, Eugene Anthony, III.
Extending the HybridThread SMP Model for Distributed Memory Systems.
Degree: MSCmpE, 2012, University of Arkansas
URL: https://scholarworks.uark.edu/etd/400
► Memory Hierarchy is of growing importance in system design today. As Moore's Law allows system designers to include more processors within their designs, data…
(more)
▼ Memory Hierarchy is of growing importance in system design today. As Moore's Law allows system designers to include more processors within their designs, data locality becomes a priority. Traditional multiprocessor systems on chip (MPSoC) experience difficulty scaling as the quantity of processors increases. This challenge is common behavior of memory accesses in a shared memory environment and causes a decrease in memory bandwidth as processor numbers increase. In order to provide the necessary levels of scalability, the computer architecture community has sought to decentralize memory accesses by distributing memory throughout the system. Distributed memory offers greater bandwidth due to decoupled access paths. Today's million gate Field Programmable Gate Arrays (FPGA) offer an invaluable opportunity to explore this type of memory hierarchy. FPGA vendors such as Xilinx provide dual-ported on-chip memory for decoupled access in addition to configurable sized memories. In this work, a new platform was created around the use of dual-ported SRAMs for distributed memory to explore the possible scalability of this form of memory hierarchy. However, developing distributed memory poses a tremendous challenge: supporting a linear address space that allows wide applicability to be achieved. Many have agreed that a linear address space eases the programmability of a system. Although the abstraction of disjointed memories via underlying architecture and/or new programming presents an advantage in exploring the possibilities of distributed memory, automatic data partitioning and migration remains a considerable challenge. In this research this challenge was dealt with by the inclusion of both a shared memory and distributed memory model. This research is vital because exposing the programmer to the underlying architecture while providing a linear address space results in desired standards of programmability and performance alike. In addition, standard shared memory programming models can be applied allowing the user to enjoy full scalable performance potential.
Advisors/Committee Members: David Andrews, Miaoqing Huang, Christophe Bobda.
Subjects/Keywords: Applied sciences; FPGA; Memory hierarchy; Multiprocessor; Reconfigurable computing; Digital Communications and Networking; Graphics and Human Computer Interfaces
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APA ·
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APA (6th Edition):
Cartwright, Eugene Anthony, I. (2012). Extending the HybridThread SMP Model for Distributed Memory Systems. (Masters Thesis). University of Arkansas. Retrieved from https://scholarworks.uark.edu/etd/400
Chicago Manual of Style (16th Edition):
Cartwright, Eugene Anthony, III. “Extending the HybridThread SMP Model for Distributed Memory Systems.” 2012. Masters Thesis, University of Arkansas. Accessed November 14, 2019.
https://scholarworks.uark.edu/etd/400.
MLA Handbook (7th Edition):
Cartwright, Eugene Anthony, III. “Extending the HybridThread SMP Model for Distributed Memory Systems.” 2012. Web. 14 Nov 2019.
Vancouver:
Cartwright, Eugene Anthony I. Extending the HybridThread SMP Model for Distributed Memory Systems. [Internet] [Masters thesis]. University of Arkansas; 2012. [cited 2019 Nov 14].
Available from: https://scholarworks.uark.edu/etd/400.
Council of Science Editors:
Cartwright, Eugene Anthony I. Extending the HybridThread SMP Model for Distributed Memory Systems. [Masters Thesis]. University of Arkansas; 2012. Available from: https://scholarworks.uark.edu/etd/400
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