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You searched for +publisher:"Texas A&M University" +contributor:("Shi, Weiping"). Showing records 1 – 30 of 74 total matches.

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Texas A&M University

1. Li, Youjie. Energy Efficient Spiking Neuromorphic Architectures for Pattern Recognition.

Degree: MS, Computer Engineering, 2016, Texas A&M University

 There is a growing concern over reliability, power consumption, and performance of traditional Von Neumann machines, especially when dealing with complex tasks like pattern recognition.… (more)

Subjects/Keywords: Neuromorphic VLSI; spiking neural networks; approximate computing; pattern recognition

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APA (6th Edition):

Li, Y. (2016). Energy Efficient Spiking Neuromorphic Architectures for Pattern Recognition. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/156946

Chicago Manual of Style (16th Edition):

Li, Youjie. “Energy Efficient Spiking Neuromorphic Architectures for Pattern Recognition.” 2016. Masters Thesis, Texas A&M University. Accessed July 21, 2019. http://hdl.handle.net/1969.1/156946.

MLA Handbook (7th Edition):

Li, Youjie. “Energy Efficient Spiking Neuromorphic Architectures for Pattern Recognition.” 2016. Web. 21 Jul 2019.

Vancouver:

Li Y. Energy Efficient Spiking Neuromorphic Architectures for Pattern Recognition. [Internet] [Masters thesis]. Texas A&M University; 2016. [cited 2019 Jul 21]. Available from: http://hdl.handle.net/1969.1/156946.

Council of Science Editors:

Li Y. Energy Efficient Spiking Neuromorphic Architectures for Pattern Recognition. [Masters Thesis]. Texas A&M University; 2016. Available from: http://hdl.handle.net/1969.1/156946


Texas A&M University

2. Boga, Viswanath. Optimization of Pseudo Functional Path Delay Test Through Embedded Memories.

Degree: MS, Computer Science, 2016, Texas A&M University

 Traditional automatic test pattern generation achieves high coverage of logic faults in integrated circuits. Automatic test of embedded memory arrays uses built-in self-test. Testing the… (more)

Subjects/Keywords: embedded memory; circuit; path; generation; gate; heuristics; optimization; esperance; SmartPERT; PERT

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APA (6th Edition):

Boga, V. (2016). Optimization of Pseudo Functional Path Delay Test Through Embedded Memories. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/156962

Chicago Manual of Style (16th Edition):

Boga, Viswanath. “Optimization of Pseudo Functional Path Delay Test Through Embedded Memories.” 2016. Masters Thesis, Texas A&M University. Accessed July 21, 2019. http://hdl.handle.net/1969.1/156962.

MLA Handbook (7th Edition):

Boga, Viswanath. “Optimization of Pseudo Functional Path Delay Test Through Embedded Memories.” 2016. Web. 21 Jul 2019.

Vancouver:

Boga V. Optimization of Pseudo Functional Path Delay Test Through Embedded Memories. [Internet] [Masters thesis]. Texas A&M University; 2016. [cited 2019 Jul 21]. Available from: http://hdl.handle.net/1969.1/156962.

Council of Science Editors:

Boga V. Optimization of Pseudo Functional Path Delay Test Through Embedded Memories. [Masters Thesis]. Texas A&M University; 2016. Available from: http://hdl.handle.net/1969.1/156962


Texas A&M University

3. Bekal, Prasanna. Analysis and Modeling of Parasitic Capacitances in Advanced Nanoscale Devices.

Degree: 2012, Texas A&M University

 In order to correctly perform circuit simulation, it is crucial that parasitic capacitances near devices are accurately extracted and are consistent with the SPICE models.… (more)

Subjects/Keywords: Parasitic Extraction; fringing capacitance; MOSFET; Vertical BJT; FinFET; 3D Fieldsolver; Calibre xACT

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APA (6th Edition):

Bekal, P. (2012). Analysis and Modeling of Parasitic Capacitances in Advanced Nanoscale Devices. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2012-05-11215

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Bekal, Prasanna. “Analysis and Modeling of Parasitic Capacitances in Advanced Nanoscale Devices.” 2012. Thesis, Texas A&M University. Accessed July 21, 2019. http://hdl.handle.net/1969.1/ETD-TAMU-2012-05-11215.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Bekal, Prasanna. “Analysis and Modeling of Parasitic Capacitances in Advanced Nanoscale Devices.” 2012. Web. 21 Jul 2019.

Vancouver:

Bekal P. Analysis and Modeling of Parasitic Capacitances in Advanced Nanoscale Devices. [Internet] [Thesis]. Texas A&M University; 2012. [cited 2019 Jul 21]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2012-05-11215.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Bekal P. Analysis and Modeling of Parasitic Capacitances in Advanced Nanoscale Devices. [Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2012-05-11215

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

4. Yang, Gongming. NoC Resource Allocation Based on Physical Design Techniques.

Degree: 2014, Texas A&M University

 Networks-on-Chip (NoC) has been recognized as a scalable approach for on-chip communication. Quality-of-Service (QoS) is a fundamental part of application specific NoCs. This thesis focuses… (more)

Subjects/Keywords: Networks-on-Chip; NoC; TDM; application-specific; QoS; Resource allocation; TDM; RRR

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APA (6th Edition):

Yang, G. (2014). NoC Resource Allocation Based on Physical Design Techniques. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/152739

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yang, Gongming. “NoC Resource Allocation Based on Physical Design Techniques.” 2014. Thesis, Texas A&M University. Accessed July 21, 2019. http://hdl.handle.net/1969.1/152739.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yang, Gongming. “NoC Resource Allocation Based on Physical Design Techniques.” 2014. Web. 21 Jul 2019.

Vancouver:

Yang G. NoC Resource Allocation Based on Physical Design Techniques. [Internet] [Thesis]. Texas A&M University; 2014. [cited 2019 Jul 21]. Available from: http://hdl.handle.net/1969.1/152739.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yang G. NoC Resource Allocation Based on Physical Design Techniques. [Thesis]. Texas A&M University; 2014. Available from: http://hdl.handle.net/1969.1/152739

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

5. Li, Zhixing. Machine Learning Applied in 2D Parasitic Extraction.

Degree: 2014, Texas A&M University

 With the scale of interconnect number grows to billions, parasitic capacitance extraction speed is an important issue for fast turn-around time for designers. In this… (more)

Subjects/Keywords: Machine learning; fast and accurate extraction

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Li, Z. (2014). Machine Learning Applied in 2D Parasitic Extraction. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/154203

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Li, Zhixing. “Machine Learning Applied in 2D Parasitic Extraction.” 2014. Thesis, Texas A&M University. Accessed July 21, 2019. http://hdl.handle.net/1969.1/154203.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Li, Zhixing. “Machine Learning Applied in 2D Parasitic Extraction.” 2014. Web. 21 Jul 2019.

Vancouver:

Li Z. Machine Learning Applied in 2D Parasitic Extraction. [Internet] [Thesis]. Texas A&M University; 2014. [cited 2019 Jul 21]. Available from: http://hdl.handle.net/1969.1/154203.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Li Z. Machine Learning Applied in 2D Parasitic Extraction. [Thesis]. Texas A&M University; 2014. Available from: http://hdl.handle.net/1969.1/154203

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

6. Elliott, Lee Bryan. Utilizing Criticality Stacks for Dynamic Voltage and Frequency Scaling.

Degree: MS, Computer Engineering, 2018, Texas A&M University

 Thread imbalance is inevitable for multithreaded applications due to the necessity of synchronization primitives to coordinate access to memory and system resources. This imbalance leads… (more)

Subjects/Keywords: Criticality; Scalability; Mutlti-threaded Applications; Chip Multi-Processors; Dynamic Voltage and Frequency Scaling; DVFS; Load Imbalance; Energy

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Elliott, L. B. (2018). Utilizing Criticality Stacks for Dynamic Voltage and Frequency Scaling. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/174128

Chicago Manual of Style (16th Edition):

Elliott, Lee Bryan. “Utilizing Criticality Stacks for Dynamic Voltage and Frequency Scaling.” 2018. Masters Thesis, Texas A&M University. Accessed July 21, 2019. http://hdl.handle.net/1969.1/174128.

MLA Handbook (7th Edition):

Elliott, Lee Bryan. “Utilizing Criticality Stacks for Dynamic Voltage and Frequency Scaling.” 2018. Web. 21 Jul 2019.

Vancouver:

Elliott LB. Utilizing Criticality Stacks for Dynamic Voltage and Frequency Scaling. [Internet] [Masters thesis]. Texas A&M University; 2018. [cited 2019 Jul 21]. Available from: http://hdl.handle.net/1969.1/174128.

Council of Science Editors:

Elliott LB. Utilizing Criticality Stacks for Dynamic Voltage and Frequency Scaling. [Masters Thesis]. Texas A&M University; 2018. Available from: http://hdl.handle.net/1969.1/174128


Texas A&M University

7. Chakraborty, Avijit. Observability Driven Path Generation for Delay Test.

Degree: 2015, Texas A&M University

 This research describes an approach for path generation using an observability metric for delay test. K Longest Path Per Gate (KLPG) tests are generated for… (more)

Subjects/Keywords: Delay Test; Observability; Scan Architecture; At-Speed Test; Test Coverage

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chakraborty, A. (2015). Observability Driven Path Generation for Delay Test. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/156207

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chakraborty, Avijit. “Observability Driven Path Generation for Delay Test.” 2015. Thesis, Texas A&M University. Accessed July 21, 2019. http://hdl.handle.net/1969.1/156207.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chakraborty, Avijit. “Observability Driven Path Generation for Delay Test.” 2015. Web. 21 Jul 2019.

Vancouver:

Chakraborty A. Observability Driven Path Generation for Delay Test. [Internet] [Thesis]. Texas A&M University; 2015. [cited 2019 Jul 21]. Available from: http://hdl.handle.net/1969.1/156207.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chakraborty A. Observability Driven Path Generation for Delay Test. [Thesis]. Texas A&M University; 2015. Available from: http://hdl.handle.net/1969.1/156207

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

8. Lee, Won Suk. High Performance Organic Transistors for Organic Electronic Applications.

Degree: 2017, Texas A&M University

 Thin-film transistor (TFT) devices using organic semiconducting materials have attracted widespread attentions due to their low cost, flexible form factor, and easy fabrication. However, organic… (more)

Subjects/Keywords: Organic electronics; OTFT; OMESFET; OHBT

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APA (6th Edition):

Lee, W. S. (2017). High Performance Organic Transistors for Organic Electronic Applications. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/161384

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lee, Won Suk. “High Performance Organic Transistors for Organic Electronic Applications.” 2017. Thesis, Texas A&M University. Accessed July 21, 2019. http://hdl.handle.net/1969.1/161384.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lee, Won Suk. “High Performance Organic Transistors for Organic Electronic Applications.” 2017. Web. 21 Jul 2019.

Vancouver:

Lee WS. High Performance Organic Transistors for Organic Electronic Applications. [Internet] [Thesis]. Texas A&M University; 2017. [cited 2019 Jul 21]. Available from: http://hdl.handle.net/1969.1/161384.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lee WS. High Performance Organic Transistors for Organic Electronic Applications. [Thesis]. Texas A&M University; 2017. Available from: http://hdl.handle.net/1969.1/161384

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

9. Ahn, Seungjai. Energy-efficient Q-learning for Collision Avoidance of Autonomous Robots.

Degree: 2017, Texas A&M University

 Recently, many companies have been studying intelligent cars, and improvements in sensor technology and computing are required. The intelligent cars use GPS to know where… (more)

Subjects/Keywords: Reinforcement Learning; Robot

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APA (6th Edition):

Ahn, S. (2017). Energy-efficient Q-learning for Collision Avoidance of Autonomous Robots. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/161486

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ahn, Seungjai. “Energy-efficient Q-learning for Collision Avoidance of Autonomous Robots.” 2017. Thesis, Texas A&M University. Accessed July 21, 2019. http://hdl.handle.net/1969.1/161486.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ahn, Seungjai. “Energy-efficient Q-learning for Collision Avoidance of Autonomous Robots.” 2017. Web. 21 Jul 2019.

Vancouver:

Ahn S. Energy-efficient Q-learning for Collision Avoidance of Autonomous Robots. [Internet] [Thesis]. Texas A&M University; 2017. [cited 2019 Jul 21]. Available from: http://hdl.handle.net/1969.1/161486.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ahn S. Energy-efficient Q-learning for Collision Avoidance of Autonomous Robots. [Thesis]. Texas A&M University; 2017. Available from: http://hdl.handle.net/1969.1/161486

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

10. Wu, Lei. An efficient logic fault diagnosis framework based on effect-cause approach.

Degree: 2009, Texas A&M University

 Fault diagnosis plays an important role in improving the circuit design process and the manufacturing yield. With the increasing number of gates in modern circuits,… (more)

Subjects/Keywords: VLSI; diagnosis; effect-cause; critical path tracing; logic fault

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APA (6th Edition):

Wu, L. (2009). An efficient logic fault diagnosis framework based on effect-cause approach. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2442

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wu, Lei. “An efficient logic fault diagnosis framework based on effect-cause approach.” 2009. Thesis, Texas A&M University. Accessed July 21, 2019. http://hdl.handle.net/1969.1/ETD-TAMU-2442.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wu, Lei. “An efficient logic fault diagnosis framework based on effect-cause approach.” 2009. Web. 21 Jul 2019.

Vancouver:

Wu L. An efficient logic fault diagnosis framework based on effect-cause approach. [Internet] [Thesis]. Texas A&M University; 2009. [cited 2019 Jul 21]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2442.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wu L. An efficient logic fault diagnosis framework based on effect-cause approach. [Thesis]. Texas A&M University; 2009. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2442

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

11. Doddannagari, Uday. A p-cell approach to integer gate sizing.

Degree: 2009, Texas A&M University

 Standard-Cell-library-based design ow is widely followed in the Application Specific Integrated Circuit(ASIC) industry. Most of the realistic cell libraries are geometrically spaced introducing significant sparseness… (more)

Subjects/Keywords: p-cell; delay model

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APA (6th Edition):

Doddannagari, U. (2009). A p-cell approach to integer gate sizing. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2443

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Doddannagari, Uday. “A p-cell approach to integer gate sizing.” 2009. Thesis, Texas A&M University. Accessed July 21, 2019. http://hdl.handle.net/1969.1/ETD-TAMU-2443.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Doddannagari, Uday. “A p-cell approach to integer gate sizing.” 2009. Web. 21 Jul 2019.

Vancouver:

Doddannagari U. A p-cell approach to integer gate sizing. [Internet] [Thesis]. Texas A&M University; 2009. [cited 2019 Jul 21]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2443.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Doddannagari U. A p-cell approach to integer gate sizing. [Thesis]. Texas A&M University; 2009. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2443

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

12. Men, Kun. Long term voltage stability analysis for small disturbances.

Degree: 2009, Texas A&M University

 This dissertation attempts to establish an analytical and comprehensive framework to deal with two critical challenges associated with voltage stability analysis: 1. To study the… (more)

Subjects/Keywords: power system; voltage stability; small disturbance analysis; stability margin; numerical simulation

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APA (6th Edition):

Men, K. (2009). Long term voltage stability analysis for small disturbances. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2499

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Men, Kun. “Long term voltage stability analysis for small disturbances.” 2009. Thesis, Texas A&M University. Accessed July 21, 2019. http://hdl.handle.net/1969.1/ETD-TAMU-2499.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Men, Kun. “Long term voltage stability analysis for small disturbances.” 2009. Web. 21 Jul 2019.

Vancouver:

Men K. Long term voltage stability analysis for small disturbances. [Internet] [Thesis]. Texas A&M University; 2009. [cited 2019 Jul 21]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2499.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Men K. Long term voltage stability analysis for small disturbances. [Thesis]. Texas A&M University; 2009. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2499

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

13. Samanta, Rupak. Design methodologies for variation-aware integrated circuits.

Degree: 2009, Texas A&M University

 The scaling of VLSI technology has spurred a rapid growth in the semiconductor industry. With the CMOS device dimension scaling to and beyond 90nm technology,… (more)

Subjects/Keywords: Clock; Buffer; Variation; Power; Noise; Elastic; Sizing

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APA (6th Edition):

Samanta, R. (2009). Design methodologies for variation-aware integrated circuits. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-3119

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Samanta, Rupak. “Design methodologies for variation-aware integrated circuits.” 2009. Thesis, Texas A&M University. Accessed July 21, 2019. http://hdl.handle.net/1969.1/ETD-TAMU-3119.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Samanta, Rupak. “Design methodologies for variation-aware integrated circuits.” 2009. Web. 21 Jul 2019.

Vancouver:

Samanta R. Design methodologies for variation-aware integrated circuits. [Internet] [Thesis]. Texas A&M University; 2009. [cited 2019 Jul 21]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-3119.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Samanta R. Design methodologies for variation-aware integrated circuits. [Thesis]. Texas A&M University; 2009. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-3119

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

14. Shah, Pratik Jitendra. Case studies on lithography-friendly vlsi circuit layout.

Degree: 2009, Texas A&M University

 Moore?s Law has driven a continuous demand for decreasing feature sizes used in Very Large Scale Integrated (VLSI) technology which has outpaced the solutions offered… (more)

Subjects/Keywords: Lithography; VLSI; layout

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APA (6th Edition):

Shah, P. J. (2009). Case studies on lithography-friendly vlsi circuit layout. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-3120

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Shah, Pratik Jitendra. “Case studies on lithography-friendly vlsi circuit layout.” 2009. Thesis, Texas A&M University. Accessed July 21, 2019. http://hdl.handle.net/1969.1/ETD-TAMU-3120.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Shah, Pratik Jitendra. “Case studies on lithography-friendly vlsi circuit layout.” 2009. Web. 21 Jul 2019.

Vancouver:

Shah PJ. Case studies on lithography-friendly vlsi circuit layout. [Internet] [Thesis]. Texas A&M University; 2009. [cited 2019 Jul 21]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-3120.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Shah PJ. Case studies on lithography-friendly vlsi circuit layout. [Thesis]. Texas A&M University; 2009. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-3120

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

15. Venkataraman, Ganesh. Variation and power issues in VLSI clock networks.

Degree: 2009, Texas A&M University

 Clock Distribution Network (CDN) is an important component of any synchronous logic circuit. The function of CDN is to deliver the clock signal to the… (more)

Subjects/Keywords: variation; power; clock distribution

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Venkataraman, G. (2009). Variation and power issues in VLSI clock networks. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-1250

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Venkataraman, Ganesh. “Variation and power issues in VLSI clock networks.” 2009. Thesis, Texas A&M University. Accessed July 21, 2019. http://hdl.handle.net/1969.1/ETD-TAMU-1250.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Venkataraman, Ganesh. “Variation and power issues in VLSI clock networks.” 2009. Web. 21 Jul 2019.

Vancouver:

Venkataraman G. Variation and power issues in VLSI clock networks. [Internet] [Thesis]. Texas A&M University; 2009. [cited 2019 Jul 21]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-1250.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Venkataraman G. Variation and power issues in VLSI clock networks. [Thesis]. Texas A&M University; 2009. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-1250

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

16. Henrichson, Trenton D. Countering Aging Effects through Field Gate Sizing.

Degree: 2010, Texas A&M University

 Transistor aging through negative bias temperature instability (NBTI) has become a major lifetime constraint in VLSI circuits. We propose a technique that uses antifuses to… (more)

Subjects/Keywords: Transistor Ageing Antifuse NBTI negative bias temperature instability FTS Field Transistor Sizing

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Henrichson, T. D. (2010). Countering Aging Effects through Field Gate Sizing. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2008-12-100

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Henrichson, Trenton D. “Countering Aging Effects through Field Gate Sizing.” 2010. Thesis, Texas A&M University. Accessed July 21, 2019. http://hdl.handle.net/1969.1/ETD-TAMU-2008-12-100.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Henrichson, Trenton D. “Countering Aging Effects through Field Gate Sizing.” 2010. Web. 21 Jul 2019.

Vancouver:

Henrichson TD. Countering Aging Effects through Field Gate Sizing. [Internet] [Thesis]. Texas A&M University; 2010. [cited 2019 Jul 21]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2008-12-100.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Henrichson TD. Countering Aging Effects through Field Gate Sizing. [Thesis]. Texas A&M University; 2010. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2008-12-100

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

17. Zhou, Ying. Modeling and Simulation of Advanced Nano-Scale Very Large Scale Integration Circuits.

Degree: 2010, Texas A&M University

 With VLSI(very large scale integration) technology shrinking and frequency increasing, the minimum feature size is smaller than sub-wavelength lithography wavelength, and the manufacturing cost is… (more)

Subjects/Keywords: capacitance extraction; BEOL impact; lithography effect; physical synthesis flow

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APA (6th Edition):

Zhou, Y. (2010). Modeling and Simulation of Advanced Nano-Scale Very Large Scale Integration Circuits. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2010-05-7677

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Zhou, Ying. “Modeling and Simulation of Advanced Nano-Scale Very Large Scale Integration Circuits.” 2010. Thesis, Texas A&M University. Accessed July 21, 2019. http://hdl.handle.net/1969.1/ETD-TAMU-2010-05-7677.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Zhou, Ying. “Modeling and Simulation of Advanced Nano-Scale Very Large Scale Integration Circuits.” 2010. Web. 21 Jul 2019.

Vancouver:

Zhou Y. Modeling and Simulation of Advanced Nano-Scale Very Large Scale Integration Circuits. [Internet] [Thesis]. Texas A&M University; 2010. [cited 2019 Jul 21]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2010-05-7677.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zhou Y. Modeling and Simulation of Advanced Nano-Scale Very Large Scale Integration Circuits. [Thesis]. Texas A&M University; 2010. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2010-05-7677

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

18. Ahn, Youngwoo. Real-Time Task Scheduling under Thermal Constraints.

Degree: 2010, Texas A&M University

 As the speed of integrated circuits increases, so does their power consumption. Most of this power is turned into heat, which must be dissipated effectively… (more)

Subjects/Keywords: Real-Time; Task Scheduling; Thermal

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APA (6th Edition):

Ahn, Y. (2010). Real-Time Task Scheduling under Thermal Constraints. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2010-08-8578

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ahn, Youngwoo. “Real-Time Task Scheduling under Thermal Constraints.” 2010. Thesis, Texas A&M University. Accessed July 21, 2019. http://hdl.handle.net/1969.1/ETD-TAMU-2010-08-8578.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ahn, Youngwoo. “Real-Time Task Scheduling under Thermal Constraints.” 2010. Web. 21 Jul 2019.

Vancouver:

Ahn Y. Real-Time Task Scheduling under Thermal Constraints. [Internet] [Thesis]. Texas A&M University; 2010. [cited 2019 Jul 21]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2010-08-8578.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ahn Y. Real-Time Task Scheduling under Thermal Constraints. [Thesis]. Texas A&M University; 2010. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2010-08-8578

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

19. Yi, Yang. Fast Algorithms for High Frequency Interconnect Modeling in VLSI Circuits and Packages.

Degree: 2011, Texas A&M University

 Interconnect modeling plays an important role in design and verification of VLSI circuits and packages. For low frequency circuits, great advances for parasitic resistance and… (more)

Subjects/Keywords: Interconnect Modeling; Boundary Element Method; Inductance; Impedance.

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APA (6th Edition):

Yi, Y. (2011). Fast Algorithms for High Frequency Interconnect Modeling in VLSI Circuits and Packages. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2009-12-2912

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yi, Yang. “Fast Algorithms for High Frequency Interconnect Modeling in VLSI Circuits and Packages.” 2011. Thesis, Texas A&M University. Accessed July 21, 2019. http://hdl.handle.net/1969.1/ETD-TAMU-2009-12-2912.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yi, Yang. “Fast Algorithms for High Frequency Interconnect Modeling in VLSI Circuits and Packages.” 2011. Web. 21 Jul 2019.

Vancouver:

Yi Y. Fast Algorithms for High Frequency Interconnect Modeling in VLSI Circuits and Packages. [Internet] [Thesis]. Texas A&M University; 2011. [cited 2019 Jul 21]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2009-12-2912.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yi Y. Fast Algorithms for High Frequency Interconnect Modeling in VLSI Circuits and Packages. [Thesis]. Texas A&M University; 2011. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2009-12-2912

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

20. Lu, Hong. Optimization Algorithms for Information Retrieval and Transmission in Distributed Ad Hoc Networks.

Degree: 2010, Texas A&M University

 An ad hoc network is formed by a group of self-configuring nodes, typically deployed in two or three dimensional spaces, and communicating with each other… (more)

Subjects/Keywords: information retrieval; ad hoc network; distance sensitivity

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APA (6th Edition):

Lu, H. (2010). Optimization Algorithms for Information Retrieval and Transmission in Distributed Ad Hoc Networks. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2008-12-187

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lu, Hong. “Optimization Algorithms for Information Retrieval and Transmission in Distributed Ad Hoc Networks.” 2010. Thesis, Texas A&M University. Accessed July 21, 2019. http://hdl.handle.net/1969.1/ETD-TAMU-2008-12-187.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lu, Hong. “Optimization Algorithms for Information Retrieval and Transmission in Distributed Ad Hoc Networks.” 2010. Web. 21 Jul 2019.

Vancouver:

Lu H. Optimization Algorithms for Information Retrieval and Transmission in Distributed Ad Hoc Networks. [Internet] [Thesis]. Texas A&M University; 2010. [cited 2019 Jul 21]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2008-12-187.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lu H. Optimization Algorithms for Information Retrieval and Transmission in Distributed Ad Hoc Networks. [Thesis]. Texas A&M University; 2010. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2008-12-187

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

21. Cobb, Jeffrey Lee. A robust window-based multi-node minimization technique using Boolean relations.

Degree: 2009, Texas A&M University

 Multi-node optimization using Boolean relations is a powerful approach for network minimization. The approach has been studied in theory, and so far its superiority over… (more)

Subjects/Keywords: logic; minimization; relation; don't; cares

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APA (6th Edition):

Cobb, J. L. (2009). A robust window-based multi-node minimization technique using Boolean relations. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2023

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Cobb, Jeffrey Lee. “A robust window-based multi-node minimization technique using Boolean relations.” 2009. Thesis, Texas A&M University. Accessed July 21, 2019. http://hdl.handle.net/1969.1/ETD-TAMU-2023.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Cobb, Jeffrey Lee. “A robust window-based multi-node minimization technique using Boolean relations.” 2009. Web. 21 Jul 2019.

Vancouver:

Cobb JL. A robust window-based multi-node minimization technique using Boolean relations. [Internet] [Thesis]. Texas A&M University; 2009. [cited 2019 Jul 21]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2023.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Cobb JL. A robust window-based multi-node minimization technique using Boolean relations. [Thesis]. Texas A&M University; 2009. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2023

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

22. Jiang, Zhanyuan. Performance and power optimization in VLSI physical design.

Degree: 2009, Texas A&M University

 As VLSI technology enters the nanoscale regime, a great amount of efforts have been made to reduce interconnect delay. Among them, buffer insertion stands out… (more)

Subjects/Keywords: VLSI; physical design; buffer insertion

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APA (6th Edition):

Jiang, Z. (2009). Performance and power optimization in VLSI physical design. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2024

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Jiang, Zhanyuan. “Performance and power optimization in VLSI physical design.” 2009. Thesis, Texas A&M University. Accessed July 21, 2019. http://hdl.handle.net/1969.1/ETD-TAMU-2024.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Jiang, Zhanyuan. “Performance and power optimization in VLSI physical design.” 2009. Web. 21 Jul 2019.

Vancouver:

Jiang Z. Performance and power optimization in VLSI physical design. [Internet] [Thesis]. Texas A&M University; 2009. [cited 2019 Jul 21]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2024.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Jiang Z. Performance and power optimization in VLSI physical design. [Thesis]. Texas A&M University; 2009. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2024

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

23. Kumar, Rajeev. An Efficient Arithmetic Sum-of-Product (SOP) based Multiplication Approach for FIR Filters and DFT.

Degree: 2013, Texas A&M University

 Discrete Fourier Transform (DFT) and Finite Impulse Response (FIR) filters are extensively used in Digital Signal Processing (DSP) and Image Processing. As a result, there… (more)

Subjects/Keywords: SOP; DFT; FIR; MCM

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APA (6th Edition):

Kumar, R. (2013). An Efficient Arithmetic Sum-of-Product (SOP) based Multiplication Approach for FIR Filters and DFT. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/149498

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kumar, Rajeev. “An Efficient Arithmetic Sum-of-Product (SOP) based Multiplication Approach for FIR Filters and DFT.” 2013. Thesis, Texas A&M University. Accessed July 21, 2019. http://hdl.handle.net/1969.1/149498.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kumar, Rajeev. “An Efficient Arithmetic Sum-of-Product (SOP) based Multiplication Approach for FIR Filters and DFT.” 2013. Web. 21 Jul 2019.

Vancouver:

Kumar R. An Efficient Arithmetic Sum-of-Product (SOP) based Multiplication Approach for FIR Filters and DFT. [Internet] [Thesis]. Texas A&M University; 2013. [cited 2019 Jul 21]. Available from: http://hdl.handle.net/1969.1/149498.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kumar R. An Efficient Arithmetic Sum-of-Product (SOP) based Multiplication Approach for FIR Filters and DFT. [Thesis]. Texas A&M University; 2013. Available from: http://hdl.handle.net/1969.1/149498

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

24. Amanor-Boadu, Judy M. A User Programmable Battery Charging System.

Degree: 2013, Texas A&M University

 Rechargeable batteries are found in almost every battery powered application. Be it portable, stationary or motive applications, these batteries go hand in hand with battery… (more)

Subjects/Keywords: batteries; Li-ion; NiMH; power management; energy harvesting; chargers; switched capacitor converter

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APA (6th Edition):

Amanor-Boadu, J. M. (2013). A User Programmable Battery Charging System. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/149560

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Amanor-Boadu, Judy M. “A User Programmable Battery Charging System.” 2013. Thesis, Texas A&M University. Accessed July 21, 2019. http://hdl.handle.net/1969.1/149560.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Amanor-Boadu, Judy M. “A User Programmable Battery Charging System.” 2013. Web. 21 Jul 2019.

Vancouver:

Amanor-Boadu JM. A User Programmable Battery Charging System. [Internet] [Thesis]. Texas A&M University; 2013. [cited 2019 Jul 21]. Available from: http://hdl.handle.net/1969.1/149560.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Amanor-Boadu JM. A User Programmable Battery Charging System. [Thesis]. Texas A&M University; 2013. Available from: http://hdl.handle.net/1969.1/149560

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

25. Xu, Zhaoyan. Analysis and Defense of Emerging Malware Attacks.

Degree: 2014, Texas A&M University

 The persistent evolution of malware intrusion brings great challenges to current anti-malware industry. First, the traditional signature-based detection and prevention schemes produce outgrown signature databases… (more)

Subjects/Keywords: Computer Security; Malware Analysis and Defense

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APA (6th Edition):

Xu, Z. (2014). Analysis and Defense of Emerging Malware Attacks. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/153235

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Xu, Zhaoyan. “Analysis and Defense of Emerging Malware Attacks.” 2014. Thesis, Texas A&M University. Accessed July 21, 2019. http://hdl.handle.net/1969.1/153235.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Xu, Zhaoyan. “Analysis and Defense of Emerging Malware Attacks.” 2014. Web. 21 Jul 2019.

Vancouver:

Xu Z. Analysis and Defense of Emerging Malware Attacks. [Internet] [Thesis]. Texas A&M University; 2014. [cited 2019 Jul 21]. Available from: http://hdl.handle.net/1969.1/153235.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Xu Z. Analysis and Defense of Emerging Malware Attacks. [Thesis]. Texas A&M University; 2014. Available from: http://hdl.handle.net/1969.1/153235

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

26. Pokharel, Mallika Shree. Multi-Cycle at Speed Test.

Degree: MS, Computer Engineering, 2017, Texas A&M University

 In this research, we focus on the development of an algorithm that is used to generate a minimal number of patterns for path delay test… (more)

Subjects/Keywords: preamble; coda; functional cycles

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APA (6th Edition):

Pokharel, M. S. (2017). Multi-Cycle at Speed Test. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/166031

Chicago Manual of Style (16th Edition):

Pokharel, Mallika Shree. “Multi-Cycle at Speed Test.” 2017. Masters Thesis, Texas A&M University. Accessed July 21, 2019. http://hdl.handle.net/1969.1/166031.

MLA Handbook (7th Edition):

Pokharel, Mallika Shree. “Multi-Cycle at Speed Test.” 2017. Web. 21 Jul 2019.

Vancouver:

Pokharel MS. Multi-Cycle at Speed Test. [Internet] [Masters thesis]. Texas A&M University; 2017. [cited 2019 Jul 21]. Available from: http://hdl.handle.net/1969.1/166031.

Council of Science Editors:

Pokharel MS. Multi-Cycle at Speed Test. [Masters Thesis]. Texas A&M University; 2017. Available from: http://hdl.handle.net/1969.1/166031


Texas A&M University

27. Zhai, Sitong. A Layer Centric VLSI Physical Design Methodology Considering Non-uniform Metal Stacks.

Degree: MS, Computer Engineering, 2015, Texas A&M University

 VLSI technology scaling has caused interconnect delay to increasingly dominate the overall chip performance. Optimization techniques such as buffer insertion, wire sizing and layer assignment… (more)

Subjects/Keywords: Layer planning; Interconnect Optimization; buffer insertion; layer assignment; Lagrangian relaxation method; Global routing; VLSI; Physical design

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APA (6th Edition):

Zhai, S. (2015). A Layer Centric VLSI Physical Design Methodology Considering Non-uniform Metal Stacks. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/174189

Chicago Manual of Style (16th Edition):

Zhai, Sitong. “A Layer Centric VLSI Physical Design Methodology Considering Non-uniform Metal Stacks.” 2015. Masters Thesis, Texas A&M University. Accessed July 21, 2019. http://hdl.handle.net/1969.1/174189.

MLA Handbook (7th Edition):

Zhai, Sitong. “A Layer Centric VLSI Physical Design Methodology Considering Non-uniform Metal Stacks.” 2015. Web. 21 Jul 2019.

Vancouver:

Zhai S. A Layer Centric VLSI Physical Design Methodology Considering Non-uniform Metal Stacks. [Internet] [Masters thesis]. Texas A&M University; 2015. [cited 2019 Jul 21]. Available from: http://hdl.handle.net/1969.1/174189.

Council of Science Editors:

Zhai S. A Layer Centric VLSI Physical Design Methodology Considering Non-uniform Metal Stacks. [Masters Thesis]. Texas A&M University; 2015. Available from: http://hdl.handle.net/1969.1/174189


Texas A&M University

28. Lawrence, Ignatius Praveen. Improving Power, Performance and Area with Test: A Case Study.

Degree: MS, Computer Engineering, 2018, Texas A&M University

 As more low power devices are needed for applications such as Internet of Things, reducing power and area is becoming more critical. Reducing power consumption… (more)

Subjects/Keywords: partial scan; stuck-at faults; transition; delay faults; PPA; ATPG; frequency; TNS; near-threshold technology

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APA (6th Edition):

Lawrence, I. P. (2018). Improving Power, Performance and Area with Test: A Case Study. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/173669

Chicago Manual of Style (16th Edition):

Lawrence, Ignatius Praveen. “Improving Power, Performance and Area with Test: A Case Study.” 2018. Masters Thesis, Texas A&M University. Accessed July 21, 2019. http://hdl.handle.net/1969.1/173669.

MLA Handbook (7th Edition):

Lawrence, Ignatius Praveen. “Improving Power, Performance and Area with Test: A Case Study.” 2018. Web. 21 Jul 2019.

Vancouver:

Lawrence IP. Improving Power, Performance and Area with Test: A Case Study. [Internet] [Masters thesis]. Texas A&M University; 2018. [cited 2019 Jul 21]. Available from: http://hdl.handle.net/1969.1/173669.

Council of Science Editors:

Lawrence IP. Improving Power, Performance and Area with Test: A Case Study. [Masters Thesis]. Texas A&M University; 2018. Available from: http://hdl.handle.net/1969.1/173669


Texas A&M University

29. Aishwarya, Fnu. Evaluation of Motion Velocity as a Feature for Sign Language Detection.

Degree: MS, Computer Engineering, 2018, Texas A&M University

 Popular video sharing websites contain a large collection of videos in various sign languages. These websites have the potential of being a significant source of… (more)

Subjects/Keywords: sign language detection; ASL; motion velocity

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APA (6th Edition):

Aishwarya, F. (2018). Evaluation of Motion Velocity as a Feature for Sign Language Detection. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/173575

Chicago Manual of Style (16th Edition):

Aishwarya, Fnu. “Evaluation of Motion Velocity as a Feature for Sign Language Detection.” 2018. Masters Thesis, Texas A&M University. Accessed July 21, 2019. http://hdl.handle.net/1969.1/173575.

MLA Handbook (7th Edition):

Aishwarya, Fnu. “Evaluation of Motion Velocity as a Feature for Sign Language Detection.” 2018. Web. 21 Jul 2019.

Vancouver:

Aishwarya F. Evaluation of Motion Velocity as a Feature for Sign Language Detection. [Internet] [Masters thesis]. Texas A&M University; 2018. [cited 2019 Jul 21]. Available from: http://hdl.handle.net/1969.1/173575.

Council of Science Editors:

Aishwarya F. Evaluation of Motion Velocity as a Feature for Sign Language Detection. [Masters Thesis]. Texas A&M University; 2018. Available from: http://hdl.handle.net/1969.1/173575


Texas A&M University

30. Fan, Xiaohua. High performance building blocks for wireless receiver: multi-stage amplifiers and low noise amplifiers.

Degree: 2009, Texas A&M University

 Different wireless communication systems utilizing different standards and for multiple applications have penetrated the normal people's life, such as Cell phone, Wireless LAN, Bluetooth, Ultra… (more)

Subjects/Keywords: Multi-stage amplifier; Low noise amplifier; LNA; UWB; BIT

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Fan, X. (2009). High performance building blocks for wireless receiver: multi-stage amplifiers and low noise amplifiers. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2497

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Fan, Xiaohua. “High performance building blocks for wireless receiver: multi-stage amplifiers and low noise amplifiers.” 2009. Thesis, Texas A&M University. Accessed July 21, 2019. http://hdl.handle.net/1969.1/ETD-TAMU-2497.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Fan, Xiaohua. “High performance building blocks for wireless receiver: multi-stage amplifiers and low noise amplifiers.” 2009. Web. 21 Jul 2019.

Vancouver:

Fan X. High performance building blocks for wireless receiver: multi-stage amplifiers and low noise amplifiers. [Internet] [Thesis]. Texas A&M University; 2009. [cited 2019 Jul 21]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2497.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Fan X. High performance building blocks for wireless receiver: multi-stage amplifiers and low noise amplifiers. [Thesis]. Texas A&M University; 2009. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2497

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

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