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You searched for +publisher:"Texas A&M University" +contributor:("Kim, Eun Jung"). Showing records 1 – 30 of 63 total matches.

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Texas A&M University

1. Puli, Ramprakash Reddy. Active Routing: Compute on the Way for Near-Data Processing.

Degree: MS, Computer Engineering, 2018, Texas A&M University

 The explosion of data availability and fast data analytic requirements led to the advent of data-intensive applications, characterized by their large memory footprint and low… (more)

Subjects/Keywords: Die-Stacked Memories; Hybrid Memory Cubes; Memory Networks; Near-Data Processing; Commutative Reductions

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APA (6th Edition):

Puli, R. R. (2018). Active Routing: Compute on the Way for Near-Data Processing. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/173535

Chicago Manual of Style (16th Edition):

Puli, Ramprakash Reddy. “Active Routing: Compute on the Way for Near-Data Processing.” 2018. Masters Thesis, Texas A&M University. Accessed September 19, 2020. http://hdl.handle.net/1969.1/173535.

MLA Handbook (7th Edition):

Puli, Ramprakash Reddy. “Active Routing: Compute on the Way for Near-Data Processing.” 2018. Web. 19 Sep 2020.

Vancouver:

Puli RR. Active Routing: Compute on the Way for Near-Data Processing. [Internet] [Masters thesis]. Texas A&M University; 2018. [cited 2020 Sep 19]. Available from: http://hdl.handle.net/1969.1/173535.

Council of Science Editors:

Puli RR. Active Routing: Compute on the Way for Near-Data Processing. [Masters Thesis]. Texas A&M University; 2018. Available from: http://hdl.handle.net/1969.1/173535


Texas A&M University

2. Ni, Ruixiao. On the Effectiveness of Source Throttling for Networks-on-Chip in Chip Multiprocessor Designs.

Degree: MS, Computer Engineering, 2014, Texas A&M University

 In modern chip-multiprocessor (CMP) designs, with the increasing number of cores, traffic between different cores keeps increasing. Consequently, on-chip interconnection networks experience increasingly large communication… (more)

Subjects/Keywords: Source Throtting; Networks-on-Chip; Chip Multiprocessor; TCP-Vegas; gem5; ocin-tsim

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APA (6th Edition):

Ni, R. (2014). On the Effectiveness of Source Throttling for Networks-on-Chip in Chip Multiprocessor Designs. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/152481

Chicago Manual of Style (16th Edition):

Ni, Ruixiao. “On the Effectiveness of Source Throttling for Networks-on-Chip in Chip Multiprocessor Designs.” 2014. Masters Thesis, Texas A&M University. Accessed September 19, 2020. http://hdl.handle.net/1969.1/152481.

MLA Handbook (7th Edition):

Ni, Ruixiao. “On the Effectiveness of Source Throttling for Networks-on-Chip in Chip Multiprocessor Designs.” 2014. Web. 19 Sep 2020.

Vancouver:

Ni R. On the Effectiveness of Source Throttling for Networks-on-Chip in Chip Multiprocessor Designs. [Internet] [Masters thesis]. Texas A&M University; 2014. [cited 2020 Sep 19]. Available from: http://hdl.handle.net/1969.1/152481.

Council of Science Editors:

Ni R. On the Effectiveness of Source Throttling for Networks-on-Chip in Chip Multiprocessor Designs. [Masters Thesis]. Texas A&M University; 2014. Available from: http://hdl.handle.net/1969.1/152481


Texas A&M University

3. Mahapatra, Sonali. Priority Based Switch Allocator in Adaptive Physical Channel Regulator for On Chip Interconnects.

Degree: MS, Computer Engineering, 2014, Texas A&M University

 Chip multiprocessors (CMPs) are now popular design paradigm for microprocessors due to their power, performance and complexity advantages where a number of relatively simple cores… (more)

Subjects/Keywords: CMP; On-Chip Interconnects; Scheduling

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APA (6th Edition):

Mahapatra, S. (2014). Priority Based Switch Allocator in Adaptive Physical Channel Regulator for On Chip Interconnects. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/153378

Chicago Manual of Style (16th Edition):

Mahapatra, Sonali. “Priority Based Switch Allocator in Adaptive Physical Channel Regulator for On Chip Interconnects.” 2014. Masters Thesis, Texas A&M University. Accessed September 19, 2020. http://hdl.handle.net/1969.1/153378.

MLA Handbook (7th Edition):

Mahapatra, Sonali. “Priority Based Switch Allocator in Adaptive Physical Channel Regulator for On Chip Interconnects.” 2014. Web. 19 Sep 2020.

Vancouver:

Mahapatra S. Priority Based Switch Allocator in Adaptive Physical Channel Regulator for On Chip Interconnects. [Internet] [Masters thesis]. Texas A&M University; 2014. [cited 2020 Sep 19]. Available from: http://hdl.handle.net/1969.1/153378.

Council of Science Editors:

Mahapatra S. Priority Based Switch Allocator in Adaptive Physical Channel Regulator for On Chip Interconnects. [Masters Thesis]. Texas A&M University; 2014. Available from: http://hdl.handle.net/1969.1/153378


Texas A&M University

4. Bhosekar, Shilpa. Best Effort Minimal Routing for Fly-Over: A Light Weight Distributed Mechanism for Energy Efficient Network-On-Chip.

Degree: MS, Computer Engineering, 2018, Texas A&M University

 Scalable Networks-on-Chip (NoCs) have become the de facto interconnection mechanism in large scale Chip Multiprocessors. NoCs devour a large fraction of the on-chip power budget… (more)

Subjects/Keywords: FLOV+; power-gating routers; energy efficient NoCs

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APA (6th Edition):

Bhosekar, S. (2018). Best Effort Minimal Routing for Fly-Over: A Light Weight Distributed Mechanism for Energy Efficient Network-On-Chip. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/174084

Chicago Manual of Style (16th Edition):

Bhosekar, Shilpa. “Best Effort Minimal Routing for Fly-Over: A Light Weight Distributed Mechanism for Energy Efficient Network-On-Chip.” 2018. Masters Thesis, Texas A&M University. Accessed September 19, 2020. http://hdl.handle.net/1969.1/174084.

MLA Handbook (7th Edition):

Bhosekar, Shilpa. “Best Effort Minimal Routing for Fly-Over: A Light Weight Distributed Mechanism for Energy Efficient Network-On-Chip.” 2018. Web. 19 Sep 2020.

Vancouver:

Bhosekar S. Best Effort Minimal Routing for Fly-Over: A Light Weight Distributed Mechanism for Energy Efficient Network-On-Chip. [Internet] [Masters thesis]. Texas A&M University; 2018. [cited 2020 Sep 19]. Available from: http://hdl.handle.net/1969.1/174084.

Council of Science Editors:

Bhosekar S. Best Effort Minimal Routing for Fly-Over: A Light Weight Distributed Mechanism for Energy Efficient Network-On-Chip. [Masters Thesis]. Texas A&M University; 2018. Available from: http://hdl.handle.net/1969.1/174084


Texas A&M University

5. Byoun, Jae Guen. Data Traffic Reduction by Exploiting Data Criticality With A Compressor in GPU.

Degree: MS, Computer Science, 2018, Texas A&M University

 Graphics Processing Units (GPUs) have been predominantly accepted for various general purpose applications due to a massive degree of parallelism. The demand for large-scale GPUs… (more)

Subjects/Keywords: GPU; computer architecture

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APA (6th Edition):

Byoun, J. G. (2018). Data Traffic Reduction by Exploiting Data Criticality With A Compressor in GPU. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/173719

Chicago Manual of Style (16th Edition):

Byoun, Jae Guen. “Data Traffic Reduction by Exploiting Data Criticality With A Compressor in GPU.” 2018. Masters Thesis, Texas A&M University. Accessed September 19, 2020. http://hdl.handle.net/1969.1/173719.

MLA Handbook (7th Edition):

Byoun, Jae Guen. “Data Traffic Reduction by Exploiting Data Criticality With A Compressor in GPU.” 2018. Web. 19 Sep 2020.

Vancouver:

Byoun JG. Data Traffic Reduction by Exploiting Data Criticality With A Compressor in GPU. [Internet] [Masters thesis]. Texas A&M University; 2018. [cited 2020 Sep 19]. Available from: http://hdl.handle.net/1969.1/173719.

Council of Science Editors:

Byoun JG. Data Traffic Reduction by Exploiting Data Criticality With A Compressor in GPU. [Masters Thesis]. Texas A&M University; 2018. Available from: http://hdl.handle.net/1969.1/173719


Texas A&M University

6. Chen, Chih-Yuan. A Sub-Centimeter Ranging Precision LIDAR Sensor Prototype Based on ILO-TDC.

Degree: MS, Electrical Engineering, 2016, Texas A&M University

 This thesis introduces a high-resolution light detection and ranging (LIDAR) sensor system-on-a-chip (SoC) that performs sub-centimeter ranging precision and maximally 124-meter ranging distance. With off-chip… (more)

Subjects/Keywords: LIDAR; TCSPC; TDC; ILO; PLL; TIA; LA; clock distribution; jitter

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APA (6th Edition):

Chen, C. (2016). A Sub-Centimeter Ranging Precision LIDAR Sensor Prototype Based on ILO-TDC. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/157844

Chicago Manual of Style (16th Edition):

Chen, Chih-Yuan. “A Sub-Centimeter Ranging Precision LIDAR Sensor Prototype Based on ILO-TDC.” 2016. Masters Thesis, Texas A&M University. Accessed September 19, 2020. http://hdl.handle.net/1969.1/157844.

MLA Handbook (7th Edition):

Chen, Chih-Yuan. “A Sub-Centimeter Ranging Precision LIDAR Sensor Prototype Based on ILO-TDC.” 2016. Web. 19 Sep 2020.

Vancouver:

Chen C. A Sub-Centimeter Ranging Precision LIDAR Sensor Prototype Based on ILO-TDC. [Internet] [Masters thesis]. Texas A&M University; 2016. [cited 2020 Sep 19]. Available from: http://hdl.handle.net/1969.1/157844.

Council of Science Editors:

Chen C. A Sub-Centimeter Ranging Precision LIDAR Sensor Prototype Based on ILO-TDC. [Masters Thesis]. Texas A&M University; 2016. Available from: http://hdl.handle.net/1969.1/157844


Texas A&M University

7. Byoun, Jae Guen. Data Traffic Reduction by Exploiting Data Criticality With A Compressor in GPU.

Degree: MS, Computer Science, 2018, Texas A&M University

 Graphics Processing Units (GPUs) have been predominantly accepted for various general purpose applications due to a massive degree of parallelism. The demand for large-scale GPUs… (more)

Subjects/Keywords: GPU; computer architecture

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APA (6th Edition):

Byoun, J. G. (2018). Data Traffic Reduction by Exploiting Data Criticality With A Compressor in GPU. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/173814

Chicago Manual of Style (16th Edition):

Byoun, Jae Guen. “Data Traffic Reduction by Exploiting Data Criticality With A Compressor in GPU.” 2018. Masters Thesis, Texas A&M University. Accessed September 19, 2020. http://hdl.handle.net/1969.1/173814.

MLA Handbook (7th Edition):

Byoun, Jae Guen. “Data Traffic Reduction by Exploiting Data Criticality With A Compressor in GPU.” 2018. Web. 19 Sep 2020.

Vancouver:

Byoun JG. Data Traffic Reduction by Exploiting Data Criticality With A Compressor in GPU. [Internet] [Masters thesis]. Texas A&M University; 2018. [cited 2020 Sep 19]. Available from: http://hdl.handle.net/1969.1/173814.

Council of Science Editors:

Byoun JG. Data Traffic Reduction by Exploiting Data Criticality With A Compressor in GPU. [Masters Thesis]. Texas A&M University; 2018. Available from: http://hdl.handle.net/1969.1/173814


Texas A&M University

8. Karkala, Vinay. A PLL Design Based on a Standing Wave Resonant Oscillator.

Degree: MS, Computer Engineering, 2011, Texas A&M University

 In this thesis, we present a new continuously variable high frequency standing wave oscillator and demonstrate its use in generating the phase locked clock signal… (more)

Subjects/Keywords: Voltage Controlled Oscillator; VCO; Phase Locked Loop; PLL; Standing Wave Resonant Oscillator; Traveling Wave Resonant Oscillator; Fine Tuning; Coarse Tuning; Transmission line; Parasitic Extraction; Locking Range; Clock distribution

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APA (6th Edition):

Karkala, V. (2011). A PLL Design Based on a Standing Wave Resonant Oscillator. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2010-08-8546

Chicago Manual of Style (16th Edition):

Karkala, Vinay. “A PLL Design Based on a Standing Wave Resonant Oscillator.” 2011. Masters Thesis, Texas A&M University. Accessed September 19, 2020. http://hdl.handle.net/1969.1/ETD-TAMU-2010-08-8546.

MLA Handbook (7th Edition):

Karkala, Vinay. “A PLL Design Based on a Standing Wave Resonant Oscillator.” 2011. Web. 19 Sep 2020.

Vancouver:

Karkala V. A PLL Design Based on a Standing Wave Resonant Oscillator. [Internet] [Masters thesis]. Texas A&M University; 2011. [cited 2020 Sep 19]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2010-08-8546.

Council of Science Editors:

Karkala V. A PLL Design Based on a Standing Wave Resonant Oscillator. [Masters Thesis]. Texas A&M University; 2011. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2010-08-8546


Texas A&M University

9. Yuan, Wen. Hybrid Nanophotonic NOC Design for GPGPU.

Degree: MS, Computer Engineering, 2012, Texas A&M University

 Due to the massive computational power, Graphics Processing Units (GPUs) have become a popular platform for executing general purpose parallel applications. The majority of on-chip… (more)

Subjects/Keywords: NoC; GPGPU; Topology Design; Nanophotonics

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APA (6th Edition):

Yuan, W. (2012). Hybrid Nanophotonic NOC Design for GPGPU. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2012-05-10913

Chicago Manual of Style (16th Edition):

Yuan, Wen. “Hybrid Nanophotonic NOC Design for GPGPU.” 2012. Masters Thesis, Texas A&M University. Accessed September 19, 2020. http://hdl.handle.net/1969.1/ETD-TAMU-2012-05-10913.

MLA Handbook (7th Edition):

Yuan, Wen. “Hybrid Nanophotonic NOC Design for GPGPU.” 2012. Web. 19 Sep 2020.

Vancouver:

Yuan W. Hybrid Nanophotonic NOC Design for GPGPU. [Internet] [Masters thesis]. Texas A&M University; 2012. [cited 2020 Sep 19]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2012-05-10913.

Council of Science Editors:

Yuan W. Hybrid Nanophotonic NOC Design for GPGPU. [Masters Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2012-05-10913


Texas A&M University

10. Chen, Pu. Security Attack Models for Split Manufacturing of Integrated Circuits.

Degree: MS, Computer Engineering, 2016, Texas A&M University

 Split manufacturing of integrated circuits reduces vulnerabilities introduced by an untrusted foundry by manufacturing only a part of design at an untrusted high-end foundry and… (more)

Subjects/Keywords: Security; Split manufacturing; Binary decision diagram; Automatic test pattern generation

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APA (6th Edition):

Chen, P. (2016). Security Attack Models for Split Manufacturing of Integrated Circuits. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/158619

Chicago Manual of Style (16th Edition):

Chen, Pu. “Security Attack Models for Split Manufacturing of Integrated Circuits.” 2016. Masters Thesis, Texas A&M University. Accessed September 19, 2020. http://hdl.handle.net/1969.1/158619.

MLA Handbook (7th Edition):

Chen, Pu. “Security Attack Models for Split Manufacturing of Integrated Circuits.” 2016. Web. 19 Sep 2020.

Vancouver:

Chen P. Security Attack Models for Split Manufacturing of Integrated Circuits. [Internet] [Masters thesis]. Texas A&M University; 2016. [cited 2020 Sep 19]. Available from: http://hdl.handle.net/1969.1/158619.

Council of Science Editors:

Chen P. Security Attack Models for Split Manufacturing of Integrated Circuits. [Masters Thesis]. Texas A&M University; 2016. Available from: http://hdl.handle.net/1969.1/158619


Texas A&M University

11. Boyapati, Rahul. Application Centric Networks-On-Chip Design Solutions for Future Multicore Systems.

Degree: PhD, Computer Engineering, 2017, Texas A&M University

 With advances in technology, future multicore systems scaled to 100s and 1000s of cores/accelerators are being touted as an effective solution for extracting huge performance… (more)

Subjects/Keywords: Networks-On-Chip; Power efficient Designs; Approximate Computing; STT-MRAM technology

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APA (6th Edition):

Boyapati, R. (2017). Application Centric Networks-On-Chip Design Solutions for Future Multicore Systems. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/161506

Chicago Manual of Style (16th Edition):

Boyapati, Rahul. “Application Centric Networks-On-Chip Design Solutions for Future Multicore Systems.” 2017. Doctoral Dissertation, Texas A&M University. Accessed September 19, 2020. http://hdl.handle.net/1969.1/161506.

MLA Handbook (7th Edition):

Boyapati, Rahul. “Application Centric Networks-On-Chip Design Solutions for Future Multicore Systems.” 2017. Web. 19 Sep 2020.

Vancouver:

Boyapati R. Application Centric Networks-On-Chip Design Solutions for Future Multicore Systems. [Internet] [Doctoral dissertation]. Texas A&M University; 2017. [cited 2020 Sep 19]. Available from: http://hdl.handle.net/1969.1/161506.

Council of Science Editors:

Boyapati R. Application Centric Networks-On-Chip Design Solutions for Future Multicore Systems. [Doctoral Dissertation]. Texas A&M University; 2017. Available from: http://hdl.handle.net/1969.1/161506


Texas A&M University

12. Patra, Biplab. Hybrid Router Design for High Performance Photonic Network-On-Chip.

Degree: MS, Computer Engineering, 2015, Texas A&M University

 With rising density of cores in Chip-Multiprocessors, traditional metallic interconnects won't be able to cater to the high demand in communication bandwidth at lower power… (more)

Subjects/Keywords: Photonic; Network-on-chip

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APA (6th Edition):

Patra, B. (2015). Hybrid Router Design for High Performance Photonic Network-On-Chip. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/186979

Chicago Manual of Style (16th Edition):

Patra, Biplab. “Hybrid Router Design for High Performance Photonic Network-On-Chip.” 2015. Masters Thesis, Texas A&M University. Accessed September 19, 2020. http://hdl.handle.net/1969.1/186979.

MLA Handbook (7th Edition):

Patra, Biplab. “Hybrid Router Design for High Performance Photonic Network-On-Chip.” 2015. Web. 19 Sep 2020.

Vancouver:

Patra B. Hybrid Router Design for High Performance Photonic Network-On-Chip. [Internet] [Masters thesis]. Texas A&M University; 2015. [cited 2020 Sep 19]. Available from: http://hdl.handle.net/1969.1/186979.

Council of Science Editors:

Patra B. Hybrid Router Design for High Performance Photonic Network-On-Chip. [Masters Thesis]. Texas A&M University; 2015. Available from: http://hdl.handle.net/1969.1/186979


Texas A&M University

13. Li, Yue. Algorithms and Data Representations for Emerging Non-Volatile Memories.

Degree: PhD, Computer Science, 2014, Texas A&M University

 The evolution of data storage technologies has been extraordinary. Hard disk drives that fit in current personal computers have the capacity that requires tons of… (more)

Subjects/Keywords: Nonvolatile memory; flash memory; phase-change memory; coding theory; error correcting code; write-once memory; reliability; endurance; rank modulation code; scrubbing

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APA (6th Edition):

Li, Y. (2014). Algorithms and Data Representations for Emerging Non-Volatile Memories. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/152646

Chicago Manual of Style (16th Edition):

Li, Yue. “Algorithms and Data Representations for Emerging Non-Volatile Memories.” 2014. Doctoral Dissertation, Texas A&M University. Accessed September 19, 2020. http://hdl.handle.net/1969.1/152646.

MLA Handbook (7th Edition):

Li, Yue. “Algorithms and Data Representations for Emerging Non-Volatile Memories.” 2014. Web. 19 Sep 2020.

Vancouver:

Li Y. Algorithms and Data Representations for Emerging Non-Volatile Memories. [Internet] [Doctoral dissertation]. Texas A&M University; 2014. [cited 2020 Sep 19]. Available from: http://hdl.handle.net/1969.1/152646.

Council of Science Editors:

Li Y. Algorithms and Data Representations for Emerging Non-Volatile Memories. [Doctoral Dissertation]. Texas A&M University; 2014. Available from: http://hdl.handle.net/1969.1/152646


Texas A&M University

14. Vikram Kulkarni, Nikhil. STT-MRAM Based NoC Buffer Design.

Degree: MS, Computer Engineering, 2012, Texas A&M University

 As Chip Multiprocessor (CMP) design moves toward many-core architectures, communication delay in Network-on-Chip (NoC) is a major bottleneck in CMP design. An emerging non-volatile memory… (more)

Subjects/Keywords: STT-MRAM; Noc; Buffer

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APA (6th Edition):

Vikram Kulkarni, N. (2012). STT-MRAM Based NoC Buffer Design. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11684

Chicago Manual of Style (16th Edition):

Vikram Kulkarni, Nikhil. “STT-MRAM Based NoC Buffer Design.” 2012. Masters Thesis, Texas A&M University. Accessed September 19, 2020. http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11684.

MLA Handbook (7th Edition):

Vikram Kulkarni, Nikhil. “STT-MRAM Based NoC Buffer Design.” 2012. Web. 19 Sep 2020.

Vancouver:

Vikram Kulkarni N. STT-MRAM Based NoC Buffer Design. [Internet] [Masters thesis]. Texas A&M University; 2012. [cited 2020 Sep 19]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11684.

Council of Science Editors:

Vikram Kulkarni N. STT-MRAM Based NoC Buffer Design. [Masters Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11684


Texas A&M University

15. Jayabalan, Jagadish. Handshake and Circulation Flow Control in Nanaphotonic Interconnects.

Degree: MS, Computer Engineering, 2012, Texas A&M University

 Nanophotonics has been proposed to design low latency and high bandwidth Network-On-Chip (NOC) for future Chip Multi-Processors (CMPs). Recent nanophotonic NOC designs adopt the token-based… (more)

Subjects/Keywords: Nanophotonics; NOC; Handshake; Circulation

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APA (6th Edition):

Jayabalan, J. (2012). Handshake and Circulation Flow Control in Nanaphotonic Interconnects. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11837

Chicago Manual of Style (16th Edition):

Jayabalan, Jagadish. “Handshake and Circulation Flow Control in Nanaphotonic Interconnects.” 2012. Masters Thesis, Texas A&M University. Accessed September 19, 2020. http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11837.

MLA Handbook (7th Edition):

Jayabalan, Jagadish. “Handshake and Circulation Flow Control in Nanaphotonic Interconnects.” 2012. Web. 19 Sep 2020.

Vancouver:

Jayabalan J. Handshake and Circulation Flow Control in Nanaphotonic Interconnects. [Internet] [Masters thesis]. Texas A&M University; 2012. [cited 2020 Sep 19]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11837.

Council of Science Editors:

Jayabalan J. Handshake and Circulation Flow Control in Nanaphotonic Interconnects. [Masters Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11837


Texas A&M University

16. Gu, Haiyin. VLPW: The Very Long Packet Window Architecture for High Throughput Network-On-Chip Router Designs.

Degree: MS, Electrical Engineering, 2012, Texas A&M University

 ChipMulti-processor (CMP) architectures have become mainstream for designing processors. With a large number of cores, Network-On-Chip (NOC) provides a scalable communication method for CMPs. NOC… (more)

Subjects/Keywords: NOC; High Throughput

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APA (6th Edition):

Gu, H. (2012). VLPW: The Very Long Packet Window Architecture for High Throughput Network-On-Chip Router Designs. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2011-08-10094

Chicago Manual of Style (16th Edition):

Gu, Haiyin. “VLPW: The Very Long Packet Window Architecture for High Throughput Network-On-Chip Router Designs.” 2012. Masters Thesis, Texas A&M University. Accessed September 19, 2020. http://hdl.handle.net/1969.1/ETD-TAMU-2011-08-10094.

MLA Handbook (7th Edition):

Gu, Haiyin. “VLPW: The Very Long Packet Window Architecture for High Throughput Network-On-Chip Router Designs.” 2012. Web. 19 Sep 2020.

Vancouver:

Gu H. VLPW: The Very Long Packet Window Architecture for High Throughput Network-On-Chip Router Designs. [Internet] [Masters thesis]. Texas A&M University; 2012. [cited 2020 Sep 19]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2011-08-10094.

Council of Science Editors:

Gu H. VLPW: The Very Long Packet Window Architecture for High Throughput Network-On-Chip Router Designs. [Masters Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2011-08-10094


Texas A&M University

17. Narayana, Sagar 1986-. Throughput-Efficient Network-on-Chip Router Design with STT-MRAM.

Degree: MS, Computer Engineering, 2012, Texas A&M University

 As the number of processor cores on a chip increases with the advance of CMOS technology, there has been a growing need of more efficient… (more)

Subjects/Keywords: input buffer; router; STT-MRAM; Network-on-Chip

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APA (6th Edition):

Narayana, S. 1. (2012). Throughput-Efficient Network-on-Chip Router Design with STT-MRAM. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/148157

Chicago Manual of Style (16th Edition):

Narayana, Sagar 1986-. “Throughput-Efficient Network-on-Chip Router Design with STT-MRAM.” 2012. Masters Thesis, Texas A&M University. Accessed September 19, 2020. http://hdl.handle.net/1969.1/148157.

MLA Handbook (7th Edition):

Narayana, Sagar 1986-. “Throughput-Efficient Network-on-Chip Router Design with STT-MRAM.” 2012. Web. 19 Sep 2020.

Vancouver:

Narayana S1. Throughput-Efficient Network-on-Chip Router Design with STT-MRAM. [Internet] [Masters thesis]. Texas A&M University; 2012. [cited 2020 Sep 19]. Available from: http://hdl.handle.net/1969.1/148157.

Council of Science Editors:

Narayana S1. Throughput-Efficient Network-on-Chip Router Design with STT-MRAM. [Masters Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/148157


Texas A&M University

18. Kim, Hong-Hoe. Analysis of Children's Sketches to Improve Recognition Accuracy in Sketch-Based Applications.

Degree: MS, Computer Science, 2012, Texas A&M University

 The current education systems in elementary schools are usually using traditional teaching methods such as paper and pencil or drawing on the board. The benefit… (more)

Subjects/Keywords: Sketch Recognition; Children's Sketch

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APA (6th Edition):

Kim, H. (2012). Analysis of Children's Sketches to Improve Recognition Accuracy in Sketch-Based Applications. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/148207

Chicago Manual of Style (16th Edition):

Kim, Hong-Hoe. “Analysis of Children's Sketches to Improve Recognition Accuracy in Sketch-Based Applications.” 2012. Masters Thesis, Texas A&M University. Accessed September 19, 2020. http://hdl.handle.net/1969.1/148207.

MLA Handbook (7th Edition):

Kim, Hong-Hoe. “Analysis of Children's Sketches to Improve Recognition Accuracy in Sketch-Based Applications.” 2012. Web. 19 Sep 2020.

Vancouver:

Kim H. Analysis of Children's Sketches to Improve Recognition Accuracy in Sketch-Based Applications. [Internet] [Masters thesis]. Texas A&M University; 2012. [cited 2020 Sep 19]. Available from: http://hdl.handle.net/1969.1/148207.

Council of Science Editors:

Kim H. Analysis of Children's Sketches to Improve Recognition Accuracy in Sketch-Based Applications. [Masters Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/148207


Texas A&M University

19. Wang, Lei. High Performance Interconnect System Design for Future Chip Multiprocessors.

Degree: PhD, Computer Engineering, 2013, Texas A&M University

 Chip Multi-Processor (CMP) architectures have become mainstream for designing processors. With a large number of cores, Network-On-Chip (NOC) provides a scalable communication method for CMP… (more)

Subjects/Keywords: Network-On-Chip; Chip Multiprocessors

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APA (6th Edition):

Wang, L. (2013). High Performance Interconnect System Design for Future Chip Multiprocessors. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/149541

Chicago Manual of Style (16th Edition):

Wang, Lei. “High Performance Interconnect System Design for Future Chip Multiprocessors.” 2013. Doctoral Dissertation, Texas A&M University. Accessed September 19, 2020. http://hdl.handle.net/1969.1/149541.

MLA Handbook (7th Edition):

Wang, Lei. “High Performance Interconnect System Design for Future Chip Multiprocessors.” 2013. Web. 19 Sep 2020.

Vancouver:

Wang L. High Performance Interconnect System Design for Future Chip Multiprocessors. [Internet] [Doctoral dissertation]. Texas A&M University; 2013. [cited 2020 Sep 19]. Available from: http://hdl.handle.net/1969.1/149541.

Council of Science Editors:

Wang L. High Performance Interconnect System Design for Future Chip Multiprocessors. [Doctoral Dissertation]. Texas A&M University; 2013. Available from: http://hdl.handle.net/1969.1/149541


Texas A&M University

20. Deshpande, Hrishikesh. Multipath Router Architectures to Reduce Latency in Network-on-Chips.

Degree: MS, Computer Engineering, 2012, Texas A&M University

 The low latency is a prime concern for large Network-on-Chips (NoCs) typically used in chip-multiprocessors (CMPs) and multiprocessor system-on-chips (MPSoCs). A significant component of overall… (more)

Subjects/Keywords: Network-on-chips; Serialization Latency; Multipath Routing

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APA (6th Edition):

Deshpande, H. (2012). Multipath Router Architectures to Reduce Latency in Network-on-Chips. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2012-05-11208

Chicago Manual of Style (16th Edition):

Deshpande, Hrishikesh. “Multipath Router Architectures to Reduce Latency in Network-on-Chips.” 2012. Masters Thesis, Texas A&M University. Accessed September 19, 2020. http://hdl.handle.net/1969.1/ETD-TAMU-2012-05-11208.

MLA Handbook (7th Edition):

Deshpande, Hrishikesh. “Multipath Router Architectures to Reduce Latency in Network-on-Chips.” 2012. Web. 19 Sep 2020.

Vancouver:

Deshpande H. Multipath Router Architectures to Reduce Latency in Network-on-Chips. [Internet] [Masters thesis]. Texas A&M University; 2012. [cited 2020 Sep 19]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2012-05-11208.

Council of Science Editors:

Deshpande H. Multipath Router Architectures to Reduce Latency in Network-on-Chips. [Masters Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2012-05-11208


Texas A&M University

21. An, Baik Song. Architectural Support for High-Performance, Power-Efficient and Secure Multiprocessor Systems.

Degree: PhD, Computer Science, 2012, Texas A&M University

 High performance systems have been widely adopted in many fields and the demand for better performance is constantly increasing. And the need of powerful yet… (more)

Subjects/Keywords: computer architecture; chip multiprocessor; network-on-chip

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APA (6th Edition):

An, B. S. (2012). Architectural Support for High-Performance, Power-Efficient and Secure Multiprocessor Systems. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11665

Chicago Manual of Style (16th Edition):

An, Baik Song. “Architectural Support for High-Performance, Power-Efficient and Secure Multiprocessor Systems.” 2012. Doctoral Dissertation, Texas A&M University. Accessed September 19, 2020. http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11665.

MLA Handbook (7th Edition):

An, Baik Song. “Architectural Support for High-Performance, Power-Efficient and Secure Multiprocessor Systems.” 2012. Web. 19 Sep 2020.

Vancouver:

An BS. Architectural Support for High-Performance, Power-Efficient and Secure Multiprocessor Systems. [Internet] [Doctoral dissertation]. Texas A&M University; 2012. [cited 2020 Sep 19]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11665.

Council of Science Editors:

An BS. Architectural Support for High-Performance, Power-Efficient and Secure Multiprocessor Systems. [Doctoral Dissertation]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11665


Texas A&M University

22. Wang, Zhe. Improving Processor Design by Exploiting Performance Variance.

Degree: PhD, Computer Science, 2014, Texas A&M University

 Programs exhibit significant performance variance in their access to microarchitectural structures. There are three types of performance variance. First, semantically equivalent programs running on the… (more)

Subjects/Keywords: Performance Model; Cache; DRAM; Replacement Policy; Wirte-Induced Interference; Non-Volatile Memory

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APA (6th Edition):

Wang, Z. (2014). Improving Processor Design by Exploiting Performance Variance. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/153330

Chicago Manual of Style (16th Edition):

Wang, Zhe. “Improving Processor Design by Exploiting Performance Variance.” 2014. Doctoral Dissertation, Texas A&M University. Accessed September 19, 2020. http://hdl.handle.net/1969.1/153330.

MLA Handbook (7th Edition):

Wang, Zhe. “Improving Processor Design by Exploiting Performance Variance.” 2014. Web. 19 Sep 2020.

Vancouver:

Wang Z. Improving Processor Design by Exploiting Performance Variance. [Internet] [Doctoral dissertation]. Texas A&M University; 2014. [cited 2020 Sep 19]. Available from: http://hdl.handle.net/1969.1/153330.

Council of Science Editors:

Wang Z. Improving Processor Design by Exploiting Performance Variance. [Doctoral Dissertation]. Texas A&M University; 2014. Available from: http://hdl.handle.net/1969.1/153330


Texas A&M University

23. Liu, Shan. Coordinated Variable Structure Switching Attacks for Smart Grid.

Degree: PhD, Electrical Engineering, 2013, Texas A&M University

 The effective modeling and analysis of large-scale power system disturbances especially those stemming from intentional attack represents an open engineering and research problem. Challenges stem… (more)

Subjects/Keywords: coordinated switching attacks; power system attacks; cyber security; smart grid modeling; variable structure systems; cyber-physical system theory

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APA (6th Edition):

Liu, S. (2013). Coordinated Variable Structure Switching Attacks for Smart Grid. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/149223

Chicago Manual of Style (16th Edition):

Liu, Shan. “Coordinated Variable Structure Switching Attacks for Smart Grid.” 2013. Doctoral Dissertation, Texas A&M University. Accessed September 19, 2020. http://hdl.handle.net/1969.1/149223.

MLA Handbook (7th Edition):

Liu, Shan. “Coordinated Variable Structure Switching Attacks for Smart Grid.” 2013. Web. 19 Sep 2020.

Vancouver:

Liu S. Coordinated Variable Structure Switching Attacks for Smart Grid. [Internet] [Doctoral dissertation]. Texas A&M University; 2013. [cited 2020 Sep 19]. Available from: http://hdl.handle.net/1969.1/149223.

Council of Science Editors:

Liu S. Coordinated Variable Structure Switching Attacks for Smart Grid. [Doctoral Dissertation]. Texas A&M University; 2013. Available from: http://hdl.handle.net/1969.1/149223


Texas A&M University

24. Ahn, Minseon. Accelerating Communication in On-Chip Interconnection Networks.

Degree: PhD, Computer Science, 2012, Texas A&M University

 Due to the ever-shrinking feature size in CMOS process technology, it is expected that future chip multiprocessors (CMPs) will have hundreds or thousands of processing… (more)

Subjects/Keywords: On-Chip Interconnection Networks; Chip Multiprocessors

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APA (6th Edition):

Ahn, M. (2012). Accelerating Communication in On-Chip Interconnection Networks. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2012-05-10975

Chicago Manual of Style (16th Edition):

Ahn, Minseon. “Accelerating Communication in On-Chip Interconnection Networks.” 2012. Doctoral Dissertation, Texas A&M University. Accessed September 19, 2020. http://hdl.handle.net/1969.1/ETD-TAMU-2012-05-10975.

MLA Handbook (7th Edition):

Ahn, Minseon. “Accelerating Communication in On-Chip Interconnection Networks.” 2012. Web. 19 Sep 2020.

Vancouver:

Ahn M. Accelerating Communication in On-Chip Interconnection Networks. [Internet] [Doctoral dissertation]. Texas A&M University; 2012. [cited 2020 Sep 19]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2012-05-10975.

Council of Science Editors:

Ahn M. Accelerating Communication in On-Chip Interconnection Networks. [Doctoral Dissertation]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2012-05-10975


Texas A&M University

25. Lively, Charles. E-AMOM: An Energy-Aware Modeling and Optimization Methodology for Scientific Applications on Multicore Systems.

Degree: PhD, Computer Engineering, 2012, Texas A&M University

 Power consumption is an important constraint in achieving efficient execution on High Performance Computing Multicore Systems. As the number of cores available on a chip… (more)

Subjects/Keywords: Performance Modeling; Power consumption; Multicore; Parallel Programming; MPI; Hybrid; Power prediction

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APA (6th Edition):

Lively, C. (2012). E-AMOM: An Energy-Aware Modeling and Optimization Methodology for Scientific Applications on Multicore Systems. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2012-05-11095

Chicago Manual of Style (16th Edition):

Lively, Charles. “E-AMOM: An Energy-Aware Modeling and Optimization Methodology for Scientific Applications on Multicore Systems.” 2012. Doctoral Dissertation, Texas A&M University. Accessed September 19, 2020. http://hdl.handle.net/1969.1/ETD-TAMU-2012-05-11095.

MLA Handbook (7th Edition):

Lively, Charles. “E-AMOM: An Energy-Aware Modeling and Optimization Methodology for Scientific Applications on Multicore Systems.” 2012. Web. 19 Sep 2020.

Vancouver:

Lively C. E-AMOM: An Energy-Aware Modeling and Optimization Methodology for Scientific Applications on Multicore Systems. [Internet] [Doctoral dissertation]. Texas A&M University; 2012. [cited 2020 Sep 19]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2012-05-11095.

Council of Science Editors:

Lively C. E-AMOM: An Energy-Aware Modeling and Optimization Methodology for Scientific Applications on Multicore Systems. [Doctoral Dissertation]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2012-05-11095


Texas A&M University

26. Kumar, Reeshav. Communication Reliability in Network on Chip Designs.

Degree: MS, Electrical Engineering, 2012, Texas A&M University

 The performance of low latency Network on Chip (NoC) architectures, which incorporate fast bypass paths to reduce communication latency, is limited by crosstalk induced skewing… (more)

Subjects/Keywords: NoC; Latency; Synchronization; Asynchronous bypass; Crosstalk; Skew; Communication Reliability

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APA (6th Edition):

Kumar, R. (2012). Communication Reliability in Network on Chip Designs. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2011-08-10080

Chicago Manual of Style (16th Edition):

Kumar, Reeshav. “Communication Reliability in Network on Chip Designs.” 2012. Masters Thesis, Texas A&M University. Accessed September 19, 2020. http://hdl.handle.net/1969.1/ETD-TAMU-2011-08-10080.

MLA Handbook (7th Edition):

Kumar, Reeshav. “Communication Reliability in Network on Chip Designs.” 2012. Web. 19 Sep 2020.

Vancouver:

Kumar R. Communication Reliability in Network on Chip Designs. [Internet] [Masters thesis]. Texas A&M University; 2012. [cited 2020 Sep 19]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2011-08-10080.

Council of Science Editors:

Kumar R. Communication Reliability in Network on Chip Designs. [Masters Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2011-08-10080


Texas A&M University

27. Yeo, In Choon. Design and Analysis of Dynamic Thermal Management in Chip Multiprocessors (CMPs).

Degree: PhD, Computer Science, 2011, Texas A&M University

 Chip Multiprocessors (CMPs) have been prevailing in the modern microprocessor market. As the significant heat is converted by the ever-increasing power density and current leakage,… (more)

Subjects/Keywords: Dynamic Thermal Management

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APA (6th Edition):

Yeo, I. C. (2011). Design and Analysis of Dynamic Thermal Management in Chip Multiprocessors (CMPs). (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2009-12-7596

Chicago Manual of Style (16th Edition):

Yeo, In Choon. “Design and Analysis of Dynamic Thermal Management in Chip Multiprocessors (CMPs).” 2011. Doctoral Dissertation, Texas A&M University. Accessed September 19, 2020. http://hdl.handle.net/1969.1/ETD-TAMU-2009-12-7596.

MLA Handbook (7th Edition):

Yeo, In Choon. “Design and Analysis of Dynamic Thermal Management in Chip Multiprocessors (CMPs).” 2011. Web. 19 Sep 2020.

Vancouver:

Yeo IC. Design and Analysis of Dynamic Thermal Management in Chip Multiprocessors (CMPs). [Internet] [Doctoral dissertation]. Texas A&M University; 2011. [cited 2020 Sep 19]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2009-12-7596.

Council of Science Editors:

Yeo IC. Design and Analysis of Dynamic Thermal Management in Chip Multiprocessors (CMPs). [Doctoral Dissertation]. Texas A&M University; 2011. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2009-12-7596


Texas A&M University

28. Jang, Hyunjun. High Performance On-Chip Interconnects Design for Future Many-Core Architectures.

Degree: PhD, Computer Engineering, 2015, Texas A&M University

 Switch-based Network-on-Chip (NoC) is a widely accepted inter-core communication infrastructure for Chip Multiprocessors (CMPs). With the continued advance of CMOS technology, the number of cores… (more)

Subjects/Keywords: Chip Multiprocessors; Network-on-Chip; General Purpose Graphics Processing Units

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APA (6th Edition):

Jang, H. (2015). High Performance On-Chip Interconnects Design for Future Many-Core Architectures. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/156384

Chicago Manual of Style (16th Edition):

Jang, Hyunjun. “High Performance On-Chip Interconnects Design for Future Many-Core Architectures.” 2015. Doctoral Dissertation, Texas A&M University. Accessed September 19, 2020. http://hdl.handle.net/1969.1/156384.

MLA Handbook (7th Edition):

Jang, Hyunjun. “High Performance On-Chip Interconnects Design for Future Many-Core Architectures.” 2015. Web. 19 Sep 2020.

Vancouver:

Jang H. High Performance On-Chip Interconnects Design for Future Many-Core Architectures. [Internet] [Doctoral dissertation]. Texas A&M University; 2015. [cited 2020 Sep 19]. Available from: http://hdl.handle.net/1969.1/156384.

Council of Science Editors:

Jang H. High Performance On-Chip Interconnects Design for Future Many-Core Architectures. [Doctoral Dissertation]. Texas A&M University; 2015. Available from: http://hdl.handle.net/1969.1/156384


Texas A&M University

29. Mirbagher Ajorpaz, Samira. Applying Microarchitectural Prediction to Improve Performance and Security.

Degree: PhD, Computer Science, 2019, Texas A&M University

 Modern processors rely heavily on speculation to provide performance. Techniques such as branch prediction, caching, prefetching, memory dependence prediction etc. use features from recent program… (more)

Subjects/Keywords: Microarchitecture; Prediction; Security; Replacement Policy; Cache; TLB; BTB

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APA (6th Edition):

Mirbagher Ajorpaz, S. (2019). Applying Microarchitectural Prediction to Improve Performance and Security. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/188777

Chicago Manual of Style (16th Edition):

Mirbagher Ajorpaz, Samira. “Applying Microarchitectural Prediction to Improve Performance and Security.” 2019. Doctoral Dissertation, Texas A&M University. Accessed September 19, 2020. http://hdl.handle.net/1969.1/188777.

MLA Handbook (7th Edition):

Mirbagher Ajorpaz, Samira. “Applying Microarchitectural Prediction to Improve Performance and Security.” 2019. Web. 19 Sep 2020.

Vancouver:

Mirbagher Ajorpaz S. Applying Microarchitectural Prediction to Improve Performance and Security. [Internet] [Doctoral dissertation]. Texas A&M University; 2019. [cited 2020 Sep 19]. Available from: http://hdl.handle.net/1969.1/188777.

Council of Science Editors:

Mirbagher Ajorpaz S. Applying Microarchitectural Prediction to Improve Performance and Security. [Doctoral Dissertation]. Texas A&M University; 2019. Available from: http://hdl.handle.net/1969.1/188777

30. Kim, Dongkun. Automatic Seedpoint Selection and Tracing of Microstructures in the Knife-Edge Scanning Microscope Mouse Brain Data Set.

Degree: MS, Computer Science, 2011, Texas A&M University

 The Knife-Edge Scanning Microscope (KESM) enables imaging of an entire mouse brain at sub-micrometer resolution. By using the data sets from the KESM, we can… (more)

Subjects/Keywords: KESM; Automatic seedpoint selection; Tracing neuronal structure; Counting soma

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APA (6th Edition):

Kim, D. (2011). Automatic Seedpoint Selection and Tracing of Microstructures in the Knife-Edge Scanning Microscope Mouse Brain Data Set. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2011-08-10122

Chicago Manual of Style (16th Edition):

Kim, Dongkun. “Automatic Seedpoint Selection and Tracing of Microstructures in the Knife-Edge Scanning Microscope Mouse Brain Data Set.” 2011. Masters Thesis, Texas A&M University. Accessed September 19, 2020. http://hdl.handle.net/1969.1/ETD-TAMU-2011-08-10122.

MLA Handbook (7th Edition):

Kim, Dongkun. “Automatic Seedpoint Selection and Tracing of Microstructures in the Knife-Edge Scanning Microscope Mouse Brain Data Set.” 2011. Web. 19 Sep 2020.

Vancouver:

Kim D. Automatic Seedpoint Selection and Tracing of Microstructures in the Knife-Edge Scanning Microscope Mouse Brain Data Set. [Internet] [Masters thesis]. Texas A&M University; 2011. [cited 2020 Sep 19]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2011-08-10122.

Council of Science Editors:

Kim D. Automatic Seedpoint Selection and Tracing of Microstructures in the Knife-Edge Scanning Microscope Mouse Brain Data Set. [Masters Thesis]. Texas A&M University; 2011. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2011-08-10122

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