Advanced search options

Advanced Search Options 🞨

Browse by author name (“Author name starts with…”).

Find ETDs with:

in
/  
in
/  
in
/  
in

Written in Published in Earliest date Latest date

Sorted by

Results per page:

Sorted by: relevance · author · university · dateNew search

You searched for +publisher:"Texas A&M University" +contributor:("Harris, Rusty H"). Showing records 1 – 2 of 2 total matches.

Search Limiters

Last 2 Years | English Only

No search limiters apply to these results.

▼ Search Limiters


Texas A&M University

1. Kadjo, David. Energy Efficiency and Performance in Multiprocessors Systems on Chip.

Degree: 2015, Texas A&M University

As process technology shrinks, the transistor count on CPUs has increased. The breakdown of Dennard scaling has led to diminishing returns in terms of performance per power. A trend which promises to impact future CPU designs. This breakdown is due in part to the increase in transistor leakage driven static power. We, now, have constrained energy and power budgets. Thus, energy consumption has to be justified by an increased in performance. Simultaneously, architects have shifted to chip multiprocessors(CMPs) designs with large shared last level cache(LLC) to mitigate the cost of long latency off-chip memory access. A primary reason for that shift is the power efficiency of CMPs. Additionally, technology scaling has allowed the integration of platform components on the chip; a design referred to as multiprocessors system on chip (MpSoC). This integration improves the system performance as the communication latency between the components is reduced. Memory subsystems are essential to CPUs performance. Larger caches provide the CPU faster access to a larger data set. Consequently, the size of last level caches have increased to become a significant leakage power dissipation source. We propose a technique to facilitate power gating a partition of the LLC by migrating the high temporal blocks to a live partition; Thus reducing the performance impact. Given the high latency of memory subsystems, prefetching improves CPU performance by speculating future memory accesses and requesting the data ahead of the demand. In the context of CMPs running multiple concurrent processes, prefetching accuracy is critical to prevent cache pollution effects. Furthermore, given the current constraint energy environment, there is a need for lightweight prefetchers with high accuracy. To this end, we present BFetch a lightweight and accurate prefetcher driven by control flow predictions and effective address speculation. MpSoCs have mostly been used in mobile devices. The energy constraint is more pronounced in MpSoCs-based, battery powered mobile devices. The need to address the energy consumption in MpSoCs is further accentuated by the proliferation of mobile devices. This dissertation presents a framework to optimize the energy in MpSoCs. The proposed framework minimizes the energy consumption while meeting performance and power budgets constraints. We first apply this framework to the CPU then extend it to accommodate the GPU. Advisors/Committee Members: Gratz, Paul V. (advisor), Hu, Jiang (committee member), Harris, Rusty H (committee member), Sarin, Vivek (committee member).

Subjects/Keywords: Energy Efficiency; Performance; Graphics; GPU; Cache; Power

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kadjo, D. (2015). Energy Efficiency and Performance in Multiprocessors Systems on Chip. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/155132

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kadjo, David. “Energy Efficiency and Performance in Multiprocessors Systems on Chip.” 2015. Thesis, Texas A&M University. Accessed April 22, 2019. http://hdl.handle.net/1969.1/155132.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kadjo, David. “Energy Efficiency and Performance in Multiprocessors Systems on Chip.” 2015. Web. 22 Apr 2019.

Vancouver:

Kadjo D. Energy Efficiency and Performance in Multiprocessors Systems on Chip. [Internet] [Thesis]. Texas A&M University; 2015. [cited 2019 Apr 22]. Available from: http://hdl.handle.net/1969.1/155132.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kadjo D. Energy Efficiency and Performance in Multiprocessors Systems on Chip. [Thesis]. Texas A&M University; 2015. Available from: http://hdl.handle.net/1969.1/155132

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

2. Lo, Yi-Chen. Patterning Organic Electronics Based on Nanoimprint Lithography.

Degree: 2014, Texas A&M University

The objective of this work is to investigate a high-resolution patterning method based on nanoimprint lithography (NIL) for the fabrication of organic electronics. First, a high-resolution, nondestructive method was developed to pattern organic semiconductors. In this approach, a sacrificial template made of amorphous fluorinated polymer (Teflon-AF) was first patterned by NIL. Poly(3-hexylthiophene) (P3HT), a organic semiconductor, was then spin-coated on the Teflon-AF template. Removing the sacrificial template by a fluorinated solvent achieved high-resolution P3HT patterns. P3HT lines and squares of various sizes (0.35 micron to tens of microns) were obtained by this method. This process of removing the sacrificial template is fully compatible with organic semiconductors. This technique was then used to fabricate passive-matrix organic light-emitting diode (PMOLED) arrays for flat-panel display applications. Fabrication of a self-aligned bottom gate electrode for organic metal semiconductor field effect transistor (OMESFET) was also developed. This self-aligned gate allows the transistor to have a potential to operate in the high frequency. Owing to the lack of an insulating layer, OMESFET can also work in a relatively low voltage range compared to other organic field effect transistors with an insulating layer. This work also demonstrates its capability of patterning alternating self-aligned metals at the nanoscale. This research also developed a low-cost and time-saving technique to create nanostructures by transferring nanoscale polymeric sidewalls into a substrate. This polymer sidewall transfer lithographic technique can be used for generating nanostructures without advanced electron-beam lithography. Potential applications include the fabrication of nanoimprint molds with high-resolution patterns for applications in nanofluidics and nanophotonics. The polymeric sidewall is a vertically spreading layer deposited by spin-coating a polymer solution on a vertical template. Varying processing parameters such as the solution concentration or the spin-coating speed, changes the sidewall dimension, which, after pattern transfer, also changes the structure dimension on the substrate. High-resolution trenches of about 15 nm have been achieved after transferring straight-line sidewalls into the substrate. Other than straight-line sidewall patterns, this method also fabricated ring-shaped patterns including circles, squares, and concentric squares. Finally, a new structure of organic solar cells (OSCs) was investigated for increasing the solar power conversion efficiency. Although the experimental result did not meet the theoretical expectation, reasonable modifications of the device structure will be tested to achieve the goal in the future. Advisors/Committee Members: Cheng, Xing (advisor), Harris, Rusty H (committee member), Sanchez-Sinencio, Edgar (committee member), Grunlan, Jaime (committee member).

Subjects/Keywords: Nanoimprint lithography; Organic electronics; Organic transistors; Organic light emitting diodes; Organic solar cells

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lo, Y. (2014). Patterning Organic Electronics Based on Nanoimprint Lithography. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/152821

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lo, Yi-Chen. “Patterning Organic Electronics Based on Nanoimprint Lithography.” 2014. Thesis, Texas A&M University. Accessed April 22, 2019. http://hdl.handle.net/1969.1/152821.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lo, Yi-Chen. “Patterning Organic Electronics Based on Nanoimprint Lithography.” 2014. Web. 22 Apr 2019.

Vancouver:

Lo Y. Patterning Organic Electronics Based on Nanoimprint Lithography. [Internet] [Thesis]. Texas A&M University; 2014. [cited 2019 Apr 22]. Available from: http://hdl.handle.net/1969.1/152821.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lo Y. Patterning Organic Electronics Based on Nanoimprint Lithography. [Thesis]. Texas A&M University; 2014. Available from: http://hdl.handle.net/1969.1/152821

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

.