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You searched for +publisher:"Texas A&M University" +contributor:("Gratz, Paul"). Showing records 1 – 30 of 71 total matches.

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Texas A&M University

1. Shome, Prithviraj. Towards a Principled Wireless Support in SDN.

Degree: MS, Computer Engineering, 2016, Texas A&M University

 Software Defined Networking (SDN) has recently emerged as a transformational tool to design and operate communication networks and services. While the SDN approach has significant… (more)

Subjects/Keywords: software defined networking; software defined radio; transport layer security protocol; transmission control protocol

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APA (6th Edition):

Shome, P. (2016). Towards a Principled Wireless Support in SDN. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/156986

Chicago Manual of Style (16th Edition):

Shome, Prithviraj. “Towards a Principled Wireless Support in SDN.” 2016. Masters Thesis, Texas A&M University. Accessed April 06, 2020. http://hdl.handle.net/1969.1/156986.

MLA Handbook (7th Edition):

Shome, Prithviraj. “Towards a Principled Wireless Support in SDN.” 2016. Web. 06 Apr 2020.

Vancouver:

Shome P. Towards a Principled Wireless Support in SDN. [Internet] [Masters thesis]. Texas A&M University; 2016. [cited 2020 Apr 06]. Available from: http://hdl.handle.net/1969.1/156986.

Council of Science Editors:

Shome P. Towards a Principled Wireless Support in SDN. [Masters Thesis]. Texas A&M University; 2016. Available from: http://hdl.handle.net/1969.1/156986


Texas A&M University

2. Prabhu, Subodh. Ocin_tsim - A DVFS Aware Simulator for NoC Design Space Exploration and Optimization.

Degree: 2010, Texas A&M University

 Networks-on-Chip (NoCs) are a general purpose, scalable replacement for shared medium wired interconnects offering many practical applications in industry. Dynamic Voltage Frequency Scaling (DVFS) is… (more)

Subjects/Keywords: NoC; DVFS; Network on Chip; Dynamic Voltage Frequency Scaling; NoC Simulator; Power Modeling; Performance Simulator; Ocin_tsim; On Chip Interconnect Network Timing Simulator; OCTS

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APA (6th Edition):

Prabhu, S. (2010). Ocin_tsim - A DVFS Aware Simulator for NoC Design Space Exploration and Optimization. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2010-05-7798

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Prabhu, Subodh. “Ocin_tsim - A DVFS Aware Simulator for NoC Design Space Exploration and Optimization.” 2010. Thesis, Texas A&M University. Accessed April 06, 2020. http://hdl.handle.net/1969.1/ETD-TAMU-2010-05-7798.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Prabhu, Subodh. “Ocin_tsim - A DVFS Aware Simulator for NoC Design Space Exploration and Optimization.” 2010. Web. 06 Apr 2020.

Vancouver:

Prabhu S. Ocin_tsim - A DVFS Aware Simulator for NoC Design Space Exploration and Optimization. [Internet] [Thesis]. Texas A&M University; 2010. [cited 2020 Apr 06]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2010-05-7798.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Prabhu S. Ocin_tsim - A DVFS Aware Simulator for NoC Design Space Exploration and Optimization. [Thesis]. Texas A&M University; 2010. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2010-05-7798

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

3. Ni, Ruixiao. On the Effectiveness of Source Throttling for Networks-on-Chip in Chip Multiprocessor Designs.

Degree: 2014, Texas A&M University

 In modern chip-multiprocessor (CMP) designs, with the increasing number of cores, traffic between different cores keeps increasing. Consequently, on-chip interconnection networks experience increasingly large communication… (more)

Subjects/Keywords: Source Throtting; Networks-on-Chip; Chip Multiprocessor; TCP-Vegas; gem5; ocin-tsim

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ni, R. (2014). On the Effectiveness of Source Throttling for Networks-on-Chip in Chip Multiprocessor Designs. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/152481

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ni, Ruixiao. “On the Effectiveness of Source Throttling for Networks-on-Chip in Chip Multiprocessor Designs.” 2014. Thesis, Texas A&M University. Accessed April 06, 2020. http://hdl.handle.net/1969.1/152481.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ni, Ruixiao. “On the Effectiveness of Source Throttling for Networks-on-Chip in Chip Multiprocessor Designs.” 2014. Web. 06 Apr 2020.

Vancouver:

Ni R. On the Effectiveness of Source Throttling for Networks-on-Chip in Chip Multiprocessor Designs. [Internet] [Thesis]. Texas A&M University; 2014. [cited 2020 Apr 06]. Available from: http://hdl.handle.net/1969.1/152481.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ni R. On the Effectiveness of Source Throttling for Networks-on-Chip in Chip Multiprocessor Designs. [Thesis]. Texas A&M University; 2014. Available from: http://hdl.handle.net/1969.1/152481

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

4. Saha, Sujoy. SDN Enabled Network Efficient Data Regeneration for Distributed Storage Systems.

Degree: MS, Computer Engineering, 2017, Texas A&M University

 Distributed Storage Systems (DSSs) have seen increasing levels of deployment in data centers and in cloud storage networks. DSS provides efficient and cost-effective ways to… (more)

Subjects/Keywords: Reverse Multicast Protocol; SDN

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APA (6th Edition):

Saha, S. (2017). SDN Enabled Network Efficient Data Regeneration for Distributed Storage Systems. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/174892

Chicago Manual of Style (16th Edition):

Saha, Sujoy. “SDN Enabled Network Efficient Data Regeneration for Distributed Storage Systems.” 2017. Masters Thesis, Texas A&M University. Accessed April 06, 2020. http://hdl.handle.net/1969.1/174892.

MLA Handbook (7th Edition):

Saha, Sujoy. “SDN Enabled Network Efficient Data Regeneration for Distributed Storage Systems.” 2017. Web. 06 Apr 2020.

Vancouver:

Saha S. SDN Enabled Network Efficient Data Regeneration for Distributed Storage Systems. [Internet] [Masters thesis]. Texas A&M University; 2017. [cited 2020 Apr 06]. Available from: http://hdl.handle.net/1969.1/174892.

Council of Science Editors:

Saha S. SDN Enabled Network Efficient Data Regeneration for Distributed Storage Systems. [Masters Thesis]. Texas A&M University; 2017. Available from: http://hdl.handle.net/1969.1/174892


Texas A&M University

5. Won, Jae Yeon. Dynamic Voltage and Frequency Scaling Techniques for Chip Multiprocessor Designs.

Degree: 2015, Texas A&M University

 Due to chip power density limitations as well as the recent breakdown of Dennard's Scalingover the past decade, performance growth in microprocessor design has largely… (more)

Subjects/Keywords: power management; DVFS; CMP; resource

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APA (6th Edition):

Won, J. Y. (2015). Dynamic Voltage and Frequency Scaling Techniques for Chip Multiprocessor Designs. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/155587

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Won, Jae Yeon. “Dynamic Voltage and Frequency Scaling Techniques for Chip Multiprocessor Designs.” 2015. Thesis, Texas A&M University. Accessed April 06, 2020. http://hdl.handle.net/1969.1/155587.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Won, Jae Yeon. “Dynamic Voltage and Frequency Scaling Techniques for Chip Multiprocessor Designs.” 2015. Web. 06 Apr 2020.

Vancouver:

Won JY. Dynamic Voltage and Frequency Scaling Techniques for Chip Multiprocessor Designs. [Internet] [Thesis]. Texas A&M University; 2015. [cited 2020 Apr 06]. Available from: http://hdl.handle.net/1969.1/155587.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Won JY. Dynamic Voltage and Frequency Scaling Techniques for Chip Multiprocessor Designs. [Thesis]. Texas A&M University; 2015. Available from: http://hdl.handle.net/1969.1/155587

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

6. Pappireddy, Madhukarreddy. PRITEXT: Processor Reliability Improvement Through Exercise Technique.

Degree: 2016, Texas A&M University

 With continuous improvements in CMOS technology, transistor sizes are shrinking aggressively every year. Unfortunately, such deep submicron process technologies are severely degraded by several wearout… (more)

Subjects/Keywords: NBTI; processor reliability; PMOS stress; input vector control; ATPG; PRITEXT

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APA (6th Edition):

Pappireddy, M. (2016). PRITEXT: Processor Reliability Improvement Through Exercise Technique. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/157769

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Pappireddy, Madhukarreddy. “PRITEXT: Processor Reliability Improvement Through Exercise Technique.” 2016. Thesis, Texas A&M University. Accessed April 06, 2020. http://hdl.handle.net/1969.1/157769.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Pappireddy, Madhukarreddy. “PRITEXT: Processor Reliability Improvement Through Exercise Technique.” 2016. Web. 06 Apr 2020.

Vancouver:

Pappireddy M. PRITEXT: Processor Reliability Improvement Through Exercise Technique. [Internet] [Thesis]. Texas A&M University; 2016. [cited 2020 Apr 06]. Available from: http://hdl.handle.net/1969.1/157769.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Pappireddy M. PRITEXT: Processor Reliability Improvement Through Exercise Technique. [Thesis]. Texas A&M University; 2016. Available from: http://hdl.handle.net/1969.1/157769

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

7. Yang, Yu. Clustering-Based Simultaneous Task and Voltage Scheduling for NoC Systems.

Degree: 2011, Texas A&M University

 Network-on-Chip (NoC) is emerging as a promising communication structure, which is scalable with respect to chip complexity. Meanwhile, latest chip designs are increasingly leveraging multiple… (more)

Subjects/Keywords: Networks-on-chip; multiple voltage-frequency domains; Lagrangian relaxation; clustering

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APA (6th Edition):

Yang, Y. (2011). Clustering-Based Simultaneous Task and Voltage Scheduling for NoC Systems. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2011-05-9130

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yang, Yu. “Clustering-Based Simultaneous Task and Voltage Scheduling for NoC Systems.” 2011. Thesis, Texas A&M University. Accessed April 06, 2020. http://hdl.handle.net/1969.1/ETD-TAMU-2011-05-9130.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yang, Yu. “Clustering-Based Simultaneous Task and Voltage Scheduling for NoC Systems.” 2011. Web. 06 Apr 2020.

Vancouver:

Yang Y. Clustering-Based Simultaneous Task and Voltage Scheduling for NoC Systems. [Internet] [Thesis]. Texas A&M University; 2011. [cited 2020 Apr 06]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2011-05-9130.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yang Y. Clustering-Based Simultaneous Task and Voltage Scheduling for NoC Systems. [Thesis]. Texas A&M University; 2011. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2011-05-9130

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

8. Jain, Tushar Naveen Kumar. Asynchronous Bypass Channels Improving Performance for Multi-synchronous Network-on-chips.

Degree: 2011, Texas A&M University

 Dr. Paul V. Gratz Network-on-Chip (NoC) designs have emerged as a replacement for traditional shared-bus designs for on-chip communications. As with all current VLSI design,… (more)

Subjects/Keywords: NoC; Mesochronous clocking; GALS; asynchronous interconnect; on-chip networks

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APA (6th Edition):

Jain, T. N. K. (2011). Asynchronous Bypass Channels Improving Performance for Multi-synchronous Network-on-chips. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2010-08-8457

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Jain, Tushar Naveen Kumar. “Asynchronous Bypass Channels Improving Performance for Multi-synchronous Network-on-chips.” 2011. Thesis, Texas A&M University. Accessed April 06, 2020. http://hdl.handle.net/1969.1/ETD-TAMU-2010-08-8457.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Jain, Tushar Naveen Kumar. “Asynchronous Bypass Channels Improving Performance for Multi-synchronous Network-on-chips.” 2011. Web. 06 Apr 2020.

Vancouver:

Jain TNK. Asynchronous Bypass Channels Improving Performance for Multi-synchronous Network-on-chips. [Internet] [Thesis]. Texas A&M University; 2011. [cited 2020 Apr 06]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2010-08-8457.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Jain TNK. Asynchronous Bypass Channels Improving Performance for Multi-synchronous Network-on-chips. [Thesis]. Texas A&M University; 2011. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2010-08-8457

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

9. Malave-Bonet, Javier. A Benchmarking Platform For Network-On-Chip (NOC) Multiprocessor System-On- Chips.

Degree: 2012, Texas A&M University

 Network-on-Chip (NOC) based designs have garnered significant attention from both researchers and industry over the past several years. The analysis of these designs has focused… (more)

Subjects/Keywords: Network-on-Chip; Benchmarking; System-on-Chip; Multicore; System C

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APA (6th Edition):

Malave-Bonet, J. (2012). A Benchmarking Platform For Network-On-Chip (NOC) Multiprocessor System-On- Chips. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8662

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Malave-Bonet, Javier. “A Benchmarking Platform For Network-On-Chip (NOC) Multiprocessor System-On- Chips.” 2012. Thesis, Texas A&M University. Accessed April 06, 2020. http://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8662.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Malave-Bonet, Javier. “A Benchmarking Platform For Network-On-Chip (NOC) Multiprocessor System-On- Chips.” 2012. Web. 06 Apr 2020.

Vancouver:

Malave-Bonet J. A Benchmarking Platform For Network-On-Chip (NOC) Multiprocessor System-On- Chips. [Internet] [Thesis]. Texas A&M University; 2012. [cited 2020 Apr 06]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8662.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Malave-Bonet J. A Benchmarking Platform For Network-On-Chip (NOC) Multiprocessor System-On- Chips. [Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8662

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

10. Yuan, Wen. Hybrid Nanophotonic NOC Design for GPGPU.

Degree: 2012, Texas A&M University

 Due to the massive computational power, Graphics Processing Units (GPUs) have become a popular platform for executing general purpose parallel applications. The majority of on-chip… (more)

Subjects/Keywords: NoC; GPGPU; Topology Design; Nanophotonics

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APA (6th Edition):

Yuan, W. (2012). Hybrid Nanophotonic NOC Design for GPGPU. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2012-05-10913

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yuan, Wen. “Hybrid Nanophotonic NOC Design for GPGPU.” 2012. Thesis, Texas A&M University. Accessed April 06, 2020. http://hdl.handle.net/1969.1/ETD-TAMU-2012-05-10913.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yuan, Wen. “Hybrid Nanophotonic NOC Design for GPGPU.” 2012. Web. 06 Apr 2020.

Vancouver:

Yuan W. Hybrid Nanophotonic NOC Design for GPGPU. [Internet] [Thesis]. Texas A&M University; 2012. [cited 2020 Apr 06]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2012-05-10913.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yuan W. Hybrid Nanophotonic NOC Design for GPGPU. [Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2012-05-10913

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

11. Deshpande, Hrishikesh. Multipath Router Architectures to Reduce Latency in Network-on-Chips.

Degree: 2012, Texas A&M University

 The low latency is a prime concern for large Network-on-Chips (NoCs) typically used in chip-multiprocessors (CMPs) and multiprocessor system-on-chips (MPSoCs). A significant component of overall… (more)

Subjects/Keywords: Network-on-chips; Serialization Latency; Multipath Routing

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Deshpande, H. (2012). Multipath Router Architectures to Reduce Latency in Network-on-Chips. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2012-05-11208

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Deshpande, Hrishikesh. “Multipath Router Architectures to Reduce Latency in Network-on-Chips.” 2012. Thesis, Texas A&M University. Accessed April 06, 2020. http://hdl.handle.net/1969.1/ETD-TAMU-2012-05-11208.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Deshpande, Hrishikesh. “Multipath Router Architectures to Reduce Latency in Network-on-Chips.” 2012. Web. 06 Apr 2020.

Vancouver:

Deshpande H. Multipath Router Architectures to Reduce Latency in Network-on-Chips. [Internet] [Thesis]. Texas A&M University; 2012. [cited 2020 Apr 06]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2012-05-11208.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Deshpande H. Multipath Router Architectures to Reduce Latency in Network-on-Chips. [Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2012-05-11208

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

12. Vikram Kulkarni, Nikhil. STT-MRAM Based NoC Buffer Design.

Degree: 2012, Texas A&M University

 As Chip Multiprocessor (CMP) design moves toward many-core architectures, communication delay in Network-on-Chip (NoC) is a major bottleneck in CMP design. An emerging non-volatile memory… (more)

Subjects/Keywords: STT-MRAM; Noc; Buffer

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APA (6th Edition):

Vikram Kulkarni, N. (2012). STT-MRAM Based NoC Buffer Design. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11684

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Vikram Kulkarni, Nikhil. “STT-MRAM Based NoC Buffer Design.” 2012. Thesis, Texas A&M University. Accessed April 06, 2020. http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11684.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Vikram Kulkarni, Nikhil. “STT-MRAM Based NoC Buffer Design.” 2012. Web. 06 Apr 2020.

Vancouver:

Vikram Kulkarni N. STT-MRAM Based NoC Buffer Design. [Internet] [Thesis]. Texas A&M University; 2012. [cited 2020 Apr 06]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11684.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Vikram Kulkarni N. STT-MRAM Based NoC Buffer Design. [Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11684

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

13. Ramakrishna, Mukund. GCA: Global Congestion Awareness for Load Balance in Networks-on-Chip.

Degree: 2012, Texas A&M University

 As modern CMPs scale to ever increasing core counts, Networks-on-Chip (NoCs) are emerging as an interconnection fabric, enabling communication between components. While NoCs are easy… (more)

Subjects/Keywords: computer architecture; on-chip networks; networks-on-chip; multicores; adaptive routing

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APA (6th Edition):

Ramakrishna, M. (2012). GCA: Global Congestion Awareness for Load Balance in Networks-on-Chip. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11712

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ramakrishna, Mukund. “GCA: Global Congestion Awareness for Load Balance in Networks-on-Chip.” 2012. Thesis, Texas A&M University. Accessed April 06, 2020. http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11712.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ramakrishna, Mukund. “GCA: Global Congestion Awareness for Load Balance in Networks-on-Chip.” 2012. Web. 06 Apr 2020.

Vancouver:

Ramakrishna M. GCA: Global Congestion Awareness for Load Balance in Networks-on-Chip. [Internet] [Thesis]. Texas A&M University; 2012. [cited 2020 Apr 06]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11712.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ramakrishna M. GCA: Global Congestion Awareness for Load Balance in Networks-on-Chip. [Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11712

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

14. Shaukat, Noman. B-RPM: An Efficient One-to-Many Communication Framework for On-Chip Networks.

Degree: 2012, Texas A&M University

 The prevalence of multicore architectures has accentuated the need for scalable on-chip communication media. Various parallel applications and programming paradigms use a mix of unicast… (more)

Subjects/Keywords: Multicast; On-Chip Networks; B-RPM; Dynamically Sized Virtual Networks; Virtual Networks; Deadlock

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APA (6th Edition):

Shaukat, N. (2012). B-RPM: An Efficient One-to-Many Communication Framework for On-Chip Networks. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11731

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Shaukat, Noman. “B-RPM: An Efficient One-to-Many Communication Framework for On-Chip Networks.” 2012. Thesis, Texas A&M University. Accessed April 06, 2020. http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11731.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Shaukat, Noman. “B-RPM: An Efficient One-to-Many Communication Framework for On-Chip Networks.” 2012. Web. 06 Apr 2020.

Vancouver:

Shaukat N. B-RPM: An Efficient One-to-Many Communication Framework for On-Chip Networks. [Internet] [Thesis]. Texas A&M University; 2012. [cited 2020 Apr 06]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11731.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Shaukat N. B-RPM: An Efficient One-to-Many Communication Framework for On-Chip Networks. [Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11731

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

15. Jayabalan, Jagadish. Handshake and Circulation Flow Control in Nanaphotonic Interconnects.

Degree: 2012, Texas A&M University

 Nanophotonics has been proposed to design low latency and high bandwidth Network-On-Chip (NOC) for future Chip Multi-Processors (CMPs). Recent nanophotonic NOC designs adopt the token-based… (more)

Subjects/Keywords: Nanophotonics; NOC; Handshake; Circulation

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APA (6th Edition):

Jayabalan, J. (2012). Handshake and Circulation Flow Control in Nanaphotonic Interconnects. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11837

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Jayabalan, Jagadish. “Handshake and Circulation Flow Control in Nanaphotonic Interconnects.” 2012. Thesis, Texas A&M University. Accessed April 06, 2020. http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11837.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Jayabalan, Jagadish. “Handshake and Circulation Flow Control in Nanaphotonic Interconnects.” 2012. Web. 06 Apr 2020.

Vancouver:

Jayabalan J. Handshake and Circulation Flow Control in Nanaphotonic Interconnects. [Internet] [Thesis]. Texas A&M University; 2012. [cited 2020 Apr 06]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11837.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Jayabalan J. Handshake and Circulation Flow Control in Nanaphotonic Interconnects. [Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11837

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

16. Gu, Haiyin. VLPW: The Very Long Packet Window Architecture for High Throughput Network-On-Chip Router Designs.

Degree: 2012, Texas A&M University

 ChipMulti-processor (CMP) architectures have become mainstream for designing processors. With a large number of cores, Network-On-Chip (NOC) provides a scalable communication method for CMPs. NOC… (more)

Subjects/Keywords: NOC; High Throughput

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APA (6th Edition):

Gu, H. (2012). VLPW: The Very Long Packet Window Architecture for High Throughput Network-On-Chip Router Designs. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2011-08-10094

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Gu, Haiyin. “VLPW: The Very Long Packet Window Architecture for High Throughput Network-On-Chip Router Designs.” 2012. Thesis, Texas A&M University. Accessed April 06, 2020. http://hdl.handle.net/1969.1/ETD-TAMU-2011-08-10094.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Gu, Haiyin. “VLPW: The Very Long Packet Window Architecture for High Throughput Network-On-Chip Router Designs.” 2012. Web. 06 Apr 2020.

Vancouver:

Gu H. VLPW: The Very Long Packet Window Architecture for High Throughput Network-On-Chip Router Designs. [Internet] [Thesis]. Texas A&M University; 2012. [cited 2020 Apr 06]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2011-08-10094.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Gu H. VLPW: The Very Long Packet Window Architecture for High Throughput Network-On-Chip Router Designs. [Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2011-08-10094

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

17. Narayana, Sagar 1986-. Throughput-Efficient Network-on-Chip Router Design with STT-MRAM.

Degree: 2012, Texas A&M University

 As the number of processor cores on a chip increases with the advance of CMOS technology, there has been a growing need of more efficient… (more)

Subjects/Keywords: input buffer; router; STT-MRAM; Network-on-Chip

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APA (6th Edition):

Narayana, S. 1. (2012). Throughput-Efficient Network-on-Chip Router Design with STT-MRAM. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/148157

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Narayana, Sagar 1986-. “Throughput-Efficient Network-on-Chip Router Design with STT-MRAM.” 2012. Thesis, Texas A&M University. Accessed April 06, 2020. http://hdl.handle.net/1969.1/148157.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Narayana, Sagar 1986-. “Throughput-Efficient Network-on-Chip Router Design with STT-MRAM.” 2012. Web. 06 Apr 2020.

Vancouver:

Narayana S1. Throughput-Efficient Network-on-Chip Router Design with STT-MRAM. [Internet] [Thesis]. Texas A&M University; 2012. [cited 2020 Apr 06]. Available from: http://hdl.handle.net/1969.1/148157.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Narayana S1. Throughput-Efficient Network-on-Chip Router Design with STT-MRAM. [Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/148157

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

18. Pokharel, Punj. Path Delay Test Through Memory Arrays.

Degree: 2013, Texas A&M University

 Memory arrays cannot be as easily tested as other storage elements in a chip. Most of the flip-flops (FFs) in a chip can be replaced… (more)

Subjects/Keywords: DFT; Test; ATPG; KLPG; Memory arrays

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APA (6th Edition):

Pokharel, P. (2013). Path Delay Test Through Memory Arrays. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/151274

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Pokharel, Punj. “Path Delay Test Through Memory Arrays.” 2013. Thesis, Texas A&M University. Accessed April 06, 2020. http://hdl.handle.net/1969.1/151274.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Pokharel, Punj. “Path Delay Test Through Memory Arrays.” 2013. Web. 06 Apr 2020.

Vancouver:

Pokharel P. Path Delay Test Through Memory Arrays. [Internet] [Thesis]. Texas A&M University; 2013. [cited 2020 Apr 06]. Available from: http://hdl.handle.net/1969.1/151274.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Pokharel P. Path Delay Test Through Memory Arrays. [Thesis]. Texas A&M University; 2013. Available from: http://hdl.handle.net/1969.1/151274

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

19. Bian, Kun. Efficient Path Delay Test Generation with Boolean Satisfiability.

Degree: 2013, Texas A&M University

 This dissertation focuses on improving the accuracy and efficiency of path delay test generation using a Boolean satisfiability (SAT) solver. As part of this research,… (more)

Subjects/Keywords: Delay Test; ATPG; SAT

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APA (6th Edition):

Bian, K. (2013). Efficient Path Delay Test Generation with Boolean Satisfiability. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/151900

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Bian, Kun. “Efficient Path Delay Test Generation with Boolean Satisfiability.” 2013. Thesis, Texas A&M University. Accessed April 06, 2020. http://hdl.handle.net/1969.1/151900.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Bian, Kun. “Efficient Path Delay Test Generation with Boolean Satisfiability.” 2013. Web. 06 Apr 2020.

Vancouver:

Bian K. Efficient Path Delay Test Generation with Boolean Satisfiability. [Internet] [Thesis]. Texas A&M University; 2013. [cited 2020 Apr 06]. Available from: http://hdl.handle.net/1969.1/151900.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Bian K. Efficient Path Delay Test Generation with Boolean Satisfiability. [Thesis]. Texas A&M University; 2013. Available from: http://hdl.handle.net/1969.1/151900

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

20. Zhang, Yong. Simulation and Design of Biological and Biologically-Motivated Computing Systems.

Degree: 2014, Texas A&M University

 In life science, there is a great need in understandings of biological systems for therapeutics, synthetic biology, and biomedical applications. However, complex behaviors and dynamics… (more)

Subjects/Keywords: simulation; biological; computing; brain

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APA (6th Edition):

Zhang, Y. (2014). Simulation and Design of Biological and Biologically-Motivated Computing Systems. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/152573

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Zhang, Yong. “Simulation and Design of Biological and Biologically-Motivated Computing Systems.” 2014. Thesis, Texas A&M University. Accessed April 06, 2020. http://hdl.handle.net/1969.1/152573.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Zhang, Yong. “Simulation and Design of Biological and Biologically-Motivated Computing Systems.” 2014. Web. 06 Apr 2020.

Vancouver:

Zhang Y. Simulation and Design of Biological and Biologically-Motivated Computing Systems. [Internet] [Thesis]. Texas A&M University; 2014. [cited 2020 Apr 06]. Available from: http://hdl.handle.net/1969.1/152573.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zhang Y. Simulation and Design of Biological and Biologically-Motivated Computing Systems. [Thesis]. Texas A&M University; 2014. Available from: http://hdl.handle.net/1969.1/152573

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

21. Rasheed, Shalimar. A Network-on-Chip Router for Low-Latency and High-Throughput Dimension-Order Routing.

Degree: 2014, Texas A&M University

 Networks-on-Chip (NoCs) offer a scalable means of on-chip communication for future many-core chips. As NoC size increases with core count in future many-core chips, NoC… (more)

Subjects/Keywords: Network-on-Chip; Router

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APA (6th Edition):

Rasheed, S. (2014). A Network-on-Chip Router for Low-Latency and High-Throughput Dimension-Order Routing. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/152655

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Rasheed, Shalimar. “A Network-on-Chip Router for Low-Latency and High-Throughput Dimension-Order Routing.” 2014. Thesis, Texas A&M University. Accessed April 06, 2020. http://hdl.handle.net/1969.1/152655.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Rasheed, Shalimar. “A Network-on-Chip Router for Low-Latency and High-Throughput Dimension-Order Routing.” 2014. Web. 06 Apr 2020.

Vancouver:

Rasheed S. A Network-on-Chip Router for Low-Latency and High-Throughput Dimension-Order Routing. [Internet] [Thesis]. Texas A&M University; 2014. [cited 2020 Apr 06]. Available from: http://hdl.handle.net/1969.1/152655.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Rasheed S. A Network-on-Chip Router for Low-Latency and High-Throughput Dimension-Order Routing. [Thesis]. Texas A&M University; 2014. Available from: http://hdl.handle.net/1969.1/152655

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

22. Belsare, Aditya Sanjay. Sparse LU Factorization for Large Circuit Matrices on Heterogenous Parallel Computing Platforms.

Degree: 2014, Texas A&M University

 Direct sparse solvers are traditionally known to be robust, yet difficult to parallelize. In the context of circuit simulators, they present an important bottleneck where… (more)

Subjects/Keywords: Sparse matrix solver; LU Factorization

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APA (6th Edition):

Belsare, A. S. (2014). Sparse LU Factorization for Large Circuit Matrices on Heterogenous Parallel Computing Platforms. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/153210

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Belsare, Aditya Sanjay. “Sparse LU Factorization for Large Circuit Matrices on Heterogenous Parallel Computing Platforms.” 2014. Thesis, Texas A&M University. Accessed April 06, 2020. http://hdl.handle.net/1969.1/153210.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Belsare, Aditya Sanjay. “Sparse LU Factorization for Large Circuit Matrices on Heterogenous Parallel Computing Platforms.” 2014. Web. 06 Apr 2020.

Vancouver:

Belsare AS. Sparse LU Factorization for Large Circuit Matrices on Heterogenous Parallel Computing Platforms. [Internet] [Thesis]. Texas A&M University; 2014. [cited 2020 Apr 06]. Available from: http://hdl.handle.net/1969.1/153210.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Belsare AS. Sparse LU Factorization for Large Circuit Matrices on Heterogenous Parallel Computing Platforms. [Thesis]. Texas A&M University; 2014. Available from: http://hdl.handle.net/1969.1/153210

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

23. Harms, Joel K. Synthetic Aperture Digital Beamsteering Array for Global Positioning System Interference Mitigation: A Study on Array Topology.

Degree: 2014, Texas A&M University

 The Global Positioning System (GPS) satellite navigation system is deeply intertwined with civilian everyday life. Unfortunately for the civilians that use the system, the GPS… (more)

Subjects/Keywords: GPS; synthetic aperture; direction of arrival; beamsteering

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APA (6th Edition):

Harms, J. K. (2014). Synthetic Aperture Digital Beamsteering Array for Global Positioning System Interference Mitigation: A Study on Array Topology. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/153219

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Harms, Joel K. “Synthetic Aperture Digital Beamsteering Array for Global Positioning System Interference Mitigation: A Study on Array Topology.” 2014. Thesis, Texas A&M University. Accessed April 06, 2020. http://hdl.handle.net/1969.1/153219.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Harms, Joel K. “Synthetic Aperture Digital Beamsteering Array for Global Positioning System Interference Mitigation: A Study on Array Topology.” 2014. Web. 06 Apr 2020.

Vancouver:

Harms JK. Synthetic Aperture Digital Beamsteering Array for Global Positioning System Interference Mitigation: A Study on Array Topology. [Internet] [Thesis]. Texas A&M University; 2014. [cited 2020 Apr 06]. Available from: http://hdl.handle.net/1969.1/153219.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Harms JK. Synthetic Aperture Digital Beamsteering Array for Global Positioning System Interference Mitigation: A Study on Array Topology. [Thesis]. Texas A&M University; 2014. Available from: http://hdl.handle.net/1969.1/153219

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

24. Shankar, Anusha. Lock Prediction to Reduce the Overhead of Synchronization Primitives.

Degree: 2014, Texas A&M University

 The advent of chip multi-processors has led to an increase in computational performance in recent years. Employing efficient parallel algorithms has become important to harness… (more)

Subjects/Keywords: locks; synchronization primitives

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APA (6th Edition):

Shankar, A. (2014). Lock Prediction to Reduce the Overhead of Synchronization Primitives. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/154146

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Shankar, Anusha. “Lock Prediction to Reduce the Overhead of Synchronization Primitives.” 2014. Thesis, Texas A&M University. Accessed April 06, 2020. http://hdl.handle.net/1969.1/154146.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Shankar, Anusha. “Lock Prediction to Reduce the Overhead of Synchronization Primitives.” 2014. Web. 06 Apr 2020.

Vancouver:

Shankar A. Lock Prediction to Reduce the Overhead of Synchronization Primitives. [Internet] [Thesis]. Texas A&M University; 2014. [cited 2020 Apr 06]. Available from: http://hdl.handle.net/1969.1/154146.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Shankar A. Lock Prediction to Reduce the Overhead of Synchronization Primitives. [Thesis]. Texas A&M University; 2014. Available from: http://hdl.handle.net/1969.1/154146

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

25. Fatehi, Ehsan. ILP and TLP in Shared Memory Applications: A Limit Study.

Degree: 2015, Texas A&M University

 The work in this dissertation explores the limits of Chip-multiprocessors (CMPs) with respect to shared-memory, multi-threaded benchmarks, which will help aid in identifying microarchitectural bottlenecks.… (more)

Subjects/Keywords: instruction-level parallelism; limits parallelism; concurrency pthreads; thread-level parallelism

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APA (6th Edition):

Fatehi, E. (2015). ILP and TLP in Shared Memory Applications: A Limit Study. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/155119

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Fatehi, Ehsan. “ILP and TLP in Shared Memory Applications: A Limit Study.” 2015. Thesis, Texas A&M University. Accessed April 06, 2020. http://hdl.handle.net/1969.1/155119.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Fatehi, Ehsan. “ILP and TLP in Shared Memory Applications: A Limit Study.” 2015. Web. 06 Apr 2020.

Vancouver:

Fatehi E. ILP and TLP in Shared Memory Applications: A Limit Study. [Internet] [Thesis]. Texas A&M University; 2015. [cited 2020 Apr 06]. Available from: http://hdl.handle.net/1969.1/155119.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Fatehi E. ILP and TLP in Shared Memory Applications: A Limit Study. [Thesis]. Texas A&M University; 2015. Available from: http://hdl.handle.net/1969.1/155119

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

26. Gao, Yukun. Pseudo Functional Path Delay Test through Embedded Memories.

Degree: 2015, Texas A&M University

 On-chip memory arrays are widely used in systems-on-chip. Prior research has shown that timing critical paths often go through these memories. Embedded memories are typically… (more)

Subjects/Keywords: Pseudo Functional Path Delay; KLPG; Memory Testing

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APA (6th Edition):

Gao, Y. (2015). Pseudo Functional Path Delay Test through Embedded Memories. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/155297

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Gao, Yukun. “Pseudo Functional Path Delay Test through Embedded Memories.” 2015. Thesis, Texas A&M University. Accessed April 06, 2020. http://hdl.handle.net/1969.1/155297.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Gao, Yukun. “Pseudo Functional Path Delay Test through Embedded Memories.” 2015. Web. 06 Apr 2020.

Vancouver:

Gao Y. Pseudo Functional Path Delay Test through Embedded Memories. [Internet] [Thesis]. Texas A&M University; 2015. [cited 2020 Apr 06]. Available from: http://hdl.handle.net/1969.1/155297.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Gao Y. Pseudo Functional Path Delay Test through Embedded Memories. [Thesis]. Texas A&M University; 2015. Available from: http://hdl.handle.net/1969.1/155297

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

27. Backes Drault, Luna B. Evaluation of Cache Inclusion Policies in Cache Management.

Degree: MS, Computer Engineering, 2017, Texas A&M University

 Processor speed has been increasing at a higher rate than the speed of memories over the last years. Caches were designed to mitigate this gap… (more)

Subjects/Keywords: cache management; inclusion policy; replacement policy; prefetching; memory hierarchy

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Backes Drault, L. B. (2017). Evaluation of Cache Inclusion Policies in Cache Management. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/166081

Chicago Manual of Style (16th Edition):

Backes Drault, Luna B. “Evaluation of Cache Inclusion Policies in Cache Management.” 2017. Masters Thesis, Texas A&M University. Accessed April 06, 2020. http://hdl.handle.net/1969.1/166081.

MLA Handbook (7th Edition):

Backes Drault, Luna B. “Evaluation of Cache Inclusion Policies in Cache Management.” 2017. Web. 06 Apr 2020.

Vancouver:

Backes Drault LB. Evaluation of Cache Inclusion Policies in Cache Management. [Internet] [Masters thesis]. Texas A&M University; 2017. [cited 2020 Apr 06]. Available from: http://hdl.handle.net/1969.1/166081.

Council of Science Editors:

Backes Drault LB. Evaluation of Cache Inclusion Policies in Cache Management. [Masters Thesis]. Texas A&M University; 2017. Available from: http://hdl.handle.net/1969.1/166081


Texas A&M University

28. Albarakat, Laith Mohammad. Multithreading Aware Hardware Prefetching for Chip Multiprocessors.

Degree: MS, Computer Engineering, 2017, Texas A&M University

 To take advantage of the processing power in the Chip Multiprocessors design, applications must be divided into semi-independent processes that can run concur- rently on… (more)

Subjects/Keywords: prefetcher

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Albarakat, L. M. (2017). Multithreading Aware Hardware Prefetching for Chip Multiprocessors. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/165781

Chicago Manual of Style (16th Edition):

Albarakat, Laith Mohammad. “Multithreading Aware Hardware Prefetching for Chip Multiprocessors.” 2017. Masters Thesis, Texas A&M University. Accessed April 06, 2020. http://hdl.handle.net/1969.1/165781.

MLA Handbook (7th Edition):

Albarakat, Laith Mohammad. “Multithreading Aware Hardware Prefetching for Chip Multiprocessors.” 2017. Web. 06 Apr 2020.

Vancouver:

Albarakat LM. Multithreading Aware Hardware Prefetching for Chip Multiprocessors. [Internet] [Masters thesis]. Texas A&M University; 2017. [cited 2020 Apr 06]. Available from: http://hdl.handle.net/1969.1/165781.

Council of Science Editors:

Albarakat LM. Multithreading Aware Hardware Prefetching for Chip Multiprocessors. [Masters Thesis]. Texas A&M University; 2017. Available from: http://hdl.handle.net/1969.1/165781


Texas A&M University

29. Kodati, Vamsi Krishna. Probability-Based Memory Access Controller (PMAC) for Energy Reduction in High Performance Processors.

Degree: 2015, Texas A&M University

 The increasing transistor density due to Moore's law scaling continues to drive the improvement in processor core performance with each process generation. The additional transistors… (more)

Subjects/Keywords: Wrong Path Execution; Energy Reduction

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kodati, V. K. (2015). Probability-Based Memory Access Controller (PMAC) for Energy Reduction in High Performance Processors. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/156215

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kodati, Vamsi Krishna. “Probability-Based Memory Access Controller (PMAC) for Energy Reduction in High Performance Processors.” 2015. Thesis, Texas A&M University. Accessed April 06, 2020. http://hdl.handle.net/1969.1/156215.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kodati, Vamsi Krishna. “Probability-Based Memory Access Controller (PMAC) for Energy Reduction in High Performance Processors.” 2015. Web. 06 Apr 2020.

Vancouver:

Kodati VK. Probability-Based Memory Access Controller (PMAC) for Energy Reduction in High Performance Processors. [Internet] [Thesis]. Texas A&M University; 2015. [cited 2020 Apr 06]. Available from: http://hdl.handle.net/1969.1/156215.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kodati VK. Probability-Based Memory Access Controller (PMAC) for Energy Reduction in High Performance Processors. [Thesis]. Texas A&M University; 2015. Available from: http://hdl.handle.net/1969.1/156215

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

30. He, Hao. Resource Management Algorithms for Computing Hardware Design and Operations: From Circuits to Systems.

Degree: PhD, Computer Engineering, 2016, Texas A&M University

 The complexity of computation hardware has increased at an unprecedented rate for the last few decades. On the computer chip level, we have entered the… (more)

Subjects/Keywords: Resource Management; Data Center

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

He, H. (2016). Resource Management Algorithms for Computing Hardware Design and Operations: From Circuits to Systems. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/174272

Chicago Manual of Style (16th Edition):

He, Hao. “Resource Management Algorithms for Computing Hardware Design and Operations: From Circuits to Systems.” 2016. Doctoral Dissertation, Texas A&M University. Accessed April 06, 2020. http://hdl.handle.net/1969.1/174272.

MLA Handbook (7th Edition):

He, Hao. “Resource Management Algorithms for Computing Hardware Design and Operations: From Circuits to Systems.” 2016. Web. 06 Apr 2020.

Vancouver:

He H. Resource Management Algorithms for Computing Hardware Design and Operations: From Circuits to Systems. [Internet] [Doctoral dissertation]. Texas A&M University; 2016. [cited 2020 Apr 06]. Available from: http://hdl.handle.net/1969.1/174272.

Council of Science Editors:

He H. Resource Management Algorithms for Computing Hardware Design and Operations: From Circuits to Systems. [Doctoral Dissertation]. Texas A&M University; 2016. Available from: http://hdl.handle.net/1969.1/174272

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