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You searched for +publisher:"Syracuse University" +contributor:("C. Y. Roger Chen"). Showing records 1 – 2 of 2 total matches.

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Syracuse University

1. Alqudah, Rajaa Khaled. State-Based Techniques For Designing, Verifying And Debugging Message Passing Systems.

Degree: PhD, Electrical Engineering and Computer Science, 2011, Syracuse University

Message passing systems support the applications of concurrent events, where independent or semi-independent events occur simultaneously in a nondeterministic fashion. The nature of independence, random interactions and concurrency made the code development of such applications complicated and error-prone. Conventional code development environments or IDEs, such as Microsoft Visual Studio, provide little programming support in this regard. Furthermore, ensuring the correctness of a message passing system is a challenge. Typically, it is important to guarantee that a system meets its desired specifications along its construction process. Model checking is one of the techniques used in software verification which has proven to be effective in discovering hidden design and implementation errors. The required advanced knowledge of formal methods and temporal languages is one of the impediments in adopting model checking by software developers. To integrate model checking environments and conventional IDEs, this dissertation proposes a multi-phase development framework that facilitates designing, verifying, implementing and debugging state-based message passing systems. The techniques and design principles of the proposed framework focus on improving and easing the software development experience. In the first phase, a two-level design methodology is proposed through using abstract high-level communication blocks and hierarchical state-behavioral descriptions that were developed in this research. In the second phase, a new method based on choosing from a pre-determined set of patterns in concurrent communication properties is proposed to facilitate collecting the essential specifications of the system where the atomic propositions are linked with the system design. A complex property can be attained by hierarchically nesting some of these patterns. A procedure to automatically generate formal models in a model checker (MC) language is proposed. Once the model that contains both the design and the properties of the system are generated, a model checker is used to verify the correctness of the proposed system and ensure its compliance with specifications. To help in locating the source of an undesired specification, if any, a procedure to map a counter example generated by the MC to the original design is presented. In the third phase, a skeleton code of the design specification is generated in a general programming language such as Microsoft C\#, Java, etc. moreover, the ability to debug the generated code using a conventional IDE while tracing the debugging process back to the original design was established. Finally, a graphical software tool that supports the proposed framework is developed where SPIN MC is used as a verifier. The tool was used to develop and verify several case studies. The proposed framework and the developed software tool can be considered a key solution for message passing systems design and verification. Advisors/Committee Members: C. Y. Roger Chen.

Subjects/Keywords: Message passing systems; IDEs; Code development; Computer Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Alqudah, R. K. (2011). State-Based Techniques For Designing, Verifying And Debugging Message Passing Systems. (Doctoral Dissertation). Syracuse University. Retrieved from https://surface.syr.edu/eecs_etd/313

Chicago Manual of Style (16th Edition):

Alqudah, Rajaa Khaled. “State-Based Techniques For Designing, Verifying And Debugging Message Passing Systems.” 2011. Doctoral Dissertation, Syracuse University. Accessed October 16, 2019. https://surface.syr.edu/eecs_etd/313.

MLA Handbook (7th Edition):

Alqudah, Rajaa Khaled. “State-Based Techniques For Designing, Verifying And Debugging Message Passing Systems.” 2011. Web. 16 Oct 2019.

Vancouver:

Alqudah RK. State-Based Techniques For Designing, Verifying And Debugging Message Passing Systems. [Internet] [Doctoral dissertation]. Syracuse University; 2011. [cited 2019 Oct 16]. Available from: https://surface.syr.edu/eecs_etd/313.

Council of Science Editors:

Alqudah RK. State-Based Techniques For Designing, Verifying And Debugging Message Passing Systems. [Doctoral Dissertation]. Syracuse University; 2011. Available from: https://surface.syr.edu/eecs_etd/313


Syracuse University

2. Chun, Jae Woong. Methodology for Standby Leakage Power Reduction in Nanometer-Scale CMOS Circuits.

Degree: PhD, Electrical Engineering and Computer Science, 2012, Syracuse University

In nanometer-scale CMOS technology, leakage power has become a major component of the total power dissipation due to the downscaling of threshold voltage and gate oxide thickness. The leakage power consumption has received even more attention by increasing demand for mobile devices. Since mobile devices spend a majority of their time in a standby mode, the leakage power savings in standby state is critical to extend battery lifetime. For this reason, low power has become a major factor in designing CMOS circuits. In this dissertation, we propose a novel transistor reordering methodology for leakage reduction. Unlike previous technique, the proposed method provides exact reordering rules for minimum leakage formation by considering all leakage components. Thus, this method formulates an optimized structure for leakage reduction even in complex CMOS logic gate, and can be used in combination with other leakage reduction techniques to achieve further improvement. We also propose a new standby leakage reduction methodology, leakage-aware body biasing, to overcome the shortcomings of a conventional Reverse Body Biasing (RBB) technique. The RBB technique has been used to reduce subthreshold leakage current. Therefore, this technique works well under subthreshold dominant region even though it has intrinsic structural drawbacks. However, such drawbacks cannot be overlooked anymore since gate leakage has become comparable to subthreshold leakage in nanometer-scale region. In addition, BTBT leakage also increases with technology scaling due to the higher doping concentration applied in each process technology. In these circumstances, the objective of leakage minimization is not a single leakage source but the overall leakage sources. The proposed leakage-aware body biasing technique, unlike conventional RBB technique, considers all major leakage sources to minimize the negative effects of existing body biasing approach. This can be achieved by intelligently applying body bias to appropriate CMOS network based on its status (on-/off-state) with the aid of a pin/transistor reordering technique. Advisors/Committee Members: C. Y. Roger Chen.

Subjects/Keywords: Leakage currents; Low power design; Minimum leakage vector; Stacking effect; Substrate bias; Technology scaling; Electrical and Computer Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chun, J. W. (2012). Methodology for Standby Leakage Power Reduction in Nanometer-Scale CMOS Circuits. (Doctoral Dissertation). Syracuse University. Retrieved from https://surface.syr.edu/eecs_etd/328

Chicago Manual of Style (16th Edition):

Chun, Jae Woong. “Methodology for Standby Leakage Power Reduction in Nanometer-Scale CMOS Circuits.” 2012. Doctoral Dissertation, Syracuse University. Accessed October 16, 2019. https://surface.syr.edu/eecs_etd/328.

MLA Handbook (7th Edition):

Chun, Jae Woong. “Methodology for Standby Leakage Power Reduction in Nanometer-Scale CMOS Circuits.” 2012. Web. 16 Oct 2019.

Vancouver:

Chun JW. Methodology for Standby Leakage Power Reduction in Nanometer-Scale CMOS Circuits. [Internet] [Doctoral dissertation]. Syracuse University; 2012. [cited 2019 Oct 16]. Available from: https://surface.syr.edu/eecs_etd/328.

Council of Science Editors:

Chun JW. Methodology for Standby Leakage Power Reduction in Nanometer-Scale CMOS Circuits. [Doctoral Dissertation]. Syracuse University; 2012. Available from: https://surface.syr.edu/eecs_etd/328

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