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You searched for +publisher:"Rochester Institute of Technology" +contributor:("Sohail A. Dianat"). Showing records 1 – 30 of 46 total matches.

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1. Goldberg, Connor Jan. The Design of a Custom 32-bit RISC CPU and LLVM Compiler Backend.

Degree: MS, Electrical Engineering, 2017, Rochester Institute of Technology

  Compiler infrastructures are often an area of high interest for research. As the necessity for digital information and technology increases, so does the need… (more)

Subjects/Keywords: None provided

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APA (6th Edition):

Goldberg, C. J. (2017). The Design of a Custom 32-bit RISC CPU and LLVM Compiler Backend. (Masters Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/9550

Chicago Manual of Style (16th Edition):

Goldberg, Connor Jan. “The Design of a Custom 32-bit RISC CPU and LLVM Compiler Backend.” 2017. Masters Thesis, Rochester Institute of Technology. Accessed February 28, 2020. https://scholarworks.rit.edu/theses/9550.

MLA Handbook (7th Edition):

Goldberg, Connor Jan. “The Design of a Custom 32-bit RISC CPU and LLVM Compiler Backend.” 2017. Web. 28 Feb 2020.

Vancouver:

Goldberg CJ. The Design of a Custom 32-bit RISC CPU and LLVM Compiler Backend. [Internet] [Masters thesis]. Rochester Institute of Technology; 2017. [cited 2020 Feb 28]. Available from: https://scholarworks.rit.edu/theses/9550.

Council of Science Editors:

Goldberg CJ. The Design of a Custom 32-bit RISC CPU and LLVM Compiler Backend. [Masters Thesis]. Rochester Institute of Technology; 2017. Available from: https://scholarworks.rit.edu/theses/9550


Rochester Institute of Technology

2. Glauser, Lincoln. The Design of a 24-bit Hardware Gaussian Noise Generator via the Box-Muller Method and its Error Analysis.

Degree: MS, Electrical Engineering, 2017, Rochester Institute of Technology

  In regards to data transmission in communication systems, there is need for robust emulation of communication channels via Gaussian noise generation. Over time, larger… (more)

Subjects/Keywords: Noise generators; Random number generation; Approximation methods; Error analysis; Optimization methods; Gaussian processes; Parity check codes

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APA (6th Edition):

Glauser, L. (2017). The Design of a 24-bit Hardware Gaussian Noise Generator via the Box-Muller Method and its Error Analysis. (Masters Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/9572

Chicago Manual of Style (16th Edition):

Glauser, Lincoln. “The Design of a 24-bit Hardware Gaussian Noise Generator via the Box-Muller Method and its Error Analysis.” 2017. Masters Thesis, Rochester Institute of Technology. Accessed February 28, 2020. https://scholarworks.rit.edu/theses/9572.

MLA Handbook (7th Edition):

Glauser, Lincoln. “The Design of a 24-bit Hardware Gaussian Noise Generator via the Box-Muller Method and its Error Analysis.” 2017. Web. 28 Feb 2020.

Vancouver:

Glauser L. The Design of a 24-bit Hardware Gaussian Noise Generator via the Box-Muller Method and its Error Analysis. [Internet] [Masters thesis]. Rochester Institute of Technology; 2017. [cited 2020 Feb 28]. Available from: https://scholarworks.rit.edu/theses/9572.

Council of Science Editors:

Glauser L. The Design of a 24-bit Hardware Gaussian Noise Generator via the Box-Muller Method and its Error Analysis. [Masters Thesis]. Rochester Institute of Technology; 2017. Available from: https://scholarworks.rit.edu/theses/9572


Rochester Institute of Technology

3. Wilbee, Aaron J. A Framework For Learning Scene Independent Edge Detection.

Degree: MS, Electrical Engineering, 2014, Rochester Institute of Technology

  In this work, a framework for a system which will intelligently assign an edge detection filter to an image based on features taken from… (more)

Subjects/Keywords: Cellular automata; Edge detection; Learning algorithms; Scene recognition

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APA (6th Edition):

Wilbee, A. J. (2014). A Framework For Learning Scene Independent Edge Detection. (Masters Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/8642

Chicago Manual of Style (16th Edition):

Wilbee, Aaron J. “A Framework For Learning Scene Independent Edge Detection.” 2014. Masters Thesis, Rochester Institute of Technology. Accessed February 28, 2020. https://scholarworks.rit.edu/theses/8642.

MLA Handbook (7th Edition):

Wilbee, Aaron J. “A Framework For Learning Scene Independent Edge Detection.” 2014. Web. 28 Feb 2020.

Vancouver:

Wilbee AJ. A Framework For Learning Scene Independent Edge Detection. [Internet] [Masters thesis]. Rochester Institute of Technology; 2014. [cited 2020 Feb 28]. Available from: https://scholarworks.rit.edu/theses/8642.

Council of Science Editors:

Wilbee AJ. A Framework For Learning Scene Independent Edge Detection. [Masters Thesis]. Rochester Institute of Technology; 2014. Available from: https://scholarworks.rit.edu/theses/8642


Rochester Institute of Technology

4. Argade, Nikhil. Global Routing Protocols for Wireless Body Area Networks.

Degree: MS, Electrical Engineering, 2013, Rochester Institute of Technology

  This work primarily consists of two parts. The first part deals with a wireless body area network with battery operated nodes. Global routing protocols… (more)

Subjects/Keywords: Body sensor networks; Global routing protocols; Network lifetime; Wireless body area networks; Wireless networks

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APA (6th Edition):

Argade, N. (2013). Global Routing Protocols for Wireless Body Area Networks. (Masters Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/8593

Chicago Manual of Style (16th Edition):

Argade, Nikhil. “Global Routing Protocols for Wireless Body Area Networks.” 2013. Masters Thesis, Rochester Institute of Technology. Accessed February 28, 2020. https://scholarworks.rit.edu/theses/8593.

MLA Handbook (7th Edition):

Argade, Nikhil. “Global Routing Protocols for Wireless Body Area Networks.” 2013. Web. 28 Feb 2020.

Vancouver:

Argade N. Global Routing Protocols for Wireless Body Area Networks. [Internet] [Masters thesis]. Rochester Institute of Technology; 2013. [cited 2020 Feb 28]. Available from: https://scholarworks.rit.edu/theses/8593.

Council of Science Editors:

Argade N. Global Routing Protocols for Wireless Body Area Networks. [Masters Thesis]. Rochester Institute of Technology; 2013. Available from: https://scholarworks.rit.edu/theses/8593


Rochester Institute of Technology

5. Ahir, Prashant. Lightweight Architectures for Reliable and Fault Detection Simon and Speck Cryptographic Algorithms on FPGA.

Degree: MS, Electrical Engineering, 2016, Rochester Institute of Technology

  The widespread use of sensitive and constrained applications necessitates lightweight (lowpower and low-area) algorithms developed for constrained nano-devices. However, nearly all of such algorithms… (more)

Subjects/Keywords: None provided

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APA (6th Edition):

Ahir, P. (2016). Lightweight Architectures for Reliable and Fault Detection Simon and Speck Cryptographic Algorithms on FPGA. (Masters Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/9251

Chicago Manual of Style (16th Edition):

Ahir, Prashant. “Lightweight Architectures for Reliable and Fault Detection Simon and Speck Cryptographic Algorithms on FPGA.” 2016. Masters Thesis, Rochester Institute of Technology. Accessed February 28, 2020. https://scholarworks.rit.edu/theses/9251.

MLA Handbook (7th Edition):

Ahir, Prashant. “Lightweight Architectures for Reliable and Fault Detection Simon and Speck Cryptographic Algorithms on FPGA.” 2016. Web. 28 Feb 2020.

Vancouver:

Ahir P. Lightweight Architectures for Reliable and Fault Detection Simon and Speck Cryptographic Algorithms on FPGA. [Internet] [Masters thesis]. Rochester Institute of Technology; 2016. [cited 2020 Feb 28]. Available from: https://scholarworks.rit.edu/theses/9251.

Council of Science Editors:

Ahir P. Lightweight Architectures for Reliable and Fault Detection Simon and Speck Cryptographic Algorithms on FPGA. [Masters Thesis]. Rochester Institute of Technology; 2016. Available from: https://scholarworks.rit.edu/theses/9251


Rochester Institute of Technology

6. Lima, Thiago Pinheiro Felix da Silva e. Reconfigurable Model for RISC Processors.

Degree: MS, Electrical Engineering, 2016, Rochester Institute of Technology

  The instruction set of a processor is embodied in the particular micro-architecture representing the processor hardware. Verifying proper operation of the instruction set for… (more)

Subjects/Keywords: RISC; Processor; SystemC; SystemVerilog; Micro-architecture; Instruction Set Architecture​

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APA (6th Edition):

Lima, T. P. F. d. S. e. (2016). Reconfigurable Model for RISC Processors. (Masters Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/9326

Chicago Manual of Style (16th Edition):

Lima, Thiago Pinheiro Felix da Silva e. “Reconfigurable Model for RISC Processors.” 2016. Masters Thesis, Rochester Institute of Technology. Accessed February 28, 2020. https://scholarworks.rit.edu/theses/9326.

MLA Handbook (7th Edition):

Lima, Thiago Pinheiro Felix da Silva e. “Reconfigurable Model for RISC Processors.” 2016. Web. 28 Feb 2020.

Vancouver:

Lima TPFdSe. Reconfigurable Model for RISC Processors. [Internet] [Masters thesis]. Rochester Institute of Technology; 2016. [cited 2020 Feb 28]. Available from: https://scholarworks.rit.edu/theses/9326.

Council of Science Editors:

Lima TPFdSe. Reconfigurable Model for RISC Processors. [Masters Thesis]. Rochester Institute of Technology; 2016. Available from: https://scholarworks.rit.edu/theses/9326


Rochester Institute of Technology

7. Simha, Shashank. The Design of a Custom 32-Bit SIMD Enhanced Digital Signal Processor.

Degree: MS, Electrical Engineering, 2017, Rochester Institute of Technology

  For a number of years, the hardware industry has seen a drastic rise in embedded applications. Thanks to the Internet of Things (IoT) revolution,… (more)

Subjects/Keywords: Logic design; Circuits; Design methodology; Hardware description languages; Digital signal processing; Digital signal processing

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APA (6th Edition):

Simha, S. (2017). The Design of a Custom 32-Bit SIMD Enhanced Digital Signal Processor. (Masters Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/9705

Chicago Manual of Style (16th Edition):

Simha, Shashank. “The Design of a Custom 32-Bit SIMD Enhanced Digital Signal Processor.” 2017. Masters Thesis, Rochester Institute of Technology. Accessed February 28, 2020. https://scholarworks.rit.edu/theses/9705.

MLA Handbook (7th Edition):

Simha, Shashank. “The Design of a Custom 32-Bit SIMD Enhanced Digital Signal Processor.” 2017. Web. 28 Feb 2020.

Vancouver:

Simha S. The Design of a Custom 32-Bit SIMD Enhanced Digital Signal Processor. [Internet] [Masters thesis]. Rochester Institute of Technology; 2017. [cited 2020 Feb 28]. Available from: https://scholarworks.rit.edu/theses/9705.

Council of Science Editors:

Simha S. The Design of a Custom 32-Bit SIMD Enhanced Digital Signal Processor. [Masters Thesis]. Rochester Institute of Technology; 2017. Available from: https://scholarworks.rit.edu/theses/9705

8. Keni, Mayuresh Vijay. Design of a Single Precision Floating Point Divider and Multiplier with Pipelined Architecture.

Degree: MS, Electrical Engineering, 2017, Rochester Institute of Technology

  High speed computation is the need of today’s generation of Processors. To accomplish this major task, many functions are implemented inside the hardware of… (more)

Subjects/Keywords: Logic design; Circuits; Design methodology; Hardware description languages; Floating point arithmetic; Equations

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APA (6th Edition):

Keni, M. V. (2017). Design of a Single Precision Floating Point Divider and Multiplier with Pipelined Architecture. (Masters Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/9706

Chicago Manual of Style (16th Edition):

Keni, Mayuresh Vijay. “Design of a Single Precision Floating Point Divider and Multiplier with Pipelined Architecture.” 2017. Masters Thesis, Rochester Institute of Technology. Accessed February 28, 2020. https://scholarworks.rit.edu/theses/9706.

MLA Handbook (7th Edition):

Keni, Mayuresh Vijay. “Design of a Single Precision Floating Point Divider and Multiplier with Pipelined Architecture.” 2017. Web. 28 Feb 2020.

Vancouver:

Keni MV. Design of a Single Precision Floating Point Divider and Multiplier with Pipelined Architecture. [Internet] [Masters thesis]. Rochester Institute of Technology; 2017. [cited 2020 Feb 28]. Available from: https://scholarworks.rit.edu/theses/9706.

Council of Science Editors:

Keni MV. Design of a Single Precision Floating Point Divider and Multiplier with Pipelined Architecture. [Masters Thesis]. Rochester Institute of Technology; 2017. Available from: https://scholarworks.rit.edu/theses/9706

9. Mange, Krunal. Configurable Random Instruction Generator for RISC Processors.

Degree: MS, Electrical Engineering, 2017, Rochester Institute of Technology

  Processors have evolved and grown more complex to serve enormous computational needs. Even though modern-day processors share same dna with processors half century ago,… (more)

Subjects/Keywords: RISC; Processor; RISC processor verification; Harvard architecture; von Neumann architecture; System verilog

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APA (6th Edition):

Mange, K. (2017). Configurable Random Instruction Generator for RISC Processors. (Masters Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/9707

Chicago Manual of Style (16th Edition):

Mange, Krunal. “Configurable Random Instruction Generator for RISC Processors.” 2017. Masters Thesis, Rochester Institute of Technology. Accessed February 28, 2020. https://scholarworks.rit.edu/theses/9707.

MLA Handbook (7th Edition):

Mange, Krunal. “Configurable Random Instruction Generator for RISC Processors.” 2017. Web. 28 Feb 2020.

Vancouver:

Mange K. Configurable Random Instruction Generator for RISC Processors. [Internet] [Masters thesis]. Rochester Institute of Technology; 2017. [cited 2020 Feb 28]. Available from: https://scholarworks.rit.edu/theses/9707.

Council of Science Editors:

Mange K. Configurable Random Instruction Generator for RISC Processors. [Masters Thesis]. Rochester Institute of Technology; 2017. Available from: https://scholarworks.rit.edu/theses/9707


Rochester Institute of Technology

10. Salunkhe, Balaji. Automatic Protein Shake Freestyle Vending Machine.

Degree: MS, Electrical Engineering, 2017, Rochester Institute of Technology

  This paper discusses the design and implementation of an automatic protein shake freestyle vending machine. This machine is capable of providing protein shakes as… (more)

Subjects/Keywords: Logic design; Circuits; Design methodology; Hardware description languages; Liquids; Containers

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APA (6th Edition):

Salunkhe, B. (2017). Automatic Protein Shake Freestyle Vending Machine. (Masters Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/9708

Chicago Manual of Style (16th Edition):

Salunkhe, Balaji. “Automatic Protein Shake Freestyle Vending Machine.” 2017. Masters Thesis, Rochester Institute of Technology. Accessed February 28, 2020. https://scholarworks.rit.edu/theses/9708.

MLA Handbook (7th Edition):

Salunkhe, Balaji. “Automatic Protein Shake Freestyle Vending Machine.” 2017. Web. 28 Feb 2020.

Vancouver:

Salunkhe B. Automatic Protein Shake Freestyle Vending Machine. [Internet] [Masters thesis]. Rochester Institute of Technology; 2017. [cited 2020 Feb 28]. Available from: https://scholarworks.rit.edu/theses/9708.

Council of Science Editors:

Salunkhe B. Automatic Protein Shake Freestyle Vending Machine. [Masters Thesis]. Rochester Institute of Technology; 2017. Available from: https://scholarworks.rit.edu/theses/9708


Rochester Institute of Technology

11. Srinivasan, Avinash. SystemVerilog Verification of Wishbone-Compliant Serial Peripheral Interface.

Degree: MS, Electrical Engineering, 2017, Rochester Institute of Technology

  Synchronous serial interfaces provide economical on-board communication between the processor, digital to analog and analog to digital converters, memory, and other building blocks on… (more)

Subjects/Keywords: SystemVerilog; Protocols; Master-slave; Logic design; Circuits; Data communication

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APA (6th Edition):

Srinivasan, A. (2017). SystemVerilog Verification of Wishbone-Compliant Serial Peripheral Interface. (Masters Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/9709

Chicago Manual of Style (16th Edition):

Srinivasan, Avinash. “SystemVerilog Verification of Wishbone-Compliant Serial Peripheral Interface.” 2017. Masters Thesis, Rochester Institute of Technology. Accessed February 28, 2020. https://scholarworks.rit.edu/theses/9709.

MLA Handbook (7th Edition):

Srinivasan, Avinash. “SystemVerilog Verification of Wishbone-Compliant Serial Peripheral Interface.” 2017. Web. 28 Feb 2020.

Vancouver:

Srinivasan A. SystemVerilog Verification of Wishbone-Compliant Serial Peripheral Interface. [Internet] [Masters thesis]. Rochester Institute of Technology; 2017. [cited 2020 Feb 28]. Available from: https://scholarworks.rit.edu/theses/9709.

Council of Science Editors:

Srinivasan A. SystemVerilog Verification of Wishbone-Compliant Serial Peripheral Interface. [Masters Thesis]. Rochester Institute of Technology; 2017. Available from: https://scholarworks.rit.edu/theses/9709


Rochester Institute of Technology

12. Mohan Dass, Manikandan Sriram. Design and Verification of a Dual Port RAM Using UVM Methodology.

Degree: MS, Electrical Engineering, 2018, Rochester Institute of Technology

  Data-intensive applications such as Deep Learning, Big Data, and Computer Vision have resulted in more demand for on-chip memory storage. Hence, state of the… (more)

Subjects/Keywords: UVM; SystemVerilog; Reusability; Memory architecture; Circuit faults; Built-in self-test

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APA (6th Edition):

Mohan Dass, M. S. (2018). Design and Verification of a Dual Port RAM Using UVM Methodology. (Masters Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/9792

Chicago Manual of Style (16th Edition):

Mohan Dass, Manikandan Sriram. “Design and Verification of a Dual Port RAM Using UVM Methodology.” 2018. Masters Thesis, Rochester Institute of Technology. Accessed February 28, 2020. https://scholarworks.rit.edu/theses/9792.

MLA Handbook (7th Edition):

Mohan Dass, Manikandan Sriram. “Design and Verification of a Dual Port RAM Using UVM Methodology.” 2018. Web. 28 Feb 2020.

Vancouver:

Mohan Dass MS. Design and Verification of a Dual Port RAM Using UVM Methodology. [Internet] [Masters thesis]. Rochester Institute of Technology; 2018. [cited 2020 Feb 28]. Available from: https://scholarworks.rit.edu/theses/9792.

Council of Science Editors:

Mohan Dass MS. Design and Verification of a Dual Port RAM Using UVM Methodology. [Masters Thesis]. Rochester Institute of Technology; 2018. Available from: https://scholarworks.rit.edu/theses/9792


Rochester Institute of Technology

13. Parthipan, Deepak Siddharth. UVM Verification of an SPI Master Core.

Degree: MS, Electrical Engineering, 2018, Rochester Institute of Technology

  In today’s world, more and more functionalities in the form of IP cores are integrated into a single chip or SOC. System-level verification of… (more)

Subjects/Keywords: UVM; SystemVerilog; Reusability; Protocols; Peripheral interfaces; Serial peripheral interface

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APA (6th Edition):

Parthipan, D. S. (2018). UVM Verification of an SPI Master Core. (Masters Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/9793

Chicago Manual of Style (16th Edition):

Parthipan, Deepak Siddharth. “UVM Verification of an SPI Master Core.” 2018. Masters Thesis, Rochester Institute of Technology. Accessed February 28, 2020. https://scholarworks.rit.edu/theses/9793.

MLA Handbook (7th Edition):

Parthipan, Deepak Siddharth. “UVM Verification of an SPI Master Core.” 2018. Web. 28 Feb 2020.

Vancouver:

Parthipan DS. UVM Verification of an SPI Master Core. [Internet] [Masters thesis]. Rochester Institute of Technology; 2018. [cited 2020 Feb 28]. Available from: https://scholarworks.rit.edu/theses/9793.

Council of Science Editors:

Parthipan DS. UVM Verification of an SPI Master Core. [Masters Thesis]. Rochester Institute of Technology; 2018. Available from: https://scholarworks.rit.edu/theses/9793

14. Pashupathy Manjula Devi, Namratha. Configurable Verification of RISC Processors.

Degree: MS, Electrical Engineering, 2017, Rochester Institute of Technology

  The Verification methodology of modern processor designs is an enormous challenge. As processor design complexity increases, an elaborate and sophisticated verification environment has to… (more)

Subjects/Keywords: RISC; Processor; RISC processor verification; Harvard architecture; von Neumann architecture; SystemVerilog; Micro-architecture; Instruction Set Architecture

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APA (6th Edition):

Pashupathy Manjula Devi, N. (2017). Configurable Verification of RISC Processors. (Masters Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/9420

Chicago Manual of Style (16th Edition):

Pashupathy Manjula Devi, Namratha. “Configurable Verification of RISC Processors.” 2017. Masters Thesis, Rochester Institute of Technology. Accessed February 28, 2020. https://scholarworks.rit.edu/theses/9420.

MLA Handbook (7th Edition):

Pashupathy Manjula Devi, Namratha. “Configurable Verification of RISC Processors.” 2017. Web. 28 Feb 2020.

Vancouver:

Pashupathy Manjula Devi N. Configurable Verification of RISC Processors. [Internet] [Masters thesis]. Rochester Institute of Technology; 2017. [cited 2020 Feb 28]. Available from: https://scholarworks.rit.edu/theses/9420.

Council of Science Editors:

Pashupathy Manjula Devi N. Configurable Verification of RISC Processors. [Masters Thesis]. Rochester Institute of Technology; 2017. Available from: https://scholarworks.rit.edu/theses/9420


Rochester Institute of Technology

15. Manoharan, Niranjan. Reliable and Fault-Resilient Schemes for Efficient Radix-4 Complex Division.

Degree: MS, Electrical Engineering, 2014, Rochester Institute of Technology

  Complex division is commonly used in various applications in signal processing and control theory including astronomy and nonlinear RF measurements. Nevertheless, unless reliability and… (more)

Subjects/Keywords: None provided

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APA (6th Edition):

Manoharan, N. (2014). Reliable and Fault-Resilient Schemes for Efficient Radix-4 Complex Division. (Masters Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/8780

Chicago Manual of Style (16th Edition):

Manoharan, Niranjan. “Reliable and Fault-Resilient Schemes for Efficient Radix-4 Complex Division.” 2014. Masters Thesis, Rochester Institute of Technology. Accessed February 28, 2020. https://scholarworks.rit.edu/theses/8780.

MLA Handbook (7th Edition):

Manoharan, Niranjan. “Reliable and Fault-Resilient Schemes for Efficient Radix-4 Complex Division.” 2014. Web. 28 Feb 2020.

Vancouver:

Manoharan N. Reliable and Fault-Resilient Schemes for Efficient Radix-4 Complex Division. [Internet] [Masters thesis]. Rochester Institute of Technology; 2014. [cited 2020 Feb 28]. Available from: https://scholarworks.rit.edu/theses/8780.

Council of Science Editors:

Manoharan N. Reliable and Fault-Resilient Schemes for Efficient Radix-4 Complex Division. [Masters Thesis]. Rochester Institute of Technology; 2014. Available from: https://scholarworks.rit.edu/theses/8780


Rochester Institute of Technology

16. Ramadoss, Rajkumar. Reliable Hardware Architectures of CORDIC Algorithm with Fixed Angle of Rotations.

Degree: MS, Electrical Engineering, 2015, Rochester Institute of Technology

  Fixed-angle rotation operation of vectors is widely used in signal processing, graphics, and robotics. Various optimized coordinate rotation digital computer (CORDIC) designs have been… (more)

Subjects/Keywords: None provided

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APA (6th Edition):

Ramadoss, R. (2015). Reliable Hardware Architectures of CORDIC Algorithm with Fixed Angle of Rotations. (Masters Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/8782

Chicago Manual of Style (16th Edition):

Ramadoss, Rajkumar. “Reliable Hardware Architectures of CORDIC Algorithm with Fixed Angle of Rotations.” 2015. Masters Thesis, Rochester Institute of Technology. Accessed February 28, 2020. https://scholarworks.rit.edu/theses/8782.

MLA Handbook (7th Edition):

Ramadoss, Rajkumar. “Reliable Hardware Architectures of CORDIC Algorithm with Fixed Angle of Rotations.” 2015. Web. 28 Feb 2020.

Vancouver:

Ramadoss R. Reliable Hardware Architectures of CORDIC Algorithm with Fixed Angle of Rotations. [Internet] [Masters thesis]. Rochester Institute of Technology; 2015. [cited 2020 Feb 28]. Available from: https://scholarworks.rit.edu/theses/8782.

Council of Science Editors:

Ramadoss R. Reliable Hardware Architectures of CORDIC Algorithm with Fixed Angle of Rotations. [Masters Thesis]. Rochester Institute of Technology; 2015. Available from: https://scholarworks.rit.edu/theses/8782


Rochester Institute of Technology

17. Aboketaf, Abdelsalam A. High-speed and Robust Integrated Silicon Nanophotonics for On-Chip Interconnects.

Degree: PhD, Microsystems Engineering, 2014, Rochester Institute of Technology

  Optical interconnects offer advantages over electrical interconnects such as higher bandwidth, low power, reduced interconnects delay, and immunity to electro-magnetic interference and signal crosstalk.… (more)

Subjects/Keywords: Binary phase shift on chip; Electro-optic modulator; High speed systems on chip; On chip interconnects; Optical-time-division-multiplexing; Silicon photonics

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APA (6th Edition):

Aboketaf, A. A. (2014). High-speed and Robust Integrated Silicon Nanophotonics for On-Chip Interconnects. (Doctoral Dissertation). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/7847

Chicago Manual of Style (16th Edition):

Aboketaf, Abdelsalam A. “High-speed and Robust Integrated Silicon Nanophotonics for On-Chip Interconnects.” 2014. Doctoral Dissertation, Rochester Institute of Technology. Accessed February 28, 2020. https://scholarworks.rit.edu/theses/7847.

MLA Handbook (7th Edition):

Aboketaf, Abdelsalam A. “High-speed and Robust Integrated Silicon Nanophotonics for On-Chip Interconnects.” 2014. Web. 28 Feb 2020.

Vancouver:

Aboketaf AA. High-speed and Robust Integrated Silicon Nanophotonics for On-Chip Interconnects. [Internet] [Doctoral dissertation]. Rochester Institute of Technology; 2014. [cited 2020 Feb 28]. Available from: https://scholarworks.rit.edu/theses/7847.

Council of Science Editors:

Aboketaf AA. High-speed and Robust Integrated Silicon Nanophotonics for On-Chip Interconnects. [Doctoral Dissertation]. Rochester Institute of Technology; 2014. Available from: https://scholarworks.rit.edu/theses/7847


Rochester Institute of Technology

18. Graydon, Tucker B. Novel Detection and Analysis using Deep Variational Autoencoders.

Degree: MS, Electrical Engineering, 2018, Rochester Institute of Technology

  This paper presents a Novel Identification System which uses generative modeling techniques and Gaussian Mixture Models (GMMs) to identify the main process variables involved… (more)

Subjects/Keywords: Fault detection; Feature extraction; Machine learning; One class classification; Statistical modeling

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APA (6th Edition):

Graydon, T. B. (2018). Novel Detection and Analysis using Deep Variational Autoencoders. (Masters Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/9897

Chicago Manual of Style (16th Edition):

Graydon, Tucker B. “Novel Detection and Analysis using Deep Variational Autoencoders.” 2018. Masters Thesis, Rochester Institute of Technology. Accessed February 28, 2020. https://scholarworks.rit.edu/theses/9897.

MLA Handbook (7th Edition):

Graydon, Tucker B. “Novel Detection and Analysis using Deep Variational Autoencoders.” 2018. Web. 28 Feb 2020.

Vancouver:

Graydon TB. Novel Detection and Analysis using Deep Variational Autoencoders. [Internet] [Masters thesis]. Rochester Institute of Technology; 2018. [cited 2020 Feb 28]. Available from: https://scholarworks.rit.edu/theses/9897.

Council of Science Editors:

Graydon TB. Novel Detection and Analysis using Deep Variational Autoencoders. [Masters Thesis]. Rochester Institute of Technology; 2018. Available from: https://scholarworks.rit.edu/theses/9897


Rochester Institute of Technology

19. Dhanaraj, Mayur. Incremental and Adaptive L1-Norm Principal Component Analysis: Novel Algorithms and Applications.

Degree: MS, Electrical Engineering, 2018, Rochester Institute of Technology

  L1-norm Principal-Component Analysis (L1-PCA) is known to attain remarkable resistance against faulty/corrupted points among the processed data. However, computing L1-PCA of “big data” with… (more)

Subjects/Keywords: None provided

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APA (6th Edition):

Dhanaraj, M. (2018). Incremental and Adaptive L1-Norm Principal Component Analysis: Novel Algorithms and Applications. (Masters Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/9868

Chicago Manual of Style (16th Edition):

Dhanaraj, Mayur. “Incremental and Adaptive L1-Norm Principal Component Analysis: Novel Algorithms and Applications.” 2018. Masters Thesis, Rochester Institute of Technology. Accessed February 28, 2020. https://scholarworks.rit.edu/theses/9868.

MLA Handbook (7th Edition):

Dhanaraj, Mayur. “Incremental and Adaptive L1-Norm Principal Component Analysis: Novel Algorithms and Applications.” 2018. Web. 28 Feb 2020.

Vancouver:

Dhanaraj M. Incremental and Adaptive L1-Norm Principal Component Analysis: Novel Algorithms and Applications. [Internet] [Masters thesis]. Rochester Institute of Technology; 2018. [cited 2020 Feb 28]. Available from: https://scholarworks.rit.edu/theses/9868.

Council of Science Editors:

Dhanaraj M. Incremental and Adaptive L1-Norm Principal Component Analysis: Novel Algorithms and Applications. [Masters Thesis]. Rochester Institute of Technology; 2018. Available from: https://scholarworks.rit.edu/theses/9868


Rochester Institute of Technology

20. Sunnerberg, Timothy Douglas. Analog Musical Distortion Circuits for Electric Guitars.

Degree: MS, Electrical Engineering, 2019, Rochester Institute of Technology

  Distortion, while seen as undesirable in most contexts, has taken a different role in electronic music. Musical distortion refers to nonlinear changes in a… (more)

Subjects/Keywords: audio signal processing; Nonlinear distortion; Frequency domain analysis; Nonlinear circuits; Coupling circuits; Circuit measurements

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APA (6th Edition):

Sunnerberg, T. D. (2019). Analog Musical Distortion Circuits for Electric Guitars. (Masters Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/10066

Chicago Manual of Style (16th Edition):

Sunnerberg, Timothy Douglas. “Analog Musical Distortion Circuits for Electric Guitars.” 2019. Masters Thesis, Rochester Institute of Technology. Accessed February 28, 2020. https://scholarworks.rit.edu/theses/10066.

MLA Handbook (7th Edition):

Sunnerberg, Timothy Douglas. “Analog Musical Distortion Circuits for Electric Guitars.” 2019. Web. 28 Feb 2020.

Vancouver:

Sunnerberg TD. Analog Musical Distortion Circuits for Electric Guitars. [Internet] [Masters thesis]. Rochester Institute of Technology; 2019. [cited 2020 Feb 28]. Available from: https://scholarworks.rit.edu/theses/10066.

Council of Science Editors:

Sunnerberg TD. Analog Musical Distortion Circuits for Electric Guitars. [Masters Thesis]. Rochester Institute of Technology; 2019. Available from: https://scholarworks.rit.edu/theses/10066


Rochester Institute of Technology

21. Ramakrishnan, Gowtham. Design and Verification of an RSA Encryption Core.

Degree: MS, Electrical Engineering, 2019, Rochester Institute of Technology

  Cryptoprocessors are becoming a standard to make the data-usage more discrete. A wellknown elector-mechanical cipher machine called the “enigma machine” was used in early… (more)

Subjects/Keywords: Public key cryptography; Cryptography; Interleaved codes; Coprocessors; Computer architecture; Application software

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APA (6th Edition):

Ramakrishnan, G. (2019). Design and Verification of an RSA Encryption Core. (Masters Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/10067

Chicago Manual of Style (16th Edition):

Ramakrishnan, Gowtham. “Design and Verification of an RSA Encryption Core.” 2019. Masters Thesis, Rochester Institute of Technology. Accessed February 28, 2020. https://scholarworks.rit.edu/theses/10067.

MLA Handbook (7th Edition):

Ramakrishnan, Gowtham. “Design and Verification of an RSA Encryption Core.” 2019. Web. 28 Feb 2020.

Vancouver:

Ramakrishnan G. Design and Verification of an RSA Encryption Core. [Internet] [Masters thesis]. Rochester Institute of Technology; 2019. [cited 2020 Feb 28]. Available from: https://scholarworks.rit.edu/theses/10067.

Council of Science Editors:

Ramakrishnan G. Design and Verification of an RSA Encryption Core. [Masters Thesis]. Rochester Institute of Technology; 2019. Available from: https://scholarworks.rit.edu/theses/10067


Rochester Institute of Technology

22. Levitan, Sabrina Rose. Investigation of the Benefits of Interlocked Synchronous Pipelines.

Degree: MS, Electrical Engineering, 2019, Rochester Institute of Technology

  The majority of today’s digital circuits use synchronous pipelines. As the technology nodes get smaller, these pipelines are facing problems with area, power, and… (more)

Subjects/Keywords: asynchronous circuits; CMOS logic circuits; current-mode logic; low-power electronics; pipeline arithmetic; Pipelines

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APA (6th Edition):

Levitan, S. R. (2019). Investigation of the Benefits of Interlocked Synchronous Pipelines. (Masters Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/10068

Chicago Manual of Style (16th Edition):

Levitan, Sabrina Rose. “Investigation of the Benefits of Interlocked Synchronous Pipelines.” 2019. Masters Thesis, Rochester Institute of Technology. Accessed February 28, 2020. https://scholarworks.rit.edu/theses/10068.

MLA Handbook (7th Edition):

Levitan, Sabrina Rose. “Investigation of the Benefits of Interlocked Synchronous Pipelines.” 2019. Web. 28 Feb 2020.

Vancouver:

Levitan SR. Investigation of the Benefits of Interlocked Synchronous Pipelines. [Internet] [Masters thesis]. Rochester Institute of Technology; 2019. [cited 2020 Feb 28]. Available from: https://scholarworks.rit.edu/theses/10068.

Council of Science Editors:

Levitan SR. Investigation of the Benefits of Interlocked Synchronous Pipelines. [Masters Thesis]. Rochester Institute of Technology; 2019. Available from: https://scholarworks.rit.edu/theses/10068

23. Bashkaran, Dinesh Anand. Verification of SHA-256 and MD5 Hash Functions Using UVM.

Degree: MS, Electrical Engineering, 2019, Rochester Institute of Technology

  Data integrity assurance and data origin authentication are important security aspects in commerce, financial transfer, banking, software, email, data storage, etc. Cryptographic hash functions… (more)

Subjects/Keywords: MD5; message-digest algorithm; SHA-2; Secure Hash Algorithm 2; Cryptography; Data security

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APA (6th Edition):

Bashkaran, D. A. (2019). Verification of SHA-256 and MD5 Hash Functions Using UVM. (Masters Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/10069

Chicago Manual of Style (16th Edition):

Bashkaran, Dinesh Anand. “Verification of SHA-256 and MD5 Hash Functions Using UVM.” 2019. Masters Thesis, Rochester Institute of Technology. Accessed February 28, 2020. https://scholarworks.rit.edu/theses/10069.

MLA Handbook (7th Edition):

Bashkaran, Dinesh Anand. “Verification of SHA-256 and MD5 Hash Functions Using UVM.” 2019. Web. 28 Feb 2020.

Vancouver:

Bashkaran DA. Verification of SHA-256 and MD5 Hash Functions Using UVM. [Internet] [Masters thesis]. Rochester Institute of Technology; 2019. [cited 2020 Feb 28]. Available from: https://scholarworks.rit.edu/theses/10069.

Council of Science Editors:

Bashkaran DA. Verification of SHA-256 and MD5 Hash Functions Using UVM. [Masters Thesis]. Rochester Institute of Technology; 2019. Available from: https://scholarworks.rit.edu/theses/10069

24. Balaraju, Shravani. UVM Verification of an I2C Master Core.

Degree: MS, Electrical Engineering, 2019, Rochester Institute of Technology

  With the increasing complexity of IP designs, verification has become quite popular yet is still a significant challenge for a verification engineer. A proper… (more)

Subjects/Keywords: I2C bus protocol; I2C protocol; Testing; Protocols; Clocks; Hardware

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APA (6th Edition):

Balaraju, S. (2019). UVM Verification of an I2C Master Core. (Masters Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/10070

Chicago Manual of Style (16th Edition):

Balaraju, Shravani. “UVM Verification of an I2C Master Core.” 2019. Masters Thesis, Rochester Institute of Technology. Accessed February 28, 2020. https://scholarworks.rit.edu/theses/10070.

MLA Handbook (7th Edition):

Balaraju, Shravani. “UVM Verification of an I2C Master Core.” 2019. Web. 28 Feb 2020.

Vancouver:

Balaraju S. UVM Verification of an I2C Master Core. [Internet] [Masters thesis]. Rochester Institute of Technology; 2019. [cited 2020 Feb 28]. Available from: https://scholarworks.rit.edu/theses/10070.

Council of Science Editors:

Balaraju S. UVM Verification of an I2C Master Core. [Masters Thesis]. Rochester Institute of Technology; 2019. Available from: https://scholarworks.rit.edu/theses/10070


Rochester Institute of Technology

25. Marsaw, Nicholas J. UVM Verification of a Floating Point Multiplier.

Degree: MS, Electrical Engineering, 2019, Rochester Institute of Technology

  Increased design complexity has resulted in the need for efficient verification. The verification process is crucial for discovering and fixing bugs prior to fabrication… (more)

Subjects/Keywords: UVM; Verification; Layering protocols; Pipeline; Pipelined architecture; Testing

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APA (6th Edition):

Marsaw, N. J. (2019). UVM Verification of a Floating Point Multiplier. (Masters Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/10327

Chicago Manual of Style (16th Edition):

Marsaw, Nicholas J. “UVM Verification of a Floating Point Multiplier.” 2019. Masters Thesis, Rochester Institute of Technology. Accessed February 28, 2020. https://scholarworks.rit.edu/theses/10327.

MLA Handbook (7th Edition):

Marsaw, Nicholas J. “UVM Verification of a Floating Point Multiplier.” 2019. Web. 28 Feb 2020.

Vancouver:

Marsaw NJ. UVM Verification of a Floating Point Multiplier. [Internet] [Masters thesis]. Rochester Institute of Technology; 2019. [cited 2020 Feb 28]. Available from: https://scholarworks.rit.edu/theses/10327.

Council of Science Editors:

Marsaw NJ. UVM Verification of a Floating Point Multiplier. [Masters Thesis]. Rochester Institute of Technology; 2019. Available from: https://scholarworks.rit.edu/theses/10327


Rochester Institute of Technology

26. Shende, Gaurav Mohan. A Novel System To Improve Over-Speeding Traffic Violation Ticketing using a Black Box.

Degree: MS, Electrical Engineering, 2019, Rochester Institute of Technology

  The paper will discuss the implementation of a novel system using a black box to make the overspeeding ticketing system more robust. The system… (more)

Subjects/Keywords: OBD-II PIDs; Bluetooth low energy; MQTT; CAN; Communication system control; Protocols

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APA (6th Edition):

Shende, G. M. (2019). A Novel System To Improve Over-Speeding Traffic Violation Ticketing using a Black Box. (Masters Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/10328

Chicago Manual of Style (16th Edition):

Shende, Gaurav Mohan. “A Novel System To Improve Over-Speeding Traffic Violation Ticketing using a Black Box.” 2019. Masters Thesis, Rochester Institute of Technology. Accessed February 28, 2020. https://scholarworks.rit.edu/theses/10328.

MLA Handbook (7th Edition):

Shende, Gaurav Mohan. “A Novel System To Improve Over-Speeding Traffic Violation Ticketing using a Black Box.” 2019. Web. 28 Feb 2020.

Vancouver:

Shende GM. A Novel System To Improve Over-Speeding Traffic Violation Ticketing using a Black Box. [Internet] [Masters thesis]. Rochester Institute of Technology; 2019. [cited 2020 Feb 28]. Available from: https://scholarworks.rit.edu/theses/10328.

Council of Science Editors:

Shende GM. A Novel System To Improve Over-Speeding Traffic Violation Ticketing using a Black Box. [Masters Thesis]. Rochester Institute of Technology; 2019. Available from: https://scholarworks.rit.edu/theses/10328

27. Chiu, Patrick. A Practical Application of Wave-Pipelining Theory on a Adaptive Differential Pulse Code Modulation Coder-Decoder Design.

Degree: MS, Electrical Engineering, 2016, Rochester Institute of Technology

  Pipeline architectures are often considered in VLSI designs that require high throughput. The draw-backs for traditional pipelined architectures are the increased area, power, and… (more)

Subjects/Keywords: Wave pipeline; Pipeline; Pipelined architecture; Clock frequency; Digital system

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APA (6th Edition):

Chiu, P. (2016). A Practical Application of Wave-Pipelining Theory on a Adaptive Differential Pulse Code Modulation Coder-Decoder Design. (Masters Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/8977

Chicago Manual of Style (16th Edition):

Chiu, Patrick. “A Practical Application of Wave-Pipelining Theory on a Adaptive Differential Pulse Code Modulation Coder-Decoder Design.” 2016. Masters Thesis, Rochester Institute of Technology. Accessed February 28, 2020. https://scholarworks.rit.edu/theses/8977.

MLA Handbook (7th Edition):

Chiu, Patrick. “A Practical Application of Wave-Pipelining Theory on a Adaptive Differential Pulse Code Modulation Coder-Decoder Design.” 2016. Web. 28 Feb 2020.

Vancouver:

Chiu P. A Practical Application of Wave-Pipelining Theory on a Adaptive Differential Pulse Code Modulation Coder-Decoder Design. [Internet] [Masters thesis]. Rochester Institute of Technology; 2016. [cited 2020 Feb 28]. Available from: https://scholarworks.rit.edu/theses/8977.

Council of Science Editors:

Chiu P. A Practical Application of Wave-Pipelining Theory on a Adaptive Differential Pulse Code Modulation Coder-Decoder Design. [Masters Thesis]. Rochester Institute of Technology; 2016. Available from: https://scholarworks.rit.edu/theses/8977

28. Peng, Honghong. Automatic Denoising and Unmixing in Hyperspectral Image Processing.

Degree: PhD, Chester F. Carlson Center for Imaging Science (COS), 2014, Rochester Institute of Technology

  This thesis addresses two important aspects in hyperspectral image processing: automatic hyperspectral image denoising and unmixing. The first part of this thesis is devoted… (more)

Subjects/Keywords: Denoising; Hyperspectral image processing; Unmixing; Unsupervised learning

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APA (6th Edition):

Peng, H. (2014). Automatic Denoising and Unmixing in Hyperspectral Image Processing. (Doctoral Dissertation). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/7949

Chicago Manual of Style (16th Edition):

Peng, Honghong. “Automatic Denoising and Unmixing in Hyperspectral Image Processing.” 2014. Doctoral Dissertation, Rochester Institute of Technology. Accessed February 28, 2020. https://scholarworks.rit.edu/theses/7949.

MLA Handbook (7th Edition):

Peng, Honghong. “Automatic Denoising and Unmixing in Hyperspectral Image Processing.” 2014. Web. 28 Feb 2020.

Vancouver:

Peng H. Automatic Denoising and Unmixing in Hyperspectral Image Processing. [Internet] [Doctoral dissertation]. Rochester Institute of Technology; 2014. [cited 2020 Feb 28]. Available from: https://scholarworks.rit.edu/theses/7949.

Council of Science Editors:

Peng H. Automatic Denoising and Unmixing in Hyperspectral Image Processing. [Doctoral Dissertation]. Rochester Institute of Technology; 2014. Available from: https://scholarworks.rit.edu/theses/7949

29. Traitruengsakul, Supachan. Automatic Localization of Epileptic Spikes in EEGs of Children with Infantile Spasms.

Degree: MS, Electrical Engineering, 2015, Rochester Institute of Technology

  Infantile Spasms (ISS) characterized by electroencephalogram (EEG) recordings exhibiting hypsarrythmia (HYPS) are a severe form of epilepsy. Many clinicians have been trying to improve… (more)

Subjects/Keywords: Classification; Feature extraction; Hypsarrythmia; Nonnegative matrix factorization; Time-frequency representations

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APA (6th Edition):

Traitruengsakul, S. (2015). Automatic Localization of Epileptic Spikes in EEGs of Children with Infantile Spasms. (Masters Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/8867

Chicago Manual of Style (16th Edition):

Traitruengsakul, Supachan. “Automatic Localization of Epileptic Spikes in EEGs of Children with Infantile Spasms.” 2015. Masters Thesis, Rochester Institute of Technology. Accessed February 28, 2020. https://scholarworks.rit.edu/theses/8867.

MLA Handbook (7th Edition):

Traitruengsakul, Supachan. “Automatic Localization of Epileptic Spikes in EEGs of Children with Infantile Spasms.” 2015. Web. 28 Feb 2020.

Vancouver:

Traitruengsakul S. Automatic Localization of Epileptic Spikes in EEGs of Children with Infantile Spasms. [Internet] [Masters thesis]. Rochester Institute of Technology; 2015. [cited 2020 Feb 28]. Available from: https://scholarworks.rit.edu/theses/8867.

Council of Science Editors:

Traitruengsakul S. Automatic Localization of Epileptic Spikes in EEGs of Children with Infantile Spasms. [Masters Thesis]. Rochester Institute of Technology; 2015. Available from: https://scholarworks.rit.edu/theses/8867

30. Singh, Vineeta Pannalal. Reliable Low-Latency and Low-Complexity Viterbi Architectures Benchmarked on ASIC and FPGA.

Degree: MS, Electrical Engineering, 2015, Rochester Institute of Technology

  The Viterbi algorithm is commonly applied in a number of sensitive usage models including decoding convolutional codes used in communications such as satellite communication,… (more)

Subjects/Keywords: None provided

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APA (6th Edition):

Singh, V. P. (2015). Reliable Low-Latency and Low-Complexity Viterbi Architectures Benchmarked on ASIC and FPGA. (Masters Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/8781

Chicago Manual of Style (16th Edition):

Singh, Vineeta Pannalal. “Reliable Low-Latency and Low-Complexity Viterbi Architectures Benchmarked on ASIC and FPGA.” 2015. Masters Thesis, Rochester Institute of Technology. Accessed February 28, 2020. https://scholarworks.rit.edu/theses/8781.

MLA Handbook (7th Edition):

Singh, Vineeta Pannalal. “Reliable Low-Latency and Low-Complexity Viterbi Architectures Benchmarked on ASIC and FPGA.” 2015. Web. 28 Feb 2020.

Vancouver:

Singh VP. Reliable Low-Latency and Low-Complexity Viterbi Architectures Benchmarked on ASIC and FPGA. [Internet] [Masters thesis]. Rochester Institute of Technology; 2015. [cited 2020 Feb 28]. Available from: https://scholarworks.rit.edu/theses/8781.

Council of Science Editors:

Singh VP. Reliable Low-Latency and Low-Complexity Viterbi Architectures Benchmarked on ASIC and FPGA. [Masters Thesis]. Rochester Institute of Technology; 2015. Available from: https://scholarworks.rit.edu/theses/8781

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