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You searched for +publisher:"Rice University" +contributor:("Mellor-Crummey, John"). Showing records 1 – 30 of 37 total matches.

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Rice University

1. Yang, Chaoran. Runtime Technologies of High Performance Parallel Computing.

Degree: PhD, Engineering, 2016, Rice University

 Due to power constraints, future growth in computing capability must explicitly leverage parallelism in software to effectively exploit hardware parallelism found in both distributed and… (more)

Subjects/Keywords: Runtime Technologies; High Performance Computing; Parallel Computing; Partitioned Global Address Space; Work-stealing; Concurrent Data Structures

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APA (6th Edition):

Yang, C. (2016). Runtime Technologies of High Performance Parallel Computing. (Doctoral Dissertation). Rice University. Retrieved from http://hdl.handle.net/1911/95637

Chicago Manual of Style (16th Edition):

Yang, Chaoran. “Runtime Technologies of High Performance Parallel Computing.” 2016. Doctoral Dissertation, Rice University. Accessed January 22, 2020. http://hdl.handle.net/1911/95637.

MLA Handbook (7th Edition):

Yang, Chaoran. “Runtime Technologies of High Performance Parallel Computing.” 2016. Web. 22 Jan 2020.

Vancouver:

Yang C. Runtime Technologies of High Performance Parallel Computing. [Internet] [Doctoral dissertation]. Rice University; 2016. [cited 2020 Jan 22]. Available from: http://hdl.handle.net/1911/95637.

Council of Science Editors:

Yang C. Runtime Technologies of High Performance Parallel Computing. [Doctoral Dissertation]. Rice University; 2016. Available from: http://hdl.handle.net/1911/95637


Rice University

2. Paul, Sri Raj. Performance Analysis and Optimization of a Hybrid Distributed Reverse Time Migration Application.

Degree: MS, Engineering, 2016, Rice University

 To fully exploit emerging processor architectures, programs will need to employ threaded parallelism within a node and message passing across nodes. Today, MPI+OpenMP is the… (more)

Subjects/Keywords: Performance Analysis tools; Reverse time migration; Hybrid programming model; MPI+OpenMP

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APA (6th Edition):

Paul, S. R. (2016). Performance Analysis and Optimization of a Hybrid Distributed Reverse Time Migration Application. (Masters Thesis). Rice University. Retrieved from http://hdl.handle.net/1911/96190

Chicago Manual of Style (16th Edition):

Paul, Sri Raj. “Performance Analysis and Optimization of a Hybrid Distributed Reverse Time Migration Application.” 2016. Masters Thesis, Rice University. Accessed January 22, 2020. http://hdl.handle.net/1911/96190.

MLA Handbook (7th Edition):

Paul, Sri Raj. “Performance Analysis and Optimization of a Hybrid Distributed Reverse Time Migration Application.” 2016. Web. 22 Jan 2020.

Vancouver:

Paul SR. Performance Analysis and Optimization of a Hybrid Distributed Reverse Time Migration Application. [Internet] [Masters thesis]. Rice University; 2016. [cited 2020 Jan 22]. Available from: http://hdl.handle.net/1911/96190.

Council of Science Editors:

Paul SR. Performance Analysis and Optimization of a Hybrid Distributed Reverse Time Migration Application. [Masters Thesis]. Rice University; 2016. Available from: http://hdl.handle.net/1911/96190


Rice University

3. Youssefi, Annahita. Exploring the potential for accelerating sparse matrix-vector product on a Processing-in-Memory architecture.

Degree: MS, Engineering, 2009, Rice University

 As the importance of memory access delays on performance has mushroomed over the past few decades, researchers have begun exploring Processing-in-Memory (PIM) technology, which offers… (more)

Subjects/Keywords: Computer science; Applied sciences

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APA (6th Edition):

Youssefi, A. (2009). Exploring the potential for accelerating sparse matrix-vector product on a Processing-in-Memory architecture. (Masters Thesis). Rice University. Retrieved from http://hdl.handle.net/1911/61946

Chicago Manual of Style (16th Edition):

Youssefi, Annahita. “Exploring the potential for accelerating sparse matrix-vector product on a Processing-in-Memory architecture.” 2009. Masters Thesis, Rice University. Accessed January 22, 2020. http://hdl.handle.net/1911/61946.

MLA Handbook (7th Edition):

Youssefi, Annahita. “Exploring the potential for accelerating sparse matrix-vector product on a Processing-in-Memory architecture.” 2009. Web. 22 Jan 2020.

Vancouver:

Youssefi A. Exploring the potential for accelerating sparse matrix-vector product on a Processing-in-Memory architecture. [Internet] [Masters thesis]. Rice University; 2009. [cited 2020 Jan 22]. Available from: http://hdl.handle.net/1911/61946.

Council of Science Editors:

Youssefi A. Exploring the potential for accelerating sparse matrix-vector product on a Processing-in-Memory architecture. [Masters Thesis]. Rice University; 2009. Available from: http://hdl.handle.net/1911/61946


Rice University

4. Tallent, Nathan Russell. Performance analysis for parallel programs from multicore to petascale.

Degree: PhD, Engineering, 2010, Rice University

 Cutting-edge science and engineering applications require petascale computing. Petascale computing platforms are characterized by both extreme parallelism (systems of hundreds of thousands to millions of… (more)

Subjects/Keywords: Computer science; Applied sciences

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APA (6th Edition):

Tallent, N. R. (2010). Performance analysis for parallel programs from multicore to petascale. (Doctoral Dissertation). Rice University. Retrieved from http://hdl.handle.net/1911/62106

Chicago Manual of Style (16th Edition):

Tallent, Nathan Russell. “Performance analysis for parallel programs from multicore to petascale.” 2010. Doctoral Dissertation, Rice University. Accessed January 22, 2020. http://hdl.handle.net/1911/62106.

MLA Handbook (7th Edition):

Tallent, Nathan Russell. “Performance analysis for parallel programs from multicore to petascale.” 2010. Web. 22 Jan 2020.

Vancouver:

Tallent NR. Performance analysis for parallel programs from multicore to petascale. [Internet] [Doctoral dissertation]. Rice University; 2010. [cited 2020 Jan 22]. Available from: http://hdl.handle.net/1911/62106.

Council of Science Editors:

Tallent NR. Performance analysis for parallel programs from multicore to petascale. [Doctoral Dissertation]. Rice University; 2010. Available from: http://hdl.handle.net/1911/62106

5. Yang, Chaoran. Function Shipping in a Scalable Parallel Programming Model.

Degree: MS, Engineering, 2012, Rice University

 Increasingly, a large number of scientific and technical applications exhibit dynamically generated parallelism or irregular data access patterns. These applications pose significant challenges to achieving… (more)

Subjects/Keywords: Applied sciences; Computer engineering; Computer science

…x5B;9] language under development at Rice University. CAF 2.0 is a rich set of PGAS… 

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APA (6th Edition):

Yang, C. (2012). Function Shipping in a Scalable Parallel Programming Model. (Masters Thesis). Rice University. Retrieved from http://hdl.handle.net/1911/70500

Chicago Manual of Style (16th Edition):

Yang, Chaoran. “Function Shipping in a Scalable Parallel Programming Model.” 2012. Masters Thesis, Rice University. Accessed January 22, 2020. http://hdl.handle.net/1911/70500.

MLA Handbook (7th Edition):

Yang, Chaoran. “Function Shipping in a Scalable Parallel Programming Model.” 2012. Web. 22 Jan 2020.

Vancouver:

Yang C. Function Shipping in a Scalable Parallel Programming Model. [Internet] [Masters thesis]. Rice University; 2012. [cited 2020 Jan 22]. Available from: http://hdl.handle.net/1911/70500.

Council of Science Editors:

Yang C. Function Shipping in a Scalable Parallel Programming Model. [Masters Thesis]. Rice University; 2012. Available from: http://hdl.handle.net/1911/70500


Rice University

6. Srinivasa Murthy, Karthik. Code Generation for Extreme Scale Parallel Systems.

Degree: PhD, Engineering, 2017, Rice University

 Power consumption and fabrication limitations are increasingly playing significant roles in the design of extreme scale parallel systems. These factors are influencing system designers to… (more)

Subjects/Keywords: .5D algorithms; compiler; polyhedral model; cofence; phasers; modulo operations; collectives; code generation; vectorization

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APA (6th Edition):

Srinivasa Murthy, K. (2017). Code Generation for Extreme Scale Parallel Systems. (Doctoral Dissertation). Rice University. Retrieved from http://hdl.handle.net/1911/96060

Chicago Manual of Style (16th Edition):

Srinivasa Murthy, Karthik. “Code Generation for Extreme Scale Parallel Systems.” 2017. Doctoral Dissertation, Rice University. Accessed January 22, 2020. http://hdl.handle.net/1911/96060.

MLA Handbook (7th Edition):

Srinivasa Murthy, Karthik. “Code Generation for Extreme Scale Parallel Systems.” 2017. Web. 22 Jan 2020.

Vancouver:

Srinivasa Murthy K. Code Generation for Extreme Scale Parallel Systems. [Internet] [Doctoral dissertation]. Rice University; 2017. [cited 2020 Jan 22]. Available from: http://hdl.handle.net/1911/96060.

Council of Science Editors:

Srinivasa Murthy K. Code Generation for Extreme Scale Parallel Systems. [Doctoral Dissertation]. Rice University; 2017. Available from: http://hdl.handle.net/1911/96060


Rice University

7. Taffet, Philip Adam. Understanding Congestion in High Performance Interconnection Networks Using Sampling.

Degree: MS, Engineering, 2018, Rice University

 The computational needs of many applications outstrip the capabilities of a single compute node. Communication is necessary to employ multiple nodes, but slow communication often… (more)

Subjects/Keywords: network congestion; reservoir sampling; probabilistic; high performance computing; network simulation; InfiniBand; interconnection networks; communication performance; Omni-Path; MPI

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APA (6th Edition):

Taffet, P. A. (2018). Understanding Congestion in High Performance Interconnection Networks Using Sampling. (Masters Thesis). Rice University. Retrieved from http://hdl.handle.net/1911/103413

Chicago Manual of Style (16th Edition):

Taffet, Philip Adam. “Understanding Congestion in High Performance Interconnection Networks Using Sampling.” 2018. Masters Thesis, Rice University. Accessed January 22, 2020. http://hdl.handle.net/1911/103413.

MLA Handbook (7th Edition):

Taffet, Philip Adam. “Understanding Congestion in High Performance Interconnection Networks Using Sampling.” 2018. Web. 22 Jan 2020.

Vancouver:

Taffet PA. Understanding Congestion in High Performance Interconnection Networks Using Sampling. [Internet] [Masters thesis]. Rice University; 2018. [cited 2020 Jan 22]. Available from: http://hdl.handle.net/1911/103413.

Council of Science Editors:

Taffet PA. Understanding Congestion in High Performance Interconnection Networks Using Sampling. [Masters Thesis]. Rice University; 2018. Available from: http://hdl.handle.net/1911/103413


Rice University

8. Zhang, Rui. Performance Optimizations for Software Transactional Memory.

Degree: PhD, Engineering, 2011, Rice University

 The transition from single-core processors to multi-core processors demands a change from sequential programming to concurrent programming for mainstream programmers. However, concurrent programming has long… (more)

Subjects/Keywords: Applied sciences; Transactional memory; Parallel computing; Concurrent programming; Computer science

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APA (6th Edition):

Zhang, R. (2011). Performance Optimizations for Software Transactional Memory. (Doctoral Dissertation). Rice University. Retrieved from http://hdl.handle.net/1911/70517

Chicago Manual of Style (16th Edition):

Zhang, Rui. “Performance Optimizations for Software Transactional Memory.” 2011. Doctoral Dissertation, Rice University. Accessed January 22, 2020. http://hdl.handle.net/1911/70517.

MLA Handbook (7th Edition):

Zhang, Rui. “Performance Optimizations for Software Transactional Memory.” 2011. Web. 22 Jan 2020.

Vancouver:

Zhang R. Performance Optimizations for Software Transactional Memory. [Internet] [Doctoral dissertation]. Rice University; 2011. [cited 2020 Jan 22]. Available from: http://hdl.handle.net/1911/70517.

Council of Science Editors:

Zhang R. Performance Optimizations for Software Transactional Memory. [Doctoral Dissertation]. Rice University; 2011. Available from: http://hdl.handle.net/1911/70517


Rice University

9. Chatterjee, Sanjay. Runtime Systems for Extreme Scale Platforms.

Degree: PhD, Engineering, 2013, Rice University

 Future extreme-scale systems are expected to contain homogeneous and heterogeneous many-core processors, with O(103) cores per node and O(106) nodes overall. Effective combination of inter… (more)

Subjects/Keywords: Task parallelism; Data-flow; Runtime; Extreme-scale; Exascale; Communications; Locality; Tuning; Phaser; Synchronization

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APA (6th Edition):

Chatterjee, S. (2013). Runtime Systems for Extreme Scale Platforms. (Doctoral Dissertation). Rice University. Retrieved from http://hdl.handle.net/1911/76173

Chicago Manual of Style (16th Edition):

Chatterjee, Sanjay. “Runtime Systems for Extreme Scale Platforms.” 2013. Doctoral Dissertation, Rice University. Accessed January 22, 2020. http://hdl.handle.net/1911/76173.

MLA Handbook (7th Edition):

Chatterjee, Sanjay. “Runtime Systems for Extreme Scale Platforms.” 2013. Web. 22 Jan 2020.

Vancouver:

Chatterjee S. Runtime Systems for Extreme Scale Platforms. [Internet] [Doctoral dissertation]. Rice University; 2013. [cited 2020 Jan 22]. Available from: http://hdl.handle.net/1911/76173.

Council of Science Editors:

Chatterjee S. Runtime Systems for Extreme Scale Platforms. [Doctoral Dissertation]. Rice University; 2013. Available from: http://hdl.handle.net/1911/76173


Rice University

10. Chatterjee, Sanjay. Runtime Models for Extreme Scale Systems.

Degree: PhD, Engineering, 2013, Rice University

 Future extreme-scale systems are expected to contain homogeneous and heterogeneous many-core processors, with up to O(103) cores per node and O(106) nodes overall. Effective combination… (more)

Subjects/Keywords: Task parallelism; Data-flow; Runtime; Extreme-scale; Exascale; Communications; Locality; Tuning; Phaser; Synchronization

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APA (6th Edition):

Chatterjee, S. (2013). Runtime Models for Extreme Scale Systems. (Doctoral Dissertation). Rice University. Retrieved from http://hdl.handle.net/1911/76416

Chicago Manual of Style (16th Edition):

Chatterjee, Sanjay. “Runtime Models for Extreme Scale Systems.” 2013. Doctoral Dissertation, Rice University. Accessed January 22, 2020. http://hdl.handle.net/1911/76416.

MLA Handbook (7th Edition):

Chatterjee, Sanjay. “Runtime Models for Extreme Scale Systems.” 2013. Web. 22 Jan 2020.

Vancouver:

Chatterjee S. Runtime Models for Extreme Scale Systems. [Internet] [Doctoral dissertation]. Rice University; 2013. [cited 2020 Jan 22]. Available from: http://hdl.handle.net/1911/76416.

Council of Science Editors:

Chatterjee S. Runtime Models for Extreme Scale Systems. [Doctoral Dissertation]. Rice University; 2013. Available from: http://hdl.handle.net/1911/76416


Rice University

11. Zhang, Yunming. Optimized Runtime Systems for MapReduce Applications in Multi-core Clusters.

Degree: MS, Engineering, 2014, Rice University

 This research proposes a novel runtime system, Habanero Hadoop, to tackle the inefficient utilization of multi-core machines' memory in the existing Hadoop MapReduce runtime system.… (more)

Subjects/Keywords: MapReduce; Memory

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APA (6th Edition):

Zhang, Y. (2014). Optimized Runtime Systems for MapReduce Applications in Multi-core Clusters. (Masters Thesis). Rice University. Retrieved from http://hdl.handle.net/1911/87782

Chicago Manual of Style (16th Edition):

Zhang, Yunming. “Optimized Runtime Systems for MapReduce Applications in Multi-core Clusters.” 2014. Masters Thesis, Rice University. Accessed January 22, 2020. http://hdl.handle.net/1911/87782.

MLA Handbook (7th Edition):

Zhang, Yunming. “Optimized Runtime Systems for MapReduce Applications in Multi-core Clusters.” 2014. Web. 22 Jan 2020.

Vancouver:

Zhang Y. Optimized Runtime Systems for MapReduce Applications in Multi-core Clusters. [Internet] [Masters thesis]. Rice University; 2014. [cited 2020 Jan 22]. Available from: http://hdl.handle.net/1911/87782.

Council of Science Editors:

Zhang Y. Optimized Runtime Systems for MapReduce Applications in Multi-core Clusters. [Masters Thesis]. Rice University; 2014. Available from: http://hdl.handle.net/1911/87782


Rice University

12. Liu, Xu. Performance Analysis of Program Executions on Modern Parallel Architectures.

Degree: PhD, Engineering, 2014, Rice University

 Parallel architectures have become common in supercomputers, data centers, and mobile chips. Usually, parallel architectures have complex features: many hardware threads, deep memory hierarchies, and… (more)

Subjects/Keywords: OpenMP; data locality; performance

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APA (6th Edition):

Liu, X. (2014). Performance Analysis of Program Executions on Modern Parallel Architectures. (Doctoral Dissertation). Rice University. Retrieved from http://hdl.handle.net/1911/87790

Chicago Manual of Style (16th Edition):

Liu, Xu. “Performance Analysis of Program Executions on Modern Parallel Architectures.” 2014. Doctoral Dissertation, Rice University. Accessed January 22, 2020. http://hdl.handle.net/1911/87790.

MLA Handbook (7th Edition):

Liu, Xu. “Performance Analysis of Program Executions on Modern Parallel Architectures.” 2014. Web. 22 Jan 2020.

Vancouver:

Liu X. Performance Analysis of Program Executions on Modern Parallel Architectures. [Internet] [Doctoral dissertation]. Rice University; 2014. [cited 2020 Jan 22]. Available from: http://hdl.handle.net/1911/87790.

Council of Science Editors:

Liu X. Performance Analysis of Program Executions on Modern Parallel Architectures. [Doctoral Dissertation]. Rice University; 2014. Available from: http://hdl.handle.net/1911/87790


Rice University

13. Li, Conglong. GD-Wheel: A Cost-Aware Replacement Policy for Key-Value Stores.

Degree: MS, Engineering, 2014, Rice University

 Various memory-based key-value stores, such as Memcached and Redis, are used to speed up dynamic web applications. Specifically, they are used to cache the results… (more)

Subjects/Keywords: Key-Value Store; Replacement Policy; Distributed System

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APA (6th Edition):

Li, C. (2014). GD-Wheel: A Cost-Aware Replacement Policy for Key-Value Stores. (Masters Thesis). Rice University. Retrieved from http://hdl.handle.net/1911/88084

Chicago Manual of Style (16th Edition):

Li, Conglong. “GD-Wheel: A Cost-Aware Replacement Policy for Key-Value Stores.” 2014. Masters Thesis, Rice University. Accessed January 22, 2020. http://hdl.handle.net/1911/88084.

MLA Handbook (7th Edition):

Li, Conglong. “GD-Wheel: A Cost-Aware Replacement Policy for Key-Value Stores.” 2014. Web. 22 Jan 2020.

Vancouver:

Li C. GD-Wheel: A Cost-Aware Replacement Policy for Key-Value Stores. [Internet] [Masters thesis]. Rice University; 2014. [cited 2020 Jan 22]. Available from: http://hdl.handle.net/1911/88084.

Council of Science Editors:

Li C. GD-Wheel: A Cost-Aware Replacement Policy for Key-Value Stores. [Masters Thesis]. Rice University; 2014. Available from: http://hdl.handle.net/1911/88084


Rice University

14. Liu, Ruoyu. Performance Analysis and Optimization of Apache Pig.

Degree: MS, Engineering, 2014, Rice University

 Apache Pig is a language, compiler, and run-time library for simplifying the development of data-analytics applications on Apache Hadoop. Specifically, it enables developers to write… (more)

Subjects/Keywords: Apache Hadoop; Apache Pig; MapReduce; Performance; Hash join

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APA (6th Edition):

Liu, R. (2014). Performance Analysis and Optimization of Apache Pig. (Masters Thesis). Rice University. Retrieved from http://hdl.handle.net/1911/88101

Chicago Manual of Style (16th Edition):

Liu, Ruoyu. “Performance Analysis and Optimization of Apache Pig.” 2014. Masters Thesis, Rice University. Accessed January 22, 2020. http://hdl.handle.net/1911/88101.

MLA Handbook (7th Edition):

Liu, Ruoyu. “Performance Analysis and Optimization of Apache Pig.” 2014. Web. 22 Jan 2020.

Vancouver:

Liu R. Performance Analysis and Optimization of Apache Pig. [Internet] [Masters thesis]. Rice University; 2014. [cited 2020 Jan 22]. Available from: http://hdl.handle.net/1911/88101.

Council of Science Editors:

Liu R. Performance Analysis and Optimization of Apache Pig. [Masters Thesis]. Rice University; 2014. Available from: http://hdl.handle.net/1911/88101


Rice University

15. Sharma, Kamal Gopal. Locality Transformations of Computation and Data for Portable Performance.

Degree: PhD, Engineering, 2014, Rice University

 Recently, multi-cores chips have become omnipresent in computer systems ranging from high-end servers to mobile phones. A variety of multi-core architectures have been developed which… (more)

Subjects/Keywords: Locality Transformations; Cache Optimization; Tile size selection; Data Layout Optimization; Performance; Distributed Function Selection

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APA (6th Edition):

Sharma, K. G. (2014). Locality Transformations of Computation and Data for Portable Performance. (Doctoral Dissertation). Rice University. Retrieved from http://hdl.handle.net/1911/88159

Chicago Manual of Style (16th Edition):

Sharma, Kamal Gopal. “Locality Transformations of Computation and Data for Portable Performance.” 2014. Doctoral Dissertation, Rice University. Accessed January 22, 2020. http://hdl.handle.net/1911/88159.

MLA Handbook (7th Edition):

Sharma, Kamal Gopal. “Locality Transformations of Computation and Data for Portable Performance.” 2014. Web. 22 Jan 2020.

Vancouver:

Sharma KG. Locality Transformations of Computation and Data for Portable Performance. [Internet] [Doctoral dissertation]. Rice University; 2014. [cited 2020 Jan 22]. Available from: http://hdl.handle.net/1911/88159.

Council of Science Editors:

Sharma KG. Locality Transformations of Computation and Data for Portable Performance. [Doctoral Dissertation]. Rice University; 2014. Available from: http://hdl.handle.net/1911/88159


Rice University

16. Imam, Shams Mahmood. Cooperative Execution of Parallel Tasks with Synchronization Constraints.

Degree: PhD, Engineering, 2015, Rice University

 The topic of this thesis is the effective execution of parallel applications on emerging multicore and manycore systems in the presence of modern synchronization and… (more)

Subjects/Keywords: Cooperative Techniques; Cooperative Runtime; Synchronization Constraints; Eureka Programming Model; Selector Model; Task Parallel Model; Actor Model; Habanero Java

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APA (6th Edition):

Imam, S. M. (2015). Cooperative Execution of Parallel Tasks with Synchronization Constraints. (Doctoral Dissertation). Rice University. Retrieved from http://hdl.handle.net/1911/88129

Chicago Manual of Style (16th Edition):

Imam, Shams Mahmood. “Cooperative Execution of Parallel Tasks with Synchronization Constraints.” 2015. Doctoral Dissertation, Rice University. Accessed January 22, 2020. http://hdl.handle.net/1911/88129.

MLA Handbook (7th Edition):

Imam, Shams Mahmood. “Cooperative Execution of Parallel Tasks with Synchronization Constraints.” 2015. Web. 22 Jan 2020.

Vancouver:

Imam SM. Cooperative Execution of Parallel Tasks with Synchronization Constraints. [Internet] [Doctoral dissertation]. Rice University; 2015. [cited 2020 Jan 22]. Available from: http://hdl.handle.net/1911/88129.

Council of Science Editors:

Imam SM. Cooperative Execution of Parallel Tasks with Synchronization Constraints. [Doctoral Dissertation]. Rice University; 2015. Available from: http://hdl.handle.net/1911/88129


Rice University

17. Vrvilo, Nick. Implementing Asynchronous Checkpoint/Restart for the Concurrent Collections Model.

Degree: MS, Engineering, 2014, Rice University

 It has been claimed that what simplifies parallelism can also simplify resilience. Based on that assertion, we present the Concurrent Collections programming model (CnC) as… (more)

Subjects/Keywords: Concurrent Collections; Resilience; Checkpoint/Restart

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APA (6th Edition):

Vrvilo, N. (2014). Implementing Asynchronous Checkpoint/Restart for the Concurrent Collections Model. (Masters Thesis). Rice University. Retrieved from http://hdl.handle.net/1911/88191

Chicago Manual of Style (16th Edition):

Vrvilo, Nick. “Implementing Asynchronous Checkpoint/Restart for the Concurrent Collections Model.” 2014. Masters Thesis, Rice University. Accessed January 22, 2020. http://hdl.handle.net/1911/88191.

MLA Handbook (7th Edition):

Vrvilo, Nick. “Implementing Asynchronous Checkpoint/Restart for the Concurrent Collections Model.” 2014. Web. 22 Jan 2020.

Vancouver:

Vrvilo N. Implementing Asynchronous Checkpoint/Restart for the Concurrent Collections Model. [Internet] [Masters thesis]. Rice University; 2014. [cited 2020 Jan 22]. Available from: http://hdl.handle.net/1911/88191.

Council of Science Editors:

Vrvilo N. Implementing Asynchronous Checkpoint/Restart for the Concurrent Collections Model. [Masters Thesis]. Rice University; 2014. Available from: http://hdl.handle.net/1911/88191


Rice University

18. Majeti, Deepak. Portable Programming Models for Heterogeneous Platforms.

Degree: PhD, Engineering, 2015, Rice University

 With the end of Dennard scaling and emergence of dark silicon, the bets are high on heterogeneous architectures to achieve both application performance and energy… (more)

Subjects/Keywords: programming models; heterogeneous architectures; OpenCL; C++; C

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APA (6th Edition):

Majeti, D. (2015). Portable Programming Models for Heterogeneous Platforms. (Doctoral Dissertation). Rice University. Retrieved from http://hdl.handle.net/1911/88096

Chicago Manual of Style (16th Edition):

Majeti, Deepak. “Portable Programming Models for Heterogeneous Platforms.” 2015. Doctoral Dissertation, Rice University. Accessed January 22, 2020. http://hdl.handle.net/1911/88096.

MLA Handbook (7th Edition):

Majeti, Deepak. “Portable Programming Models for Heterogeneous Platforms.” 2015. Web. 22 Jan 2020.

Vancouver:

Majeti D. Portable Programming Models for Heterogeneous Platforms. [Internet] [Doctoral dissertation]. Rice University; 2015. [cited 2020 Jan 22]. Available from: http://hdl.handle.net/1911/88096.

Council of Science Editors:

Majeti D. Portable Programming Models for Heterogeneous Platforms. [Doctoral Dissertation]. Rice University; 2015. Available from: http://hdl.handle.net/1911/88096


Rice University

19. Imam, Shams Mahmood. Cooperative Execution of Parallel Tasks with Synchronization Constraints.

Degree: PhD, Computer Science, 2015, Rice University

 The topic of this thesis is the effective execution of parallel applications on emerging multicore and manycore systems in the presence of modern synchronization and… (more)

Subjects/Keywords: Cooperative Techniques; Cooperative Runtime; Synchronization Constraints; Eureka Programming Model; Selector Model; Task Parallel Model; Actor Model; Habanero Java

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APA (6th Edition):

Imam, S. M. (2015). Cooperative Execution of Parallel Tasks with Synchronization Constraints. (Doctoral Dissertation). Rice University. Retrieved from http://hdl.handle.net/1911/88130

Chicago Manual of Style (16th Edition):

Imam, Shams Mahmood. “Cooperative Execution of Parallel Tasks with Synchronization Constraints.” 2015. Doctoral Dissertation, Rice University. Accessed January 22, 2020. http://hdl.handle.net/1911/88130.

MLA Handbook (7th Edition):

Imam, Shams Mahmood. “Cooperative Execution of Parallel Tasks with Synchronization Constraints.” 2015. Web. 22 Jan 2020.

Vancouver:

Imam SM. Cooperative Execution of Parallel Tasks with Synchronization Constraints. [Internet] [Doctoral dissertation]. Rice University; 2015. [cited 2020 Jan 22]. Available from: http://hdl.handle.net/1911/88130.

Council of Science Editors:

Imam SM. Cooperative Execution of Parallel Tasks with Synchronization Constraints. [Doctoral Dissertation]. Rice University; 2015. Available from: http://hdl.handle.net/1911/88130

20. Chabbi, Milind Mohan. Software Support for Efficient Use of Modern Computer Architectures.

Degree: PhD, Engineering, 2015, Rice University

 Parallelism is ubiquitous in modern computer architectures. Heterogeneity of CPU cores and deep memory hierarchies make modern architectures difficult to program efficiently. Achieving top performance… (more)

Subjects/Keywords: performance analysis; resource idleness; blame shifting; heterogeneous architectures; GPU; dynamic analysis; barrier elision; PGAS; NWChem; mutual exclusion; locks; MCS lock; hierarchical MCS lock; HMCS lock; Power7; Power8; SGI UV 1000; Adaptive HMCS; AHMCS; fast path; contention managament; hysteresis; hardware transactional memory; DeadSpy; dead writes; Pin; fine-grained monitoring; CCTLib; fine-grained execution monitoring

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APA (6th Edition):

Chabbi, M. M. (2015). Software Support for Efficient Use of Modern Computer Architectures. (Doctoral Dissertation). Rice University. Retrieved from http://hdl.handle.net/1911/87730

Chicago Manual of Style (16th Edition):

Chabbi, Milind Mohan. “Software Support for Efficient Use of Modern Computer Architectures.” 2015. Doctoral Dissertation, Rice University. Accessed January 22, 2020. http://hdl.handle.net/1911/87730.

MLA Handbook (7th Edition):

Chabbi, Milind Mohan. “Software Support for Efficient Use of Modern Computer Architectures.” 2015. Web. 22 Jan 2020.

Vancouver:

Chabbi MM. Software Support for Efficient Use of Modern Computer Architectures. [Internet] [Doctoral dissertation]. Rice University; 2015. [cited 2020 Jan 22]. Available from: http://hdl.handle.net/1911/87730.

Council of Science Editors:

Chabbi MM. Software Support for Efficient Use of Modern Computer Architectures. [Doctoral Dissertation]. Rice University; 2015. Available from: http://hdl.handle.net/1911/87730

21. Wei, Lai. Autotuning Memory-intensive Software for Node Architectures.

Degree: MS, Engineering, 2015, Rice University

 Today, scientific computing plays an important role in scientific research. People build supercomputers to support the computational needs of large-scale scientific applications. Achieving high performance… (more)

Subjects/Keywords: autotuning; memory-intensive software; tensor transposition; hardware performance counters; memory hierachy

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APA (6th Edition):

Wei, L. (2015). Autotuning Memory-intensive Software for Node Architectures. (Masters Thesis). Rice University. Retrieved from http://hdl.handle.net/1911/88422

Chicago Manual of Style (16th Edition):

Wei, Lai. “Autotuning Memory-intensive Software for Node Architectures.” 2015. Masters Thesis, Rice University. Accessed January 22, 2020. http://hdl.handle.net/1911/88422.

MLA Handbook (7th Edition):

Wei, Lai. “Autotuning Memory-intensive Software for Node Architectures.” 2015. Web. 22 Jan 2020.

Vancouver:

Wei L. Autotuning Memory-intensive Software for Node Architectures. [Internet] [Masters thesis]. Rice University; 2015. [cited 2020 Jan 22]. Available from: http://hdl.handle.net/1911/88422.

Council of Science Editors:

Wei L. Autotuning Memory-intensive Software for Node Architectures. [Masters Thesis]. Rice University; 2015. Available from: http://hdl.handle.net/1911/88422

22. Raman, Raghavan. Dynamic Data Race Detection for Structured Parallelism.

Degree: PhD, Engineering, 2013, Rice University

 With the advent of multicore processors and an increased emphasis on parallel computing, parallel programming has become a fundamental requirement for achieving available performance. Parallel… (more)

Subjects/Keywords: Structured parallelism; Data races; Program analysis

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APA (6th Edition):

Raman, R. (2013). Dynamic Data Race Detection for Structured Parallelism. (Doctoral Dissertation). Rice University. Retrieved from http://hdl.handle.net/1911/71681

Chicago Manual of Style (16th Edition):

Raman, Raghavan. “Dynamic Data Race Detection for Structured Parallelism.” 2013. Doctoral Dissertation, Rice University. Accessed January 22, 2020. http://hdl.handle.net/1911/71681.

MLA Handbook (7th Edition):

Raman, Raghavan. “Dynamic Data Race Detection for Structured Parallelism.” 2013. Web. 22 Jan 2020.

Vancouver:

Raman R. Dynamic Data Race Detection for Structured Parallelism. [Internet] [Doctoral dissertation]. Rice University; 2013. [cited 2020 Jan 22]. Available from: http://hdl.handle.net/1911/71681.

Council of Science Editors:

Raman R. Dynamic Data Race Detection for Structured Parallelism. [Doctoral Dissertation]. Rice University; 2013. Available from: http://hdl.handle.net/1911/71681

23. Grossman, Max. Programming Models and Runtimes for Heterogeneous Systems.

Degree: MS, Engineering, 2013, Rice University

 With the plateauing of processor frequencies and increase in energy consumption in computing, application developers are seeking new sources of performance acceleration. Heterogeneous platforms with… (more)

Subjects/Keywords: Heterogeneous; GPU; GPGPU; Programming models; Runtime; Multicore; Abstraction; Distributed; CUDA; OpenCL; Hadoop

…consider the CPUs and GPUs installed in the DAVINCI cluster at Rice University. The core… 

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APA (6th Edition):

Grossman, M. (2013). Programming Models and Runtimes for Heterogeneous Systems. (Masters Thesis). Rice University. Retrieved from http://hdl.handle.net/1911/71959

Chicago Manual of Style (16th Edition):

Grossman, Max. “Programming Models and Runtimes for Heterogeneous Systems.” 2013. Masters Thesis, Rice University. Accessed January 22, 2020. http://hdl.handle.net/1911/71959.

MLA Handbook (7th Edition):

Grossman, Max. “Programming Models and Runtimes for Heterogeneous Systems.” 2013. Web. 22 Jan 2020.

Vancouver:

Grossman M. Programming Models and Runtimes for Heterogeneous Systems. [Internet] [Masters thesis]. Rice University; 2013. [cited 2020 Jan 22]. Available from: http://hdl.handle.net/1911/71959.

Council of Science Editors:

Grossman M. Programming Models and Runtimes for Heterogeneous Systems. [Masters Thesis]. Rice University; 2013. Available from: http://hdl.handle.net/1911/71959

24. Hilburn, Guy. Studies of Low Luminosity Active Galactic Nuclei with Monte Carlo and Magnetohydrodynamic Simulations.

Degree: PhD, Natural Sciences, 2012, Rice University

 Results from several studies are presented which detail explorations of the physical and spectral properties of low luminosity active galactic nuclei. An initial Sagittarius A*… (more)

Subjects/Keywords: Active galactic nuclei; Accretion disk; Monte Carlo; Magnetohydrodynamics; Sagittarius A*; M87

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APA (6th Edition):

Hilburn, G. (2012). Studies of Low Luminosity Active Galactic Nuclei with Monte Carlo and Magnetohydrodynamic Simulations. (Doctoral Dissertation). Rice University. Retrieved from http://hdl.handle.net/1911/64694

Chicago Manual of Style (16th Edition):

Hilburn, Guy. “Studies of Low Luminosity Active Galactic Nuclei with Monte Carlo and Magnetohydrodynamic Simulations.” 2012. Doctoral Dissertation, Rice University. Accessed January 22, 2020. http://hdl.handle.net/1911/64694.

MLA Handbook (7th Edition):

Hilburn, Guy. “Studies of Low Luminosity Active Galactic Nuclei with Monte Carlo and Magnetohydrodynamic Simulations.” 2012. Web. 22 Jan 2020.

Vancouver:

Hilburn G. Studies of Low Luminosity Active Galactic Nuclei with Monte Carlo and Magnetohydrodynamic Simulations. [Internet] [Doctoral dissertation]. Rice University; 2012. [cited 2020 Jan 22]. Available from: http://hdl.handle.net/1911/64694.

Council of Science Editors:

Hilburn G. Studies of Low Luminosity Active Galactic Nuclei with Monte Carlo and Magnetohydrodynamic Simulations. [Doctoral Dissertation]. Rice University; 2012. Available from: http://hdl.handle.net/1911/64694


Rice University

25. Marin, Gabriel. Application insight through performance modeling.

Degree: PhD, Engineering, 2008, Rice University

 Tuning the performance of applications requires understanding the interactions between code and target architecture. Hardware counters, present in all modern processors, can identify possible causes… (more)

Subjects/Keywords: Computer science

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APA (6th Edition):

Marin, G. (2008). Application insight through performance modeling. (Doctoral Dissertation). Rice University. Retrieved from http://hdl.handle.net/1911/22189

Chicago Manual of Style (16th Edition):

Marin, Gabriel. “Application insight through performance modeling.” 2008. Doctoral Dissertation, Rice University. Accessed January 22, 2020. http://hdl.handle.net/1911/22189.

MLA Handbook (7th Edition):

Marin, Gabriel. “Application insight through performance modeling.” 2008. Web. 22 Jan 2020.

Vancouver:

Marin G. Application insight through performance modeling. [Internet] [Doctoral dissertation]. Rice University; 2008. [cited 2020 Jan 22]. Available from: http://hdl.handle.net/1911/22189.

Council of Science Editors:

Marin G. Application insight through performance modeling. [Doctoral Dissertation]. Rice University; 2008. Available from: http://hdl.handle.net/1911/22189


Rice University

26. Tallent, Nathan Russell. Binary analysis for attribution and interpretation of performance measurements on fully-optimized code.

Degree: MA, Engineering, 2007, Rice University

 Modern scientific codes frequently employ sophisticated object-oriented design. In these codes, deep loop nests are often spread across multiple routines. To achieve high performance, such… (more)

Subjects/Keywords: Computer science

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APA (6th Edition):

Tallent, N. R. (2007). Binary analysis for attribution and interpretation of performance measurements on fully-optimized code. (Masters Thesis). Rice University. Retrieved from http://hdl.handle.net/1911/20542

Chicago Manual of Style (16th Edition):

Tallent, Nathan Russell. “Binary analysis for attribution and interpretation of performance measurements on fully-optimized code.” 2007. Masters Thesis, Rice University. Accessed January 22, 2020. http://hdl.handle.net/1911/20542.

MLA Handbook (7th Edition):

Tallent, Nathan Russell. “Binary analysis for attribution and interpretation of performance measurements on fully-optimized code.” 2007. Web. 22 Jan 2020.

Vancouver:

Tallent NR. Binary analysis for attribution and interpretation of performance measurements on fully-optimized code. [Internet] [Masters thesis]. Rice University; 2007. [cited 2020 Jan 22]. Available from: http://hdl.handle.net/1911/20542.

Council of Science Editors:

Tallent NR. Binary analysis for attribution and interpretation of performance measurements on fully-optimized code. [Masters Thesis]. Rice University; 2007. Available from: http://hdl.handle.net/1911/20542


Rice University

27. Bordelon, Adam. Developing a scalable, extensible parallel performance analysis toolkit.

Degree: MA, Engineering, 2007, Rice University

 Modern parallel systems and applications are constantly increasing in scale and complexity, and consequently good parallel performance is impossible to achieve without the help of… (more)

Subjects/Keywords: Computer science

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APA (6th Edition):

Bordelon, A. (2007). Developing a scalable, extensible parallel performance analysis toolkit. (Masters Thesis). Rice University. Retrieved from http://hdl.handle.net/1911/20491

Chicago Manual of Style (16th Edition):

Bordelon, Adam. “Developing a scalable, extensible parallel performance analysis toolkit.” 2007. Masters Thesis, Rice University. Accessed January 22, 2020. http://hdl.handle.net/1911/20491.

MLA Handbook (7th Edition):

Bordelon, Adam. “Developing a scalable, extensible parallel performance analysis toolkit.” 2007. Web. 22 Jan 2020.

Vancouver:

Bordelon A. Developing a scalable, extensible parallel performance analysis toolkit. [Internet] [Masters thesis]. Rice University; 2007. [cited 2020 Jan 22]. Available from: http://hdl.handle.net/1911/20491.

Council of Science Editors:

Bordelon A. Developing a scalable, extensible parallel performance analysis toolkit. [Masters Thesis]. Rice University; 2007. Available from: http://hdl.handle.net/1911/20491


Rice University

28. Coarfa, Cristian. Portable high performance and scalability of partitioned global address space languages.

Degree: PhD, Engineering, 2007, Rice University

 Large scale parallel simulations are fundamental tools for engineers and scientists. Consequently, it is critical to develop both programming models and tools that enhance development… (more)

Subjects/Keywords: Computer science

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APA (6th Edition):

Coarfa, C. (2007). Portable high performance and scalability of partitioned global address space languages. (Doctoral Dissertation). Rice University. Retrieved from http://hdl.handle.net/1911/20592

Chicago Manual of Style (16th Edition):

Coarfa, Cristian. “Portable high performance and scalability of partitioned global address space languages.” 2007. Doctoral Dissertation, Rice University. Accessed January 22, 2020. http://hdl.handle.net/1911/20592.

MLA Handbook (7th Edition):

Coarfa, Cristian. “Portable high performance and scalability of partitioned global address space languages.” 2007. Web. 22 Jan 2020.

Vancouver:

Coarfa C. Portable high performance and scalability of partitioned global address space languages. [Internet] [Doctoral dissertation]. Rice University; 2007. [cited 2020 Jan 22]. Available from: http://hdl.handle.net/1911/20592.

Council of Science Editors:

Coarfa C. Portable high performance and scalability of partitioned global address space languages. [Doctoral Dissertation]. Rice University; 2007. Available from: http://hdl.handle.net/1911/20592


Rice University

29. Lu, Bo. Compiling reductions in data parallel programs for distributed memory multiprocessors.

Degree: MS, Engineering, 1998, Rice University

 Reduction recognition and optimization are crucial techniques in parallelizing compilers. They are used to detect the recurrences in a program and transform the originally sequential… (more)

Subjects/Keywords: Computer science

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APA (6th Edition):

Lu, B. (1998). Compiling reductions in data parallel programs for distributed memory multiprocessors. (Masters Thesis). Rice University. Retrieved from http://hdl.handle.net/1911/17397

Chicago Manual of Style (16th Edition):

Lu, Bo. “Compiling reductions in data parallel programs for distributed memory multiprocessors.” 1998. Masters Thesis, Rice University. Accessed January 22, 2020. http://hdl.handle.net/1911/17397.

MLA Handbook (7th Edition):

Lu, Bo. “Compiling reductions in data parallel programs for distributed memory multiprocessors.” 1998. Web. 22 Jan 2020.

Vancouver:

Lu B. Compiling reductions in data parallel programs for distributed memory multiprocessors. [Internet] [Masters thesis]. Rice University; 1998. [cited 2020 Jan 22]. Available from: http://hdl.handle.net/1911/17397.

Council of Science Editors:

Lu B. Compiling reductions in data parallel programs for distributed memory multiprocessors. [Masters Thesis]. Rice University; 1998. Available from: http://hdl.handle.net/1911/17397


Rice University

30. Froyd, Nathan. Efficient call path profiles on unmodified, optimized code.

Degree: MS, Engineering, 2005, Rice University

 Identifying performance bottlenecks and their associated calling contexts is critical for tuning high-performance applications. This thesis presents a new approach to measuring resource utilization and… (more)

Subjects/Keywords: Computer science

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APA (6th Edition):

Froyd, N. (2005). Efficient call path profiles on unmodified, optimized code. (Masters Thesis). Rice University. Retrieved from http://hdl.handle.net/1911/17780

Chicago Manual of Style (16th Edition):

Froyd, Nathan. “Efficient call path profiles on unmodified, optimized code.” 2005. Masters Thesis, Rice University. Accessed January 22, 2020. http://hdl.handle.net/1911/17780.

MLA Handbook (7th Edition):

Froyd, Nathan. “Efficient call path profiles on unmodified, optimized code.” 2005. Web. 22 Jan 2020.

Vancouver:

Froyd N. Efficient call path profiles on unmodified, optimized code. [Internet] [Masters thesis]. Rice University; 2005. [cited 2020 Jan 22]. Available from: http://hdl.handle.net/1911/17780.

Council of Science Editors:

Froyd N. Efficient call path profiles on unmodified, optimized code. [Masters Thesis]. Rice University; 2005. Available from: http://hdl.handle.net/1911/17780

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