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You searched for +publisher:"Penn State University" +contributor:("Vijaykrishnan Narayanan, Committee Member"). Showing records 1 – 30 of 42 total matches.

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Penn State University

1. Park, Jun Hyuk. IMPROVED TIQ FLASH ADC TRANSISTOR SIZING ALGORITHMS TO REDUCE LINEARITY ERRORS.

Degree: 2017, Penn State University

 Integral nonlinearity and differential nonlinearity are the two main performance parameters for a high speed flash analog-to-digital converter, which determine the accuracy of the converter.… (more)

Subjects/Keywords: TIQ Flash ADC; TIQ Voltage Comparator; Nonlinearity; DNL; INL; Process Variation

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Park, J. H. (2017). IMPROVED TIQ FLASH ADC TRANSISTOR SIZING ALGORITHMS TO REDUCE LINEARITY ERRORS. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/14332jzp152

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Park, Jun Hyuk. “IMPROVED TIQ FLASH ADC TRANSISTOR SIZING ALGORITHMS TO REDUCE LINEARITY ERRORS.” 2017. Thesis, Penn State University. Accessed December 04, 2020. https://submit-etda.libraries.psu.edu/catalog/14332jzp152.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Park, Jun Hyuk. “IMPROVED TIQ FLASH ADC TRANSISTOR SIZING ALGORITHMS TO REDUCE LINEARITY ERRORS.” 2017. Web. 04 Dec 2020.

Vancouver:

Park JH. IMPROVED TIQ FLASH ADC TRANSISTOR SIZING ALGORITHMS TO REDUCE LINEARITY ERRORS. [Internet] [Thesis]. Penn State University; 2017. [cited 2020 Dec 04]. Available from: https://submit-etda.libraries.psu.edu/catalog/14332jzp152.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Park JH. IMPROVED TIQ FLASH ADC TRANSISTOR SIZING ALGORITHMS TO REDUCE LINEARITY ERRORS. [Thesis]. Penn State University; 2017. Available from: https://submit-etda.libraries.psu.edu/catalog/14332jzp152

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

2. Mohapatra, Jagruti. PREDICTION AND ASSESSMENT OF AMBIENT ENERGY SIGNALS FOR ENERGY HARVESTING SYSTEMS.

Degree: 2016, Penn State University

 Prediction of Wi-Fi and cellular signals is a challenge as the signals fluctuate with time. There is no definite trend or seasonality associated with the… (more)

Subjects/Keywords: Prediction; energy harvesting; Non-volatile processors; backup

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APA (6th Edition):

Mohapatra, J. (2016). PREDICTION AND ASSESSMENT OF AMBIENT ENERGY SIGNALS FOR ENERGY HARVESTING SYSTEMS. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/4f16c2806

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mohapatra, Jagruti. “PREDICTION AND ASSESSMENT OF AMBIENT ENERGY SIGNALS FOR ENERGY HARVESTING SYSTEMS.” 2016. Thesis, Penn State University. Accessed December 04, 2020. https://submit-etda.libraries.psu.edu/catalog/4f16c2806.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mohapatra, Jagruti. “PREDICTION AND ASSESSMENT OF AMBIENT ENERGY SIGNALS FOR ENERGY HARVESTING SYSTEMS.” 2016. Web. 04 Dec 2020.

Vancouver:

Mohapatra J. PREDICTION AND ASSESSMENT OF AMBIENT ENERGY SIGNALS FOR ENERGY HARVESTING SYSTEMS. [Internet] [Thesis]. Penn State University; 2016. [cited 2020 Dec 04]. Available from: https://submit-etda.libraries.psu.edu/catalog/4f16c2806.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mohapatra J. PREDICTION AND ASSESSMENT OF AMBIENT ENERGY SIGNALS FOR ENERGY HARVESTING SYSTEMS. [Thesis]. Penn State University; 2016. Available from: https://submit-etda.libraries.psu.edu/catalog/4f16c2806

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

3. Mohata, Dheeraj Kumar. Arsendie-Antmonide Tunnel Transistors for Low Power Logic Applications.

Degree: 2013, Penn State University

 Aggressive supply voltage (VCC) scaling of future transistors without increasing the off-state leakage while maintaining performance remains an important challenge. Hetero-junction Tunnel FETs (HTFETs) with… (more)

Subjects/Keywords: Transistor; TFET; Arsenide; Antimonide; Hetero-junction; Fabrication; low power; steep switching; supply voltage

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APA (6th Edition):

Mohata, D. K. (2013). Arsendie-Antmonide Tunnel Transistors for Low Power Logic Applications. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/16456

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mohata, Dheeraj Kumar. “Arsendie-Antmonide Tunnel Transistors for Low Power Logic Applications.” 2013. Thesis, Penn State University. Accessed December 04, 2020. https://submit-etda.libraries.psu.edu/catalog/16456.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mohata, Dheeraj Kumar. “Arsendie-Antmonide Tunnel Transistors for Low Power Logic Applications.” 2013. Web. 04 Dec 2020.

Vancouver:

Mohata DK. Arsendie-Antmonide Tunnel Transistors for Low Power Logic Applications. [Internet] [Thesis]. Penn State University; 2013. [cited 2020 Dec 04]. Available from: https://submit-etda.libraries.psu.edu/catalog/16456.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mohata DK. Arsendie-Antmonide Tunnel Transistors for Low Power Logic Applications. [Thesis]. Penn State University; 2013. Available from: https://submit-etda.libraries.psu.edu/catalog/16456

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

4. Agrawal, Nidhi. Variation Study on Advanced Cmos Systems for Low Voltage Applications.

Degree: 2015, Penn State University

 One of the key challenges in scaling beyond 10nm technology node is device-to-device variation. Variation in device performance, mainly threshold voltage (VT) inhibits supply voltage… (more)

Subjects/Keywords: FinFET; TFET; Line Edge Roughness (LER); Line Width Roughness (LWR); SRAM; Rean Static Noise Margin (RSNM); NBTI; PBTI

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Agrawal, N. (2015). Variation Study on Advanced Cmos Systems for Low Voltage Applications. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/26674

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Agrawal, Nidhi. “Variation Study on Advanced Cmos Systems for Low Voltage Applications.” 2015. Thesis, Penn State University. Accessed December 04, 2020. https://submit-etda.libraries.psu.edu/catalog/26674.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Agrawal, Nidhi. “Variation Study on Advanced Cmos Systems for Low Voltage Applications.” 2015. Web. 04 Dec 2020.

Vancouver:

Agrawal N. Variation Study on Advanced Cmos Systems for Low Voltage Applications. [Internet] [Thesis]. Penn State University; 2015. [cited 2020 Dec 04]. Available from: https://submit-etda.libraries.psu.edu/catalog/26674.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Agrawal N. Variation Study on Advanced Cmos Systems for Low Voltage Applications. [Thesis]. Penn State University; 2015. Available from: https://submit-etda.libraries.psu.edu/catalog/26674

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

5. Zou, Qiaosha. design methodologies of three-dimensional integrated circuits (3D ICs).

Degree: 2015, Penn State University

 The continuous technology scaling results in the growing delay gap between transistors and interconnects because of the significant increase inparasitics. Moreover, the increased integration density… (more)

Subjects/Keywords: Integrated circuits; design methodologies; three-dimensional circuits; cost-aware designs; reliability-aware designs

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zou, Q. (2015). design methodologies of three-dimensional integrated circuits (3D ICs). (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/24781

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Zou, Qiaosha. “design methodologies of three-dimensional integrated circuits (3D ICs).” 2015. Thesis, Penn State University. Accessed December 04, 2020. https://submit-etda.libraries.psu.edu/catalog/24781.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Zou, Qiaosha. “design methodologies of three-dimensional integrated circuits (3D ICs).” 2015. Web. 04 Dec 2020.

Vancouver:

Zou Q. design methodologies of three-dimensional integrated circuits (3D ICs). [Internet] [Thesis]. Penn State University; 2015. [cited 2020 Dec 04]. Available from: https://submit-etda.libraries.psu.edu/catalog/24781.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zou Q. design methodologies of three-dimensional integrated circuits (3D ICs). [Thesis]. Penn State University; 2015. Available from: https://submit-etda.libraries.psu.edu/catalog/24781

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

6. Poremba, Matthew Raymond. Architecting Byte-addressable Non-volatile Memories for Main Memory.

Degree: 2015, Penn State University

 New breakthroughs in memory technology in recent years has lead to increased research efforts in so-called byte-addressable non-volatile memories (NVM). As a result, questions of… (more)

Subjects/Keywords: Computer Memory; Non-Volatile Memory; DRAM; Memory Scheduling; Memory Modeling; Memory Simulation

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Poremba, M. R. (2015). Architecting Byte-addressable Non-volatile Memories for Main Memory. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/25034

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Poremba, Matthew Raymond. “Architecting Byte-addressable Non-volatile Memories for Main Memory.” 2015. Thesis, Penn State University. Accessed December 04, 2020. https://submit-etda.libraries.psu.edu/catalog/25034.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Poremba, Matthew Raymond. “Architecting Byte-addressable Non-volatile Memories for Main Memory.” 2015. Web. 04 Dec 2020.

Vancouver:

Poremba MR. Architecting Byte-addressable Non-volatile Memories for Main Memory. [Internet] [Thesis]. Penn State University; 2015. [cited 2020 Dec 04]. Available from: https://submit-etda.libraries.psu.edu/catalog/25034.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Poremba MR. Architecting Byte-addressable Non-volatile Memories for Main Memory. [Thesis]. Penn State University; 2015. Available from: https://submit-etda.libraries.psu.edu/catalog/25034

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

7. Xie, Jing. Three Dimensional Integrated Circuit Design and Test.

Degree: 2015, Penn State University

 The emerging three-dimensional integrated circuits (3D ICs) is one of the most promising solutions for future IC designs. 3D stacking enables much higher memory bandwidth… (more)

Subjects/Keywords: VLSI; Three Dimensional Integrated Circuit; Testing; Circuit Design; Low Power; High Performance

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Xie, J. (2015). Three Dimensional Integrated Circuit Design and Test. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/26281

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Xie, Jing. “Three Dimensional Integrated Circuit Design and Test.” 2015. Thesis, Penn State University. Accessed December 04, 2020. https://submit-etda.libraries.psu.edu/catalog/26281.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Xie, Jing. “Three Dimensional Integrated Circuit Design and Test.” 2015. Web. 04 Dec 2020.

Vancouver:

Xie J. Three Dimensional Integrated Circuit Design and Test. [Internet] [Thesis]. Penn State University; 2015. [cited 2020 Dec 04]. Available from: https://submit-etda.libraries.psu.edu/catalog/26281.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Xie J. Three Dimensional Integrated Circuit Design and Test. [Thesis]. Penn State University; 2015. Available from: https://submit-etda.libraries.psu.edu/catalog/26281

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

8. Sahin, Dagistan. Tracing footprints of Environmental events in tree ring chemistry using Neutron Activation Analysis .

Degree: 2012, Penn State University

 The aim of this study is to identify environmental effects on tree-ring chemistry. It is known that industrial pollution, volcanic eruptions, dust storms, acid rain… (more)

Subjects/Keywords: neutron activation analysis; NAA; kzero; k0; Westcott formalism; Geant4; MCNP; Monte Carlo; tree ring; Dendrochemistry; climate

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Sahin, D. (2012). Tracing footprints of Environmental events in tree ring chemistry using Neutron Activation Analysis . (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/16214

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sahin, Dagistan. “Tracing footprints of Environmental events in tree ring chemistry using Neutron Activation Analysis .” 2012. Thesis, Penn State University. Accessed December 04, 2020. https://submit-etda.libraries.psu.edu/catalog/16214.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sahin, Dagistan. “Tracing footprints of Environmental events in tree ring chemistry using Neutron Activation Analysis .” 2012. Web. 04 Dec 2020.

Vancouver:

Sahin D. Tracing footprints of Environmental events in tree ring chemistry using Neutron Activation Analysis . [Internet] [Thesis]. Penn State University; 2012. [cited 2020 Dec 04]. Available from: https://submit-etda.libraries.psu.edu/catalog/16214.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sahin D. Tracing footprints of Environmental events in tree ring chemistry using Neutron Activation Analysis . [Thesis]. Penn State University; 2012. Available from: https://submit-etda.libraries.psu.edu/catalog/16214

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

9. Sun, Guangyu. EXPLORING THE MEMORY HIERARCHY DESIGN WITH EMERGING MEMORY TECHNOLOGIES.

Degree: 2011, Penn State University

 The performance of a processor relies on two important resources: the micro- processor’s computing ability of processing data and the memory hierarchy that stores data… (more)

Subjects/Keywords: memory hierarchy; emerging memory; STT-RAM; PCM; performance; power; reliability

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APA (6th Edition):

Sun, G. (2011). EXPLORING THE MEMORY HIERARCHY DESIGN WITH EMERGING MEMORY TECHNOLOGIES. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/12460

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sun, Guangyu. “EXPLORING THE MEMORY HIERARCHY DESIGN WITH EMERGING MEMORY TECHNOLOGIES.” 2011. Thesis, Penn State University. Accessed December 04, 2020. https://submit-etda.libraries.psu.edu/catalog/12460.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sun, Guangyu. “EXPLORING THE MEMORY HIERARCHY DESIGN WITH EMERGING MEMORY TECHNOLOGIES.” 2011. Web. 04 Dec 2020.

Vancouver:

Sun G. EXPLORING THE MEMORY HIERARCHY DESIGN WITH EMERGING MEMORY TECHNOLOGIES. [Internet] [Thesis]. Penn State University; 2011. [cited 2020 Dec 04]. Available from: https://submit-etda.libraries.psu.edu/catalog/12460.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sun G. EXPLORING THE MEMORY HIERARCHY DESIGN WITH EMERGING MEMORY TECHNOLOGIES. [Thesis]. Penn State University; 2011. Available from: https://submit-etda.libraries.psu.edu/catalog/12460

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

10. Dong, Xiangyu. Modeling and Leveraging Emerging Non-Volatile Memories for Future Computer Designs .

Degree: 2011, Penn State University

 Energy efficiency has become a major constraint in the design of computing systems today. As CMOS continues scaling down, traditional CMOS scaling theory requires to… (more)

Subjects/Keywords: application; architecture; circuit; non-volatile memory; STTRAM; PCRAM; ReRAM

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Dong, X. (2011). Modeling and Leveraging Emerging Non-Volatile Memories for Future Computer Designs . (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/12462

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Dong, Xiangyu. “Modeling and Leveraging Emerging Non-Volatile Memories for Future Computer Designs .” 2011. Thesis, Penn State University. Accessed December 04, 2020. https://submit-etda.libraries.psu.edu/catalog/12462.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Dong, Xiangyu. “Modeling and Leveraging Emerging Non-Volatile Memories for Future Computer Designs .” 2011. Web. 04 Dec 2020.

Vancouver:

Dong X. Modeling and Leveraging Emerging Non-Volatile Memories for Future Computer Designs . [Internet] [Thesis]. Penn State University; 2011. [cited 2020 Dec 04]. Available from: https://submit-etda.libraries.psu.edu/catalog/12462.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Dong X. Modeling and Leveraging Emerging Non-Volatile Memories for Future Computer Designs . [Thesis]. Penn State University; 2011. Available from: https://submit-etda.libraries.psu.edu/catalog/12462

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

11. Chen, Yibo. VARIATION-AWARE BEHAVIORAL SYNTHESIS FOR NANOMETER VLSI CHIPS .

Degree: 2011, Penn State University

 Variability in circuit delay and power dissipation is one of the most critical challenges in nanometer VLSI era. Traditionally, performance/power variations are handled by a… (more)

Subjects/Keywords: High-Level Synthesis; Behavioral Synthesis; ESL

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chen, Y. (2011). VARIATION-AWARE BEHAVIORAL SYNTHESIS FOR NANOMETER VLSI CHIPS . (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/12416

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chen, Yibo. “VARIATION-AWARE BEHAVIORAL SYNTHESIS FOR NANOMETER VLSI CHIPS .” 2011. Thesis, Penn State University. Accessed December 04, 2020. https://submit-etda.libraries.psu.edu/catalog/12416.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chen, Yibo. “VARIATION-AWARE BEHAVIORAL SYNTHESIS FOR NANOMETER VLSI CHIPS .” 2011. Web. 04 Dec 2020.

Vancouver:

Chen Y. VARIATION-AWARE BEHAVIORAL SYNTHESIS FOR NANOMETER VLSI CHIPS . [Internet] [Thesis]. Penn State University; 2011. [cited 2020 Dec 04]. Available from: https://submit-etda.libraries.psu.edu/catalog/12416.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen Y. VARIATION-AWARE BEHAVIORAL SYNTHESIS FOR NANOMETER VLSI CHIPS . [Thesis]. Penn State University; 2011. Available from: https://submit-etda.libraries.psu.edu/catalog/12416

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

12. Ouyang, Jin. Architecting On-Chip Interconnection Network for Future Many-Core Chip-Multiprocessors.

Degree: 2012, Penn State University

 The rapid process scaling trend of the silicon industry has provided the resources to concurrently execute multiple instruction sequences on the same chip, a capability… (more)

Subjects/Keywords: Chip-Multiprocessors; Network-on-Chip; Computer Architecture

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ouyang, J. (2012). Architecting On-Chip Interconnection Network for Future Many-Core Chip-Multiprocessors. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/13160

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ouyang, Jin. “Architecting On-Chip Interconnection Network for Future Many-Core Chip-Multiprocessors.” 2012. Thesis, Penn State University. Accessed December 04, 2020. https://submit-etda.libraries.psu.edu/catalog/13160.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ouyang, Jin. “Architecting On-Chip Interconnection Network for Future Many-Core Chip-Multiprocessors.” 2012. Web. 04 Dec 2020.

Vancouver:

Ouyang J. Architecting On-Chip Interconnection Network for Future Many-Core Chip-Multiprocessors. [Internet] [Thesis]. Penn State University; 2012. [cited 2020 Dec 04]. Available from: https://submit-etda.libraries.psu.edu/catalog/13160.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ouyang J. Architecting On-Chip Interconnection Network for Future Many-Core Chip-Multiprocessors. [Thesis]. Penn State University; 2012. Available from: https://submit-etda.libraries.psu.edu/catalog/13160

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

13. Cheng, Hsiang-Yun. EXPLOITING AND ACCOMMODATING ASYMMETRIES IN MEMORY TO ENABLE EFFICIENT MULTI-CORE SYSTEMS.

Degree: 2016, Penn State University

 The memory hierarchy, including on-chip caches and off-chip main memory, is becoming the performance and energy bottleneck in multi-core systems, and architectural techniques are needed… (more)

Subjects/Keywords: Memory systems; Asymmetric access; Energy efficiency; Cache; Memory request scheduling; Power management; Non-volatile memory

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Cheng, H. (2016). EXPLOITING AND ACCOMMODATING ASYMMETRIES IN MEMORY TO ENABLE EFFICIENT MULTI-CORE SYSTEMS. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/0c483j36g

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Cheng, Hsiang-Yun. “EXPLOITING AND ACCOMMODATING ASYMMETRIES IN MEMORY TO ENABLE EFFICIENT MULTI-CORE SYSTEMS.” 2016. Thesis, Penn State University. Accessed December 04, 2020. https://submit-etda.libraries.psu.edu/catalog/0c483j36g.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Cheng, Hsiang-Yun. “EXPLOITING AND ACCOMMODATING ASYMMETRIES IN MEMORY TO ENABLE EFFICIENT MULTI-CORE SYSTEMS.” 2016. Web. 04 Dec 2020.

Vancouver:

Cheng H. EXPLOITING AND ACCOMMODATING ASYMMETRIES IN MEMORY TO ENABLE EFFICIENT MULTI-CORE SYSTEMS. [Internet] [Thesis]. Penn State University; 2016. [cited 2020 Dec 04]. Available from: https://submit-etda.libraries.psu.edu/catalog/0c483j36g.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Cheng H. EXPLOITING AND ACCOMMODATING ASYMMETRIES IN MEMORY TO ENABLE EFFICIENT MULTI-CORE SYSTEMS. [Thesis]. Penn State University; 2016. Available from: https://submit-etda.libraries.psu.edu/catalog/0c483j36g

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

14. Radhakrishnan, Chandrasekhar. FAULT TOLERANT SIGNAL PROCESSING FOR VLSI CIRCUITS.

Degree: 2011, Penn State University

 To achieve higher speed, higher density, and lower power dissipation CMOS VLSI circuits continue to be scaled down in terms of feature sizes and power… (more)

Subjects/Keywords: Discrete-time correlation; discrete-time convolution; Fermat Number Transforms; Discrete Fourier Transforms; Transient errors; Soft errors; Hardware faults; Fault tolerant signal processing; Fault tolerant transform adaptive filtering; adaptive filtering; Residue Number Systems (RNS); Modulus Replication Residue Number System (MRRNS); Arithmetic Fault Tolerance

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Radhakrishnan, C. (2011). FAULT TOLERANT SIGNAL PROCESSING FOR VLSI CIRCUITS. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/11663

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Radhakrishnan, Chandrasekhar. “FAULT TOLERANT SIGNAL PROCESSING FOR VLSI CIRCUITS.” 2011. Thesis, Penn State University. Accessed December 04, 2020. https://submit-etda.libraries.psu.edu/catalog/11663.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Radhakrishnan, Chandrasekhar. “FAULT TOLERANT SIGNAL PROCESSING FOR VLSI CIRCUITS.” 2011. Web. 04 Dec 2020.

Vancouver:

Radhakrishnan C. FAULT TOLERANT SIGNAL PROCESSING FOR VLSI CIRCUITS. [Internet] [Thesis]. Penn State University; 2011. [cited 2020 Dec 04]. Available from: https://submit-etda.libraries.psu.edu/catalog/11663.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Radhakrishnan C. FAULT TOLERANT SIGNAL PROCESSING FOR VLSI CIRCUITS. [Thesis]. Penn State University; 2011. Available from: https://submit-etda.libraries.psu.edu/catalog/11663

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

15. Jean, Evens. Sensor Network Interoperability and Reconfiguration through Mobile Agents .

Degree: 2011, Penn State University

 Sensor networks generally consist of small devices deployed in an area to perform a task through coordination and communication. The current paradigm in sensor network… (more)

Subjects/Keywords: mobile agents; sensor network; FPGA

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APA (6th Edition):

Jean, E. (2011). Sensor Network Interoperability and Reconfiguration through Mobile Agents . (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/10247

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Jean, Evens. “Sensor Network Interoperability and Reconfiguration through Mobile Agents .” 2011. Thesis, Penn State University. Accessed December 04, 2020. https://submit-etda.libraries.psu.edu/catalog/10247.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Jean, Evens. “Sensor Network Interoperability and Reconfiguration through Mobile Agents .” 2011. Web. 04 Dec 2020.

Vancouver:

Jean E. Sensor Network Interoperability and Reconfiguration through Mobile Agents . [Internet] [Thesis]. Penn State University; 2011. [cited 2020 Dec 04]. Available from: https://submit-etda.libraries.psu.edu/catalog/10247.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Jean E. Sensor Network Interoperability and Reconfiguration through Mobile Agents . [Thesis]. Penn State University; 2011. Available from: https://submit-etda.libraries.psu.edu/catalog/10247

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

16. Mishra, Asit Kumar. Design and Analysis of Heterogeneous Networks for Chip-Multiprocessors.

Degree: 2011, Penn State University

 Rarely has there been as challenging and exciting a time for research in computer architecture as now. While, the proverbial Moore’s law has consistently helped… (more)

Subjects/Keywords: NoC; network-on-chip; router; heterogeneous NoC; heterogeneous networks; multicore; CMP; STT-RAM

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APA (6th Edition):

Mishra, A. K. (2011). Design and Analysis of Heterogeneous Networks for Chip-Multiprocessors. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/11995

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mishra, Asit Kumar. “Design and Analysis of Heterogeneous Networks for Chip-Multiprocessors.” 2011. Thesis, Penn State University. Accessed December 04, 2020. https://submit-etda.libraries.psu.edu/catalog/11995.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mishra, Asit Kumar. “Design and Analysis of Heterogeneous Networks for Chip-Multiprocessors.” 2011. Web. 04 Dec 2020.

Vancouver:

Mishra AK. Design and Analysis of Heterogeneous Networks for Chip-Multiprocessors. [Internet] [Thesis]. Penn State University; 2011. [cited 2020 Dec 04]. Available from: https://submit-etda.libraries.psu.edu/catalog/11995.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mishra AK. Design and Analysis of Heterogeneous Networks for Chip-Multiprocessors. [Thesis]. Penn State University; 2011. Available from: https://submit-etda.libraries.psu.edu/catalog/11995

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

17. Aliyaru Kunju, Ashkar Ali. Design Fabrication and Characterization of Antimonide MOS Transistors.

Degree: 2012, Penn State University

 Future transistor scaling will require enhancement in device electrostatics (multigate), channel transport enhancement (beyond strained Silicon) and reduction in parasitics (contact, junction engineering etc.). Due… (more)

Subjects/Keywords: MOS; Low Power; Antimonide; MOSFET; High-k Dielectric; Quantum Well; CV

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APA (6th Edition):

Aliyaru Kunju, A. A. (2012). Design Fabrication and Characterization of Antimonide MOS Transistors. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/14777

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Aliyaru Kunju, Ashkar Ali. “Design Fabrication and Characterization of Antimonide MOS Transistors.” 2012. Thesis, Penn State University. Accessed December 04, 2020. https://submit-etda.libraries.psu.edu/catalog/14777.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Aliyaru Kunju, Ashkar Ali. “Design Fabrication and Characterization of Antimonide MOS Transistors.” 2012. Web. 04 Dec 2020.

Vancouver:

Aliyaru Kunju AA. Design Fabrication and Characterization of Antimonide MOS Transistors. [Internet] [Thesis]. Penn State University; 2012. [cited 2020 Dec 04]. Available from: https://submit-etda.libraries.psu.edu/catalog/14777.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Aliyaru Kunju AA. Design Fabrication and Characterization of Antimonide MOS Transistors. [Thesis]. Penn State University; 2012. Available from: https://submit-etda.libraries.psu.edu/catalog/14777

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

18. Liu, Lu. Classical And Coulomb Blockade Iii-v Multi-gate Quantum Well Field Effect Transistors For Ultra Low Power Logic Applications.

Degree: 2013, Penn State University

 Low power logic application requires aggressive scaling of supply voltage while maintaining performance. Recently, III-V material systems such as InGaAs and InSb have attracted lots… (more)

Subjects/Keywords: multi-gate; quantum well FET; single electron; Coulomb blockade; non-volatile; low power

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APA (6th Edition):

Liu, L. (2013). Classical And Coulomb Blockade Iii-v Multi-gate Quantum Well Field Effect Transistors For Ultra Low Power Logic Applications. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/19991

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Liu, Lu. “Classical And Coulomb Blockade Iii-v Multi-gate Quantum Well Field Effect Transistors For Ultra Low Power Logic Applications.” 2013. Thesis, Penn State University. Accessed December 04, 2020. https://submit-etda.libraries.psu.edu/catalog/19991.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Liu, Lu. “Classical And Coulomb Blockade Iii-v Multi-gate Quantum Well Field Effect Transistors For Ultra Low Power Logic Applications.” 2013. Web. 04 Dec 2020.

Vancouver:

Liu L. Classical And Coulomb Blockade Iii-v Multi-gate Quantum Well Field Effect Transistors For Ultra Low Power Logic Applications. [Internet] [Thesis]. Penn State University; 2013. [cited 2020 Dec 04]. Available from: https://submit-etda.libraries.psu.edu/catalog/19991.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Liu L. Classical And Coulomb Blockade Iii-v Multi-gate Quantum Well Field Effect Transistors For Ultra Low Power Logic Applications. [Thesis]. Penn State University; 2013. Available from: https://submit-etda.libraries.psu.edu/catalog/19991

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

19. Zhang, Tao. A Study of DRAM Optimization to Break the Memory Wall.

Degree: 2014, Penn State University

 The well-known “Memory Wall” has been raised in 1990s. At that time, the researchers noticed the diverging exponential increase in the performance of processor and… (more)

Subjects/Keywords: DRAM; Memory Wall; 3D-stacked DRAM; Wide IO; Activation; Precharge; Refresh; Sub-array Level Parallelism

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APA (6th Edition):

Zhang, T. (2014). A Study of DRAM Optimization to Break the Memory Wall. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/21517

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Zhang, Tao. “A Study of DRAM Optimization to Break the Memory Wall.” 2014. Thesis, Penn State University. Accessed December 04, 2020. https://submit-etda.libraries.psu.edu/catalog/21517.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Zhang, Tao. “A Study of DRAM Optimization to Break the Memory Wall.” 2014. Web. 04 Dec 2020.

Vancouver:

Zhang T. A Study of DRAM Optimization to Break the Memory Wall. [Internet] [Thesis]. Penn State University; 2014. [cited 2020 Dec 04]. Available from: https://submit-etda.libraries.psu.edu/catalog/21517.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zhang T. A Study of DRAM Optimization to Break the Memory Wall. [Thesis]. Penn State University; 2014. Available from: https://submit-etda.libraries.psu.edu/catalog/21517

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

20. Zhao, Jishen. Rethinking the memory hierarchy design with nonvolatile memory technologies.

Degree: 2014, Penn State University

 The memory hierarchy, including processor caches and the main memory, is an important component of various computer systems. The memory hierarchy is becoming a fundamental… (more)

Subjects/Keywords: Memory hierarchy; Nonvolatile memory; Persistence; Memory/storage stack; Energy efficiency; Graphics memory; CMP; GPU

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zhao, J. (2014). Rethinking the memory hierarchy design with nonvolatile memory technologies. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/21345

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Zhao, Jishen. “Rethinking the memory hierarchy design with nonvolatile memory technologies.” 2014. Thesis, Penn State University. Accessed December 04, 2020. https://submit-etda.libraries.psu.edu/catalog/21345.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Zhao, Jishen. “Rethinking the memory hierarchy design with nonvolatile memory technologies.” 2014. Web. 04 Dec 2020.

Vancouver:

Zhao J. Rethinking the memory hierarchy design with nonvolatile memory technologies. [Internet] [Thesis]. Penn State University; 2014. [cited 2020 Dec 04]. Available from: https://submit-etda.libraries.psu.edu/catalog/21345.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zhao J. Rethinking the memory hierarchy design with nonvolatile memory technologies. [Thesis]. Penn State University; 2014. Available from: https://submit-etda.libraries.psu.edu/catalog/21345

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

21. Cherukuri, Venkateswara Rao. Domain Enriched Learning for Brain Image Analysis.

Degree: 2020, Penn State University

 Medical imaging techniques such as magnetic resonance imaging (MRI), computed-tomography (CT), X-ray, ultra-sound, positron emission tomography (PET), and mammography have been widely used over the… (more)

Subjects/Keywords: Brain Imaging; MRI; CT; Machine Learning; Deep Learning; Priors

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APA (6th Edition):

Cherukuri, V. R. (2020). Domain Enriched Learning for Brain Image Analysis. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/17438vmc5164

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Cherukuri, Venkateswara Rao. “Domain Enriched Learning for Brain Image Analysis.” 2020. Thesis, Penn State University. Accessed December 04, 2020. https://submit-etda.libraries.psu.edu/catalog/17438vmc5164.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Cherukuri, Venkateswara Rao. “Domain Enriched Learning for Brain Image Analysis.” 2020. Web. 04 Dec 2020.

Vancouver:

Cherukuri VR. Domain Enriched Learning for Brain Image Analysis. [Internet] [Thesis]. Penn State University; 2020. [cited 2020 Dec 04]. Available from: https://submit-etda.libraries.psu.edu/catalog/17438vmc5164.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Cherukuri VR. Domain Enriched Learning for Brain Image Analysis. [Thesis]. Penn State University; 2020. Available from: https://submit-etda.libraries.psu.edu/catalog/17438vmc5164

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

22. An, Ning. Accessing Spatial Information in Resource-constrained and Resource-rich Environments.

Degree: 2008, Penn State University

 Spatial information has always been a need of the human society. Over the past two decades or so, Spatial Database Management Systems (SDBMS) have achieved… (more)

Subjects/Keywords: Geo-spatially Crawling; Cluster Computing; Energy Profile; Selectivity Estimation; Spatial Information

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

An, N. (2008). Accessing Spatial Information in Resource-constrained and Resource-rich Environments. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/5943

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

An, Ning. “Accessing Spatial Information in Resource-constrained and Resource-rich Environments.” 2008. Thesis, Penn State University. Accessed December 04, 2020. https://submit-etda.libraries.psu.edu/catalog/5943.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

An, Ning. “Accessing Spatial Information in Resource-constrained and Resource-rich Environments.” 2008. Web. 04 Dec 2020.

Vancouver:

An N. Accessing Spatial Information in Resource-constrained and Resource-rich Environments. [Internet] [Thesis]. Penn State University; 2008. [cited 2020 Dec 04]. Available from: https://submit-etda.libraries.psu.edu/catalog/5943.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

An N. Accessing Spatial Information in Resource-constrained and Resource-rich Environments. [Thesis]. Penn State University; 2008. Available from: https://submit-etda.libraries.psu.edu/catalog/5943

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

23. Yoo, Jincheol. A TIQ Based CMOS Flash A/D Converter for System-on-Chip Applications.

Degree: 2008, Penn State University

 This thesis addresses a Threshold Inverter Quantization (TIQ) based CMOS flash analog-to-digital converter (ADC) for system-on-chip (SoC) applications. The TIQ technique, which uses two cascaded… (more)

Subjects/Keywords: Threshold Inverter Quantization (TIQ); Flash ADC; Analog-to-Digital Converter; System-on-Chip (SoC)

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APA (6th Edition):

Yoo, J. (2008). A TIQ Based CMOS Flash A/D Converter for System-on-Chip Applications. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/6040

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yoo, Jincheol. “A TIQ Based CMOS Flash A/D Converter for System-on-Chip Applications.” 2008. Thesis, Penn State University. Accessed December 04, 2020. https://submit-etda.libraries.psu.edu/catalog/6040.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yoo, Jincheol. “A TIQ Based CMOS Flash A/D Converter for System-on-Chip Applications.” 2008. Web. 04 Dec 2020.

Vancouver:

Yoo J. A TIQ Based CMOS Flash A/D Converter for System-on-Chip Applications. [Internet] [Thesis]. Penn State University; 2008. [cited 2020 Dec 04]. Available from: https://submit-etda.libraries.psu.edu/catalog/6040.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yoo J. A TIQ Based CMOS Flash A/D Converter for System-on-Chip Applications. [Thesis]. Penn State University; 2008. Available from: https://submit-etda.libraries.psu.edu/catalog/6040

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

24. Park, Dongkook. Design of High-Performance, Energy-Efficient, and Reliable Network-on-Chip (NoC) Architectures.

Degree: 2008, Penn State University

 The notion of a Network-on-Chip (NoC) is rapidly gaining a foothold as the communication fabric in complex System-on-Chip (SoC) architectures including recent Multi-Core architectures. Scalability… (more)

Subjects/Keywords: Network-on-Chip; on-chip interconnection; low-power; reliability; router architecture

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APA (6th Edition):

Park, D. (2008). Design of High-Performance, Energy-Efficient, and Reliable Network-on-Chip (NoC) Architectures. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/8203

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Park, Dongkook. “Design of High-Performance, Energy-Efficient, and Reliable Network-on-Chip (NoC) Architectures.” 2008. Thesis, Penn State University. Accessed December 04, 2020. https://submit-etda.libraries.psu.edu/catalog/8203.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Park, Dongkook. “Design of High-Performance, Energy-Efficient, and Reliable Network-on-Chip (NoC) Architectures.” 2008. Web. 04 Dec 2020.

Vancouver:

Park D. Design of High-Performance, Energy-Efficient, and Reliable Network-on-Chip (NoC) Architectures. [Internet] [Thesis]. Penn State University; 2008. [cited 2020 Dec 04]. Available from: https://submit-etda.libraries.psu.edu/catalog/8203.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Park D. Design of High-Performance, Energy-Efficient, and Reliable Network-on-Chip (NoC) Architectures. [Thesis]. Penn State University; 2008. Available from: https://submit-etda.libraries.psu.edu/catalog/8203

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

25. Wang, Feng. DEEP SUBMICRON (DSM) DESIGN AUTOMATION TECHNIQUES TO MITIGATE PROCESS VARIATIONS .

Degree: 2008, Penn State University

 Technology scaling provides an integration capacity of billions of transistors and continuously enhances system performance. However, fabricating transistors at feature sizes in the deep sub-micron… (more)

Subjects/Keywords: high level synthesis; design automation; process variations

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APA (6th Edition):

Wang, F. (2008). DEEP SUBMICRON (DSM) DESIGN AUTOMATION TECHNIQUES TO MITIGATE PROCESS VARIATIONS . (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/8173

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wang, Feng. “DEEP SUBMICRON (DSM) DESIGN AUTOMATION TECHNIQUES TO MITIGATE PROCESS VARIATIONS .” 2008. Thesis, Penn State University. Accessed December 04, 2020. https://submit-etda.libraries.psu.edu/catalog/8173.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wang, Feng. “DEEP SUBMICRON (DSM) DESIGN AUTOMATION TECHNIQUES TO MITIGATE PROCESS VARIATIONS .” 2008. Web. 04 Dec 2020.

Vancouver:

Wang F. DEEP SUBMICRON (DSM) DESIGN AUTOMATION TECHNIQUES TO MITIGATE PROCESS VARIATIONS . [Internet] [Thesis]. Penn State University; 2008. [cited 2020 Dec 04]. Available from: https://submit-etda.libraries.psu.edu/catalog/8173.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wang F. DEEP SUBMICRON (DSM) DESIGN AUTOMATION TECHNIQUES TO MITIGATE PROCESS VARIATIONS . [Thesis]. Penn State University; 2008. Available from: https://submit-etda.libraries.psu.edu/catalog/8173

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

26. Hung, Wei-Lun. Designing Cool Chips: Low Power and Thermal-Aware Design Methodologies .

Degree: 2008, Penn State University

 Power is one of the rigid challenges for high performance computer system designs and for the widespread use of portable and wireless electronic systems. With… (more)

Subjects/Keywords: placement; algorithm; VLSI; CAD; thermal; EDA; floorplanning

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hung, W. (2008). Designing Cool Chips: Low Power and Thermal-Aware Design Methodologies . (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/7352

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hung, Wei-Lun. “Designing Cool Chips: Low Power and Thermal-Aware Design Methodologies .” 2008. Thesis, Penn State University. Accessed December 04, 2020. https://submit-etda.libraries.psu.edu/catalog/7352.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hung, Wei-Lun. “Designing Cool Chips: Low Power and Thermal-Aware Design Methodologies .” 2008. Web. 04 Dec 2020.

Vancouver:

Hung W. Designing Cool Chips: Low Power and Thermal-Aware Design Methodologies . [Internet] [Thesis]. Penn State University; 2008. [cited 2020 Dec 04]. Available from: https://submit-etda.libraries.psu.edu/catalog/7352.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hung W. Designing Cool Chips: Low Power and Thermal-Aware Design Methodologies . [Thesis]. Penn State University; 2008. Available from: https://submit-etda.libraries.psu.edu/catalog/7352

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

27. Kim, Jongman. A Comprehensive Approach to Design Network-on-Chip Architectures for SoC/Multicore Systems .

Degree: 2008, Penn State University

 With the advent of deep sub-micron technology, System-on-Chip (SOC) architectures are becoming possible for a range of applications. However, as single chip systems become a… (more)

Subjects/Keywords: Routing Mechanism; Computer Architecture; Network-on-Chip; System-on-Chip

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kim, J. (2008). A Comprehensive Approach to Design Network-on-Chip Architectures for SoC/Multicore Systems . (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/7656

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kim, Jongman. “A Comprehensive Approach to Design Network-on-Chip Architectures for SoC/Multicore Systems .” 2008. Thesis, Penn State University. Accessed December 04, 2020. https://submit-etda.libraries.psu.edu/catalog/7656.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kim, Jongman. “A Comprehensive Approach to Design Network-on-Chip Architectures for SoC/Multicore Systems .” 2008. Web. 04 Dec 2020.

Vancouver:

Kim J. A Comprehensive Approach to Design Network-on-Chip Architectures for SoC/Multicore Systems . [Internet] [Thesis]. Penn State University; 2008. [cited 2020 Dec 04]. Available from: https://submit-etda.libraries.psu.edu/catalog/7656.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kim J. A Comprehensive Approach to Design Network-on-Chip Architectures for SoC/Multicore Systems . [Thesis]. Penn State University; 2008. Available from: https://submit-etda.libraries.psu.edu/catalog/7656

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

28. Ye, Wu. ARCHITECTURAL LEVEL POWER ESTIMATION AND EXPERIMENTATION .

Degree: 2008, Penn State University

 With the emergence of a plethora of embedded and portable applications and ever increasing integration levels, power dissipation of integrated circuits has moved to the… (more)

Subjects/Keywords: SimplePower; Power Estimation; RTL; Architectural Level Power Estimation/Optimization; Partitioning Power Modeling Technique; Transition-Sensitive Energy Model

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ye, W. (2008). ARCHITECTURAL LEVEL POWER ESTIMATION AND EXPERIMENTATION . (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/5809

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ye, Wu. “ARCHITECTURAL LEVEL POWER ESTIMATION AND EXPERIMENTATION .” 2008. Thesis, Penn State University. Accessed December 04, 2020. https://submit-etda.libraries.psu.edu/catalog/5809.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ye, Wu. “ARCHITECTURAL LEVEL POWER ESTIMATION AND EXPERIMENTATION .” 2008. Web. 04 Dec 2020.

Vancouver:

Ye W. ARCHITECTURAL LEVEL POWER ESTIMATION AND EXPERIMENTATION . [Internet] [Thesis]. Penn State University; 2008. [cited 2020 Dec 04]. Available from: https://submit-etda.libraries.psu.edu/catalog/5809.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ye W. ARCHITECTURAL LEVEL POWER ESTIMATION AND EXPERIMENTATION . [Thesis]. Penn State University; 2008. Available from: https://submit-etda.libraries.psu.edu/catalog/5809

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

29. Duarte, David Enrique. Clock Network and Phase-Locked Loop Power Estimation and Experimentation.

Degree: 2008, Penn State University

 The clock distribution network and the generation circuitry are critical components of current synchronous digital systems and are known to consume more than a quarter… (more)

Subjects/Keywords: CPU clock energy modeling; power estimation; PLL design; low power VLSI design

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Duarte, D. E. (2008). Clock Network and Phase-Locked Loop Power Estimation and Experimentation. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/5919

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Duarte, David Enrique. “Clock Network and Phase-Locked Loop Power Estimation and Experimentation.” 2008. Thesis, Penn State University. Accessed December 04, 2020. https://submit-etda.libraries.psu.edu/catalog/5919.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Duarte, David Enrique. “Clock Network and Phase-Locked Loop Power Estimation and Experimentation.” 2008. Web. 04 Dec 2020.

Vancouver:

Duarte DE. Clock Network and Phase-Locked Loop Power Estimation and Experimentation. [Internet] [Thesis]. Penn State University; 2008. [cited 2020 Dec 04]. Available from: https://submit-etda.libraries.psu.edu/catalog/5919.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Duarte DE. Clock Network and Phase-Locked Loop Power Estimation and Experimentation. [Thesis]. Penn State University; 2008. Available from: https://submit-etda.libraries.psu.edu/catalog/5919

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

30. Yum, Ki Hwan. Quality of Service Provisioning in Clusters.

Degree: 2008, Penn State University

 Cluster systems are becoming increasingly more attractive for designing scalable servers with switched network architectures that offer much higher bandwidth than the broadcast-based networks. Design… (more)

Subjects/Keywords: VirtualClock; Quality of Service; Cluster Network; Network Interface; Network Interface; Router Architecture; Wormhole Router

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Yum, K. H. (2008). Quality of Service Provisioning in Clusters. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/5797

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yum, Ki Hwan. “Quality of Service Provisioning in Clusters.” 2008. Thesis, Penn State University. Accessed December 04, 2020. https://submit-etda.libraries.psu.edu/catalog/5797.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yum, Ki Hwan. “Quality of Service Provisioning in Clusters.” 2008. Web. 04 Dec 2020.

Vancouver:

Yum KH. Quality of Service Provisioning in Clusters. [Internet] [Thesis]. Penn State University; 2008. [cited 2020 Dec 04]. Available from: https://submit-etda.libraries.psu.edu/catalog/5797.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yum KH. Quality of Service Provisioning in Clusters. [Thesis]. Penn State University; 2008. Available from: https://submit-etda.libraries.psu.edu/catalog/5797

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

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