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You searched for +publisher:"Penn State University" +contributor:("Mary Jane Irwin, Committee Member"). Showing records 1 – 30 of 69 total matches.

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Penn State University

1. Ding, Wei. A Fresh Look At Data Locality On Emerging Multicores And Manycores.

Degree: 2014, Penn State University

 The emergence of multicore platforms offers several opportunities for boosting ap- plication performance. These opportunities, which include parallelism and data locality benefits, require strong support… (more)

Subjects/Keywords: Data Locality; Multicore; Manycore; Compiler; Loop

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ding, W. (2014). A Fresh Look At Data Locality On Emerging Multicores And Manycores. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/22506

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ding, Wei. “A Fresh Look At Data Locality On Emerging Multicores And Manycores.” 2014. Thesis, Penn State University. Accessed October 19, 2020. https://submit-etda.libraries.psu.edu/catalog/22506.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ding, Wei. “A Fresh Look At Data Locality On Emerging Multicores And Manycores.” 2014. Web. 19 Oct 2020.

Vancouver:

Ding W. A Fresh Look At Data Locality On Emerging Multicores And Manycores. [Internet] [Thesis]. Penn State University; 2014. [cited 2020 Oct 19]. Available from: https://submit-etda.libraries.psu.edu/catalog/22506.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ding W. A Fresh Look At Data Locality On Emerging Multicores And Manycores. [Thesis]. Penn State University; 2014. Available from: https://submit-etda.libraries.psu.edu/catalog/22506

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

2. Liu, Jun. Compiler Optimizations for SIMD/GPU/Multicore Architectures.

Degree: 2013, Penn State University

 In modern computer architectures, both SIMD (single-instruction multiple-data) instruction set extensions and GPUs can be used to accelerate the general purpose applications. In addition, the… (more)

Subjects/Keywords: Compiler Optimization; SIMD; GPGPU; Multicore; Scheduling; Data Layout Transformation; Tiling

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APA (6th Edition):

Liu, J. (2013). Compiler Optimizations for SIMD/GPU/Multicore Architectures. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/18798

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Liu, Jun. “Compiler Optimizations for SIMD/GPU/Multicore Architectures.” 2013. Thesis, Penn State University. Accessed October 19, 2020. https://submit-etda.libraries.psu.edu/catalog/18798.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Liu, Jun. “Compiler Optimizations for SIMD/GPU/Multicore Architectures.” 2013. Web. 19 Oct 2020.

Vancouver:

Liu J. Compiler Optimizations for SIMD/GPU/Multicore Architectures. [Internet] [Thesis]. Penn State University; 2013. [cited 2020 Oct 19]. Available from: https://submit-etda.libraries.psu.edu/catalog/18798.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Liu J. Compiler Optimizations for SIMD/GPU/Multicore Architectures. [Thesis]. Penn State University; 2013. Available from: https://submit-etda.libraries.psu.edu/catalog/18798

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

3. Niu, Dimin. Modeling and Architecting Emerging Non-volatile Resistive Random Access Memory for Future Computer System.

Degree: 2013, Penn State University

 As leakage power and fabrication difficulty have become major obstacles of DRAM scaling, the search for new technologies as DRAM alternative has gained increased attention.… (more)

Subjects/Keywords: Memory System; Non-Volatile Memory; Resistive Memory

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APA (6th Edition):

Niu, D. (2013). Modeling and Architecting Emerging Non-volatile Resistive Random Access Memory for Future Computer System. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/19113

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Niu, Dimin. “Modeling and Architecting Emerging Non-volatile Resistive Random Access Memory for Future Computer System.” 2013. Thesis, Penn State University. Accessed October 19, 2020. https://submit-etda.libraries.psu.edu/catalog/19113.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Niu, Dimin. “Modeling and Architecting Emerging Non-volatile Resistive Random Access Memory for Future Computer System.” 2013. Web. 19 Oct 2020.

Vancouver:

Niu D. Modeling and Architecting Emerging Non-volatile Resistive Random Access Memory for Future Computer System. [Internet] [Thesis]. Penn State University; 2013. [cited 2020 Oct 19]. Available from: https://submit-etda.libraries.psu.edu/catalog/19113.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Niu D. Modeling and Architecting Emerging Non-volatile Resistive Random Access Memory for Future Computer System. [Thesis]. Penn State University; 2013. Available from: https://submit-etda.libraries.psu.edu/catalog/19113

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

4. Shantharam, Manu. Algorithmic Approaches for Enhancing Speedup, Energy and Resiliency Measures of Sparse Scientific Computations.

Degree: 2012, Penn State University

 High performance computing systems have increasingly complex node and network architectures including non-uniform memory subsystems, heterogeneous processors and hierarchical interconnects. The performance of scientific applications… (more)

Subjects/Keywords: Sparse scientific computing; high performance computing; performance analysis and modeling

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APA (6th Edition):

Shantharam, M. (2012). Algorithmic Approaches for Enhancing Speedup, Energy and Resiliency Measures of Sparse Scientific Computations. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/15740

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Shantharam, Manu. “Algorithmic Approaches for Enhancing Speedup, Energy and Resiliency Measures of Sparse Scientific Computations.” 2012. Thesis, Penn State University. Accessed October 19, 2020. https://submit-etda.libraries.psu.edu/catalog/15740.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Shantharam, Manu. “Algorithmic Approaches for Enhancing Speedup, Energy and Resiliency Measures of Sparse Scientific Computations.” 2012. Web. 19 Oct 2020.

Vancouver:

Shantharam M. Algorithmic Approaches for Enhancing Speedup, Energy and Resiliency Measures of Sparse Scientific Computations. [Internet] [Thesis]. Penn State University; 2012. [cited 2020 Oct 19]. Available from: https://submit-etda.libraries.psu.edu/catalog/15740.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Shantharam M. Algorithmic Approaches for Enhancing Speedup, Energy and Resiliency Measures of Sparse Scientific Computations. [Thesis]. Penn State University; 2012. Available from: https://submit-etda.libraries.psu.edu/catalog/15740

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

5. Xu, Cong. Modeling, Circuit Design, and Microarchitectural Optimization of Emerging Resistive Memory.

Degree: 2014, Penn State University

 Conventional memories technologies such as SRAM, DRAM, and NAND flash are facing formidable device scaling challenges. Various new non-volatile memory (NVM) technologies have emerged recently,… (more)

Subjects/Keywords: Non-Volatile Memory; ReRAM; Computer Architecture; Memory System

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Xu, C. (2014). Modeling, Circuit Design, and Microarchitectural Optimization of Emerging Resistive Memory. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/23577

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Xu, Cong. “Modeling, Circuit Design, and Microarchitectural Optimization of Emerging Resistive Memory.” 2014. Thesis, Penn State University. Accessed October 19, 2020. https://submit-etda.libraries.psu.edu/catalog/23577.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Xu, Cong. “Modeling, Circuit Design, and Microarchitectural Optimization of Emerging Resistive Memory.” 2014. Web. 19 Oct 2020.

Vancouver:

Xu C. Modeling, Circuit Design, and Microarchitectural Optimization of Emerging Resistive Memory. [Internet] [Thesis]. Penn State University; 2014. [cited 2020 Oct 19]. Available from: https://submit-etda.libraries.psu.edu/catalog/23577.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Xu C. Modeling, Circuit Design, and Microarchitectural Optimization of Emerging Resistive Memory. [Thesis]. Penn State University; 2014. Available from: https://submit-etda.libraries.psu.edu/catalog/23577

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

6. Cotter, Matthew Joseph. Enabling Intelligent Vision Systems in a Configurable Multi-algorithm Pipeline.

Degree: 2015, Penn State University

 The machine vision community has expended tremendous effort in the research and development of algorithms in an effort to develop a system that is capable… (more)

Subjects/Keywords: Configurable Systems; Vision Algorithms; Intelligent Vision; Hardware Accelerators

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Cotter, M. J. (2015). Enabling Intelligent Vision Systems in a Configurable Multi-algorithm Pipeline. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/24792

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Cotter, Matthew Joseph. “Enabling Intelligent Vision Systems in a Configurable Multi-algorithm Pipeline.” 2015. Thesis, Penn State University. Accessed October 19, 2020. https://submit-etda.libraries.psu.edu/catalog/24792.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Cotter, Matthew Joseph. “Enabling Intelligent Vision Systems in a Configurable Multi-algorithm Pipeline.” 2015. Web. 19 Oct 2020.

Vancouver:

Cotter MJ. Enabling Intelligent Vision Systems in a Configurable Multi-algorithm Pipeline. [Internet] [Thesis]. Penn State University; 2015. [cited 2020 Oct 19]. Available from: https://submit-etda.libraries.psu.edu/catalog/24792.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Cotter MJ. Enabling Intelligent Vision Systems in a Configurable Multi-algorithm Pipeline. [Thesis]. Penn State University; 2015. Available from: https://submit-etda.libraries.psu.edu/catalog/24792

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

7. Poremba, Matthew Raymond. Architecting Byte-addressable Non-volatile Memories for Main Memory.

Degree: 2015, Penn State University

 New breakthroughs in memory technology in recent years has lead to increased research efforts in so-called byte-addressable non-volatile memories (NVM). As a result, questions of… (more)

Subjects/Keywords: Computer Memory; Non-Volatile Memory; DRAM; Memory Scheduling; Memory Modeling; Memory Simulation

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Poremba, M. R. (2015). Architecting Byte-addressable Non-volatile Memories for Main Memory. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/25034

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Poremba, Matthew Raymond. “Architecting Byte-addressable Non-volatile Memories for Main Memory.” 2015. Thesis, Penn State University. Accessed October 19, 2020. https://submit-etda.libraries.psu.edu/catalog/25034.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Poremba, Matthew Raymond. “Architecting Byte-addressable Non-volatile Memories for Main Memory.” 2015. Web. 19 Oct 2020.

Vancouver:

Poremba MR. Architecting Byte-addressable Non-volatile Memories for Main Memory. [Internet] [Thesis]. Penn State University; 2015. [cited 2020 Oct 19]. Available from: https://submit-etda.libraries.psu.edu/catalog/25034.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Poremba MR. Architecting Byte-addressable Non-volatile Memories for Main Memory. [Thesis]. Penn State University; 2015. Available from: https://submit-etda.libraries.psu.edu/catalog/25034

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

8. Kultursay, Emre. Compiler-based Memory Optimizations for High Performance Computing Systems.

Degree: 2013, Penn State University

 Parallelism has always been the primary method to achieve higher performance. To advance the computational capabilities of state-of-the-art high performance computing systems, we continue to… (more)

Subjects/Keywords: Compilers; memory optimizations; high performance computing; application-specific hardware accelerators; many-core processors

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kultursay, E. (2013). Compiler-based Memory Optimizations for High Performance Computing Systems. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/18832

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kultursay, Emre. “Compiler-based Memory Optimizations for High Performance Computing Systems.” 2013. Thesis, Penn State University. Accessed October 19, 2020. https://submit-etda.libraries.psu.edu/catalog/18832.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kultursay, Emre. “Compiler-based Memory Optimizations for High Performance Computing Systems.” 2013. Web. 19 Oct 2020.

Vancouver:

Kultursay E. Compiler-based Memory Optimizations for High Performance Computing Systems. [Internet] [Thesis]. Penn State University; 2013. [cited 2020 Oct 19]. Available from: https://submit-etda.libraries.psu.edu/catalog/18832.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kultursay E. Compiler-based Memory Optimizations for High Performance Computing Systems. [Thesis]. Penn State University; 2013. Available from: https://submit-etda.libraries.psu.edu/catalog/18832

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

9. Eze, Melvin. Sub-50 nm Multi-Segment Interconnect Design: A treatise on Speed, Reliability and Signal Integrity.

Degree: 2013, Penn State University

 The emergence of System-on-Chip as the dominant chip level architecture in the integrated Circuit industry, has been accompanied by a need to meet the considerable… (more)

Subjects/Keywords: Interconnect; Signal Integrity; Offset Switching; Variable Cycle Timing with Temporal Redundancy; NBTI

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Eze, M. (2013). Sub-50 nm Multi-Segment Interconnect Design: A treatise on Speed, Reliability and Signal Integrity. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/19916

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Eze, Melvin. “Sub-50 nm Multi-Segment Interconnect Design: A treatise on Speed, Reliability and Signal Integrity.” 2013. Thesis, Penn State University. Accessed October 19, 2020. https://submit-etda.libraries.psu.edu/catalog/19916.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Eze, Melvin. “Sub-50 nm Multi-Segment Interconnect Design: A treatise on Speed, Reliability and Signal Integrity.” 2013. Web. 19 Oct 2020.

Vancouver:

Eze M. Sub-50 nm Multi-Segment Interconnect Design: A treatise on Speed, Reliability and Signal Integrity. [Internet] [Thesis]. Penn State University; 2013. [cited 2020 Oct 19]. Available from: https://submit-etda.libraries.psu.edu/catalog/19916.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Eze M. Sub-50 nm Multi-Segment Interconnect Design: A treatise on Speed, Reliability and Signal Integrity. [Thesis]. Penn State University; 2013. Available from: https://submit-etda.libraries.psu.edu/catalog/19916

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

10. Park, Sungho. system-on-chip integration of heterogeneous accelerators for perceptual computing.

Degree: 2013, Penn State University

 Traditional microprocessor design has seen radical shifts over the past few years. The challenges of excessive power consumption led to the shift from faster and… (more)

Subjects/Keywords: perceptual computing; system-on-chip; heterogeneous accelerator; stream processing

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Park, S. (2013). system-on-chip integration of heterogeneous accelerators for perceptual computing. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/19218

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Park, Sungho. “system-on-chip integration of heterogeneous accelerators for perceptual computing.” 2013. Thesis, Penn State University. Accessed October 19, 2020. https://submit-etda.libraries.psu.edu/catalog/19218.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Park, Sungho. “system-on-chip integration of heterogeneous accelerators for perceptual computing.” 2013. Web. 19 Oct 2020.

Vancouver:

Park S. system-on-chip integration of heterogeneous accelerators for perceptual computing. [Internet] [Thesis]. Penn State University; 2013. [cited 2020 Oct 19]. Available from: https://submit-etda.libraries.psu.edu/catalog/19218.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Park S. system-on-chip integration of heterogeneous accelerators for perceptual computing. [Thesis]. Penn State University; 2013. Available from: https://submit-etda.libraries.psu.edu/catalog/19218

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

11. Tsai, Wei Yu. Enabling New Computation Paradigms with Emerging Technologies.

Degree: 2017, Penn State University

 For the last decade, Moore's law has slowed down while Dennard scaling has come to an end. Thus, performance improvements can no longer rely on… (more)

Subjects/Keywords: Non-Boolean Computation; Neural Networks; Coupled Scillators; Low-power Computation; Image Processing; Audio Processing

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Tsai, W. Y. (2017). Enabling New Computation Paradigms with Emerging Technologies. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/14401wzt114

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Tsai, Wei Yu. “Enabling New Computation Paradigms with Emerging Technologies.” 2017. Thesis, Penn State University. Accessed October 19, 2020. https://submit-etda.libraries.psu.edu/catalog/14401wzt114.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Tsai, Wei Yu. “Enabling New Computation Paradigms with Emerging Technologies.” 2017. Web. 19 Oct 2020.

Vancouver:

Tsai WY. Enabling New Computation Paradigms with Emerging Technologies. [Internet] [Thesis]. Penn State University; 2017. [cited 2020 Oct 19]. Available from: https://submit-etda.libraries.psu.edu/catalog/14401wzt114.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tsai WY. Enabling New Computation Paradigms with Emerging Technologies. [Thesis]. Penn State University; 2017. Available from: https://submit-etda.libraries.psu.edu/catalog/14401wzt114

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

12. Saripalli, Vinay. DEVICE AND ARCHITECTURE CO-DESIGN FOR ULTRA-LOW POWER LOGIC USING EMERGING TUNNELING-BASED DEVICES.

Degree: 2011, Penn State University

 The scaling of silicon CMOS, by delivering lower switching-energy transistors with each technology generation, has been the driving force behind total circuit-energy reduction during the… (more)

Subjects/Keywords: Tunnel FET; Single Electron Transistor; Low Power Electronics; Heterogeneous Architecture; Variation-Aware SRAM

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Saripalli, V. (2011). DEVICE AND ARCHITECTURE CO-DESIGN FOR ULTRA-LOW POWER LOGIC USING EMERGING TUNNELING-BASED DEVICES. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/12574

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Saripalli, Vinay. “DEVICE AND ARCHITECTURE CO-DESIGN FOR ULTRA-LOW POWER LOGIC USING EMERGING TUNNELING-BASED DEVICES.” 2011. Thesis, Penn State University. Accessed October 19, 2020. https://submit-etda.libraries.psu.edu/catalog/12574.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Saripalli, Vinay. “DEVICE AND ARCHITECTURE CO-DESIGN FOR ULTRA-LOW POWER LOGIC USING EMERGING TUNNELING-BASED DEVICES.” 2011. Web. 19 Oct 2020.

Vancouver:

Saripalli V. DEVICE AND ARCHITECTURE CO-DESIGN FOR ULTRA-LOW POWER LOGIC USING EMERGING TUNNELING-BASED DEVICES. [Internet] [Thesis]. Penn State University; 2011. [cited 2020 Oct 19]. Available from: https://submit-etda.libraries.psu.edu/catalog/12574.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Saripalli V. DEVICE AND ARCHITECTURE CO-DESIGN FOR ULTRA-LOW POWER LOGIC USING EMERGING TUNNELING-BASED DEVICES. [Thesis]. Penn State University; 2011. Available from: https://submit-etda.libraries.psu.edu/catalog/12574

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

13. Dong, Xiangyu. Modeling and Leveraging Emerging Non-Volatile Memories for Future Computer Designs .

Degree: 2011, Penn State University

 Energy efficiency has become a major constraint in the design of computing systems today. As CMOS continues scaling down, traditional CMOS scaling theory requires to… (more)

Subjects/Keywords: application; architecture; circuit; non-volatile memory; STTRAM; PCRAM; ReRAM

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Dong, X. (2011). Modeling and Leveraging Emerging Non-Volatile Memories for Future Computer Designs . (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/12462

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Dong, Xiangyu. “Modeling and Leveraging Emerging Non-Volatile Memories for Future Computer Designs .” 2011. Thesis, Penn State University. Accessed October 19, 2020. https://submit-etda.libraries.psu.edu/catalog/12462.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Dong, Xiangyu. “Modeling and Leveraging Emerging Non-Volatile Memories for Future Computer Designs .” 2011. Web. 19 Oct 2020.

Vancouver:

Dong X. Modeling and Leveraging Emerging Non-Volatile Memories for Future Computer Designs . [Internet] [Thesis]. Penn State University; 2011. [cited 2020 Oct 19]. Available from: https://submit-etda.libraries.psu.edu/catalog/12462.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Dong X. Modeling and Leveraging Emerging Non-Volatile Memories for Future Computer Designs . [Thesis]. Penn State University; 2011. Available from: https://submit-etda.libraries.psu.edu/catalog/12462

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

14. Prabhakar, Ramya Arkalgud. Shared Storage Resource Management to Provide predictable Performance.

Degree: 2012, Penn State University

 Emerging high-end computing platforms at petascale provide new horizons for complex modeling and large-scale simulations. While these systems have unprecedented levels of peak computational power… (more)

Subjects/Keywords: Storage systems; I/O; High Performance Computing; QoS

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Prabhakar, R. A. (2012). Shared Storage Resource Management to Provide predictable Performance. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/13726

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Prabhakar, Ramya Arkalgud. “Shared Storage Resource Management to Provide predictable Performance.” 2012. Thesis, Penn State University. Accessed October 19, 2020. https://submit-etda.libraries.psu.edu/catalog/13726.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Prabhakar, Ramya Arkalgud. “Shared Storage Resource Management to Provide predictable Performance.” 2012. Web. 19 Oct 2020.

Vancouver:

Prabhakar RA. Shared Storage Resource Management to Provide predictable Performance. [Internet] [Thesis]. Penn State University; 2012. [cited 2020 Oct 19]. Available from: https://submit-etda.libraries.psu.edu/catalog/13726.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Prabhakar RA. Shared Storage Resource Management to Provide predictable Performance. [Thesis]. Penn State University; 2012. Available from: https://submit-etda.libraries.psu.edu/catalog/13726

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

15. Patrick, Christina M. Minimizing End-To-End Interference in I/O Stacks Spanning Shared Multi-Level Buffer Caches .

Degree: 2011, Penn State University

 Service providers and IT solutions generally favor shared resources to avoid excessive cost and over-provisioning. Most applications access shared storage servers through a multi-level buffer… (more)

Subjects/Keywords: storage cache; interference; Multi-level buffer caches; performance; I/O; disk; cache

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Patrick, C. M. (2011). Minimizing End-To-End Interference in I/O Stacks Spanning Shared Multi-Level Buffer Caches . (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/11776

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Patrick, Christina M. “Minimizing End-To-End Interference in I/O Stacks Spanning Shared Multi-Level Buffer Caches .” 2011. Thesis, Penn State University. Accessed October 19, 2020. https://submit-etda.libraries.psu.edu/catalog/11776.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Patrick, Christina M. “Minimizing End-To-End Interference in I/O Stacks Spanning Shared Multi-Level Buffer Caches .” 2011. Web. 19 Oct 2020.

Vancouver:

Patrick CM. Minimizing End-To-End Interference in I/O Stacks Spanning Shared Multi-Level Buffer Caches . [Internet] [Thesis]. Penn State University; 2011. [cited 2020 Oct 19]. Available from: https://submit-etda.libraries.psu.edu/catalog/11776.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Patrick CM. Minimizing End-To-End Interference in I/O Stacks Spanning Shared Multi-Level Buffer Caches . [Thesis]. Penn State University; 2011. Available from: https://submit-etda.libraries.psu.edu/catalog/11776

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

16. DeBole, Michael Vincent. CONFIGURABLE ACCELERATORS FOR VIDEO ANALYTICS .

Degree: 2011, Penn State University

 Video analytics is the science of analyzing image sequences and video with the aim to gain a cognitive understanding of a scene. The applications which… (more)

Subjects/Keywords: FPGA; Hardware Acceleration; Image Processing; 3D IC; FPGA Framework

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

DeBole, M. V. (2011). CONFIGURABLE ACCELERATORS FOR VIDEO ANALYTICS . (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/11829

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

DeBole, Michael Vincent. “CONFIGURABLE ACCELERATORS FOR VIDEO ANALYTICS .” 2011. Thesis, Penn State University. Accessed October 19, 2020. https://submit-etda.libraries.psu.edu/catalog/11829.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

DeBole, Michael Vincent. “CONFIGURABLE ACCELERATORS FOR VIDEO ANALYTICS .” 2011. Web. 19 Oct 2020.

Vancouver:

DeBole MV. CONFIGURABLE ACCELERATORS FOR VIDEO ANALYTICS . [Internet] [Thesis]. Penn State University; 2011. [cited 2020 Oct 19]. Available from: https://submit-etda.libraries.psu.edu/catalog/11829.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

DeBole MV. CONFIGURABLE ACCELERATORS FOR VIDEO ANALYTICS . [Thesis]. Penn State University; 2011. Available from: https://submit-etda.libraries.psu.edu/catalog/11829

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

17. Kotra, Jagadish Babu. HARDWARE SOFTWARE CO-DESIGN FOR OPTIMIZING MEMORY HIERARCHY IN MANY-CORE AND MULTI-SOCKET SYSTEMS.

Degree: 2017, Penn State University

 Thanks to Moore’s law, the number of transistors on a chip have been increasing over time without increasing area of the processing die. The increased… (more)

Subjects/Keywords: Hardware-software co-design; memory hierarchy; manycore processors; memory; caches

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kotra, J. B. (2017). HARDWARE SOFTWARE CO-DESIGN FOR OPTIMIZING MEMORY HIERARCHY IN MANY-CORE AND MULTI-SOCKET SYSTEMS. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/14830jbk5155

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kotra, Jagadish Babu. “HARDWARE SOFTWARE CO-DESIGN FOR OPTIMIZING MEMORY HIERARCHY IN MANY-CORE AND MULTI-SOCKET SYSTEMS.” 2017. Thesis, Penn State University. Accessed October 19, 2020. https://submit-etda.libraries.psu.edu/catalog/14830jbk5155.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kotra, Jagadish Babu. “HARDWARE SOFTWARE CO-DESIGN FOR OPTIMIZING MEMORY HIERARCHY IN MANY-CORE AND MULTI-SOCKET SYSTEMS.” 2017. Web. 19 Oct 2020.

Vancouver:

Kotra JB. HARDWARE SOFTWARE CO-DESIGN FOR OPTIMIZING MEMORY HIERARCHY IN MANY-CORE AND MULTI-SOCKET SYSTEMS. [Internet] [Thesis]. Penn State University; 2017. [cited 2020 Oct 19]. Available from: https://submit-etda.libraries.psu.edu/catalog/14830jbk5155.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kotra JB. HARDWARE SOFTWARE CO-DESIGN FOR OPTIMIZING MEMORY HIERARCHY IN MANY-CORE AND MULTI-SOCKET SYSTEMS. [Thesis]. Penn State University; 2017. Available from: https://submit-etda.libraries.psu.edu/catalog/14830jbk5155

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

18. Cho, Yong. Accelerating Cortical Processing for Real Time Neuromorphic Vision Systems .

Degree: 2012, Penn State University

 The best computer vision systems are not able to match the performance of the mammalian vision system. Machines struggle to quickly process and make real… (more)

Subjects/Keywords: Gabor; feature extraction; primary visual cortex; multi-resolution; bio-inspired vision

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Cho, Y. (2012). Accelerating Cortical Processing for Real Time Neuromorphic Vision Systems . (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/15474

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Cho, Yong. “Accelerating Cortical Processing for Real Time Neuromorphic Vision Systems .” 2012. Thesis, Penn State University. Accessed October 19, 2020. https://submit-etda.libraries.psu.edu/catalog/15474.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Cho, Yong. “Accelerating Cortical Processing for Real Time Neuromorphic Vision Systems .” 2012. Web. 19 Oct 2020.

Vancouver:

Cho Y. Accelerating Cortical Processing for Real Time Neuromorphic Vision Systems . [Internet] [Thesis]. Penn State University; 2012. [cited 2020 Oct 19]. Available from: https://submit-etda.libraries.psu.edu/catalog/15474.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Cho Y. Accelerating Cortical Processing for Real Time Neuromorphic Vision Systems . [Thesis]. Penn State University; 2012. Available from: https://submit-etda.libraries.psu.edu/catalog/15474

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

19. Kim, Seong Jo. Parallel I/o Profiling and Optimization in Hpc Systems.

Degree: 2014, Penn State University

 Efficient execution of large-scale scientific applications requires high-performance computing systems designed to meet the I/O requirements. To achieve high-performance, such data-intensive scientific applications use multiple… (more)

Subjects/Keywords: MPI-IO; PnetCDF; HDF5; PVFS; I/O Software Stack; Code Instrumentation; Code Generation

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kim, S. J. (2014). Parallel I/o Profiling and Optimization in Hpc Systems. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/20163

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kim, Seong Jo. “Parallel I/o Profiling and Optimization in Hpc Systems.” 2014. Thesis, Penn State University. Accessed October 19, 2020. https://submit-etda.libraries.psu.edu/catalog/20163.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kim, Seong Jo. “Parallel I/o Profiling and Optimization in Hpc Systems.” 2014. Web. 19 Oct 2020.

Vancouver:

Kim SJ. Parallel I/o Profiling and Optimization in Hpc Systems. [Internet] [Thesis]. Penn State University; 2014. [cited 2020 Oct 19]. Available from: https://submit-etda.libraries.psu.edu/catalog/20163.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kim SJ. Parallel I/o Profiling and Optimization in Hpc Systems. [Thesis]. Penn State University; 2014. Available from: https://submit-etda.libraries.psu.edu/catalog/20163

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

20. Zhang, Tao. A Study of DRAM Optimization to Break the Memory Wall.

Degree: 2014, Penn State University

 The well-known “Memory Wall” has been raised in 1990s. At that time, the researchers noticed the diverging exponential increase in the performance of processor and… (more)

Subjects/Keywords: DRAM; Memory Wall; 3D-stacked DRAM; Wide IO; Activation; Precharge; Refresh; Sub-array Level Parallelism

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zhang, T. (2014). A Study of DRAM Optimization to Break the Memory Wall. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/21517

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Zhang, Tao. “A Study of DRAM Optimization to Break the Memory Wall.” 2014. Thesis, Penn State University. Accessed October 19, 2020. https://submit-etda.libraries.psu.edu/catalog/21517.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Zhang, Tao. “A Study of DRAM Optimization to Break the Memory Wall.” 2014. Web. 19 Oct 2020.

Vancouver:

Zhang T. A Study of DRAM Optimization to Break the Memory Wall. [Internet] [Thesis]. Penn State University; 2014. [cited 2020 Oct 19]. Available from: https://submit-etda.libraries.psu.edu/catalog/21517.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zhang T. A Study of DRAM Optimization to Break the Memory Wall. [Thesis]. Penn State University; 2014. Available from: https://submit-etda.libraries.psu.edu/catalog/21517

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

21. Zhao, Jishen. Rethinking the memory hierarchy design with nonvolatile memory technologies.

Degree: 2014, Penn State University

 The memory hierarchy, including processor caches and the main memory, is an important component of various computer systems. The memory hierarchy is becoming a fundamental… (more)

Subjects/Keywords: Memory hierarchy; Nonvolatile memory; Persistence; Memory/storage stack; Energy efficiency; Graphics memory; CMP; GPU

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zhao, J. (2014). Rethinking the memory hierarchy design with nonvolatile memory technologies. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/21345

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Zhao, Jishen. “Rethinking the memory hierarchy design with nonvolatile memory technologies.” 2014. Thesis, Penn State University. Accessed October 19, 2020. https://submit-etda.libraries.psu.edu/catalog/21345.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Zhao, Jishen. “Rethinking the memory hierarchy design with nonvolatile memory technologies.” 2014. Web. 19 Oct 2020.

Vancouver:

Zhao J. Rethinking the memory hierarchy design with nonvolatile memory technologies. [Internet] [Thesis]. Penn State University; 2014. [cited 2020 Oct 19]. Available from: https://submit-etda.libraries.psu.edu/catalog/21345.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zhao J. Rethinking the memory hierarchy design with nonvolatile memory technologies. [Thesis]. Penn State University; 2014. Available from: https://submit-etda.libraries.psu.edu/catalog/21345

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

22. Srikantaiah, Shekhar Shashi. Dynamic Shared Resource Management for Providing Predictable Performance in Multicore Processors .

Degree: 2011, Penn State University

 Chip multiprocessors (CMPs) are being accepted as the microprocessor architecture of choice and have received strong impetus from almost all leading chip manufactures. The dream… (more)

Subjects/Keywords: Multicore; Shared cache; predictable performance

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Srikantaiah, S. S. (2011). Dynamic Shared Resource Management for Providing Predictable Performance in Multicore Processors . (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/12062

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Srikantaiah, Shekhar Shashi. “Dynamic Shared Resource Management for Providing Predictable Performance in Multicore Processors .” 2011. Thesis, Penn State University. Accessed October 19, 2020. https://submit-etda.libraries.psu.edu/catalog/12062.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Srikantaiah, Shekhar Shashi. “Dynamic Shared Resource Management for Providing Predictable Performance in Multicore Processors .” 2011. Web. 19 Oct 2020.

Vancouver:

Srikantaiah SS. Dynamic Shared Resource Management for Providing Predictable Performance in Multicore Processors . [Internet] [Thesis]. Penn State University; 2011. [cited 2020 Oct 19]. Available from: https://submit-etda.libraries.psu.edu/catalog/12062.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Srikantaiah SS. Dynamic Shared Resource Management for Providing Predictable Performance in Multicore Processors . [Thesis]. Penn State University; 2011. Available from: https://submit-etda.libraries.psu.edu/catalog/12062

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

23. Muralidhara, Sai Prashanth. Reducing Interference in Memory Hierarchy Resources Using Application Aware Management.

Degree: 2011, Penn State University

 Aggressive technology scaling has resulted in an increase in number of cores being integrated on-chip. While on-chip cores are increasing at a fast rate, the… (more)

Subjects/Keywords: Multicores; memory hierarchy; caches; DRAM

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APA (6th Edition):

Muralidhara, S. P. (2011). Reducing Interference in Memory Hierarchy Resources Using Application Aware Management. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/12150

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Muralidhara, Sai Prashanth. “Reducing Interference in Memory Hierarchy Resources Using Application Aware Management.” 2011. Thesis, Penn State University. Accessed October 19, 2020. https://submit-etda.libraries.psu.edu/catalog/12150.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Muralidhara, Sai Prashanth. “Reducing Interference in Memory Hierarchy Resources Using Application Aware Management.” 2011. Web. 19 Oct 2020.

Vancouver:

Muralidhara SP. Reducing Interference in Memory Hierarchy Resources Using Application Aware Management. [Internet] [Thesis]. Penn State University; 2011. [cited 2020 Oct 19]. Available from: https://submit-etda.libraries.psu.edu/catalog/12150.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Muralidhara SP. Reducing Interference in Memory Hierarchy Resources Using Application Aware Management. [Thesis]. Penn State University; 2011. Available from: https://submit-etda.libraries.psu.edu/catalog/12150

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

24. Zhang, Yuanrui. CACHE-AWARE APPLICATION PARALLELIZATION AND OPTIMIZATION FOR MULTICORES .

Degree: 2011, Penn State University

 All trends clearly show that multicore machines will become the next generation mainstream computer architecture. One reason for this is the fact that it is… (more)

Subjects/Keywords: computation mapping and scheduling; data transformation; NuFFT data translation; NUCA based multicore; cache topology-aware; parallelization

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zhang, Y. (2011). CACHE-AWARE APPLICATION PARALLELIZATION AND OPTIMIZATION FOR MULTICORES . (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/12153

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Zhang, Yuanrui. “CACHE-AWARE APPLICATION PARALLELIZATION AND OPTIMIZATION FOR MULTICORES .” 2011. Thesis, Penn State University. Accessed October 19, 2020. https://submit-etda.libraries.psu.edu/catalog/12153.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Zhang, Yuanrui. “CACHE-AWARE APPLICATION PARALLELIZATION AND OPTIMIZATION FOR MULTICORES .” 2011. Web. 19 Oct 2020.

Vancouver:

Zhang Y. CACHE-AWARE APPLICATION PARALLELIZATION AND OPTIMIZATION FOR MULTICORES . [Internet] [Thesis]. Penn State University; 2011. [cited 2020 Oct 19]. Available from: https://submit-etda.libraries.psu.edu/catalog/12153.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zhang Y. CACHE-AWARE APPLICATION PARALLELIZATION AND OPTIMIZATION FOR MULTICORES . [Thesis]. Penn State University; 2011. Available from: https://submit-etda.libraries.psu.edu/catalog/12153

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

25. Ronell, Marc D. Bumble. A Parallel Architecture For Non-Deterministic Discrete Event.

Degree: 2008, Penn State University

 An architecture for a non-deterministic simulation machine is described and presented for the purposes of accelerating the simulation of road traffic. The thesis includes a… (more)

Subjects/Keywords: architecture; simulation; fpga; machine

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APA (6th Edition):

Ronell, M. D. B. (2008). A Parallel Architecture For Non-Deterministic Discrete Event. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/5847

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ronell, Marc D Bumble. “A Parallel Architecture For Non-Deterministic Discrete Event.” 2008. Thesis, Penn State University. Accessed October 19, 2020. https://submit-etda.libraries.psu.edu/catalog/5847.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ronell, Marc D Bumble. “A Parallel Architecture For Non-Deterministic Discrete Event.” 2008. Web. 19 Oct 2020.

Vancouver:

Ronell MDB. A Parallel Architecture For Non-Deterministic Discrete Event. [Internet] [Thesis]. Penn State University; 2008. [cited 2020 Oct 19]. Available from: https://submit-etda.libraries.psu.edu/catalog/5847.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ronell MDB. A Parallel Architecture For Non-Deterministic Discrete Event. [Thesis]. Penn State University; 2008. Available from: https://submit-etda.libraries.psu.edu/catalog/5847

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

26. Yoo, Jincheol. A TIQ Based CMOS Flash A/D Converter for System-on-Chip Applications.

Degree: 2008, Penn State University

 This thesis addresses a Threshold Inverter Quantization (TIQ) based CMOS flash analog-to-digital converter (ADC) for system-on-chip (SoC) applications. The TIQ technique, which uses two cascaded… (more)

Subjects/Keywords: Threshold Inverter Quantization (TIQ); Flash ADC; Analog-to-Digital Converter; System-on-Chip (SoC)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Yoo, J. (2008). A TIQ Based CMOS Flash A/D Converter for System-on-Chip Applications. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/6040

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yoo, Jincheol. “A TIQ Based CMOS Flash A/D Converter for System-on-Chip Applications.” 2008. Thesis, Penn State University. Accessed October 19, 2020. https://submit-etda.libraries.psu.edu/catalog/6040.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yoo, Jincheol. “A TIQ Based CMOS Flash A/D Converter for System-on-Chip Applications.” 2008. Web. 19 Oct 2020.

Vancouver:

Yoo J. A TIQ Based CMOS Flash A/D Converter for System-on-Chip Applications. [Internet] [Thesis]. Penn State University; 2008. [cited 2020 Oct 19]. Available from: https://submit-etda.libraries.psu.edu/catalog/6040.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yoo J. A TIQ Based CMOS Flash A/D Converter for System-on-Chip Applications. [Thesis]. Penn State University; 2008. Available from: https://submit-etda.libraries.psu.edu/catalog/6040

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

27. Kim, Soontae. ENERGY-EFFICIENT HIGH PERFORMANCE CACHE ARCHITECTURES.

Degree: 2008, Penn State University

 The demand for high-performance architectures and powerful battery-operated mobile devices has accentuated the need for low-power systems. In many media and embedded applications, the memory… (more)

Subjects/Keywords: energy; performance; caches

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kim, S. (2008). ENERGY-EFFICIENT HIGH PERFORMANCE CACHE ARCHITECTURES. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/6183

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kim, Soontae. “ENERGY-EFFICIENT HIGH PERFORMANCE CACHE ARCHITECTURES.” 2008. Thesis, Penn State University. Accessed October 19, 2020. https://submit-etda.libraries.psu.edu/catalog/6183.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kim, Soontae. “ENERGY-EFFICIENT HIGH PERFORMANCE CACHE ARCHITECTURES.” 2008. Web. 19 Oct 2020.

Vancouver:

Kim S. ENERGY-EFFICIENT HIGH PERFORMANCE CACHE ARCHITECTURES. [Internet] [Thesis]. Penn State University; 2008. [cited 2020 Oct 19]. Available from: https://submit-etda.libraries.psu.edu/catalog/6183.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kim S. ENERGY-EFFICIENT HIGH PERFORMANCE CACHE ARCHITECTURES. [Thesis]. Penn State University; 2008. Available from: https://submit-etda.libraries.psu.edu/catalog/6183

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

28. Degalahal, Vijay Sai. Soft Errors: Modeling And Interactions with Power Optimizations .

Degree: 2008, Penn State University

 Soft errors are radiation induced ionization events that cause errors in circuits. The circuit always recovers from these errors as they do not damage the… (more)

Subjects/Keywords: reliability in DSM; Soft errors; Single event upsets; low power VLSI

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Degalahal, V. S. (2008). Soft Errors: Modeling And Interactions with Power Optimizations . (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/6783

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Degalahal, Vijay Sai. “Soft Errors: Modeling And Interactions with Power Optimizations .” 2008. Thesis, Penn State University. Accessed October 19, 2020. https://submit-etda.libraries.psu.edu/catalog/6783.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Degalahal, Vijay Sai. “Soft Errors: Modeling And Interactions with Power Optimizations .” 2008. Web. 19 Oct 2020.

Vancouver:

Degalahal VS. Soft Errors: Modeling And Interactions with Power Optimizations . [Internet] [Thesis]. Penn State University; 2008. [cited 2020 Oct 19]. Available from: https://submit-etda.libraries.psu.edu/catalog/6783.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Degalahal VS. Soft Errors: Modeling And Interactions with Power Optimizations . [Thesis]. Penn State University; 2008. Available from: https://submit-etda.libraries.psu.edu/catalog/6783

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

29. Link, Greg. Temperature-Aware Computing .

Degree: 2008, Penn State University

 In the future, the peak temperature of a chip will be a primary design constraint. Higher temperatures can accelerate various chip failure mechanisms, reducing the… (more)

Subjects/Keywords: design automation; architecture; thermal; Temperature; hotspot; hot spot

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Link, G. (2008). Temperature-Aware Computing . (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/7038

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Link, Greg. “Temperature-Aware Computing .” 2008. Thesis, Penn State University. Accessed October 19, 2020. https://submit-etda.libraries.psu.edu/catalog/7038.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Link, Greg. “Temperature-Aware Computing .” 2008. Web. 19 Oct 2020.

Vancouver:

Link G. Temperature-Aware Computing . [Internet] [Thesis]. Penn State University; 2008. [cited 2020 Oct 19]. Available from: https://submit-etda.libraries.psu.edu/catalog/7038.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Link G. Temperature-Aware Computing . [Thesis]. Penn State University; 2008. Available from: https://submit-etda.libraries.psu.edu/catalog/7038

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

30. Srinivasan, Suresh. Toward Low Power and Reliable FPGA Design .

Degree: 2008, Penn State University

 Field Programmable Gate Arrays (FPGAs) are seen to be the emerging future architectures due to their extremely low NRE costs and tremendous design flexibility. This… (more)

Subjects/Keywords: Soft Errors; Leakage Power; Permanent Failures; FPGAs; Process Variations

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Srinivasan, S. (2008). Toward Low Power and Reliable FPGA Design . (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/7915

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Srinivasan, Suresh. “Toward Low Power and Reliable FPGA Design .” 2008. Thesis, Penn State University. Accessed October 19, 2020. https://submit-etda.libraries.psu.edu/catalog/7915.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Srinivasan, Suresh. “Toward Low Power and Reliable FPGA Design .” 2008. Web. 19 Oct 2020.

Vancouver:

Srinivasan S. Toward Low Power and Reliable FPGA Design . [Internet] [Thesis]. Penn State University; 2008. [cited 2020 Oct 19]. Available from: https://submit-etda.libraries.psu.edu/catalog/7915.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Srinivasan S. Toward Low Power and Reliable FPGA Design . [Thesis]. Penn State University; 2008. Available from: https://submit-etda.libraries.psu.edu/catalog/7915

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

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