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Oregon State University
1.
Yu, Wenhuan.
Design techniques for low power ADCs.
Degree: PhD, Electrical and Computer Engineering, 2010, Oregon State University
URL: http://hdl.handle.net/1957/14316 
► This dissertation presents an incremental analog-to-digital converter (ADC) with digital digital-to-analog converter (DAC) mismatch correction. A theoretical time-domain analysis technique was developed to predict the…
(more)
▼ This dissertation presents an incremental analog-to-digital converter (ADC) with digital digital-to-analog converter (DAC) mismatch correction. A theoretical time-domain analysis technique was developed to predict the noise performance of the incremental ADC, and a new optimization technique was proposed to minimize the output noise.
In the calibration mode, the incremental ADC itself is used to measure the mismatches of the internal multi-bit DAC. Three new calibration techniques, equation-solving calibration, inter-DAC mismatch calibration and modified “Sarhang-Nejad” calibration are proposed.
To verify the above techniques, a test chip was designed and fabricated in 0.18 µm CMOS process. The chip can work in single-sampling or double-sampling mode. Chopping with a fractal sequence is used to eliminate 1/f noise. The calibration circuit was implemented to calibrate the multi-bit DAC mismatches the in single-sampling mode and inter-DAC mismatches in the double-sampling mode.
Finally, two new design techniques for low-power ADCs, the two-step split-junction successive-approximation register (SAR) ADC and the hybrid cascaded ∆Σ ADC, are proposed.
Advisors/Committee Members: Temes, Gabor C. (advisor), Hanumolu, Pavan (committee member).
Subjects/Keywords: data converter; Analog-to-digital converters – Design and construction
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APA (6th Edition):
Yu, W. (2010). Design techniques for low power ADCs. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/14316
Chicago Manual of Style (16th Edition):
Yu, Wenhuan. “Design techniques for low power ADCs.” 2010. Doctoral Dissertation, Oregon State University. Accessed March 05, 2021.
http://hdl.handle.net/1957/14316.
MLA Handbook (7th Edition):
Yu, Wenhuan. “Design techniques for low power ADCs.” 2010. Web. 05 Mar 2021.
Vancouver:
Yu W. Design techniques for low power ADCs. [Internet] [Doctoral dissertation]. Oregon State University; 2010. [cited 2021 Mar 05].
Available from: http://hdl.handle.net/1957/14316.
Council of Science Editors:
Yu W. Design techniques for low power ADCs. [Doctoral Dissertation]. Oregon State University; 2010. Available from: http://hdl.handle.net/1957/14316
Oregon State University
2.
Gubbins, David Patrick.
Continuous time input pipeline ADCs.
Degree: PhD, Electrical and Computer Engineering, 2008, Oregon State University
URL: http://hdl.handle.net/1957/10160
► Analog-to-digital converters (ADCs) convert analog continuous time signals into discrete time, digital format. One precondition that must be met for conventional nyquist rate ADCs is…
(more)
▼ Analog-to-digital converters (ADCs) convert analog
continuous time signals into discrete time, digital format. One
precondition that must be met for conventional nyquist rate ADCs is
that the input signal must be suitably band-limited to an input
bandwidth less than the nyquist frequency. This mandates expensive
anti-alias filters which contribute to system noise and distortion
degradation. By choosing an OSR of 2 and adopting simple linear
phase filtering techniques, significant inherent anti-alias
filtering is achieved, avoiding the need for an explicit anti-alias
filter in many applications. Additionally the proposed continuous
time input pipeline ADC eases a number of other challenges present
in conventional switched capacitor ADCs:- sampled opamp noise
folding, sampling distortion, reduced ADC area, switched-capacitor
pipeline ADC input loading. Chapter 2 introduces the first
continuous time input pipeline ADC in the literature. This ADC,
while providing significant benefits, does not provide the inherent
filtering. Chapter 3 presents the first continuous time input
pipeline ADC with inherent anti-alias filtering.
Advisors/Committee Members: Moon, Un-Ku (advisor), Temes, Gabor C. (committee member).
Subjects/Keywords: analog; Pipelined ADCs – Design and construction – Mathematical models
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APA (6th Edition):
Gubbins, D. P. (2008). Continuous time input pipeline ADCs. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/10160
Chicago Manual of Style (16th Edition):
Gubbins, David Patrick. “Continuous time input pipeline ADCs.” 2008. Doctoral Dissertation, Oregon State University. Accessed March 05, 2021.
http://hdl.handle.net/1957/10160.
MLA Handbook (7th Edition):
Gubbins, David Patrick. “Continuous time input pipeline ADCs.” 2008. Web. 05 Mar 2021.
Vancouver:
Gubbins DP. Continuous time input pipeline ADCs. [Internet] [Doctoral dissertation]. Oregon State University; 2008. [cited 2021 Mar 05].
Available from: http://hdl.handle.net/1957/10160.
Council of Science Editors:
Gubbins DP. Continuous time input pipeline ADCs. [Doctoral Dissertation]. Oregon State University; 2008. Available from: http://hdl.handle.net/1957/10160
Oregon State University
3.
Gande, Manideep.
Design techniques for time based data converters.
Degree: PhD, Electrical and Computer Engineering, 2013, Oregon State University
URL: http://hdl.handle.net/1957/39773
► Modern day CMOS processes are characterized by voltage scaling and geometry scaling. Geometry scaling helps reduce gate delays, thereby aiding in the design of data…
(more)
▼ Modern day CMOS processes are characterized by voltage scaling and geometry scaling. Geometry scaling helps reduce gate delays, thereby aiding in the design of data converters which use time based processing. Another artifact of geometry scaling is the increase in complexity of digital circuitry available on traditional analog ICs, as digital signal processing could be used to compensate for analog inaccuracies. Calibration assisted analog-to-digital converters(ADCs), software defined radio, digital phase locked loops, etc... have all gained from improvements in the digital processing available on chip. This thesis focusses on data converters which utilize the above features of modern day CMOS processes.
The thesis is primarily divided into two parts. The first part focuses on a technique to convert the time information into a digital word. A high resolution time-to-digital converter (TDC) architecture is proposed which combines the principles of noise-shaping integrating quantizer and charge-pump to build a third-order delta-sigma TDC using a dedicated feedback DAC. Fabricated in a 0.13µm CMOS process, the prototype TDC achieves better than 71dB DR for a 2.8MHz signal bandwidth.
The second part of the thesis proposes a blind digital calibration technique to remove non-linearity in any traditional ADC architectures. The proposed technique uses the concept of downsampling and orthogonality of sinusoidal waves to estimate the harmonic distortion in ADCs and can be used to calibrate multiple harmonics simultaneously. As a proof of concept, the algorithm is demonstrated on a first-order ring oscillator based delta-sigma ADC, whose performance is harmonic distortion limited. Built in 0.13µm CMOS process, the algorithm improves the SNDR of the ADC by 39dB while improving SFDR by 45 dB.
Advisors/Committee Members: Moon, Un-Ku (advisor), Temes, Gabor C. (committee member).
Subjects/Keywords: Time based data converters; Analog-to-digital converters
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APA (6th Edition):
Gande, M. (2013). Design techniques for time based data converters. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/39773
Chicago Manual of Style (16th Edition):
Gande, Manideep. “Design techniques for time based data converters.” 2013. Doctoral Dissertation, Oregon State University. Accessed March 05, 2021.
http://hdl.handle.net/1957/39773.
MLA Handbook (7th Edition):
Gande, Manideep. “Design techniques for time based data converters.” 2013. Web. 05 Mar 2021.
Vancouver:
Gande M. Design techniques for time based data converters. [Internet] [Doctoral dissertation]. Oregon State University; 2013. [cited 2021 Mar 05].
Available from: http://hdl.handle.net/1957/39773.
Council of Science Editors:
Gande M. Design techniques for time based data converters. [Doctoral Dissertation]. Oregon State University; 2013. Available from: http://hdl.handle.net/1957/39773
Oregon State University
4.
Lee, Kyehyung.
High efficiency delta-sigma modulation data converters.
Degree: PhD, Electrical and Computer Engineering, 2008, Oregon State University
URL: http://hdl.handle.net/1957/8457
► Enabled by continued device scaling in CMOS technology, more and more functions that were previously realized in separate chips are getting integrated on a single…
(more)
▼ Enabled by continued device scaling in CMOS technology, more and more functions that were previously realized in separate chips are getting integrated on a single chip nowadays. Integration on silicon has opened the door to new portable wireless applications, and initiated a widespread use of these devices in our common everyday life. Wide signal bandwidth, high linearity and dynamic range, and low power dissipation are required of embedded data converters that are the performance-limiting key building blocks of those systems. Thus, power-efficient and highly-linear data conversion over wide range of signal bands is essential to get the full benefits from device scaling. This continued trend keeps innovation in the design of data converter continuing.
Traditionally, delta-sigma modulation data converters proved to be very effective in applications where high resolution was necessary in a relatively narrow signal band. There have been active research efforts across academia and industry on the extension of achievable signal bandwidth without compromising the performance of these data converters. In this dissertation, architectural innovations, combined with effective design techniques for delta-sigma modulation data converters, are presented to overcome the associated limitations. The effectiveness of the proposed approaches is demonstrated by test results for the following
state-of-the-art prototype designs: (1) a 0.8 V, 2.6 mW, 88 dB dual-channel audio delta-sigma modulation D/A converter with headphone driver; (2) an 88 dB ring-coupled delta-sigma ADC with 1.9 MHz bandwidth and -102.4 dB THD; (3) a multi-cell noise-coupled delta-sigma ADC with 1.9 MHz bandwidth, 88 dB DR, and -98 dB THD; (4) an 8.1 mW, 82 dB self-coupled delta-sigma ADC with 1.9 MHz bandwidth and -97 dB THD; (5) a noise-coupled time-interleaved delta-sigma ADC with 4.2 MHz bandwidth, -98 dB THD, and 79 dB SNDR; (6) a noise-coupled time-interleaved delta-sigma ADC with 2.5 MHz bandwidth, -104 dB THD, and 81 dB SNDR. As an extension of this research, two novel architectures for efficient double-sampling delta-sigma ADCs and improved low-distortion delta-sigma ADC are proposed, and validated by extensive simulations.
Advisors/Committee Members: Temes, Gabor C. (advisor), Liu, Huaping (committee member).
Subjects/Keywords: delta-sigma modulation; Analog-to-digital converters – Design and construction
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APA ·
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APA (6th Edition):
Lee, K. (2008). High efficiency delta-sigma modulation data converters. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/8457
Chicago Manual of Style (16th Edition):
Lee, Kyehyung. “High efficiency delta-sigma modulation data converters.” 2008. Doctoral Dissertation, Oregon State University. Accessed March 05, 2021.
http://hdl.handle.net/1957/8457.
MLA Handbook (7th Edition):
Lee, Kyehyung. “High efficiency delta-sigma modulation data converters.” 2008. Web. 05 Mar 2021.
Vancouver:
Lee K. High efficiency delta-sigma modulation data converters. [Internet] [Doctoral dissertation]. Oregon State University; 2008. [cited 2021 Mar 05].
Available from: http://hdl.handle.net/1957/8457.
Council of Science Editors:
Lee K. High efficiency delta-sigma modulation data converters. [Doctoral Dissertation]. Oregon State University; 2008. Available from: http://hdl.handle.net/1957/8457
Oregon State University
5.
Meng, Xin.
Wideband discrete-time delta-sigma analog-to-digital converters with shifted loop delays.
Degree: PhD, Electrical and Computer Engineering, 2015, Oregon State University
URL: http://hdl.handle.net/1957/55892
► Low-distortion architecture is widely used in wideband discrete-time switched-capacitor delta-sigma ADC design. However, it suffers from the power-hungry active adder and critical timing for quantization…
(more)
▼ Low-distortion architecture is widely used in wideband discrete-time switched-capacitor delta-sigma ADC design. However, it suffers from the power-hungry active adder and critical timing for quantization and dynamic element matching (DEM). To solve this problem, this dissertation presents a delta-sigma modulator architecture with shifted loop delays. In this project, shifted loop delays (SLD) technique can relax the speed requirements of the quantizer and the dynamic element matching (DEM) block, and eliminate the active adder. An implemented 0.18 um CMOS prototype with the proposed architecture provided 81.6 dB SNDR, 81.8 dB dynamic range, and -95.6 dB THD in a signal bandwidth of 4 MHz. It dissipates 19.2 mW with a 1.6 V power supply. The conventional low-distortion ADC was also implemented on the same chip for comparison. The new circuit has superior performance, and dissipates 25% less power (19.2 mW vs. 24.9 mW) than the conventional one. The figure-of-merit for the ADC with SLD is among the best reported for wideband discrete-time ADCs, and is almost 40% better than that of the conventional ADC.
The second project describes two techniques to enhance the noise shaping function in the proposed low-distortion ΔΣ modulator with shifted loop delays. One is self-noise coupling based on low-distortion ΔΣ structure; the other is noise-coupled time-interleaved ΔΣ modulator. Both architectures use shifted loop delays to relax the critical timing constraints in the modulator feedback path, then to save power consumption of each block in the modulators. Two ΔΣ ADCs were analyzed and simulated in a 0.18um CMOS technology. The simulation results highly verify the effectiveness of the proposed structure.
The third system describes the design technique for double-sampled wideband ΔΣ ADCs with shifted loop delays (SLD). The added loop delay in the feedback branch relaxes the critical timing for DEM logic. Delay shifting can be combined with such useful techniques as low-distortion circuitry and noise coupling for wideband ΔΣ modulators. The presented techniques relax the timing for inherent quantization delay, reduce the speed requirements for the critical circuit blocks, and achieve power efficiency by replacing the power-hungry blocks normally used in the modulators. Analysis of all architectures allows the choice of the most power-efficient topology for a wideband ΔΣ modulator. The proposed second-order and third-order ΔΣ modulators were designed and simulated to verify the effectiveness of the shifted loop delays techniques.
Advisors/Committee Members: Temes, Gabor C. (advisor), Wang, Alan (committee member).
Subjects/Keywords: ADC; Analog-to-digital converters – Design and construction
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APA ·
Chicago ·
MLA ·
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CSE |
Export
to Zotero / EndNote / Reference
Manager
APA (6th Edition):
Meng, X. (2015). Wideband discrete-time delta-sigma analog-to-digital converters with shifted loop delays. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/55892
Chicago Manual of Style (16th Edition):
Meng, Xin. “Wideband discrete-time delta-sigma analog-to-digital converters with shifted loop delays.” 2015. Doctoral Dissertation, Oregon State University. Accessed March 05, 2021.
http://hdl.handle.net/1957/55892.
MLA Handbook (7th Edition):
Meng, Xin. “Wideband discrete-time delta-sigma analog-to-digital converters with shifted loop delays.” 2015. Web. 05 Mar 2021.
Vancouver:
Meng X. Wideband discrete-time delta-sigma analog-to-digital converters with shifted loop delays. [Internet] [Doctoral dissertation]. Oregon State University; 2015. [cited 2021 Mar 05].
Available from: http://hdl.handle.net/1957/55892.
Council of Science Editors:
Meng X. Wideband discrete-time delta-sigma analog-to-digital converters with shifted loop delays. [Doctoral Dissertation]. Oregon State University; 2015. Available from: http://hdl.handle.net/1957/55892
Oregon State University
6.
Wang, Tao.
Low-power high-resolution delta-sigma ADC design techniques.
Degree: PhD, Electrical and Computer Engineering, 2012, Oregon State University
URL: http://hdl.handle.net/1957/29740
► This dissertation presents a low-power high-resolution delta-sigma ADC. Two new architectural design techniques are proposed to reduce the power dissipation of the ADC. Compared to…
(more)
▼ This dissertation presents a low-power high-resolution delta-sigma ADC. Two new architectural design techniques are proposed to reduce the power dissipation of the ADC. Compared to the conventional active adder, the direct charge transfer (DCT) adder greatly saves power by keeping the feedback factor of the active adder unity. However, the inherent delay originated from the DCT adder will cause instability to the modulator and complex additional branches are usually needed to stabilize the loop. A simple and power-efficient technique is proposed to absorb the delay from the DCT adder and the instability issue is therefore solved. Another proposed low-power design technique is to feed differentiated inverted quantization noise to the input of the last integrator. The modulator noise-shaping order with this proposed technique is effectively increased from two to three without adding additional active elements.
The delta-sigma ADC with the proposed architectural design techniques has been implemented in transistor-level and fabricated in 0.18 µm CMOS technology. Measurement results showed a SNDR of 99.3 dB, a DR of 101.3 dB and a SFDR of 112 dB over 20 kHz signal bandwidth, resulting in a very low figure-of-merit (FoM) in its application category. Finally, two new circuit ideas, low-power parasitic-insensitive switched-capacitor integrator for delta-sigma ADCs and switched-resistor tuning technique for highly linear Gm-
C filter design are presented.
Advisors/Committee Members: Temes, Gabor C. (advisor), Hanumolu, Pavan (committee member).
Subjects/Keywords: ADC; Analog-to-digital converters – Design and construction
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APA ·
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MLA ·
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APA (6th Edition):
Wang, T. (2012). Low-power high-resolution delta-sigma ADC design techniques. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/29740
Chicago Manual of Style (16th Edition):
Wang, Tao. “Low-power high-resolution delta-sigma ADC design techniques.” 2012. Doctoral Dissertation, Oregon State University. Accessed March 05, 2021.
http://hdl.handle.net/1957/29740.
MLA Handbook (7th Edition):
Wang, Tao. “Low-power high-resolution delta-sigma ADC design techniques.” 2012. Web. 05 Mar 2021.
Vancouver:
Wang T. Low-power high-resolution delta-sigma ADC design techniques. [Internet] [Doctoral dissertation]. Oregon State University; 2012. [cited 2021 Mar 05].
Available from: http://hdl.handle.net/1957/29740.
Council of Science Editors:
Wang T. Low-power high-resolution delta-sigma ADC design techniques. [Doctoral Dissertation]. Oregon State University; 2012. Available from: http://hdl.handle.net/1957/29740
Oregon State University
7.
Kuo, Ming-Hung.
Low-power high-linearity digital-to-analog converters.
Degree: MS, Electrical and Computer Engineering, 2012, Oregon State University
URL: http://hdl.handle.net/1957/28313
► In this thesis work, a design of 14-bit, 20MS/s segmented digital-to-analog converter (DAC) is presented. The segmented DAC uses switched-capacitor configuration to implement 8 (LSB)…
(more)
▼ In this thesis work, a design of 14-bit, 20MS/s segmented digital-to-analog converter
(DAC) is presented. The segmented DAC uses switched-capacitor configuration to
implement 8 (LSB) + 6 (MSB) segmented architecture to achieve high performance for
minimum area. The implemented LSB DAC is based on quasi-passive pipelined DAC
that has been proven to provide low power and high speed operation. Typically, capacitor
matching is the best among all integrated circuit components but the mismatch among
nominally equal value capacitors will introduce nonlinear distortion. By using dynamic
element matching (DEM) technique in the MSB DAC, the nonlinearity caused by
capacitor mismatch is greatly reduced. The output buffer employed direct charge transfer
(DCT) technique that can minimize kT/
C noise without increasing the power dissipation.
This segmented DAC is designed and simulated in 0.18 μm CMOS technology, and the
simulated core DAC block only consumes 403 μW.
Advisors/Committee Members: Temes, Gabor C. (advisor), Moon, Un-Ku (committee member).
Subjects/Keywords: DAC; Digital-to-analog converters – Design and construction
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APA ·
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Export
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APA (6th Edition):
Kuo, M. (2012). Low-power high-linearity digital-to-analog converters. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/28313
Chicago Manual of Style (16th Edition):
Kuo, Ming-Hung. “Low-power high-linearity digital-to-analog converters.” 2012. Masters Thesis, Oregon State University. Accessed March 05, 2021.
http://hdl.handle.net/1957/28313.
MLA Handbook (7th Edition):
Kuo, Ming-Hung. “Low-power high-linearity digital-to-analog converters.” 2012. Web. 05 Mar 2021.
Vancouver:
Kuo M. Low-power high-linearity digital-to-analog converters. [Internet] [Masters thesis]. Oregon State University; 2012. [cited 2021 Mar 05].
Available from: http://hdl.handle.net/1957/28313.
Council of Science Editors:
Kuo M. Low-power high-linearity digital-to-analog converters. [Masters Thesis]. Oregon State University; 2012. Available from: http://hdl.handle.net/1957/28313
Oregon State University
8.
Ma, Chao.
Energy-efficient clock generation for communication and computing systems using injection locking.
Degree: MS, Electrical and Computer Engineering, 2012, Oregon State University
URL: http://hdl.handle.net/1957/33929
► The design of high-performance, high-speed clock generation and distribution becomes challenging in terms of phase noise, jitter and power consumption, due to the fast development…
(more)
▼ The design of high-performance, high-speed clock generation and distribution becomes challenging in terms of phase noise, jitter and power consumption, due to the fast development of communication and computing systems. Injection locking is a promising clocking technique since it can significantly improve the energy efficiency, suppress the phase noise of the ring oscillator, enable a fast startup and conveniently generate multiple time-interleaved phases.
A quasi-linear model of injection-locked ring oscillator (ILRO) is utilized to mathematically formulate the frequency and time domain characteristics of the system, as well as the phase noise shaping and jitter tracking behavior. The settling behavior of ILRO is also exploited and shows a strong dependence on the locking range and the initial phase difference of the injected and the resultant oscillation signals.
A forwarded-clock synchronization based on injection locking is designed for a 10 Gb/s photonic interconnect according to the specific features of optical links. A single clock recovery can be used for all the four channels, resulting in a large amount of power and area saving. The applications of sub-harmonic and super-harmonic injection locking in wireless communications for frequency multiplying and division are also discussed.
Advisors/Committee Members: Chiang, Patrick Y. (advisor), Temes, Gabor C. (committee member).
Subjects/Keywords: Clock generation; Injection-locked ring oscillators; Integrated circuits
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APA ·
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APA (6th Edition):
Ma, C. (2012). Energy-efficient clock generation for communication and computing systems using injection locking. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/33929
Chicago Manual of Style (16th Edition):
Ma, Chao. “Energy-efficient clock generation for communication and computing systems using injection locking.” 2012. Masters Thesis, Oregon State University. Accessed March 05, 2021.
http://hdl.handle.net/1957/33929.
MLA Handbook (7th Edition):
Ma, Chao. “Energy-efficient clock generation for communication and computing systems using injection locking.” 2012. Web. 05 Mar 2021.
Vancouver:
Ma C. Energy-efficient clock generation for communication and computing systems using injection locking. [Internet] [Masters thesis]. Oregon State University; 2012. [cited 2021 Mar 05].
Available from: http://hdl.handle.net/1957/33929.
Council of Science Editors:
Ma C. Energy-efficient clock generation for communication and computing systems using injection locking. [Masters Thesis]. Oregon State University; 2012. Available from: http://hdl.handle.net/1957/33929
Oregon State University
9.
Nishida, Yoshio.
Improved design techniques for analog and mixed circuits.
Degree: PhD, Electrical and Computer Engineering, 2008, Oregon State University
URL: http://hdl.handle.net/1957/7985
► Although the digital revolution can realize many of past analog components in the digital forms, our world is surrounded with analog signals such as voice,…
(more)
▼ Although the digital revolution can realize many of past analog components in the digital forms, our world is surrounded with analog signals such as voice, temperature, etc. The bridge between these two worlds is one of key performance limitations among overall systems and it includes analog filters and data converters.
This thesis studies two design techniques with respect to the improvement of the performances of the bridge circuits; one is an implementation of the delta-sigma A/D converter with a new architecture and another is a proposed correlated double-sampling technique for continuous analog filters. A circuit implementation for the new architecture converter is proposed and implemented in AKM 0.18µm CMOS technology. The test results show that the modulator achieves 72dB of SNDR from the 1.8 V supply voltage. A newly proposed correlated double sampling technique compensates the gain error of a high-Q Tow-Thomas filter which originates from the op-amp imperfections. The gain error is reduced to 0.6dB from 2.5dB with the correlated double sampling technique.
Advisors/Committee Members: Temes, Gabor C. (advisor), Magana, Mario (committee member).
Subjects/Keywords: analog; Analog-to-digital converters – Design
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APA (6th Edition):
Nishida, Y. (2008). Improved design techniques for analog and mixed circuits. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/7985
Chicago Manual of Style (16th Edition):
Nishida, Yoshio. “Improved design techniques for analog and mixed circuits.” 2008. Doctoral Dissertation, Oregon State University. Accessed March 05, 2021.
http://hdl.handle.net/1957/7985.
MLA Handbook (7th Edition):
Nishida, Yoshio. “Improved design techniques for analog and mixed circuits.” 2008. Web. 05 Mar 2021.
Vancouver:
Nishida Y. Improved design techniques for analog and mixed circuits. [Internet] [Doctoral dissertation]. Oregon State University; 2008. [cited 2021 Mar 05].
Available from: http://hdl.handle.net/1957/7985.
Council of Science Editors:
Nishida Y. Improved design techniques for analog and mixed circuits. [Doctoral Dissertation]. Oregon State University; 2008. Available from: http://hdl.handle.net/1957/7985
Oregon State University
10.
Wang, Yan.
Design techniques for wideband low-power Delta-Sigma analog-to-digital converters.
Degree: PhD, Electrical and Computer Engineering, 2009, Oregon State University
URL: http://hdl.handle.net/1957/13664
► Delta-Sigma (ΔΣ) analog-to-digital converters (ADCs) are traditionally used in high quality audio systems, instrumentation and measurement (I&M) and biomedical devices. With the continued downscaling of…
(more)
▼ Delta-Sigma (ΔΣ) analog-to-digital converters (ADCs) are traditionally used in high quality audio systems, instrumentation and measurement (I&M) and biomedical devices. With the continued downscaling of CMOS technology, they are becoming popular in wideband applications such as wireless and wired communication systems,high-definition television and radar systems. There are two general realizations of a ΔΣ modulator. One is based on the discrete-time (DT) switched-capacitor (SC) circuitry and the other employs continuous-time (CT) circuitry. Compared to a CT
structure, the DT ΔΣ ADC is easier to analyze and design, is more robust to process variations and jitter noise, and is more flexible in the multi-mode applications. On the other hand, the CT ΔΣ ADC does not suffer from the strict settling accuracy requirement for the loop filter and thus can achieve lower power dissipation and higher sampling frequency than its DT counterpart.
In this thesis, both DT and CT ΔΣ ADCs are investigated. Several design innovations, in both system-level and circuit-level, are proposed to achieve lower power consumption and wider signal bandwidth.
For DT ΔΣ ADCs, a new dynamic-biasing scheme is proposed to reduce opamp bias current and the associated signal-dependent harmonic distortion is minimized by using the low-distortion architecture. The technique was verified in a 2.5MHz BW and 13bit dynamic range DT ΔΣ ADC. In addition, a second-order noise coupling technique is presented to save two integrators for the loop filter, and to achieve low power dissipation. Also, a direct-charge-transfer (DCT) technique is suggested to reduce the speed requirements of the adder, which is also preferable in wideband low-power applications.
For CT ΔΣ ADCs, a wideband low power CT 2-2 MASH has been designed. High linearity performance was achieved by using a modified low-distortion technique, and the modulator achieves higher noise-shaping ability than the single stage structure due to the inter-stage gain. Also, the quantization noise leakage due to analog circuit non-idealities can be adaptively compensated by a designed digital calibration filter. Using a 90nm process, simulation of the modulator predicts a 12bit resolution within 20MHz BW and consumes only 25mW for analog circuitry. In addition, the noise-coupling technique is investigated and proposed for the design of CT ΔΣ ADCs and it is promising to achieve low power dissipation for wideband applications.
Finally, the application of noise-coupling technique is extended and introduced to high-accuracy incremental data converters. Low power dissipation can be expected.
Advisors/Committee Members: Temes, Gabor C. (advisor), Moon, Un-ku (committee member).
Subjects/Keywords: wideband; Analog-to-digital converters – Design and construction
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APA (6th Edition):
Wang, Y. (2009). Design techniques for wideband low-power Delta-Sigma analog-to-digital converters. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/13664
Chicago Manual of Style (16th Edition):
Wang, Yan. “Design techniques for wideband low-power Delta-Sigma analog-to-digital converters.” 2009. Doctoral Dissertation, Oregon State University. Accessed March 05, 2021.
http://hdl.handle.net/1957/13664.
MLA Handbook (7th Edition):
Wang, Yan. “Design techniques for wideband low-power Delta-Sigma analog-to-digital converters.” 2009. Web. 05 Mar 2021.
Vancouver:
Wang Y. Design techniques for wideband low-power Delta-Sigma analog-to-digital converters. [Internet] [Doctoral dissertation]. Oregon State University; 2009. [cited 2021 Mar 05].
Available from: http://hdl.handle.net/1957/13664.
Council of Science Editors:
Wang Y. Design techniques for wideband low-power Delta-Sigma analog-to-digital converters. [Doctoral Dissertation]. Oregon State University; 2009. Available from: http://hdl.handle.net/1957/13664
Oregon State University
11.
Shen, Weilun.
Low-power double-sampled delta-sigma modulator for broadband applications.
Degree: PhD, Electrical and Computer Engineering, 2010, Oregon State University
URL: http://hdl.handle.net/1957/17568
► High speed and high resolution analog-to-digital converter is a key building block for broadband wireless communications, high definition video applications, medical images and so on.…
(more)
▼ High speed and high resolution analog-to-digital converter is a key building block for broadband wireless communications, high definition video applications, medical images and so on. By leveraging the down scaling of the latest CMOS technology and the noise shaping properties, delta-sigma (ΔΣ) ADCs are able to achieve wide-band operation and high accuracy simultaneously. At first in this thesis, two novel techniques which can be applied to high performance ΔΣ ADC design are proposed. The first one is a modulator architectural innovation that is able to effectively solve the feedback timing constraints in a double-sampled ΔΣ modulator. The second one is a transistor level improvement to reduce the hardware consumption in a standard Date Weighted Averaging (DWA) realization.
Next, charge-pump (CP) based switched-capacitor (SC) integrator is discussed. A cross-coupling technique is proposed to eliminate parasitic capacitor effect in a CP based SC integrator. Also design methodologies are introduced to incorporate a modified CP based SC integrator into a low-distortion ΔΣ modulator. A second-order ΔΣ modulator was designed and simulated to verify the proposed modulator topology.
Finally, design of a double-sampled broadband 12-bit ΔΣ modulator is presented. To achieve very low power consumption, this modulator utilizes the following two key design techniques:
1. Double sampled integrator to increase the effective over-sampling ratio.
2. Capacitor reset technique allows the use of only one feedback DAC at the front end of the modulator to completely eliminate the quantization noise folding back.
A 2+2 cascaded topology with 3-bit internal quantizer is used in this ΔΣ modulator to adequately suppress the quantization noise while guarantee the loop stability. This ΔΣ modulator was fabricated in a 90nm digital CMOS process and achieves an SNDR of 70dB within a 5MHz signal bandwidth. The modulator occupies a silicon area of 0.5mm² and consumes 10mW with a supply voltage of 1.2V.
Advisors/Committee Members: Temes, Gabor C. (advisor), Moon, Un-Ku (committee member).
Subjects/Keywords: Analog-to-Digital Converter; Modulators (Electronics)
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APA (6th Edition):
Shen, W. (2010). Low-power double-sampled delta-sigma modulator for broadband applications. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/17568
Chicago Manual of Style (16th Edition):
Shen, Weilun. “Low-power double-sampled delta-sigma modulator for broadband applications.” 2010. Doctoral Dissertation, Oregon State University. Accessed March 05, 2021.
http://hdl.handle.net/1957/17568.
MLA Handbook (7th Edition):
Shen, Weilun. “Low-power double-sampled delta-sigma modulator for broadband applications.” 2010. Web. 05 Mar 2021.
Vancouver:
Shen W. Low-power double-sampled delta-sigma modulator for broadband applications. [Internet] [Doctoral dissertation]. Oregon State University; 2010. [cited 2021 Mar 05].
Available from: http://hdl.handle.net/1957/17568.
Council of Science Editors:
Shen W. Low-power double-sampled delta-sigma modulator for broadband applications. [Doctoral Dissertation]. Oregon State University; 2010. Available from: http://hdl.handle.net/1957/17568
Oregon State University
12.
Rajaee, Omid.
Design of low OSR, high precision analog-to-digital converters.
Degree: PhD, Electrical and Computer Engineering, 2010, Oregon State University
URL: http://hdl.handle.net/1957/19654
► Advances in electronic systems have lead to the demand for high resolution, high bandwidth Analog-to-Digital Converters (ADCs). Oversampled ADCs are well- known for high accuracy…
(more)
▼ Advances in electronic systems have lead to the demand for high resolution, high bandwidth Analog-to-Digital Converters (ADCs). Oversampled ADCs are well- known for high accuracy applications since they benefit from noise shaping and they usually do not need highly accurate components. However, as a consequence of oversampling, they have limited signal bandwidth. The signal bandwidth (BW) of oversampled ADCs can be increased either by increasing the sampling rate or reducing the oversampling ratio (OSR). Reducing OSR is a more promising method for increasing the BW, since the sampling speed is usually limited by the technology. The advantageous properties (e.g. low in-band quantization, relaxed accuracy requirements of components) of oversampled ADCs are usually diminished at lower OSRs and preserving these properties requires complicated and power hungry architectures.
In this thesis, different combinations of delta-sigma and pipelined ADCs are explored and new techniques for designing oversampled ADCs are proposed. A Hybrid Delta-Sigma/Pipelined (HDSP) ADC is presented. This ADC uses a pipelined ADC as the quantizer of a single-loop delta-sigma modulator and benefits from
the aggressive quantization of the pipelined quantizer at low OSRs. A Noise-Shaped Pipelined ADC is proposed which exploits a delta-sigma modulator as the sub-ADC of a pipeline stage to reduce the sensitivity to the analog imperfection. Three prototype ADCs were fabricated in 0.18μm CMOS technology to verify the effectiveness of the proposed techniques. The performance of these architectures is among the best reported for high bandwidth oversampled ADCs.
Advisors/Committee Members: Moon, Un-Ku (advisor), Temes, Gabor C. (committee member).
Subjects/Keywords: Oversampled ADC; Analog-to-digital converters – Design and construction
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APA (6th Edition):
Rajaee, O. (2010). Design of low OSR, high precision analog-to-digital converters. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/19654
Chicago Manual of Style (16th Edition):
Rajaee, Omid. “Design of low OSR, high precision analog-to-digital converters.” 2010. Doctoral Dissertation, Oregon State University. Accessed March 05, 2021.
http://hdl.handle.net/1957/19654.
MLA Handbook (7th Edition):
Rajaee, Omid. “Design of low OSR, high precision analog-to-digital converters.” 2010. Web. 05 Mar 2021.
Vancouver:
Rajaee O. Design of low OSR, high precision analog-to-digital converters. [Internet] [Doctoral dissertation]. Oregon State University; 2010. [cited 2021 Mar 05].
Available from: http://hdl.handle.net/1957/19654.
Council of Science Editors:
Rajaee O. Design of low OSR, high precision analog-to-digital converters. [Doctoral Dissertation]. Oregon State University; 2010. Available from: http://hdl.handle.net/1957/19654
Oregon State University
13.
Tong, Tao.
Design techniques for successive approximation register analog-to-digital converters.
Degree: MS, Electrical and Computer Engineering, 2011, Oregon State University
URL: http://hdl.handle.net/1957/22662
► Successive approximation register analog-to-digital converters (SAR ADCs) have been widely used for medium-speed, medium-resolution applications due to their excellent power efficiency and digital compatibility. Recently,…
(more)
▼ Successive approximation register analog-to-digital converters (SAR ADCs) have been widely used for medium-speed, medium-resolution applications due to their excellent power efficiency and digital compatibility. Recently, SAR ADCs are also penetrating into the applications which have been earlier dominated by delta-sigma ADCs and pipeline ADCs. However, the resolution of SAR ADCs is limited by component mismatch, and their speed is generally slow due to serial operation. In this work, several system innovations and design techniques are investigated for SAR ADCs. First, a semi-synchronous clocking is proposed to optimize the comparator resolving time and DAC settling time in the SAR conversion. Simulations show a 40% speed-up compared with conventional synchronous processing. A self-calibration technique to correct the capacitor mismatch error is also introduced. The proposed calibration algorithm is verified to be insensitive to the non-idealities in the calibration DACs.
Advisors/Committee Members: Temes, Gabor C. (advisor), Moon, Un-Ku (committee member).
Subjects/Keywords: analog-to-digital converters
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APA (6th Edition):
Tong, T. (2011). Design techniques for successive approximation register analog-to-digital converters. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/22662
Chicago Manual of Style (16th Edition):
Tong, Tao. “Design techniques for successive approximation register analog-to-digital converters.” 2011. Masters Thesis, Oregon State University. Accessed March 05, 2021.
http://hdl.handle.net/1957/22662.
MLA Handbook (7th Edition):
Tong, Tao. “Design techniques for successive approximation register analog-to-digital converters.” 2011. Web. 05 Mar 2021.
Vancouver:
Tong T. Design techniques for successive approximation register analog-to-digital converters. [Internet] [Masters thesis]. Oregon State University; 2011. [cited 2021 Mar 05].
Available from: http://hdl.handle.net/1957/22662.
Council of Science Editors:
Tong T. Design techniques for successive approximation register analog-to-digital converters. [Masters Thesis]. Oregon State University; 2011. Available from: http://hdl.handle.net/1957/22662
Oregon State University
14.
Oh, Taehwan.
Power efficient analog-to-digital converters using both voltage and time domain information.
Degree: PhD, Electrical and Computer Engineering, 2013, Oregon State University
URL: http://hdl.handle.net/1957/39042
► As advanced wired and wireless communication systems attempt to achieve higher performance, the demand for high resolution and wide signal bandwidth in their associated ADCs…
(more)
▼ As advanced wired and wireless communication systems attempt to achieve higher performance, the demand for high resolution and wide signal bandwidth in their associated ADCs is strongly increased. Recently, time-domain quantization has drawn attention from its scalability in deep submicron CMOS processes. Furthermore, there are several interesting aspects of time-domain quantizer by processing the signal in time rather than only in voltage domain especially for power efficiency. This research focuses on developing a new architecture for power efficient, high resolution ADCs using both voltage and time domain information.
As a first approach, a new ΔƩ ADC based on a noise-shaped two-step integrating quantizer which quantizes the signal in voltage and time domains is presented. Attaining an extra order of noise-shaping from the integrating quantizer, the proposed ΔƩ ADC manifests a second-order noise-shaping with a first-order loop filter. Furthermore, this quantizer provides an 8b uantization in itself, drastically reducing the oversampling requirement. The proposed ADC also incorporates a new feedback DAC topology that alleviates the feedback DAC complexity of a two-step 8b quantizer. The measured results of the prototype ADC implemented in a 0.13μm CMOS demonstrate peak SNDR of 70.7dB (11.5b ENOB) at 8.1mW power, with an 8x OSR at 80MHz sampling frequency.
To further improve ADC performance, a Nyquist ADC based on a time-based pipelined TDC is also proposed as a second approach. In this work, a simple V-T conversion scheme with a cheap low gain amplifier in its first stage and a hybrid time-domain quantization stage based on simple charge pump and capacitive DAC in its backend stages, are also proposed to improve ADC linearity and power efficiency. Using voltage and time domain information, the proposed ADC architecture is beneficial for both resolution and power efficiency, with MSBs resolved in voltage domain and LSBs in time domain. The measured results of the prototype ADC implemented in a 0.13μm CMOS demonstrate peak SNDR of 69.3dB (11.2b ENOB) at 6.38mW power and 70MHz sampling frequency. The FOM is 38.2fJ/conversion-step.
Advisors/Committee Members: Moon, Un-Ku (advisor), Temes, Gabor C. (committee member).
Subjects/Keywords: Delta-sigma; Analog-to-digital converters
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APA ·
Chicago ·
MLA ·
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CSE |
Export
to Zotero / EndNote / Reference
Manager
APA (6th Edition):
Oh, T. (2013). Power efficient analog-to-digital converters using both voltage and time domain information. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/39042
Chicago Manual of Style (16th Edition):
Oh, Taehwan. “Power efficient analog-to-digital converters using both voltage and time domain information.” 2013. Doctoral Dissertation, Oregon State University. Accessed March 05, 2021.
http://hdl.handle.net/1957/39042.
MLA Handbook (7th Edition):
Oh, Taehwan. “Power efficient analog-to-digital converters using both voltage and time domain information.” 2013. Web. 05 Mar 2021.
Vancouver:
Oh T. Power efficient analog-to-digital converters using both voltage and time domain information. [Internet] [Doctoral dissertation]. Oregon State University; 2013. [cited 2021 Mar 05].
Available from: http://hdl.handle.net/1957/39042.
Council of Science Editors:
Oh T. Power efficient analog-to-digital converters using both voltage and time domain information. [Doctoral Dissertation]. Oregon State University; 2013. Available from: http://hdl.handle.net/1957/39042
15.
Li, Wei.
Low-power successive approximation analog to digital converter with digital calibration.
Degree: PhD, Electrical and Computer Engineering, 2014, Oregon State University
URL: http://hdl.handle.net/1957/46788
► IC designers are continuously facing the challenges from reduced CMOS feature sizes and supply voltages. ADCs that deliver satisfactory resolutions/speeds while utilizing the state-of-the-art technologies…
(more)
▼ IC designers are continuously facing the challenges from reduced CMOS feature sizes and supply voltages. ADCs that deliver satisfactory resolutions/speeds while utilizing the
state-of-the-art technologies to save power are in high demand. The analog circuits are more and more assisted by various digital calibration techniques to get boosted performances. This dissertation is focused on a low-power 12-bit 12.5-MS/s successive approximation (SAR) ADC with a couple of calibration schemes.
The performances of the proposed SAR ADC are enhanced in two directions. To reduce the power dissipation, a power saving strategy has been proposed. Also, several foreground calibration methods for SAR ADCs have been proposed to reduce power dissipation and enhance conversion accuracy. The design was fabricated in 40nm CMOS technology. Measurement results after calibration showed a SFDR of 82.2 dB, and a THD improvement of 22.5 dB.
Finally, two new schemes to realize teraohm on-chip resistance are presented. One of the schemes utilizes a switched-capacitor array, and the other utilizes a switch-capacitor ladder. Using these schemes, large resistances can be fabricated with standard CMOS process in an affordable chip area.
Advisors/Committee Members: Temes, Gabor C. (advisor), Fiez, Terri (committee member).
Subjects/Keywords: ADC; Successive approximation analog-to-digital converters – Calibration
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APA ·
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Export
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APA (6th Edition):
Li, W. (2014). Low-power successive approximation analog to digital converter with digital calibration. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/46788
Chicago Manual of Style (16th Edition):
Li, Wei. “Low-power successive approximation analog to digital converter with digital calibration.” 2014. Doctoral Dissertation, Oregon State University. Accessed March 05, 2021.
http://hdl.handle.net/1957/46788.
MLA Handbook (7th Edition):
Li, Wei. “Low-power successive approximation analog to digital converter with digital calibration.” 2014. Web. 05 Mar 2021.
Vancouver:
Li W. Low-power successive approximation analog to digital converter with digital calibration. [Internet] [Doctoral dissertation]. Oregon State University; 2014. [cited 2021 Mar 05].
Available from: http://hdl.handle.net/1957/46788.
Council of Science Editors:
Li W. Low-power successive approximation analog to digital converter with digital calibration. [Doctoral Dissertation]. Oregon State University; 2014. Available from: http://hdl.handle.net/1957/46788
Oregon State University
16.
Lee, Ho-Young.
Power-efficient two-step pipelined analog-to-digital conversion.
Degree: PhD, Electrical and Computer Engineering, 2011, Oregon State University
URL: http://hdl.handle.net/1957/26075
► Hand-held devices are among the most successful consumer electronics in modern society. Behind these successful devices, lies a key analog design technique that involves high-performance…
(more)
▼ Hand-held devices are among the most successful consumer electronics in modern society. Behind these successful devices, lies a key analog design technique that involves high-performance analog-to-digital conversion combined with very low power consumption. This dissertation presents two different approaches to achieving high power efficiency from a two-step pipelined architecture, which is generally known as one of the most power-consuming analog-to-digital converters.
In the first approach, an analog feedback loop of a residue amplifier in a two-step pipelined analog-to-digital converter is reconfigured digitally using a single comparator and an R-2R digital-to-analog converter. This comparator-based structure can reduce power consumption of a conventional two-step pipelined analog-to-digital converter which consists of an opamp-based residue amplifier followed by a second- stage analog-to-digital converter. In addition, this dissertation includes circuit design techniques that provide a digital offset correction for the comparator-based two-step structure, binary-weighted switching for an R-2R digital-to-analog converter, and reference trimming for a flash analog-to-digital converter. A 10-b prototype analog-to-digital converter achieves an FOM of 121 fJ/conversion-step under 0.7-V supply.
The second approach provides a way to achieve low power consumption for a high-resolution two-step pipelined analog-to-digital converter. An opamp is designed to consume optimized static power using a quarter-scaled residue gain together with minimized loading capacitance from the proposed second stage. A 14-b prototype analog-to-digital converter achieves an FOM of 31.3 fJ/conversion-step with an ENOB of 11.4 b, which is the lowest FOM in high-resolution analog-to-digital converters having greater than an ENOB of 10 b.
Finally, the potential for further power reduction in a two-step pipelined analog-to-digital converter is discussed as a topic for future research.
Advisors/Committee Members: Moon, Un-Ku (advisor), Temes, Gabor C. (committee member).
Subjects/Keywords: ADC; Pipelined ADCs – Design and construction
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APA ·
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MLA ·
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Export
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APA (6th Edition):
Lee, H. (2011). Power-efficient two-step pipelined analog-to-digital conversion. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/26075
Chicago Manual of Style (16th Edition):
Lee, Ho-Young. “Power-efficient two-step pipelined analog-to-digital conversion.” 2011. Doctoral Dissertation, Oregon State University. Accessed March 05, 2021.
http://hdl.handle.net/1957/26075.
MLA Handbook (7th Edition):
Lee, Ho-Young. “Power-efficient two-step pipelined analog-to-digital conversion.” 2011. Web. 05 Mar 2021.
Vancouver:
Lee H. Power-efficient two-step pipelined analog-to-digital conversion. [Internet] [Doctoral dissertation]. Oregon State University; 2011. [cited 2021 Mar 05].
Available from: http://hdl.handle.net/1957/26075.
Council of Science Editors:
Lee H. Power-efficient two-step pipelined analog-to-digital conversion. [Doctoral Dissertation]. Oregon State University; 2011. Available from: http://hdl.handle.net/1957/26075
17.
Miller, Brian A.
A DC-DC converter architecture for low-power, high-resistance thermoelectric generators for use in body-powered designs.
Degree: MS, Electrical and Computer Engineering, 2013, Oregon State University
URL: http://hdl.handle.net/1957/37393
► This thesis presents a low power DC-DC converter suitable for harvesting energy from high impedance thermoelectric generators (TEGs) for the use in body powered electronics.…
(more)
▼ This thesis presents a low power DC-DC converter suitable for harvesting energy from high impedance thermoelectric generators (TEGs) for the use in body powered electronics. The chip has been fabricated in a 130nm CMOS technology. To meet the power demands of body powered networks, a novel dual-path architecture capable of efficiently harvesting power at levels below 5 μW has been developed. To control the converter, a low power control loop has been developed. The control loop features a low-power clock and a pulse counting system that is capable of matching the converter impedance with high impedance TEGs. The system consumes less than 900nW of quiescent power and maintains an efficiency of 68% for a load of 5 μW.
Advisors/Committee Members: Fiez, Terri S. (advisor), Temes, Gabor C. (committee member).
Subjects/Keywords: DC-to-DC converters
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APA (6th Edition):
Miller, B. A. (2013). A DC-DC converter architecture for low-power, high-resistance thermoelectric generators for use in body-powered designs. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/37393
Chicago Manual of Style (16th Edition):
Miller, Brian A. “A DC-DC converter architecture for low-power, high-resistance thermoelectric generators for use in body-powered designs.” 2013. Masters Thesis, Oregon State University. Accessed March 05, 2021.
http://hdl.handle.net/1957/37393.
MLA Handbook (7th Edition):
Miller, Brian A. “A DC-DC converter architecture for low-power, high-resistance thermoelectric generators for use in body-powered designs.” 2013. Web. 05 Mar 2021.
Vancouver:
Miller BA. A DC-DC converter architecture for low-power, high-resistance thermoelectric generators for use in body-powered designs. [Internet] [Masters thesis]. Oregon State University; 2013. [cited 2021 Mar 05].
Available from: http://hdl.handle.net/1957/37393.
Council of Science Editors:
Miller BA. A DC-DC converter architecture for low-power, high-resistance thermoelectric generators for use in body-powered designs. [Masters Thesis]. Oregon State University; 2013. Available from: http://hdl.handle.net/1957/37393
18.
Cao, Jinzhou.
Linearity enhancement techniques for data converters.
Degree: PhD, Electrical and Computer Engineering, 2015, Oregon State University
URL: http://hdl.handle.net/1957/55404
► Data converters are essential interface circuits between the analog world that people live in and the digital processors that people live with. Linearity, which often…
(more)
▼ Data converters are essential interface circuits between the analog world that people live in and the digital processors that people live with. Linearity, which often is a tradeoff against other performance criteria, is one of the major performance demands from applications for both analog-to-digital converts (ADC) and digital-to-analog converters (DAC). This dissertation describes several novel linearity enhancement techniques utilizing mainly digital circuits, targeting different data converter architectures allowing their linearity performances to be enhanced without many sacrifices from other features such as conversion bandwidth or power consumption.
A background calibration method for flash ADCs was developed. It cancels the error introduced by comparator offsets and component mismatches in reference circuit. The calibration works primarily in the digital domain with small analog hardware overhead. The offsets in the flash ADC are pseudo-randomly and gradually calibrated, thus the accuracy of the ADC is eventually restored.
A foreground calibration method for delta-sigma ADCs is also proposed. The fully digital calibration technique extracts the multi-bit feedback DAC error and cancels it in the digital domain. The calibration scheme requires no precision external components and inserts only a small digital block at the modulator feedback path.
A new approach of radix-based digital technique for compensating capacitor mismatch of the two-capacitor DAC is introduced. Digital input words are pre-distorted with an ADC-like algorithm before they are fed into the DAC. The proposed methods provide better linearity performance when the DAC is converting higher number of bits. Extra peripheral circuits to achieve the digital compensation are briefly discussed.
Advisors/Committee Members: Temes, Gabor C. (advisor), Raich, Raviv (committee member).
Subjects/Keywords: data converter; Analog-to-digital converters – Calibration
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APA (6th Edition):
Cao, J. (2015). Linearity enhancement techniques for data converters. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/55404
Chicago Manual of Style (16th Edition):
Cao, Jinzhou. “Linearity enhancement techniques for data converters.” 2015. Doctoral Dissertation, Oregon State University. Accessed March 05, 2021.
http://hdl.handle.net/1957/55404.
MLA Handbook (7th Edition):
Cao, Jinzhou. “Linearity enhancement techniques for data converters.” 2015. Web. 05 Mar 2021.
Vancouver:
Cao J. Linearity enhancement techniques for data converters. [Internet] [Doctoral dissertation]. Oregon State University; 2015. [cited 2021 Mar 05].
Available from: http://hdl.handle.net/1957/55404.
Council of Science Editors:
Cao J. Linearity enhancement techniques for data converters. [Doctoral Dissertation]. Oregon State University; 2015. Available from: http://hdl.handle.net/1957/55404
19.
Lin, Jiaming.
Design techniques for low power high speed successive approximation analog-to-digital converters.
Degree: PhD, Electrical and Computer Engineering, 2013, Oregon State University
URL: http://hdl.handle.net/1957/40996
► This dissertation presents two high-speed pipeline successive approximation analog-to-digital converters (SAR ADCs). Capacitive DACs and resistive DACs are utilized in these two pipeline SAR ADCs,…
(more)
▼ This dissertation presents two high-speed pipeline successive approximation analog-to-digital converters (SAR ADCs). Capacitive DACs and resistive DACs are utilized in these two pipeline SAR ADCs, respectively.
The pipeline SAR ADC with capacitive DACs can save 50% switching power compared with other time-interleaved SAR ADCs since the total capacitance of the DACs in this ADC is more than 50% less than the conventional time-interleave ones. Several switching techniques are implemented to alleviate the impact from the parasitic capacitance and improve the performance.
The pipeline SAR ADC with resistive DACs overcomes the influence from the parasitic capacitance with negligible static power consumption on the resistive DACs. Also, the complicated switching techniques can be avoided to simplify the timing logic.
To verify the above two architectures, two chips were designed and fabricated in 40nm CMOS process.
Finally, a new architecture of multi-step capacitive-splitting SAR ADC is proposed for low power applications. By using two identical capacitor-splitting capacitor arrays, the switching power and capacitor area can be reduced significantly.
Advisors/Committee Members: Temes, Gabor C. (advisor), Moon, Un-Ku (committee member).
Subjects/Keywords: successive approximation ADC; Successive approximation analog-to-digital converters – Design and construction
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Manager
APA (6th Edition):
Lin, J. (2013). Design techniques for low power high speed successive approximation analog-to-digital converters. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/40996
Chicago Manual of Style (16th Edition):
Lin, Jiaming. “Design techniques for low power high speed successive approximation analog-to-digital converters.” 2013. Doctoral Dissertation, Oregon State University. Accessed March 05, 2021.
http://hdl.handle.net/1957/40996.
MLA Handbook (7th Edition):
Lin, Jiaming. “Design techniques for low power high speed successive approximation analog-to-digital converters.” 2013. Web. 05 Mar 2021.
Vancouver:
Lin J. Design techniques for low power high speed successive approximation analog-to-digital converters. [Internet] [Doctoral dissertation]. Oregon State University; 2013. [cited 2021 Mar 05].
Available from: http://hdl.handle.net/1957/40996.
Council of Science Editors:
Lin J. Design techniques for low power high speed successive approximation analog-to-digital converters. [Doctoral Dissertation]. Oregon State University; 2013. Available from: http://hdl.handle.net/1957/40996
Oregon State University
20.
Teng, Angela.
Process segmentation and modelling applied to time series featuring the response of biological materials to toxic agents.
Degree: MS, Electrical and Computer Engineering, 2004, Oregon State University
URL: http://hdl.handle.net/1957/11520
► The detection of biological and chemical toxins has become one of the main concerns in environmental and military fields. In this framework, the department of…
(more)
▼ The detection of biological and chemical toxins has become one of the main concerns
in environmental and military fields. In this framework, the department of Microbiology
and Biochemistry at
Oregon State University has discovered that fish living cells
are promising indicators of the presence of a wide range of toxins. Thus, an interdisciplinary
project called ”SOS Cytosensor” was launched to create an autonomous and
mobile device to detect such toxins using these living cells.
After exposing a cell culture to a specific biological or chemical agent, a sequence
of cell images is recorded. The extraction of features from the experimental sequences
of images results in time series that have to be modelled and classified in order to prove
useful in toxin detection. The chosen models should give a representation of time series
that supports accurate classification and clustering and that would also make storage
and transmission more efficient. There are many techniques for dimensionality reduction
of time series data in the literature, such as Fourier transforms, but segmentation is
the most popular technique for extracting structures from time series. Segmentation
algorithms can be classified as batch or online. The main idea is that given a time
series Y, segmentation produces the best representation using an undefined number K
of segments, such that the combined error of all segments is less than a user-specified threshold and that the maximum error for any segment doesn’t exceed a user-specified
local threshold. First, we modelled each time series data using a single ARX model
with regularly spaced breakpoints. Then, we considered improving the result by placing
the breakpoints dynamically. As a pre-analysis of the curves, we performed a piecewise
linear segmentation, thus tracking changes in the behaviour of the time series and placing
breakpoints at those locations. Piecewise linear regression refers to the approximation of
a time series Y, of length N, with K straight lines. Because K is typically much smaller
than N, this representation makes the storage, transmission and computation of data
more efficient. The piecewise linear regression is usually used for change point detection,
which is our goal in this study.
As the segmentation into several simple adequate AR models proved not to be
satisfying in terms of fitting, we combined this concept with the piecewise linear segmentation
discussed above. Instead of modelling the time series by a single ARX model
using breakpoints determined by the segmentation algorithm or by several AR models,
we model each segment with a different ARX model. We use sum of square errors or the
residual error as a measure of the cost of merging segments. Computation speed has been
increased by presegmenting the time series with a fine piecewise linear approximation.
It also enables the user to predefine the number of final segments for classification and
clustering purposes. The final
state can be detected by extracting the last segment from
the…
Advisors/Committee Members: Temes, Gabor C. (advisor).
Subjects/Keywords: Biosensors – Computer programs
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APA (6th Edition):
Teng, A. (2004). Process segmentation and modelling applied to time series featuring the response of biological materials to toxic agents. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/11520
Chicago Manual of Style (16th Edition):
Teng, Angela. “Process segmentation and modelling applied to time series featuring the response of biological materials to toxic agents.” 2004. Masters Thesis, Oregon State University. Accessed March 05, 2021.
http://hdl.handle.net/1957/11520.
MLA Handbook (7th Edition):
Teng, Angela. “Process segmentation and modelling applied to time series featuring the response of biological materials to toxic agents.” 2004. Web. 05 Mar 2021.
Vancouver:
Teng A. Process segmentation and modelling applied to time series featuring the response of biological materials to toxic agents. [Internet] [Masters thesis]. Oregon State University; 2004. [cited 2021 Mar 05].
Available from: http://hdl.handle.net/1957/11520.
Council of Science Editors:
Teng A. Process segmentation and modelling applied to time series featuring the response of biological materials to toxic agents. [Masters Thesis]. Oregon State University; 2004. Available from: http://hdl.handle.net/1957/11520
Oregon State University
21.
Ma, Mengzhe.
Design of high efficiency step-down switched capacitor DC/DC converter.
Degree: MS, Electrical and Computer Engineering, 2003, Oregon State University
URL: http://hdl.handle.net/1957/30904
► Recently, switched capacitor DC/DC converters are extensively used in portable electronic devices because they feature many advantages, such as high efficiency, small package, low quiescent…
(more)
▼ Recently, switched capacitor DC/DC converters are extensively used in
portable electronic devices because they feature many advantages, such as high
efficiency, small package, low quiescent current, minimal external components and
low cost.
In this thesis, two step-down switched capacitor DC/DC converters are
designed. One has the fixed output options 1.5V, 1.8V and 2.0V. The other one has the
output 1.2V. These two converters are implemented in 0.5μm CMOS process through
National Semiconductor Corporation. The design is verified by the circuit-level
simulations, and design issues are discussed.
Advisors/Committee Members: Temes, Gabor C. (advisor).
Subjects/Keywords: DC-to-DC converters – Design and construction
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APA (6th Edition):
Ma, M. (2003). Design of high efficiency step-down switched capacitor DC/DC converter. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/30904
Chicago Manual of Style (16th Edition):
Ma, Mengzhe. “Design of high efficiency step-down switched capacitor DC/DC converter.” 2003. Masters Thesis, Oregon State University. Accessed March 05, 2021.
http://hdl.handle.net/1957/30904.
MLA Handbook (7th Edition):
Ma, Mengzhe. “Design of high efficiency step-down switched capacitor DC/DC converter.” 2003. Web. 05 Mar 2021.
Vancouver:
Ma M. Design of high efficiency step-down switched capacitor DC/DC converter. [Internet] [Masters thesis]. Oregon State University; 2003. [cited 2021 Mar 05].
Available from: http://hdl.handle.net/1957/30904.
Council of Science Editors:
Ma M. Design of high efficiency step-down switched capacitor DC/DC converter. [Masters Thesis]. Oregon State University; 2003. Available from: http://hdl.handle.net/1957/30904
Oregon State University
22.
Rengachari, Thirumalai.
A 10 bit algorithmic A/D converter for a biosensor.
Degree: MS, Computer Science, 2004, Oregon State University
URL: http://hdl.handle.net/1957/28871
► This thesis presents a novel algorithmic A/D converter to be used in a biosensor. The converter is capable of a conversion rate of 1.5 bits/phase…
(more)
▼ This thesis presents a novel algorithmic A/D converter to be used in a biosensor.
The converter is capable of a conversion rate of 1.5 bits/phase and hence the
required conversion time is reduced. The proposed architecture is analyzed for non-ideal
effects and compared with existing algorithmic A/D architectures. The
converter needs only one op-amp, 4 comparators and 3 capacitors. Power reduction
techniques are discussed with respect to the biosensor and the ADC. The ADC is
designed for fabrication in a CMOS 0.18μm process.
Advisors/Committee Members: Temes, Gabor C. (advisor).
Subjects/Keywords: Analog-to-digital converters – Mathematical models
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APA (6th Edition):
Rengachari, T. (2004). A 10 bit algorithmic A/D converter for a biosensor. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/28871
Chicago Manual of Style (16th Edition):
Rengachari, Thirumalai. “A 10 bit algorithmic A/D converter for a biosensor.” 2004. Masters Thesis, Oregon State University. Accessed March 05, 2021.
http://hdl.handle.net/1957/28871.
MLA Handbook (7th Edition):
Rengachari, Thirumalai. “A 10 bit algorithmic A/D converter for a biosensor.” 2004. Web. 05 Mar 2021.
Vancouver:
Rengachari T. A 10 bit algorithmic A/D converter for a biosensor. [Internet] [Masters thesis]. Oregon State University; 2004. [cited 2021 Mar 05].
Available from: http://hdl.handle.net/1957/28871.
Council of Science Editors:
Rengachari T. A 10 bit algorithmic A/D converter for a biosensor. [Masters Thesis]. Oregon State University; 2004. Available from: http://hdl.handle.net/1957/28871
Oregon State University
23.
Wu, Lei.
Low-voltage pipeline A/D converter.
Degree: MS, Electrical and Computer Engineering, 1999, Oregon State University
URL: http://hdl.handle.net/1957/33270
► Continuous process scale-down and emerging markets for low-power/low-voltage mobile systems call for low-voltage analog integrated circuits. Switched-capacitor (SC) circuits are the building blocks for analog…
(more)
▼ Continuous process scale-down and emerging markets for low-power/low-voltage mobile systems call for low-voltage analog integrated circuits. Switched-capacitor (SC) circuits are the building blocks for analog signal processing and will encounter severe overdrive problems when operating at low voltage conditions. There exist three techniques to solve the problem, but with their own limitations. Multi-threshold process increases cost. Boosted clock will cause life time reliability issues. Switched-opamp slows down the speed of operation. A new low-voltage SC technique without special process and boosted-clock is studied to overcome these drawbacks.
To verify the speed advantage of the new scheme over the switched-opamp technique, a 10-bit 20 MS/s pipeline A/D converter operating at 1.5 V supply voltage was designed. A new pseudo-differential structure was proposed and some relevant design issues are discussed. Circuit implementations and layout floorplan are described. All designs are based on Matlab, SWITCAP and Hspice simulation.
Advisors/Committee Members: Temes, Gabor C. (advisor).
Subjects/Keywords: Analog-to-digital converters
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APA (6th Edition):
Wu, L. (1999). Low-voltage pipeline A/D converter. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/33270
Chicago Manual of Style (16th Edition):
Wu, Lei. “Low-voltage pipeline A/D converter.” 1999. Masters Thesis, Oregon State University. Accessed March 05, 2021.
http://hdl.handle.net/1957/33270.
MLA Handbook (7th Edition):
Wu, Lei. “Low-voltage pipeline A/D converter.” 1999. Web. 05 Mar 2021.
Vancouver:
Wu L. Low-voltage pipeline A/D converter. [Internet] [Masters thesis]. Oregon State University; 1999. [cited 2021 Mar 05].
Available from: http://hdl.handle.net/1957/33270.
Council of Science Editors:
Wu L. Low-voltage pipeline A/D converter. [Masters Thesis]. Oregon State University; 1999. Available from: http://hdl.handle.net/1957/33270
Oregon State University
24.
Yang, Yaohua, 1969-.
Effects and compensation of the analog integrator nonidealities in dual-quantization delta-sigma modulators.
Degree: MS, Electrical and Computer Engineering, 1993, Oregon State University
URL: http://hdl.handle.net/1957/36354
Subjects/Keywords: Modulators (Electronics)
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APA (6th Edition):
Yang, Yaohua, 1. (1993). Effects and compensation of the analog integrator nonidealities in dual-quantization delta-sigma modulators. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/36354
Chicago Manual of Style (16th Edition):
Yang, Yaohua, 1969-. “Effects and compensation of the analog integrator nonidealities in dual-quantization delta-sigma modulators.” 1993. Masters Thesis, Oregon State University. Accessed March 05, 2021.
http://hdl.handle.net/1957/36354.
MLA Handbook (7th Edition):
Yang, Yaohua, 1969-. “Effects and compensation of the analog integrator nonidealities in dual-quantization delta-sigma modulators.” 1993. Web. 05 Mar 2021.
Vancouver:
Yang, Yaohua 1. Effects and compensation of the analog integrator nonidealities in dual-quantization delta-sigma modulators. [Internet] [Masters thesis]. Oregon State University; 1993. [cited 2021 Mar 05].
Available from: http://hdl.handle.net/1957/36354.
Council of Science Editors:
Yang, Yaohua 1. Effects and compensation of the analog integrator nonidealities in dual-quantization delta-sigma modulators. [Masters Thesis]. Oregon State University; 1993. Available from: http://hdl.handle.net/1957/36354
Oregon State University
25.
Sharma, Vivek.
Generalized radix design techniques for low-power, low voltage pipelined and cyclic analog-digital converters.
Degree: MS, Electrical and Computer Engineering, 2004, Oregon State University
URL: http://hdl.handle.net/1957/10218
► This thesis proposes a novel technique for the design of pipelined and cyclic ADCs utilizing generalized radix gain stages. Several models have been proposed for…
(more)
▼ This thesis proposes a novel technique for the design of pipelined and
cyclic ADCs utilizing generalized radix gain stages. Several models have been
proposed for the optimization of high performance pipelined ADCs by various
researchers. This work builds upon them, using a simple but accurate model to
estimate the optimal interstage gain for a given set of specifications. The proposed
technique can then be used to implement an ADC with a generalized, non-binary
interstage gain, while maintaining the robustness of design in the face of various
circuit non-idealities and errors. It is also shown that the existing design techniques
are merely a special case of this generalized design scheme, which blends
seamlessly with these without raising design cost or complexity. The effectiveness
of the proposed technique is verified rigorously through simulations.
Also, examples are presented illustrating the relevance of this approach and
the advantages offered by it when compared to the existing techniques for design
of high-performance pipelined ADCs for high-resolution applications.
Advisors/Committee Members: Temes, Gabor C. (advisor), Liu, Huaping (committee member).
Subjects/Keywords: Analog-to-digital converters
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APA (6th Edition):
Sharma, V. (2004). Generalized radix design techniques for low-power, low voltage pipelined and cyclic analog-digital converters. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/10218
Chicago Manual of Style (16th Edition):
Sharma, Vivek. “Generalized radix design techniques for low-power, low voltage pipelined and cyclic analog-digital converters.” 2004. Masters Thesis, Oregon State University. Accessed March 05, 2021.
http://hdl.handle.net/1957/10218.
MLA Handbook (7th Edition):
Sharma, Vivek. “Generalized radix design techniques for low-power, low voltage pipelined and cyclic analog-digital converters.” 2004. Web. 05 Mar 2021.
Vancouver:
Sharma V. Generalized radix design techniques for low-power, low voltage pipelined and cyclic analog-digital converters. [Internet] [Masters thesis]. Oregon State University; 2004. [cited 2021 Mar 05].
Available from: http://hdl.handle.net/1957/10218.
Council of Science Editors:
Sharma V. Generalized radix design techniques for low-power, low voltage pipelined and cyclic analog-digital converters. [Masters Thesis]. Oregon State University; 2004. Available from: http://hdl.handle.net/1957/10218
Oregon State University
26.
da Silva, Jose Barreiro.
High-performance delta-sigma analog-to-digital converters.
Degree: PhD, Electrical and Computer Engineering, 2004, Oregon State University
URL: http://hdl.handle.net/1957/29846
Subjects/Keywords: Analog-to-digital converters – Design and construction
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APA (6th Edition):
da Silva, J. B. (2004). High-performance delta-sigma analog-to-digital converters. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/29846
Chicago Manual of Style (16th Edition):
da Silva, Jose Barreiro. “High-performance delta-sigma analog-to-digital converters.” 2004. Doctoral Dissertation, Oregon State University. Accessed March 05, 2021.
http://hdl.handle.net/1957/29846.
MLA Handbook (7th Edition):
da Silva, Jose Barreiro. “High-performance delta-sigma analog-to-digital converters.” 2004. Web. 05 Mar 2021.
Vancouver:
da Silva JB. High-performance delta-sigma analog-to-digital converters. [Internet] [Doctoral dissertation]. Oregon State University; 2004. [cited 2021 Mar 05].
Available from: http://hdl.handle.net/1957/29846.
Council of Science Editors:
da Silva JB. High-performance delta-sigma analog-to-digital converters. [Doctoral Dissertation]. Oregon State University; 2004. Available from: http://hdl.handle.net/1957/29846
Oregon State University
27.
Guo, Yuhua.
A study of basic building blocks of analog-to-digital delta-sigma modulators.
Degree: MS, Electrical and Computer Engineering, 2004, Oregon State University
URL: http://hdl.handle.net/1957/30047
► In this thesis, a novel Direct-Charge-Transfer (DCT) integrator structure is proposed, which can settle much faster than regular switch-capacitor integrators. A new Spread-Spectrum Dynamic Element…
(more)
▼ In this thesis, a novel Direct-Charge-Transfer (DCT) integrator structure is
proposed, which can settle much faster than regular switch-capacitor integrators. A
new Spread-Spectrum Dynamic Element Matching (SS-DEM) algorithm is also
introduced, which can effectively spread or shape the nonlinearity error of multi-bit
DAC in the feedback path, thus improve the SNDR and THD performance of overall
delta-sigma modulators. A three-bit quantizer design example is presented, which is
embedded in a MASH2-0 structure delta-sigma modulator prototype and has been
fabricated in AMI CMOS 1.5μm technology. Testing results indicate this quantizer
works well.
Advisors/Committee Members: Temes, Gabor C. (advisor), Gobeli, David Harold (committee member).
Subjects/Keywords: Signal processing
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APA (6th Edition):
Guo, Y. (2004). A study of basic building blocks of analog-to-digital delta-sigma modulators. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/30047
Chicago Manual of Style (16th Edition):
Guo, Yuhua. “A study of basic building blocks of analog-to-digital delta-sigma modulators.” 2004. Masters Thesis, Oregon State University. Accessed March 05, 2021.
http://hdl.handle.net/1957/30047.
MLA Handbook (7th Edition):
Guo, Yuhua. “A study of basic building blocks of analog-to-digital delta-sigma modulators.” 2004. Web. 05 Mar 2021.
Vancouver:
Guo Y. A study of basic building blocks of analog-to-digital delta-sigma modulators. [Internet] [Masters thesis]. Oregon State University; 2004. [cited 2021 Mar 05].
Available from: http://hdl.handle.net/1957/30047.
Council of Science Editors:
Guo Y. A study of basic building blocks of analog-to-digital delta-sigma modulators. [Masters Thesis]. Oregon State University; 2004. Available from: http://hdl.handle.net/1957/30047
Oregon State University
28.
Wang, Xuesheng.
A fully digital technique for the estimation and correction of the DAC error in multi-bit delta sigma ADCs.
Degree: PhD, Electrical and Computer Engineering, 2003, Oregon State University
URL: http://hdl.handle.net/1957/30720
► This thesis proposes a novel fully digital technique for the estimation and correction of the DAC error in multi-bit delta sigma ADCs. The structure of…
(more)
▼ This thesis proposes a novel fully digital technique for the estimation and
correction of the DAC error in multi-bit delta sigma ADCs. The structure of the
DAC error is indicated through a simple model for unit-element based DACs. The
impact of the DAC error on the performance of ADC is then analyzed. Various
techniques dealing with the DAC error are described and their drawbacks are
pointed out. Based on the nature of the DAC error and the surrounding signals, a
fully digital method to estimate the error from the ADC output and remove it is
proposed. Simulation results are shown to support the effectiveness of the method.
Simulations also show that the proposed technique can work together with the
technique of adaptive compensation for quantization noise leakage in cascaded
delta sigma (MASH) ADC cases. These two techniques are the foundation for the
design of high speed, high resolution delta sigma ADCs with relaxed requirements
on the analog circuits.
To verify the proposed technique, an experimental MASH ADC was built,
including the design and fabrication of a chip of a second-order multi-bit delta
sigma ADC in a 1.6μm CMOS technology. The measured results show that the
proposed DAC correction technique is highly effective.
Advisors/Committee Members: Temes, Gabor C. (advisor), Mayaram, Kartikeya (committee member).
Subjects/Keywords: Analog-to-digital converters
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Manager
APA (6th Edition):
Wang, X. (2003). A fully digital technique for the estimation and correction of the DAC error in multi-bit delta sigma ADCs. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/30720
Chicago Manual of Style (16th Edition):
Wang, Xuesheng. “A fully digital technique for the estimation and correction of the DAC error in multi-bit delta sigma ADCs.” 2003. Doctoral Dissertation, Oregon State University. Accessed March 05, 2021.
http://hdl.handle.net/1957/30720.
MLA Handbook (7th Edition):
Wang, Xuesheng. “A fully digital technique for the estimation and correction of the DAC error in multi-bit delta sigma ADCs.” 2003. Web. 05 Mar 2021.
Vancouver:
Wang X. A fully digital technique for the estimation and correction of the DAC error in multi-bit delta sigma ADCs. [Internet] [Doctoral dissertation]. Oregon State University; 2003. [cited 2021 Mar 05].
Available from: http://hdl.handle.net/1957/30720.
Council of Science Editors:
Wang X. A fully digital technique for the estimation and correction of the DAC error in multi-bit delta sigma ADCs. [Doctoral Dissertation]. Oregon State University; 2003. Available from: http://hdl.handle.net/1957/30720
Oregon State University
29.
Liu, Mingliang.
The design of delta-sigma modulators for multi-standard RF receivers.
Degree: MS, Electrical and Computer Engineering, 2003, Oregon State University
URL: http://hdl.handle.net/1957/30976
► The transition from second-generation (2G) to third-generation (3G) wireless cellular and cordless telephone systems requires multi-standard adaptability in a single RF receiver equipment. An important…
(more)
▼ The transition from second-generation (2G) to third-generation (3G) wireless
cellular and cordless telephone systems requires multi-standard adaptability in
a single RF receiver equipment. An important answer to this request is the use of
Delta-Sigma modulators for IF-to-baseband conversion, which will satisfy the dynamic
range requirements for digital signal processing, and at the same time, add
adaptability and programmability to the characteristics of a RF receiver.
This thesis addresses the issues of designing a Delta-Sigma modulator for a
multi-standard wireless receiver. A single-loop third-order modulator topology suitable
for low power and high integration multi-standard receiver design is proposed.
The trade-offs in the modulator design are also presented and explained. The modulator,
which has been implemented as a part of a monolithic receiver chip, will be
fabricated in a standard 0.35-μm CMOS process. The post-layout simulation results
have verified the outcomes of system analysis.
Advisors/Committee Members: Temes, Gabor C. (advisor), Moon, Un-Ku (committee member).
Subjects/Keywords: Radio frequency modulation – Receivers and reception
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APA (6th Edition):
Liu, M. (2003). The design of delta-sigma modulators for multi-standard RF receivers. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/30976
Chicago Manual of Style (16th Edition):
Liu, Mingliang. “The design of delta-sigma modulators for multi-standard RF receivers.” 2003. Masters Thesis, Oregon State University. Accessed March 05, 2021.
http://hdl.handle.net/1957/30976.
MLA Handbook (7th Edition):
Liu, Mingliang. “The design of delta-sigma modulators for multi-standard RF receivers.” 2003. Web. 05 Mar 2021.
Vancouver:
Liu M. The design of delta-sigma modulators for multi-standard RF receivers. [Internet] [Masters thesis]. Oregon State University; 2003. [cited 2021 Mar 05].
Available from: http://hdl.handle.net/1957/30976.
Council of Science Editors:
Liu M. The design of delta-sigma modulators for multi-standard RF receivers. [Masters Thesis]. Oregon State University; 2003. Available from: http://hdl.handle.net/1957/30976
Oregon State University
30.
Keskin, Mustafa.
Low voltage switched capacitor circuits for lowpass and bandpass [delta sigma] converters.
Degree: PhD, Electrical and Computer Engineering, 2001, Oregon State University
URL: http://hdl.handle.net/1957/32625
► The most accurate method for performing analog signal processing in MOS (metal-oxide-semiconductor) integrated circuits is through the use of switched-capacitor circuits. A switched-capacitor circuit operates…
(more)
▼ The most accurate method for performing analog signal processing in MOS
(metal-oxide-semiconductor) integrated circuits is through the use of switched-capacitor
circuits. A switched-capacitor circuit operates as a discrete-time signal
processor. These circuits have been used in a variety of applications, such as
filters, gain stages, voltage-controlled oscillators, and modulators.
A switched-capacitor circuit contains operational amplifiers (opamps), capacitators,
switches, and a clock generator. Capacitors are used to define the
state
variables of a system. They store charges for a defined time interval, and determine
the
state variables as voltage differences. Switches are used to direct
the flow of charges and to enable the charging and discharging of capacitors.
Nonoverlapping clock signals control the switches and allow charge transfer between
the capacitors. Opamps are used in order to perform high-accuracy charge
transfer from one capacitor to another.
The goal of this research is to design and explore future low-voltage switched-capacitor
circuits, which are crucial for portable devices. Low-voltage operation
is needed for two reasons: making reliable and accurate systems compatible with
the submicron CMOS technology and reducing power consumption of the digital
circuits.
To this end, three different switched-capacitor integrators are proposed, which
function with very low supply voltages. One of these configurations is used to
design a lowpass Δ∑ modulator for digital-audio applications. This modulator
is fabricated and tested demonstrating 80 dB dynamic range with a 1-V supply
voltage.
The second part of this research is to show that these low-voltage circuits are
suitable for modern wireless communication applications, where the clock and
signal frequencies are very high.
This part of the research has focused on bandpass analog-to-digital converters.
Bandpass analog-to-digital converters are among the key components in
wireless communication systems. They are used to digitize the received analog
signal at an intermediate center frequency. Such converters are used for digital
FM or AM radio applications and for portable communication devices, such as
cellular phones. The main block, in these converters, is the resonator, which is
tuned to a particular center frequency. A resonator must be designed such that
it has a sharp peak at a specific center frequency. However, because of circuit
imperfections, the resonant peak gain and/or the center frequency are degraded
in existing architectures.
Two novel switched-capacitor resonators were invented during the second
part of this research. These resonators demonstrate superior performance as
compared to previous architectures. A fourth-order low-voltage bandpass Δ∑
modulator, using one of these resonators, has been designed.
Advisors/Committee Members: Temes, Gabor C. (advisor), OLeary, Sarah (committee member).
Subjects/Keywords: Switched capacitor circuits – Design and construction
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APA (6th Edition):
Keskin, M. (2001). Low voltage switched capacitor circuits for lowpass and bandpass [delta sigma] converters. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/32625
Chicago Manual of Style (16th Edition):
Keskin, Mustafa. “Low voltage switched capacitor circuits for lowpass and bandpass [delta sigma] converters.” 2001. Doctoral Dissertation, Oregon State University. Accessed March 05, 2021.
http://hdl.handle.net/1957/32625.
MLA Handbook (7th Edition):
Keskin, Mustafa. “Low voltage switched capacitor circuits for lowpass and bandpass [delta sigma] converters.” 2001. Web. 05 Mar 2021.
Vancouver:
Keskin M. Low voltage switched capacitor circuits for lowpass and bandpass [delta sigma] converters. [Internet] [Doctoral dissertation]. Oregon State University; 2001. [cited 2021 Mar 05].
Available from: http://hdl.handle.net/1957/32625.
Council of Science Editors:
Keskin M. Low voltage switched capacitor circuits for lowpass and bandpass [delta sigma] converters. [Doctoral Dissertation]. Oregon State University; 2001. Available from: http://hdl.handle.net/1957/32625
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