Advanced search options

Advanced Search Options 🞨

Browse by author name (“Author name starts with…”).

Find ETDs with:

in
/  
in
/  
in
/  
in

Written in Published in Earliest date Latest date

Sorted by

Results per page:

Sorted by: relevance · author · university · dateNew search

You searched for +publisher:"Oregon State University" +contributor:("Kiaei, Sayfe"). Showing records 1 – 29 of 29 total matches.

Search Limiters

Last 2 Years | English Only

No search limiters apply to these results.

▼ Search Limiters


Oregon State University

1. Durgam, Jaisimha K. Dynamically configurable systolic arrays.

Degree: MS, Electrical and Computer Engineering, 1988, Oregon State University

 Digital signal and image processing and other real time applications involve simple but large amounts of computations. These problems have an enormous amount of inherent… (more)

Subjects/Keywords: Array processors

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Durgam, J. K. (1988). Dynamically configurable systolic arrays. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/39843

Chicago Manual of Style (16th Edition):

Durgam, Jaisimha K. “Dynamically configurable systolic arrays.” 1988. Masters Thesis, Oregon State University. Accessed November 17, 2019. http://hdl.handle.net/1957/39843.

MLA Handbook (7th Edition):

Durgam, Jaisimha K. “Dynamically configurable systolic arrays.” 1988. Web. 17 Nov 2019.

Vancouver:

Durgam JK. Dynamically configurable systolic arrays. [Internet] [Masters thesis]. Oregon State University; 1988. [cited 2019 Nov 17]. Available from: http://hdl.handle.net/1957/39843.

Council of Science Editors:

Durgam JK. Dynamically configurable systolic arrays. [Masters Thesis]. Oregon State University; 1988. Available from: http://hdl.handle.net/1957/39843


Oregon State University

2. Maskai, Sailesh R. Design of complex digital blocks using folded source-coupled logic for mixed-mode applications.

Degree: MS, Electrical and Computer Engineering, 1991, Oregon State University

 A series of complex digital blocks have been designed and fabricated using the newly developed current-mode differential CMOS logic family viz. the Folded Source-Coupled Logic… (more)

Subjects/Keywords: Metal oxide semiconductors; Complementary

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Maskai, S. R. (1991). Design of complex digital blocks using folded source-coupled logic for mixed-mode applications. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/37131

Chicago Manual of Style (16th Edition):

Maskai, Sailesh R. “Design of complex digital blocks using folded source-coupled logic for mixed-mode applications.” 1991. Masters Thesis, Oregon State University. Accessed November 17, 2019. http://hdl.handle.net/1957/37131.

MLA Handbook (7th Edition):

Maskai, Sailesh R. “Design of complex digital blocks using folded source-coupled logic for mixed-mode applications.” 1991. Web. 17 Nov 2019.

Vancouver:

Maskai SR. Design of complex digital blocks using folded source-coupled logic for mixed-mode applications. [Internet] [Masters thesis]. Oregon State University; 1991. [cited 2019 Nov 17]. Available from: http://hdl.handle.net/1957/37131.

Council of Science Editors:

Maskai SR. Design of complex digital blocks using folded source-coupled logic for mixed-mode applications. [Masters Thesis]. Oregon State University; 1991. Available from: http://hdl.handle.net/1957/37131


Oregon State University

3. Zahl, Eric L. Resolution enhancement of analog-to-digital converters through computationally simple digital filtering.

Degree: MS, Electrical and Computer Engineering, 1989, Oregon State University

 The resolution of analog-to-digital converters can be distinguished as absolute resolution, or average resolution. This study reviews average resolution enhancement techniques and proposes a method… (more)

Subjects/Keywords: Analog-to-digital converters

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zahl, E. L. (1989). Resolution enhancement of analog-to-digital converters through computationally simple digital filtering. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/39865

Chicago Manual of Style (16th Edition):

Zahl, Eric L. “Resolution enhancement of analog-to-digital converters through computationally simple digital filtering.” 1989. Masters Thesis, Oregon State University. Accessed November 17, 2019. http://hdl.handle.net/1957/39865.

MLA Handbook (7th Edition):

Zahl, Eric L. “Resolution enhancement of analog-to-digital converters through computationally simple digital filtering.” 1989. Web. 17 Nov 2019.

Vancouver:

Zahl EL. Resolution enhancement of analog-to-digital converters through computationally simple digital filtering. [Internet] [Masters thesis]. Oregon State University; 1989. [cited 2019 Nov 17]. Available from: http://hdl.handle.net/1957/39865.

Council of Science Editors:

Zahl EL. Resolution enhancement of analog-to-digital converters through computationally simple digital filtering. [Masters Thesis]. Oregon State University; 1989. Available from: http://hdl.handle.net/1957/39865


Oregon State University

4. Inoue, Takao. Modified conjugate gradient method for ADSL echo cancellation.

Degree: MS, Electrical and Computer Engineering, 1998, Oregon State University

 In recent years, high speed data communications over twisted pair cables has gained tremendous demand. Asymmetric Digital Subscriber Line (ADSL) was standardized for use over… (more)

Subjects/Keywords: Echo suppression (Telecommunication)

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Inoue, T. (1998). Modified conjugate gradient method for ADSL echo cancellation. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/33930

Chicago Manual of Style (16th Edition):

Inoue, Takao. “Modified conjugate gradient method for ADSL echo cancellation.” 1998. Masters Thesis, Oregon State University. Accessed November 17, 2019. http://hdl.handle.net/1957/33930.

MLA Handbook (7th Edition):

Inoue, Takao. “Modified conjugate gradient method for ADSL echo cancellation.” 1998. Web. 17 Nov 2019.

Vancouver:

Inoue T. Modified conjugate gradient method for ADSL echo cancellation. [Internet] [Masters thesis]. Oregon State University; 1998. [cited 2019 Nov 17]. Available from: http://hdl.handle.net/1957/33930.

Council of Science Editors:

Inoue T. Modified conjugate gradient method for ADSL echo cancellation. [Masters Thesis]. Oregon State University; 1998. Available from: http://hdl.handle.net/1957/33930


Oregon State University

5. McNeal, Jeff D. A comparison of two types of zero-crossing FM demodulators for wireless receivers.

Degree: MS, Electrical and Computer Engineering, 1998, Oregon State University

A comparison of two novel demodulators. The first is a basic zero crossing demodulator, as introduced by Beards. The second is an approach proposed by Hovin. The two demodulators are compared to each other and to the conventional method of demodulation. Advisors/Committee Members: Kiaei, Sayfe (advisor).

Subjects/Keywords: Frequency modulation detectors

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

McNeal, J. D. (1998). A comparison of two types of zero-crossing FM demodulators for wireless receivers. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/33713

Chicago Manual of Style (16th Edition):

McNeal, Jeff D. “A comparison of two types of zero-crossing FM demodulators for wireless receivers.” 1998. Masters Thesis, Oregon State University. Accessed November 17, 2019. http://hdl.handle.net/1957/33713.

MLA Handbook (7th Edition):

McNeal, Jeff D. “A comparison of two types of zero-crossing FM demodulators for wireless receivers.” 1998. Web. 17 Nov 2019.

Vancouver:

McNeal JD. A comparison of two types of zero-crossing FM demodulators for wireless receivers. [Internet] [Masters thesis]. Oregon State University; 1998. [cited 2019 Nov 17]. Available from: http://hdl.handle.net/1957/33713.

Council of Science Editors:

McNeal JD. A comparison of two types of zero-crossing FM demodulators for wireless receivers. [Masters Thesis]. Oregon State University; 1998. Available from: http://hdl.handle.net/1957/33713


Oregon State University

6. Zheng, Yue-Peng. Mapping of recursive algorithms onto multi-rate arrays.

Degree: PhD, Electrical and Computer Engineering, 1994, Oregon State University

 In this dissertation, multi-rate array (MRA) architecture and its synthesis are proposed and developed. Using multi-coordinate systems (MCS), a unified theory for mapping algorithms from… (more)

Subjects/Keywords: Integrated circuits  – Very large scale integration

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zheng, Y. (1994). Mapping of recursive algorithms onto multi-rate arrays. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/34997

Chicago Manual of Style (16th Edition):

Zheng, Yue-Peng. “Mapping of recursive algorithms onto multi-rate arrays.” 1994. Doctoral Dissertation, Oregon State University. Accessed November 17, 2019. http://hdl.handle.net/1957/34997.

MLA Handbook (7th Edition):

Zheng, Yue-Peng. “Mapping of recursive algorithms onto multi-rate arrays.” 1994. Web. 17 Nov 2019.

Vancouver:

Zheng Y. Mapping of recursive algorithms onto multi-rate arrays. [Internet] [Doctoral dissertation]. Oregon State University; 1994. [cited 2019 Nov 17]. Available from: http://hdl.handle.net/1957/34997.

Council of Science Editors:

Zheng Y. Mapping of recursive algorithms onto multi-rate arrays. [Doctoral Dissertation]. Oregon State University; 1994. Available from: http://hdl.handle.net/1957/34997


Oregon State University

7. Oren, Joel A. Design of an asynchronous third-order finite impulse response filter.

Degree: MS, Electrical and Computer Engineering, 1994, Oregon State University

 With the increased demand for complex digital signal processing systems, real-time signal processing requires higher throughput systems. In the past, the throughput has been increased… (more)

Subjects/Keywords: Digital filters (Mathematics)

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Oren, J. A. (1994). Design of an asynchronous third-order finite impulse response filter. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/35774

Chicago Manual of Style (16th Edition):

Oren, Joel A. “Design of an asynchronous third-order finite impulse response filter.” 1994. Masters Thesis, Oregon State University. Accessed November 17, 2019. http://hdl.handle.net/1957/35774.

MLA Handbook (7th Edition):

Oren, Joel A. “Design of an asynchronous third-order finite impulse response filter.” 1994. Web. 17 Nov 2019.

Vancouver:

Oren JA. Design of an asynchronous third-order finite impulse response filter. [Internet] [Masters thesis]. Oregon State University; 1994. [cited 2019 Nov 17]. Available from: http://hdl.handle.net/1957/35774.

Council of Science Editors:

Oren JA. Design of an asynchronous third-order finite impulse response filter. [Masters Thesis]. Oregon State University; 1994. Available from: http://hdl.handle.net/1957/35774


Oregon State University

8. Badyal, Rajeev. VLSI implementation of adaptive BIT/serial IIR filters.

Degree: MS, Electrical and Computer Engineering, 1992, Oregon State University

 A new structure for the implementation of bit/serial adaptive IIR filter is presented. The bit level system consists of gated full adders for the arithmetic… (more)

Subjects/Keywords: Electric filters; Digital  – Design and construction

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Badyal, R. (1992). VLSI implementation of adaptive BIT/serial IIR filters. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/36521

Chicago Manual of Style (16th Edition):

Badyal, Rajeev. “VLSI implementation of adaptive BIT/serial IIR filters.” 1992. Masters Thesis, Oregon State University. Accessed November 17, 2019. http://hdl.handle.net/1957/36521.

MLA Handbook (7th Edition):

Badyal, Rajeev. “VLSI implementation of adaptive BIT/serial IIR filters.” 1992. Web. 17 Nov 2019.

Vancouver:

Badyal R. VLSI implementation of adaptive BIT/serial IIR filters. [Internet] [Masters thesis]. Oregon State University; 1992. [cited 2019 Nov 17]. Available from: http://hdl.handle.net/1957/36521.

Council of Science Editors:

Badyal R. VLSI implementation of adaptive BIT/serial IIR filters. [Masters Thesis]. Oregon State University; 1992. Available from: http://hdl.handle.net/1957/36521


Oregon State University

9. Lee, Louis Wai-Fung. Fully efficient pipelined VLSI arrays for solving toeplitz matrices.

Degree: MS, Electrical and Computer Engineering, 1991, Oregon State University

 Fully efficient systolic arrays for the solution of Toeplitz matrices using Schur algorithm [1] have been obtained. By applying clustering mapping method [2], the complexity… (more)

Subjects/Keywords: Toeplitz matrices

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lee, L. W. (1991). Fully efficient pipelined VLSI arrays for solving toeplitz matrices. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/37297

Chicago Manual of Style (16th Edition):

Lee, Louis Wai-Fung. “Fully efficient pipelined VLSI arrays for solving toeplitz matrices.” 1991. Masters Thesis, Oregon State University. Accessed November 17, 2019. http://hdl.handle.net/1957/37297.

MLA Handbook (7th Edition):

Lee, Louis Wai-Fung. “Fully efficient pipelined VLSI arrays for solving toeplitz matrices.” 1991. Web. 17 Nov 2019.

Vancouver:

Lee LW. Fully efficient pipelined VLSI arrays for solving toeplitz matrices. [Internet] [Masters thesis]. Oregon State University; 1991. [cited 2019 Nov 17]. Available from: http://hdl.handle.net/1957/37297.

Council of Science Editors:

Lee LW. Fully efficient pipelined VLSI arrays for solving toeplitz matrices. [Masters Thesis]. Oregon State University; 1991. Available from: http://hdl.handle.net/1957/37297


Oregon State University

10. Chee, San-hwa. CMOS differential logic techniques for mixed-mode applications.

Degree: MS, Electrical and Computer Engineering, 1990, Oregon State University

Subjects/Keywords: Metal oxide semiconductors; Complimentary

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chee, S. (1990). CMOS differential logic techniques for mixed-mode applications. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/38201

Chicago Manual of Style (16th Edition):

Chee, San-hwa. “CMOS differential logic techniques for mixed-mode applications.” 1990. Masters Thesis, Oregon State University. Accessed November 17, 2019. http://hdl.handle.net/1957/38201.

MLA Handbook (7th Edition):

Chee, San-hwa. “CMOS differential logic techniques for mixed-mode applications.” 1990. Web. 17 Nov 2019.

Vancouver:

Chee S. CMOS differential logic techniques for mixed-mode applications. [Internet] [Masters thesis]. Oregon State University; 1990. [cited 2019 Nov 17]. Available from: http://hdl.handle.net/1957/38201.

Council of Science Editors:

Chee S. CMOS differential logic techniques for mixed-mode applications. [Masters Thesis]. Oregon State University; 1990. Available from: http://hdl.handle.net/1957/38201


Oregon State University

11. Chow, Andrew Siv-Anne. Application and analysis of CMOS FSCL for mixed-mode analog/digital ICs.

Degree: MS, Electrical and Computer Engineering, 1990, Oregon State University

 The new CMOS folded source-coupled logic (FSCL) technique intended for mixed-mode integrated circuits has been designed. It has advantages over conventional CMOS circuit in terms… (more)

Subjects/Keywords: Integrated circuits  – Very large scale integration

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chow, A. S. (1990). Application and analysis of CMOS FSCL for mixed-mode analog/digital ICs. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/40960

Chicago Manual of Style (16th Edition):

Chow, Andrew Siv-Anne. “Application and analysis of CMOS FSCL for mixed-mode analog/digital ICs.” 1990. Masters Thesis, Oregon State University. Accessed November 17, 2019. http://hdl.handle.net/1957/40960.

MLA Handbook (7th Edition):

Chow, Andrew Siv-Anne. “Application and analysis of CMOS FSCL for mixed-mode analog/digital ICs.” 1990. Web. 17 Nov 2019.

Vancouver:

Chow AS. Application and analysis of CMOS FSCL for mixed-mode analog/digital ICs. [Internet] [Masters thesis]. Oregon State University; 1990. [cited 2019 Nov 17]. Available from: http://hdl.handle.net/1957/40960.

Council of Science Editors:

Chow AS. Application and analysis of CMOS FSCL for mixed-mode analog/digital ICs. [Masters Thesis]. Oregon State University; 1990. Available from: http://hdl.handle.net/1957/40960


Oregon State University

12. Li, Aihua. Synthesis of multi-rate arrays from directional uniform recurrence equations.

Degree: MS, Electrical and Computer Engineering, 1990, Oregon State University

 Advances in VLSI array processing have led to many new parallel structures for real-time Digital Signal Processing (DSP) applications. Among all the architectures, systolic arrays… (more)

Subjects/Keywords: Array processors

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Li, A. (1990). Synthesis of multi-rate arrays from directional uniform recurrence equations. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/39873

Chicago Manual of Style (16th Edition):

Li, Aihua. “Synthesis of multi-rate arrays from directional uniform recurrence equations.” 1990. Masters Thesis, Oregon State University. Accessed November 17, 2019. http://hdl.handle.net/1957/39873.

MLA Handbook (7th Edition):

Li, Aihua. “Synthesis of multi-rate arrays from directional uniform recurrence equations.” 1990. Web. 17 Nov 2019.

Vancouver:

Li A. Synthesis of multi-rate arrays from directional uniform recurrence equations. [Internet] [Masters thesis]. Oregon State University; 1990. [cited 2019 Nov 17]. Available from: http://hdl.handle.net/1957/39873.

Council of Science Editors:

Li A. Synthesis of multi-rate arrays from directional uniform recurrence equations. [Masters Thesis]. Oregon State University; 1990. Available from: http://hdl.handle.net/1957/39873


Oregon State University

13. Shrivastava, Manu B. Comparison and analysis of current-mode logic circuits with differential and static CMOS.

Degree: MS, Electrical and Computer Engineering, 1994, Oregon State University

 This thesis describes the analysis and comparison of Folded Source-Coupled Logic (FSCL) with standard static CMOS, cascode voltage-switch logic and differential split-level logic gates. The… (more)

Subjects/Keywords: Metal oxide semiconductors; Complementary  – Design and construction

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Shrivastava, M. B. (1994). Comparison and analysis of current-mode logic circuits with differential and static CMOS. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/36770

Chicago Manual of Style (16th Edition):

Shrivastava, Manu B. “Comparison and analysis of current-mode logic circuits with differential and static CMOS.” 1994. Masters Thesis, Oregon State University. Accessed November 17, 2019. http://hdl.handle.net/1957/36770.

MLA Handbook (7th Edition):

Shrivastava, Manu B. “Comparison and analysis of current-mode logic circuits with differential and static CMOS.” 1994. Web. 17 Nov 2019.

Vancouver:

Shrivastava MB. Comparison and analysis of current-mode logic circuits with differential and static CMOS. [Internet] [Masters thesis]. Oregon State University; 1994. [cited 2019 Nov 17]. Available from: http://hdl.handle.net/1957/36770.

Council of Science Editors:

Shrivastava MB. Comparison and analysis of current-mode logic circuits with differential and static CMOS. [Masters Thesis]. Oregon State University; 1994. Available from: http://hdl.handle.net/1957/36770


Oregon State University

14. Mui, Lap K. Scheduling system of affine recurrence equations by means of piecewise affine timing functions.

Degree: MS, Electrical and Computer Engineering, 1992, Oregon State University

 Many systematic methods exist for mapping algorithms to processor arrays. The algorithm is usually specified as a set of recurrence equations, and the processor arrays… (more)

Subjects/Keywords: Production scheduling  – Mathematical models

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mui, L. K. (1992). Scheduling system of affine recurrence equations by means of piecewise affine timing functions. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/37328

Chicago Manual of Style (16th Edition):

Mui, Lap K. “Scheduling system of affine recurrence equations by means of piecewise affine timing functions.” 1992. Masters Thesis, Oregon State University. Accessed November 17, 2019. http://hdl.handle.net/1957/37328.

MLA Handbook (7th Edition):

Mui, Lap K. “Scheduling system of affine recurrence equations by means of piecewise affine timing functions.” 1992. Web. 17 Nov 2019.

Vancouver:

Mui LK. Scheduling system of affine recurrence equations by means of piecewise affine timing functions. [Internet] [Masters thesis]. Oregon State University; 1992. [cited 2019 Nov 17]. Available from: http://hdl.handle.net/1957/37328.

Council of Science Editors:

Mui LK. Scheduling system of affine recurrence equations by means of piecewise affine timing functions. [Masters Thesis]. Oregon State University; 1992. Available from: http://hdl.handle.net/1957/37328


Oregon State University

15. Lashkarian, Navid. Optimum equalization and synchronization of broadband multicarrier systems.

Degree: PhD, Electrical and Computer Engineering, 1999, Oregon State University

 The application of information theory and digital signal processing techniques to digital communication has resulted in robust methods for reliable high speed data transmission over… (more)

Subjects/Keywords: Broadband communication systems

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lashkarian, N. (1999). Optimum equalization and synchronization of broadband multicarrier systems. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/32918

Chicago Manual of Style (16th Edition):

Lashkarian, Navid. “Optimum equalization and synchronization of broadband multicarrier systems.” 1999. Doctoral Dissertation, Oregon State University. Accessed November 17, 2019. http://hdl.handle.net/1957/32918.

MLA Handbook (7th Edition):

Lashkarian, Navid. “Optimum equalization and synchronization of broadband multicarrier systems.” 1999. Web. 17 Nov 2019.

Vancouver:

Lashkarian N. Optimum equalization and synchronization of broadband multicarrier systems. [Internet] [Doctoral dissertation]. Oregon State University; 1999. [cited 2019 Nov 17]. Available from: http://hdl.handle.net/1957/32918.

Council of Science Editors:

Lashkarian N. Optimum equalization and synchronization of broadband multicarrier systems. [Doctoral Dissertation]. Oregon State University; 1999. Available from: http://hdl.handle.net/1957/32918


Oregon State University

16. Poplin, Dwight. Distributed arithmetic architecture for the discrete cosine transform.

Degree: MS, Electrical and Computer Engineering, 1997, Oregon State University

 The Discrete Cosine Transform is used in many image and video compression standards. Many methods have been developed for efficiently computing the Discrete Cosine Transform… (more)

Subjects/Keywords: Video compression  – Mathematical models

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Poplin, D. (1997). Distributed arithmetic architecture for the discrete cosine transform. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/34243

Chicago Manual of Style (16th Edition):

Poplin, Dwight. “Distributed arithmetic architecture for the discrete cosine transform.” 1997. Masters Thesis, Oregon State University. Accessed November 17, 2019. http://hdl.handle.net/1957/34243.

MLA Handbook (7th Edition):

Poplin, Dwight. “Distributed arithmetic architecture for the discrete cosine transform.” 1997. Web. 17 Nov 2019.

Vancouver:

Poplin D. Distributed arithmetic architecture for the discrete cosine transform. [Internet] [Masters thesis]. Oregon State University; 1997. [cited 2019 Nov 17]. Available from: http://hdl.handle.net/1957/34243.

Council of Science Editors:

Poplin D. Distributed arithmetic architecture for the discrete cosine transform. [Masters Thesis]. Oregon State University; 1997. Available from: http://hdl.handle.net/1957/34243


Oregon State University

17. Maleki, Mohammad. Current-mode flash analog-to-digital converter.

Degree: MS, Electrical and Computer Engineering, 1992, Oregon State University

 This thesis describes the development of a flash analog-to-digital converter based on current-mode technique. The advantages of current -mode technique are higher speed, smaller chip… (more)

Subjects/Keywords: Analog-to-digital converters

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Maleki, M. (1992). Current-mode flash analog-to-digital converter. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/37347

Chicago Manual of Style (16th Edition):

Maleki, Mohammad. “Current-mode flash analog-to-digital converter.” 1992. Masters Thesis, Oregon State University. Accessed November 17, 2019. http://hdl.handle.net/1957/37347.

MLA Handbook (7th Edition):

Maleki, Mohammad. “Current-mode flash analog-to-digital converter.” 1992. Web. 17 Nov 2019.

Vancouver:

Maleki M. Current-mode flash analog-to-digital converter. [Internet] [Masters thesis]. Oregon State University; 1992. [cited 2019 Nov 17]. Available from: http://hdl.handle.net/1957/37347.

Council of Science Editors:

Maleki M. Current-mode flash analog-to-digital converter. [Masters Thesis]. Oregon State University; 1992. Available from: http://hdl.handle.net/1957/37347


Oregon State University

18. Abdennadher, Salem. Adaptive correction techniques for delta-sigma A/D converters.

Degree: MS, Electrical and Computer Engineering, 1992, Oregon State University

 Oversampling analog-to-digital and digital-to-analog converters are gaining more popularity in many signal processing applications. Delta-sigma modulators are used in practical applications of oversampling systems because… (more)

Subjects/Keywords: Analog-to-digital converters

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Abdennadher, S. (1992). Adaptive correction techniques for delta-sigma A/D converters. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/36199

Chicago Manual of Style (16th Edition):

Abdennadher, Salem. “Adaptive correction techniques for delta-sigma A/D converters.” 1992. Masters Thesis, Oregon State University. Accessed November 17, 2019. http://hdl.handle.net/1957/36199.

MLA Handbook (7th Edition):

Abdennadher, Salem. “Adaptive correction techniques for delta-sigma A/D converters.” 1992. Web. 17 Nov 2019.

Vancouver:

Abdennadher S. Adaptive correction techniques for delta-sigma A/D converters. [Internet] [Masters thesis]. Oregon State University; 1992. [cited 2019 Nov 17]. Available from: http://hdl.handle.net/1957/36199.

Council of Science Editors:

Abdennadher S. Adaptive correction techniques for delta-sigma A/D converters. [Masters Thesis]. Oregon State University; 1992. Available from: http://hdl.handle.net/1957/36199


Oregon State University

19. Bribech, Habib. Adaptive noise cancellation for second-order delta-sigma A/D converters.

Degree: MS, Electrical and Computer Engineering, 1992, Oregon State University

 Oversampled analog-to-digital (A/D) converter architectures have been receiving increased attention for high-precision A/D converters. These architectures offer the means of exchanging resolution in time for… (more)

Subjects/Keywords: Analog-to-digital converters  – Noise

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bribech, H. (1992). Adaptive noise cancellation for second-order delta-sigma A/D converters. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/35928

Chicago Manual of Style (16th Edition):

Bribech, Habib. “Adaptive noise cancellation for second-order delta-sigma A/D converters.” 1992. Masters Thesis, Oregon State University. Accessed November 17, 2019. http://hdl.handle.net/1957/35928.

MLA Handbook (7th Edition):

Bribech, Habib. “Adaptive noise cancellation for second-order delta-sigma A/D converters.” 1992. Web. 17 Nov 2019.

Vancouver:

Bribech H. Adaptive noise cancellation for second-order delta-sigma A/D converters. [Internet] [Masters thesis]. Oregon State University; 1992. [cited 2019 Nov 17]. Available from: http://hdl.handle.net/1957/35928.

Council of Science Editors:

Bribech H. Adaptive noise cancellation for second-order delta-sigma A/D converters. [Masters Thesis]. Oregon State University; 1992. Available from: http://hdl.handle.net/1957/35928


Oregon State University

20. Freytag, Vincent R. Program allocation for hypercube based dataflow systems.

Degree: MS, Electrical and Computer Engineering, 1993, Oregon State University

 The dataflow model of computation differs from the traditional control-flow model of computation in that it does not utilize a program counter to sequence instructions… (more)

Subjects/Keywords: Data flow computing

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Freytag, V. R. (1993). Program allocation for hypercube based dataflow systems. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/36758

Chicago Manual of Style (16th Edition):

Freytag, Vincent R. “Program allocation for hypercube based dataflow systems.” 1993. Masters Thesis, Oregon State University. Accessed November 17, 2019. http://hdl.handle.net/1957/36758.

MLA Handbook (7th Edition):

Freytag, Vincent R. “Program allocation for hypercube based dataflow systems.” 1993. Web. 17 Nov 2019.

Vancouver:

Freytag VR. Program allocation for hypercube based dataflow systems. [Internet] [Masters thesis]. Oregon State University; 1993. [cited 2019 Nov 17]. Available from: http://hdl.handle.net/1957/36758.

Council of Science Editors:

Freytag VR. Program allocation for hypercube based dataflow systems. [Masters Thesis]. Oregon State University; 1993. Available from: http://hdl.handle.net/1957/36758


Oregon State University

21. Wong, Man Wa. Low noise FSCL digital circuits for decimation filter.

Degree: MS, Electrical and Computer Engineering, 1993, Oregon State University

 A new circuit technique called Folded Source Coupled Logic (FSCL) has been developed to implement the digital section of mixed-signal IC applications. This FSCL circuit… (more)

Subjects/Keywords: Logic circuits  – Design and construction

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wong, M. W. (1993). Low noise FSCL digital circuits for decimation filter. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/36625

Chicago Manual of Style (16th Edition):

Wong, Man Wa. “Low noise FSCL digital circuits for decimation filter.” 1993. Masters Thesis, Oregon State University. Accessed November 17, 2019. http://hdl.handle.net/1957/36625.

MLA Handbook (7th Edition):

Wong, Man Wa. “Low noise FSCL digital circuits for decimation filter.” 1993. Web. 17 Nov 2019.

Vancouver:

Wong MW. Low noise FSCL digital circuits for decimation filter. [Internet] [Masters thesis]. Oregon State University; 1993. [cited 2019 Nov 17]. Available from: http://hdl.handle.net/1957/36625.

Council of Science Editors:

Wong MW. Low noise FSCL digital circuits for decimation filter. [Masters Thesis]. Oregon State University; 1993. Available from: http://hdl.handle.net/1957/36625


Oregon State University

22. Qiu, Xiangping. MOSFET-only predictive track and hold circuit.

Degree: MS, Electrical and Computer Engineering, 1997, Oregon State University

 High-accuracy and high-speed CMOS track-and-hold (T/H) or sample-and-hold (S/H) circuits are an important part of the analog-to-digital interface. The switched-capacitor (SC) circuits usually contain one… (more)

Subjects/Keywords: Metal oxide semiconductor field-effect transistors

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Qiu, X. (1997). MOSFET-only predictive track and hold circuit. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/34941

Chicago Manual of Style (16th Edition):

Qiu, Xiangping. “MOSFET-only predictive track and hold circuit.” 1997. Masters Thesis, Oregon State University. Accessed November 17, 2019. http://hdl.handle.net/1957/34941.

MLA Handbook (7th Edition):

Qiu, Xiangping. “MOSFET-only predictive track and hold circuit.” 1997. Web. 17 Nov 2019.

Vancouver:

Qiu X. MOSFET-only predictive track and hold circuit. [Internet] [Masters thesis]. Oregon State University; 1997. [cited 2019 Nov 17]. Available from: http://hdl.handle.net/1957/34941.

Council of Science Editors:

Qiu X. MOSFET-only predictive track and hold circuit. [Masters Thesis]. Oregon State University; 1997. Available from: http://hdl.handle.net/1957/34941


Oregon State University

23. Gao, Hairong. Design of high-speed summing circuitry and comparator for adaptive parallel multi-level decision feedback equalization.

Degree: MS, Electrical and Computer Engineering, 1997, Oregon State University

 Multi-level decision feedback equalization (MDFE) is an effective sampled signal processing technique to remove inter-symbol interference (ISI) from disk read-back signals. Parallelism which doubles the… (more)

Subjects/Keywords: Feedback control systems  – Design and construction

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Gao, H. (1997). Design of high-speed summing circuitry and comparator for adaptive parallel multi-level decision feedback equalization. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/34282

Chicago Manual of Style (16th Edition):

Gao, Hairong. “Design of high-speed summing circuitry and comparator for adaptive parallel multi-level decision feedback equalization.” 1997. Masters Thesis, Oregon State University. Accessed November 17, 2019. http://hdl.handle.net/1957/34282.

MLA Handbook (7th Edition):

Gao, Hairong. “Design of high-speed summing circuitry and comparator for adaptive parallel multi-level decision feedback equalization.” 1997. Web. 17 Nov 2019.

Vancouver:

Gao H. Design of high-speed summing circuitry and comparator for adaptive parallel multi-level decision feedback equalization. [Internet] [Masters thesis]. Oregon State University; 1997. [cited 2019 Nov 17]. Available from: http://hdl.handle.net/1957/34282.

Council of Science Editors:

Gao H. Design of high-speed summing circuitry and comparator for adaptive parallel multi-level decision feedback equalization. [Masters Thesis]. Oregon State University; 1997. Available from: http://hdl.handle.net/1957/34282


Oregon State University

24. Dutta, Amit K. Interference cancellation for shot-code DS-CDMA in the presence of channel fading.

Degree: PhD, Electrical and Computer Engineering, 1997, Oregon State University

 Interference from other adjacent users in wireless applications is a major problem in direct-sequence code-division multiple-access (DS-CDMA). This is also known as the near-far problem… (more)

Subjects/Keywords: Code division multiple access

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Dutta, A. K. (1997). Interference cancellation for shot-code DS-CDMA in the presence of channel fading. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/33881

Chicago Manual of Style (16th Edition):

Dutta, Amit K. “Interference cancellation for shot-code DS-CDMA in the presence of channel fading.” 1997. Doctoral Dissertation, Oregon State University. Accessed November 17, 2019. http://hdl.handle.net/1957/33881.

MLA Handbook (7th Edition):

Dutta, Amit K. “Interference cancellation for shot-code DS-CDMA in the presence of channel fading.” 1997. Web. 17 Nov 2019.

Vancouver:

Dutta AK. Interference cancellation for shot-code DS-CDMA in the presence of channel fading. [Internet] [Doctoral dissertation]. Oregon State University; 1997. [cited 2019 Nov 17]. Available from: http://hdl.handle.net/1957/33881.

Council of Science Editors:

Dutta AK. Interference cancellation for shot-code DS-CDMA in the presence of channel fading. [Doctoral Dissertation]. Oregon State University; 1997. Available from: http://hdl.handle.net/1957/33881


Oregon State University

25. Xiang, Yihai. Design of high-speed adaptive parallel multi-level decision feedback equalizer.

Degree: MS, Electrical and Computer Engineering, 1997, Oregon State University

 Multi-level decision feedback equalization (MDFE) is an effective technique to remove inter-symbol interference (ISI) from disk readback signals, which uses the simple architecture of decision… (more)

Subjects/Keywords: Feedback control systems  – Design and construction

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Xiang, Y. (1997). Design of high-speed adaptive parallel multi-level decision feedback equalizer. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/34362

Chicago Manual of Style (16th Edition):

Xiang, Yihai. “Design of high-speed adaptive parallel multi-level decision feedback equalizer.” 1997. Masters Thesis, Oregon State University. Accessed November 17, 2019. http://hdl.handle.net/1957/34362.

MLA Handbook (7th Edition):

Xiang, Yihai. “Design of high-speed adaptive parallel multi-level decision feedback equalizer.” 1997. Web. 17 Nov 2019.

Vancouver:

Xiang Y. Design of high-speed adaptive parallel multi-level decision feedback equalizer. [Internet] [Masters thesis]. Oregon State University; 1997. [cited 2019 Nov 17]. Available from: http://hdl.handle.net/1957/34362.

Council of Science Editors:

Xiang Y. Design of high-speed adaptive parallel multi-level decision feedback equalizer. [Masters Thesis]. Oregon State University; 1997. Available from: http://hdl.handle.net/1957/34362


Oregon State University

26. Kulkarni, Satish S. Sensitivity analysis and architectural comparison of narrow-band sharp-transition digital filters.

Degree: MS, Electrical and Computer Engineering, 1994, Oregon State University

 Due to advances in high-density low-cost VLSI and communication technology, digital filtering and signal processing are being widely used for real-time signal processing applications. Given… (more)

Subjects/Keywords: Electric filters; Digital  – Design and construction

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kulkarni, S. S. (1994). Sensitivity analysis and architectural comparison of narrow-band sharp-transition digital filters. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/35234

Chicago Manual of Style (16th Edition):

Kulkarni, Satish S. “Sensitivity analysis and architectural comparison of narrow-band sharp-transition digital filters.” 1994. Masters Thesis, Oregon State University. Accessed November 17, 2019. http://hdl.handle.net/1957/35234.

MLA Handbook (7th Edition):

Kulkarni, Satish S. “Sensitivity analysis and architectural comparison of narrow-band sharp-transition digital filters.” 1994. Web. 17 Nov 2019.

Vancouver:

Kulkarni SS. Sensitivity analysis and architectural comparison of narrow-band sharp-transition digital filters. [Internet] [Masters thesis]. Oregon State University; 1994. [cited 2019 Nov 17]. Available from: http://hdl.handle.net/1957/35234.

Council of Science Editors:

Kulkarni SS. Sensitivity analysis and architectural comparison of narrow-band sharp-transition digital filters. [Masters Thesis]. Oregon State University; 1994. Available from: http://hdl.handle.net/1957/35234


Oregon State University

27. Beck, Jeffery S. A programmable BiCMOS transconductance-capacitor filter for high frequencies.

Degree: MS, Electrical and Computer Engineering, 1993, Oregon State University

 With advancements in CMOS technology, high speed analog circuits that were traditionally implemented with discrete circuit components can now be made monolithically. Antialiasing filters for… (more)

Subjects/Keywords: Electric filters  – Design and construction

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Beck, J. S. (1993). A programmable BiCMOS transconductance-capacitor filter for high frequencies. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/36089

Chicago Manual of Style (16th Edition):

Beck, Jeffery S. “A programmable BiCMOS transconductance-capacitor filter for high frequencies.” 1993. Masters Thesis, Oregon State University. Accessed November 17, 2019. http://hdl.handle.net/1957/36089.

MLA Handbook (7th Edition):

Beck, Jeffery S. “A programmable BiCMOS transconductance-capacitor filter for high frequencies.” 1993. Web. 17 Nov 2019.

Vancouver:

Beck JS. A programmable BiCMOS transconductance-capacitor filter for high frequencies. [Internet] [Masters thesis]. Oregon State University; 1993. [cited 2019 Nov 17]. Available from: http://hdl.handle.net/1957/36089.

Council of Science Editors:

Beck JS. A programmable BiCMOS transconductance-capacitor filter for high frequencies. [Masters Thesis]. Oregon State University; 1993. Available from: http://hdl.handle.net/1957/36089


Oregon State University

28. Luo, Lei. Power spectrum estimation of sinusoids from white and colored noises using the canonical correlation analysis method.

Degree: MS, Electrical and Computer Engineering, 1989, Oregon State University

 The purpose of this thesis is to apply the Canonical Correlation Analysis (CCA) which belongs to the parametric methods for power spectral estimation in the… (more)

Subjects/Keywords: Electronic noise

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Luo, L. (1989). Power spectrum estimation of sinusoids from white and colored noises using the canonical correlation analysis method. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/39871

Chicago Manual of Style (16th Edition):

Luo, Lei. “Power spectrum estimation of sinusoids from white and colored noises using the canonical correlation analysis method.” 1989. Masters Thesis, Oregon State University. Accessed November 17, 2019. http://hdl.handle.net/1957/39871.

MLA Handbook (7th Edition):

Luo, Lei. “Power spectrum estimation of sinusoids from white and colored noises using the canonical correlation analysis method.” 1989. Web. 17 Nov 2019.

Vancouver:

Luo L. Power spectrum estimation of sinusoids from white and colored noises using the canonical correlation analysis method. [Internet] [Masters thesis]. Oregon State University; 1989. [cited 2019 Nov 17]. Available from: http://hdl.handle.net/1957/39871.

Council of Science Editors:

Luo L. Power spectrum estimation of sinusoids from white and colored noises using the canonical correlation analysis method. [Masters Thesis]. Oregon State University; 1989. Available from: http://hdl.handle.net/1957/39871


Oregon State University

29. Zhai, Dalun. Analysis and design of bandpass delta-sigma A/D converters.

Degree: MS, Electrical and Computer Engineering, 1991, Oregon State University

 A new approach to oversampled delta-sigma A/D converters ( AZ modulators ) is introduced, where a differential pseudo-Npath filter stage is used as a basic… (more)

Subjects/Keywords: Analog-to-digital converters

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zhai, D. (1991). Analysis and design of bandpass delta-sigma A/D converters. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/6718

Chicago Manual of Style (16th Edition):

Zhai, Dalun. “Analysis and design of bandpass delta-sigma A/D converters.” 1991. Masters Thesis, Oregon State University. Accessed November 17, 2019. http://hdl.handle.net/1957/6718.

MLA Handbook (7th Edition):

Zhai, Dalun. “Analysis and design of bandpass delta-sigma A/D converters.” 1991. Web. 17 Nov 2019.

Vancouver:

Zhai D. Analysis and design of bandpass delta-sigma A/D converters. [Internet] [Masters thesis]. Oregon State University; 1991. [cited 2019 Nov 17]. Available from: http://hdl.handle.net/1957/6718.

Council of Science Editors:

Zhai D. Analysis and design of bandpass delta-sigma A/D converters. [Masters Thesis]. Oregon State University; 1991. Available from: http://hdl.handle.net/1957/6718

.