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You searched for +publisher:"Oregon State University" +contributor:("Hanumolu, Pavan"). Showing records 1 – 30 of 30 total matches.

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Oregon State University

1. Wang, Jingguang. Techniques for improving timing accuracy of multi-gigahertz track/hold circuits.

Degree: MS, Electrical and Computer Engineering, 2008, Oregon State University

 Multi-Gigahertz sampling rate Analog-to-Digital Converters (ADC) with 5-8 bits resolution are used in many signal communication applications. Unfortunately, the performance of the high speed ADC… (more)

Subjects/Keywords: ADC; Analog-to-digital converters

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APA (6th Edition):

Wang, J. (2008). Techniques for improving timing accuracy of multi-gigahertz track/hold circuits. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/10041

Chicago Manual of Style (16th Edition):

Wang, Jingguang. “Techniques for improving timing accuracy of multi-gigahertz track/hold circuits.” 2008. Masters Thesis, Oregon State University. Accessed May 21, 2019. http://hdl.handle.net/1957/10041.

MLA Handbook (7th Edition):

Wang, Jingguang. “Techniques for improving timing accuracy of multi-gigahertz track/hold circuits.” 2008. Web. 21 May 2019.

Vancouver:

Wang J. Techniques for improving timing accuracy of multi-gigahertz track/hold circuits. [Internet] [Masters thesis]. Oregon State University; 2008. [cited 2019 May 21]. Available from: http://hdl.handle.net/1957/10041.

Council of Science Editors:

Wang J. Techniques for improving timing accuracy of multi-gigahertz track/hold circuits. [Masters Thesis]. Oregon State University; 2008. Available from: http://hdl.handle.net/1957/10041


Oregon State University

2. Panitantum, Napong. Ultra-low-energy transmitters for battery-free wireless sensor networks.

Degree: PhD, Electrical and Computer Engineering, 2011, Oregon State University

 As the number of autonomous data collection applications keep increasing, the demand for wireless sensor networks (WSNs) has seen explosive growth. In this dissertation, an… (more)

Subjects/Keywords: Ultra low energy

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APA (6th Edition):

Panitantum, N. (2011). Ultra-low-energy transmitters for battery-free wireless sensor networks. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/21887

Chicago Manual of Style (16th Edition):

Panitantum, Napong. “Ultra-low-energy transmitters for battery-free wireless sensor networks.” 2011. Doctoral Dissertation, Oregon State University. Accessed May 21, 2019. http://hdl.handle.net/1957/21887.

MLA Handbook (7th Edition):

Panitantum, Napong. “Ultra-low-energy transmitters for battery-free wireless sensor networks.” 2011. Web. 21 May 2019.

Vancouver:

Panitantum N. Ultra-low-energy transmitters for battery-free wireless sensor networks. [Internet] [Doctoral dissertation]. Oregon State University; 2011. [cited 2019 May 21]. Available from: http://hdl.handle.net/1957/21887.

Council of Science Editors:

Panitantum N. Ultra-low-energy transmitters for battery-free wireless sensor networks. [Doctoral Dissertation]. Oregon State University; 2011. Available from: http://hdl.handle.net/1957/21887


Oregon State University

3. Bang, Sarvesh Jagdish. Design techniques for high efficiency LED drivers.

Degree: MS, Electrical and Computer Engineering, 2009, Oregon State University

 The increasing popularity of cellular phones with integrated cameras in the recent past has led to major improvements in its image quality. However, integration of… (more)

Subjects/Keywords: LED; Electric power  – Conservation

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APA (6th Edition):

Bang, S. J. (2009). Design techniques for high efficiency LED drivers. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/13071

Chicago Manual of Style (16th Edition):

Bang, Sarvesh Jagdish. “Design techniques for high efficiency LED drivers.” 2009. Masters Thesis, Oregon State University. Accessed May 21, 2019. http://hdl.handle.net/1957/13071.

MLA Handbook (7th Edition):

Bang, Sarvesh Jagdish. “Design techniques for high efficiency LED drivers.” 2009. Web. 21 May 2019.

Vancouver:

Bang SJ. Design techniques for high efficiency LED drivers. [Internet] [Masters thesis]. Oregon State University; 2009. [cited 2019 May 21]. Available from: http://hdl.handle.net/1957/13071.

Council of Science Editors:

Bang SJ. Design techniques for high efficiency LED drivers. [Masters Thesis]. Oregon State University; 2009. Available from: http://hdl.handle.net/1957/13071


Oregon State University

4. Arakali, Abhijith. Low-power techniques for supply-noise mitigation in phase-locked loops.

Degree: PhD, Electrical and Computer Engineering, 2010, Oregon State University

 Modern day digital systems employ frequency synthesizers to provide a common clock to the system. They are undergoing large scale integration due to which, mitigation… (more)

Subjects/Keywords: Phase-locked loops

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APA (6th Edition):

Arakali, A. (2010). Low-power techniques for supply-noise mitigation in phase-locked loops. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/14281

Chicago Manual of Style (16th Edition):

Arakali, Abhijith. “Low-power techniques for supply-noise mitigation in phase-locked loops.” 2010. Doctoral Dissertation, Oregon State University. Accessed May 21, 2019. http://hdl.handle.net/1957/14281.

MLA Handbook (7th Edition):

Arakali, Abhijith. “Low-power techniques for supply-noise mitigation in phase-locked loops.” 2010. Web. 21 May 2019.

Vancouver:

Arakali A. Low-power techniques for supply-noise mitigation in phase-locked loops. [Internet] [Doctoral dissertation]. Oregon State University; 2010. [cited 2019 May 21]. Available from: http://hdl.handle.net/1957/14281.

Council of Science Editors:

Arakali A. Low-power techniques for supply-noise mitigation in phase-locked loops. [Doctoral Dissertation]. Oregon State University; 2010. Available from: http://hdl.handle.net/1957/14281


Oregon State University

5. Yu, Wenhuan. Design techniques for low power ADCs.

Degree: PhD, Electrical and Computer Engineering, 2010, Oregon State University

 This dissertation presents an incremental analog-to-digital converter (ADC) with digital digital-to-analog converter (DAC) mismatch correction. A theoretical time-domain analysis technique was developed to predict the… (more)

Subjects/Keywords: data converter; Analog-to-digital converters  – Design and construction

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APA (6th Edition):

Yu, W. (2010). Design techniques for low power ADCs. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/14316

Chicago Manual of Style (16th Edition):

Yu, Wenhuan. “Design techniques for low power ADCs.” 2010. Doctoral Dissertation, Oregon State University. Accessed May 21, 2019. http://hdl.handle.net/1957/14316.

MLA Handbook (7th Edition):

Yu, Wenhuan. “Design techniques for low power ADCs.” 2010. Web. 21 May 2019.

Vancouver:

Yu W. Design techniques for low power ADCs. [Internet] [Doctoral dissertation]. Oregon State University; 2010. [cited 2019 May 21]. Available from: http://hdl.handle.net/1957/14316.

Council of Science Editors:

Yu W. Design techniques for low power ADCs. [Doctoral Dissertation]. Oregon State University; 2010. Available from: http://hdl.handle.net/1957/14316


Oregon State University

6. Mark, Shannon. Dual referencing guidelines to minimize power delivery noise coupling.

Degree: MS, Electrical and Computer Engineering, 2011, Oregon State University

 Dual referencing has been garnering a lot of attention in the power integrity community, specifically in the voltage mode driver application because it shows a… (more)

Subjects/Keywords: Dual Referencing

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APA (6th Edition):

Mark, S. (2011). Dual referencing guidelines to minimize power delivery noise coupling. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/21724

Chicago Manual of Style (16th Edition):

Mark, Shannon. “Dual referencing guidelines to minimize power delivery noise coupling.” 2011. Masters Thesis, Oregon State University. Accessed May 21, 2019. http://hdl.handle.net/1957/21724.

MLA Handbook (7th Edition):

Mark, Shannon. “Dual referencing guidelines to minimize power delivery noise coupling.” 2011. Web. 21 May 2019.

Vancouver:

Mark S. Dual referencing guidelines to minimize power delivery noise coupling. [Internet] [Masters thesis]. Oregon State University; 2011. [cited 2019 May 21]. Available from: http://hdl.handle.net/1957/21724.

Council of Science Editors:

Mark S. Dual referencing guidelines to minimize power delivery noise coupling. [Masters Thesis]. Oregon State University; 2011. Available from: http://hdl.handle.net/1957/21724


Oregon State University

7. Drost, Brian George. Time-based analog signal processing.

Degree: MS, Electrical and Computer Engineering, 2011, Oregon State University

 As CMOS processes size continues to shrink, a number of factors limit the ability of analog circuit performance to scale with the process. These issues… (more)

Subjects/Keywords: Analog Filter

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APA (6th Edition):

Drost, B. G. (2011). Time-based analog signal processing. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/21810

Chicago Manual of Style (16th Edition):

Drost, Brian George. “Time-based analog signal processing.” 2011. Masters Thesis, Oregon State University. Accessed May 21, 2019. http://hdl.handle.net/1957/21810.

MLA Handbook (7th Edition):

Drost, Brian George. “Time-based analog signal processing.” 2011. Web. 21 May 2019.

Vancouver:

Drost BG. Time-based analog signal processing. [Internet] [Masters thesis]. Oregon State University; 2011. [cited 2019 May 21]. Available from: http://hdl.handle.net/1957/21810.

Council of Science Editors:

Drost BG. Time-based analog signal processing. [Masters Thesis]. Oregon State University; 2011. Available from: http://hdl.handle.net/1957/21810


Oregon State University

8. Hu, Kangmin. Analysis and design on low-power multi-Gb/s serial links.

Degree: PhD, Electrical and Computer Engineering, 2011, Oregon State University

 High speed serial links are critical components for addressing the growing demand for I/O bandwidth in next-generation computing applications, such as many-core systems, backplane and… (more)

Subjects/Keywords: serial link; Radio  – Transmitter-receivers  – Energy consumption

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APA (6th Edition):

Hu, K. (2011). Analysis and design on low-power multi-Gb/s serial links. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/21944

Chicago Manual of Style (16th Edition):

Hu, Kangmin. “Analysis and design on low-power multi-Gb/s serial links.” 2011. Doctoral Dissertation, Oregon State University. Accessed May 21, 2019. http://hdl.handle.net/1957/21944.

MLA Handbook (7th Edition):

Hu, Kangmin. “Analysis and design on low-power multi-Gb/s serial links.” 2011. Web. 21 May 2019.

Vancouver:

Hu K. Analysis and design on low-power multi-Gb/s serial links. [Internet] [Doctoral dissertation]. Oregon State University; 2011. [cited 2019 May 21]. Available from: http://hdl.handle.net/1957/21944.

Council of Science Editors:

Hu K. Analysis and design on low-power multi-Gb/s serial links. [Doctoral Dissertation]. Oregon State University; 2011. Available from: http://hdl.handle.net/1957/21944


Oregon State University

9. Rapolu, Kavitha. Broadband modeling of on-chip transformers for silicon RFICs.

Degree: MS, Electrical and Computer Engineering, 2008, Oregon State University

 Magnetically coupled passive transformers are increasingly integrated on-chip for various analog and radio frequency (RF) applications including direct current (DC) isolation, impedance transformation/matching, and conversion… (more)

Subjects/Keywords: Monolithic Transformers; Radio frequency integrated circuits  – Mathematical models

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APA (6th Edition):

Rapolu, K. (2008). Broadband modeling of on-chip transformers for silicon RFICs. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/9602

Chicago Manual of Style (16th Edition):

Rapolu, Kavitha. “Broadband modeling of on-chip transformers for silicon RFICs.” 2008. Masters Thesis, Oregon State University. Accessed May 21, 2019. http://hdl.handle.net/1957/9602.

MLA Handbook (7th Edition):

Rapolu, Kavitha. “Broadband modeling of on-chip transformers for silicon RFICs.” 2008. Web. 21 May 2019.

Vancouver:

Rapolu K. Broadband modeling of on-chip transformers for silicon RFICs. [Internet] [Masters thesis]. Oregon State University; 2008. [cited 2019 May 21]. Available from: http://hdl.handle.net/1957/9602.

Council of Science Editors:

Rapolu K. Broadband modeling of on-chip transformers for silicon RFICs. [Masters Thesis]. Oregon State University; 2008. Available from: http://hdl.handle.net/1957/9602


Oregon State University

10. Rao, Sachin B. Linearizing techniques for voltage controlled oscillator based analog to digital converters.

Degree: PhD, Electrical and Computer Engineering, 2013, Oregon State University

 Voltage controlled oscillator (VCO) based ADC is an important class of time-domain ADC that has gained widespread acceptance due to their several desirable properties. VCO-based… (more)

Subjects/Keywords: VCO-based ADC; Analog-to-digital converters

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APA (6th Edition):

Rao, S. B. (2013). Linearizing techniques for voltage controlled oscillator based analog to digital converters. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/38709

Chicago Manual of Style (16th Edition):

Rao, Sachin B. “Linearizing techniques for voltage controlled oscillator based analog to digital converters.” 2013. Doctoral Dissertation, Oregon State University. Accessed May 21, 2019. http://hdl.handle.net/1957/38709.

MLA Handbook (7th Edition):

Rao, Sachin B. “Linearizing techniques for voltage controlled oscillator based analog to digital converters.” 2013. Web. 21 May 2019.

Vancouver:

Rao SB. Linearizing techniques for voltage controlled oscillator based analog to digital converters. [Internet] [Doctoral dissertation]. Oregon State University; 2013. [cited 2019 May 21]. Available from: http://hdl.handle.net/1957/38709.

Council of Science Editors:

Rao SB. Linearizing techniques for voltage controlled oscillator based analog to digital converters. [Doctoral Dissertation]. Oregon State University; 2013. Available from: http://hdl.handle.net/1957/38709


Oregon State University

11. Wang, Tao. Low-power high-resolution delta-sigma ADC design techniques.

Degree: PhD, Electrical and Computer Engineering, 2012, Oregon State University

 This dissertation presents a low-power high-resolution delta-sigma ADC. Two new architectural design techniques are proposed to reduce the power dissipation of the ADC. Compared to… (more)

Subjects/Keywords: ADC; Analog-to-digital converters  – Design and construction

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APA (6th Edition):

Wang, T. (2012). Low-power high-resolution delta-sigma ADC design techniques. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/29740

Chicago Manual of Style (16th Edition):

Wang, Tao. “Low-power high-resolution delta-sigma ADC design techniques.” 2012. Doctoral Dissertation, Oregon State University. Accessed May 21, 2019. http://hdl.handle.net/1957/29740.

MLA Handbook (7th Edition):

Wang, Tao. “Low-power high-resolution delta-sigma ADC design techniques.” 2012. Web. 21 May 2019.

Vancouver:

Wang T. Low-power high-resolution delta-sigma ADC design techniques. [Internet] [Doctoral dissertation]. Oregon State University; 2012. [cited 2019 May 21]. Available from: http://hdl.handle.net/1957/29740.

Council of Science Editors:

Wang T. Low-power high-resolution delta-sigma ADC design techniques. [Doctoral Dissertation]. Oregon State University; 2012. Available from: http://hdl.handle.net/1957/29740


Oregon State University

12. Khan, Qadeer Ahmad. Digitally assisted control techniques for high performance switching DC-DC converters.

Degree: PhD, Electrical and Computer Engineering, 2012, Oregon State University

 Digitally controlled switching DC-DC converters have recently emerged as an attractive alternative to conventional switching converters based on analog control techniques. This research focuses on… (more)

Subjects/Keywords: voltage regulator; DC-to-DC converters  – Automatic control

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APA (6th Edition):

Khan, Q. A. (2012). Digitally assisted control techniques for high performance switching DC-DC converters. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/30174

Chicago Manual of Style (16th Edition):

Khan, Qadeer Ahmad. “Digitally assisted control techniques for high performance switching DC-DC converters.” 2012. Doctoral Dissertation, Oregon State University. Accessed May 21, 2019. http://hdl.handle.net/1957/30174.

MLA Handbook (7th Edition):

Khan, Qadeer Ahmad. “Digitally assisted control techniques for high performance switching DC-DC converters.” 2012. Web. 21 May 2019.

Vancouver:

Khan QA. Digitally assisted control techniques for high performance switching DC-DC converters. [Internet] [Doctoral dissertation]. Oregon State University; 2012. [cited 2019 May 21]. Available from: http://hdl.handle.net/1957/30174.

Council of Science Editors:

Khan QA. Digitally assisted control techniques for high performance switching DC-DC converters. [Doctoral Dissertation]. Oregon State University; 2012. Available from: http://hdl.handle.net/1957/30174


Oregon State University

13. Elshazly, Amr. Performance enhancement techniques for low power digital phase locked loops.

Degree: PhD, Electrical and Computer Engineering, 2012, Oregon State University

 Desire for low-power, high performance computing has been at core of the symbiotic union between digital circuits and CMOS scaling. While digital circuit performance improves… (more)

Subjects/Keywords: Phase locked loops; Phase-locked loops

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APA (6th Edition):

Elshazly, A. (2012). Performance enhancement techniques for low power digital phase locked loops. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/31116

Chicago Manual of Style (16th Edition):

Elshazly, Amr. “Performance enhancement techniques for low power digital phase locked loops.” 2012. Doctoral Dissertation, Oregon State University. Accessed May 21, 2019. http://hdl.handle.net/1957/31116.

MLA Handbook (7th Edition):

Elshazly, Amr. “Performance enhancement techniques for low power digital phase locked loops.” 2012. Web. 21 May 2019.

Vancouver:

Elshazly A. Performance enhancement techniques for low power digital phase locked loops. [Internet] [Doctoral dissertation]. Oregon State University; 2012. [cited 2019 May 21]. Available from: http://hdl.handle.net/1957/31116.

Council of Science Editors:

Elshazly A. Performance enhancement techniques for low power digital phase locked loops. [Doctoral Dissertation]. Oregon State University; 2012. Available from: http://hdl.handle.net/1957/31116


Oregon State University

14. Guerber, Jon. Time and statistical information utilization in high efficiency sub-micron CMOS successive approximation analog to digital converters.

Degree: PhD, Electrical and Computer Engineering, 2012, Oregon State University

 In an industrial and consumer electronic marketplace that is increasingly demanding greater real-world interactivity in portable and distributed devices, analog to digital converter efficiency and… (more)

Subjects/Keywords: SAR ADC; Analog-to-digital converters

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APA (6th Edition):

Guerber, J. (2012). Time and statistical information utilization in high efficiency sub-micron CMOS successive approximation analog to digital converters. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/36019

Chicago Manual of Style (16th Edition):

Guerber, Jon. “Time and statistical information utilization in high efficiency sub-micron CMOS successive approximation analog to digital converters.” 2012. Doctoral Dissertation, Oregon State University. Accessed May 21, 2019. http://hdl.handle.net/1957/36019.

MLA Handbook (7th Edition):

Guerber, Jon. “Time and statistical information utilization in high efficiency sub-micron CMOS successive approximation analog to digital converters.” 2012. Web. 21 May 2019.

Vancouver:

Guerber J. Time and statistical information utilization in high efficiency sub-micron CMOS successive approximation analog to digital converters. [Internet] [Doctoral dissertation]. Oregon State University; 2012. [cited 2019 May 21]. Available from: http://hdl.handle.net/1957/36019.

Council of Science Editors:

Guerber J. Time and statistical information utilization in high efficiency sub-micron CMOS successive approximation analog to digital converters. [Doctoral Dissertation]. Oregon State University; 2012. Available from: http://hdl.handle.net/1957/36019


Oregon State University

15. Prabha, Praveen. Design techniques for VCO based digital sensor readout circuits.

Degree: MS, Electrical and Computer Engineering, 2014, Oregon State University

 Sensors find a variety of applications in portable electronics, automotive and biomedical solutions. The demand for low power and high dynamic range makes the design… (more)

Subjects/Keywords: VCO based ADC; Voltage-controlled oscillators

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APA (6th Edition):

Prabha, P. (2014). Design techniques for VCO based digital sensor readout circuits. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/46796

Chicago Manual of Style (16th Edition):

Prabha, Praveen. “Design techniques for VCO based digital sensor readout circuits.” 2014. Masters Thesis, Oregon State University. Accessed May 21, 2019. http://hdl.handle.net/1957/46796.

MLA Handbook (7th Edition):

Prabha, Praveen. “Design techniques for VCO based digital sensor readout circuits.” 2014. Web. 21 May 2019.

Vancouver:

Prabha P. Design techniques for VCO based digital sensor readout circuits. [Internet] [Masters thesis]. Oregon State University; 2014. [cited 2019 May 21]. Available from: http://hdl.handle.net/1957/46796.

Council of Science Editors:

Prabha P. Design techniques for VCO based digital sensor readout circuits. [Masters Thesis]. Oregon State University; 2014. Available from: http://hdl.handle.net/1957/46796


Oregon State University

16. Musah, Tawfiq. Low power design techniques for analog-to-digital converters in submicron CMOS.

Degree: PhD, Electrical and Computer Engineering, 2010, Oregon State University

 Advances in process technologies have led to the development of low-power high speed digital signal processing blocks that occupy small areas. These advances are critical… (more)

Subjects/Keywords: correlated level shifting; Analog-to-digital converters

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APA (6th Edition):

Musah, T. (2010). Low power design techniques for analog-to-digital converters in submicron CMOS. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/18826

Chicago Manual of Style (16th Edition):

Musah, Tawfiq. “Low power design techniques for analog-to-digital converters in submicron CMOS.” 2010. Doctoral Dissertation, Oregon State University. Accessed May 21, 2019. http://hdl.handle.net/1957/18826.

MLA Handbook (7th Edition):

Musah, Tawfiq. “Low power design techniques for analog-to-digital converters in submicron CMOS.” 2010. Web. 21 May 2019.

Vancouver:

Musah T. Low power design techniques for analog-to-digital converters in submicron CMOS. [Internet] [Doctoral dissertation]. Oregon State University; 2010. [cited 2019 May 21]. Available from: http://hdl.handle.net/1957/18826.

Council of Science Editors:

Musah T. Low power design techniques for analog-to-digital converters in submicron CMOS. [Doctoral Dissertation]. Oregon State University; 2010. Available from: http://hdl.handle.net/1957/18826


Oregon State University

17. Yin, Wenjing. Design techniques for high-performance digital PLLs and CDRs.

Degree: PhD, Electrical and Computer Engineering, 2010, Oregon State University

 Phase-Locked Loops (PLLs) are essential building blocks in many communication systems. Designing high performance analog PLLs in the presence of technology imposed constraints such as… (more)

Subjects/Keywords: digital PLL; Phase-locked loops

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APA (6th Edition):

Yin, W. (2010). Design techniques for high-performance digital PLLs and CDRs. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/19407

Chicago Manual of Style (16th Edition):

Yin, Wenjing. “Design techniques for high-performance digital PLLs and CDRs.” 2010. Doctoral Dissertation, Oregon State University. Accessed May 21, 2019. http://hdl.handle.net/1957/19407.

MLA Handbook (7th Edition):

Yin, Wenjing. “Design techniques for high-performance digital PLLs and CDRs.” 2010. Web. 21 May 2019.

Vancouver:

Yin W. Design techniques for high-performance digital PLLs and CDRs. [Internet] [Doctoral dissertation]. Oregon State University; 2010. [cited 2019 May 21]. Available from: http://hdl.handle.net/1957/19407.

Council of Science Editors:

Yin W. Design techniques for high-performance digital PLLs and CDRs. [Doctoral Dissertation]. Oregon State University; 2010. Available from: http://hdl.handle.net/1957/19407


Oregon State University

18. Yang, Bangda. Feedforward noise cancellation techniques.

Degree: MS, Electrical and Computer Engineering, 2010, Oregon State University

 Supply noise is one of the major considerations in almost all analog building blocks. In the past, adequate supply rejection is usually achieved with circuit… (more)

Subjects/Keywords: supply noise; Electronic noise

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APA (6th Edition):

Yang, B. (2010). Feedforward noise cancellation techniques. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/19485

Chicago Manual of Style (16th Edition):

Yang, Bangda. “Feedforward noise cancellation techniques.” 2010. Masters Thesis, Oregon State University. Accessed May 21, 2019. http://hdl.handle.net/1957/19485.

MLA Handbook (7th Edition):

Yang, Bangda. “Feedforward noise cancellation techniques.” 2010. Web. 21 May 2019.

Vancouver:

Yang B. Feedforward noise cancellation techniques. [Internet] [Masters thesis]. Oregon State University; 2010. [cited 2019 May 21]. Available from: http://hdl.handle.net/1957/19485.

Council of Science Editors:

Yang B. Feedforward noise cancellation techniques. [Masters Thesis]. Oregon State University; 2010. Available from: http://hdl.handle.net/1957/19485


Oregon State University

19. Inti, Rajesh. Highly digital power efficient techniques for serial links.

Degree: PhD, Electrical and Computer Engineering, 2011, Oregon State University

 Low power, high speed serial transceivers are employed in a wide range of applications ranging from chip-to-chip, backplane, and optical interconnects. Apart from being capable… (more)

Subjects/Keywords: Digital PLL; Radio  – Transmitter-receivers

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APA (6th Edition):

Inti, R. (2011). Highly digital power efficient techniques for serial links. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/25855

Chicago Manual of Style (16th Edition):

Inti, Rajesh. “Highly digital power efficient techniques for serial links.” 2011. Doctoral Dissertation, Oregon State University. Accessed May 21, 2019. http://hdl.handle.net/1957/25855.

MLA Handbook (7th Edition):

Inti, Rajesh. “Highly digital power efficient techniques for serial links.” 2011. Web. 21 May 2019.

Vancouver:

Inti R. Highly digital power efficient techniques for serial links. [Internet] [Doctoral dissertation]. Oregon State University; 2011. [cited 2019 May 21]. Available from: http://hdl.handle.net/1957/25855.

Council of Science Editors:

Inti R. Highly digital power efficient techniques for serial links. [Doctoral Dissertation]. Oregon State University; 2011. Available from: http://hdl.handle.net/1957/25855

20. Lee, Sang Hyeon. High efficiency wideband low-power delta-sigma modulators.

Degree: PhD, Electrical and Computer Engineering, 2012, Oregon State University

 Delta-sigma analog-to-digital converters traditionally have been used for low speed, high resolution applications such as measurements, sensors, voice and audio systems. Through continued device scaling… (more)

Subjects/Keywords: delta sigma; Modulators (Electronics)

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APA (6th Edition):

Lee, S. H. (2012). High efficiency wideband low-power delta-sigma modulators. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/30022

Chicago Manual of Style (16th Edition):

Lee, Sang Hyeon. “High efficiency wideband low-power delta-sigma modulators.” 2012. Doctoral Dissertation, Oregon State University. Accessed May 21, 2019. http://hdl.handle.net/1957/30022.

MLA Handbook (7th Edition):

Lee, Sang Hyeon. “High efficiency wideband low-power delta-sigma modulators.” 2012. Web. 21 May 2019.

Vancouver:

Lee SH. High efficiency wideband low-power delta-sigma modulators. [Internet] [Doctoral dissertation]. Oregon State University; 2012. [cited 2019 May 21]. Available from: http://hdl.handle.net/1957/30022.

Council of Science Editors:

Lee SH. High efficiency wideband low-power delta-sigma modulators. [Doctoral Dissertation]. Oregon State University; 2012. Available from: http://hdl.handle.net/1957/30022

21. Peterson, Brett. Automated model parameter extraction for noise coupling analysis in silicon substrates.

Degree: MS, Electrical and Computer Engineering, 2008, Oregon State University

 An automated method, requiring the fabrication of a small set of test structures, efficiently extracts the coefficients of Z-parameter based macromodels. The extraction approach has… (more)

Subjects/Keywords: substrate; Substrate noise  – Mathematical models

…submitted to Oregon State University in partial fulfillment of the requirements for the degree of… …collection of Oregon State University libraries. My signature below authorizes release of my thesis… …research. During my time at Oregon State University I have come to know many outstanding… 

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APA (6th Edition):

Peterson, B. (2008). Automated model parameter extraction for noise coupling analysis in silicon substrates. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/8182

Chicago Manual of Style (16th Edition):

Peterson, Brett. “Automated model parameter extraction for noise coupling analysis in silicon substrates.” 2008. Masters Thesis, Oregon State University. Accessed May 21, 2019. http://hdl.handle.net/1957/8182.

MLA Handbook (7th Edition):

Peterson, Brett. “Automated model parameter extraction for noise coupling analysis in silicon substrates.” 2008. Web. 21 May 2019.

Vancouver:

Peterson B. Automated model parameter extraction for noise coupling analysis in silicon substrates. [Internet] [Masters thesis]. Oregon State University; 2008. [cited 2019 May 21]. Available from: http://hdl.handle.net/1957/8182.

Council of Science Editors:

Peterson B. Automated model parameter extraction for noise coupling analysis in silicon substrates. [Masters Thesis]. Oregon State University; 2008. Available from: http://hdl.handle.net/1957/8182

22. Pai, Jeff. An efficient frequency controlled PFM for DC-DC converters.

Degree: MS, Electrical and Computer Engineering, 2010, Oregon State University

 As more features are being integrated into mobile platforms, the demand for long battery life during standby mode has been increasing. Light load efficiency becomes… (more)

Subjects/Keywords: DC-DC

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APA (6th Edition):

Pai, J. (2010). An efficient frequency controlled PFM for DC-DC converters. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/19549

Chicago Manual of Style (16th Edition):

Pai, Jeff. “An efficient frequency controlled PFM for DC-DC converters.” 2010. Masters Thesis, Oregon State University. Accessed May 21, 2019. http://hdl.handle.net/1957/19549.

MLA Handbook (7th Edition):

Pai, Jeff. “An efficient frequency controlled PFM for DC-DC converters.” 2010. Web. 21 May 2019.

Vancouver:

Pai J. An efficient frequency controlled PFM for DC-DC converters. [Internet] [Masters thesis]. Oregon State University; 2010. [cited 2019 May 21]. Available from: http://hdl.handle.net/1957/19549.

Council of Science Editors:

Pai J. An efficient frequency controlled PFM for DC-DC converters. [Masters Thesis]. Oregon State University; 2010. Available from: http://hdl.handle.net/1957/19549

23. Uttarwar, Tushar. A digital multiplying delay locked loop for high frequency clock generation.

Degree: MS, Electrical and Computer Engineering, 2011, Oregon State University

 As Moore’s Law continues to give rise to ever shrinking channel lengths, circuits are becoming more digital and ever increasingly faster. Generating high frequency clocks… (more)

Subjects/Keywords: PLL; Phase-locked loops

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APA (6th Edition):

Uttarwar, T. (2011). A digital multiplying delay locked loop for high frequency clock generation. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/25739

Chicago Manual of Style (16th Edition):

Uttarwar, Tushar. “A digital multiplying delay locked loop for high frequency clock generation.” 2011. Masters Thesis, Oregon State University. Accessed May 21, 2019. http://hdl.handle.net/1957/25739.

MLA Handbook (7th Edition):

Uttarwar, Tushar. “A digital multiplying delay locked loop for high frequency clock generation.” 2011. Web. 21 May 2019.

Vancouver:

Uttarwar T. A digital multiplying delay locked loop for high frequency clock generation. [Internet] [Masters thesis]. Oregon State University; 2011. [cited 2019 May 21]. Available from: http://hdl.handle.net/1957/25739.

Council of Science Editors:

Uttarwar T. A digital multiplying delay locked loop for high frequency clock generation. [Masters Thesis]. Oregon State University; 2011. Available from: http://hdl.handle.net/1957/25739

24. Reddy, Karthikeyan. Design techniques for delta sigma modulators using VCO based ADCs.

Degree: PhD, Electrical and Computer Engineering, 2014, Oregon State University

 VCO-based ADCs have recently emerged as attractive alternative to conventional DeltaSigma (ΔΣ) modulator architectures. Few salient features of a VCObased ADC are: 1) the quantization… (more)

Subjects/Keywords: Delta Sigma Modulator; Modulators (Electronics)  – Design and construction

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APA (6th Edition):

Reddy, K. (2014). Design techniques for delta sigma modulators using VCO based ADCs. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/46827

Chicago Manual of Style (16th Edition):

Reddy, Karthikeyan. “Design techniques for delta sigma modulators using VCO based ADCs.” 2014. Doctoral Dissertation, Oregon State University. Accessed May 21, 2019. http://hdl.handle.net/1957/46827.

MLA Handbook (7th Edition):

Reddy, Karthikeyan. “Design techniques for delta sigma modulators using VCO based ADCs.” 2014. Web. 21 May 2019.

Vancouver:

Reddy K. Design techniques for delta sigma modulators using VCO based ADCs. [Internet] [Doctoral dissertation]. Oregon State University; 2014. [cited 2019 May 21]. Available from: http://hdl.handle.net/1957/46827.

Council of Science Editors:

Reddy K. Design techniques for delta sigma modulators using VCO based ADCs. [Doctoral Dissertation]. Oregon State University; 2014. Available from: http://hdl.handle.net/1957/46827

25. Young, Brian LeRoy. Time-based noise-shaping techniques for time-to-digital and analog-to-digital converters.

Degree: PhD, Electrical and Computer Engineering, 2013, Oregon State University

 In this dissertation, time-based signal processing techniques and their applications in oversampling and noise-shaping data converters are examined. These techniques demonstrate the ability to shift… (more)

Subjects/Keywords: Signal processing

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APA (6th Edition):

Young, B. L. (2013). Time-based noise-shaping techniques for time-to-digital and analog-to-digital converters. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/39692

Chicago Manual of Style (16th Edition):

Young, Brian LeRoy. “Time-based noise-shaping techniques for time-to-digital and analog-to-digital converters.” 2013. Doctoral Dissertation, Oregon State University. Accessed May 21, 2019. http://hdl.handle.net/1957/39692.

MLA Handbook (7th Edition):

Young, Brian LeRoy. “Time-based noise-shaping techniques for time-to-digital and analog-to-digital converters.” 2013. Web. 21 May 2019.

Vancouver:

Young BL. Time-based noise-shaping techniques for time-to-digital and analog-to-digital converters. [Internet] [Doctoral dissertation]. Oregon State University; 2013. [cited 2019 May 21]. Available from: http://hdl.handle.net/1957/39692.

Council of Science Editors:

Young BL. Time-based noise-shaping techniques for time-to-digital and analog-to-digital converters. [Doctoral Dissertation]. Oregon State University; 2013. Available from: http://hdl.handle.net/1957/39692

26. George, Edmond (Edmond Fernandez). Semi-digital PLL architecture for ultra low bandwidth applications.

Degree: MS, Electrical and Computer Engineering, 2013, Oregon State University

 Phase Locked Loops(PLLs) are an integral part of almost every electronic system. Systems involving low frequency clocks often require PLLs with low bandwidth. The area… (more)

Subjects/Keywords: PLL; Phase-locked loops

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APA (6th Edition):

George, E. (. F. (2013). Semi-digital PLL architecture for ultra low bandwidth applications. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/37710

Chicago Manual of Style (16th Edition):

George, Edmond (Edmond Fernandez). “Semi-digital PLL architecture for ultra low bandwidth applications.” 2013. Masters Thesis, Oregon State University. Accessed May 21, 2019. http://hdl.handle.net/1957/37710.

MLA Handbook (7th Edition):

George, Edmond (Edmond Fernandez). “Semi-digital PLL architecture for ultra low bandwidth applications.” 2013. Web. 21 May 2019.

Vancouver:

George E(F. Semi-digital PLL architecture for ultra low bandwidth applications. [Internet] [Masters thesis]. Oregon State University; 2013. [cited 2019 May 21]. Available from: http://hdl.handle.net/1957/37710.

Council of Science Editors:

George E(F. Semi-digital PLL architecture for ultra low bandwidth applications. [Masters Thesis]. Oregon State University; 2013. Available from: http://hdl.handle.net/1957/37710

27. Ni, Ronghua. Low power receivers for wireless sensor networks.

Degree: PhD, Electrical and Computer Engineering, 2013, Oregon State University

 Wireless sensor networks are becoming important in several monitoring and sensing applications. Ultra low power consumption in the sensor nodes is important for extending the… (more)

Subjects/Keywords: receiver; Wireless sensor networks

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APA (6th Edition):

Ni, R. (2013). Low power receivers for wireless sensor networks. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/37785

Chicago Manual of Style (16th Edition):

Ni, Ronghua. “Low power receivers for wireless sensor networks.” 2013. Doctoral Dissertation, Oregon State University. Accessed May 21, 2019. http://hdl.handle.net/1957/37785.

MLA Handbook (7th Edition):

Ni, Ronghua. “Low power receivers for wireless sensor networks.” 2013. Web. 21 May 2019.

Vancouver:

Ni R. Low power receivers for wireless sensor networks. [Internet] [Doctoral dissertation]. Oregon State University; 2013. [cited 2019 May 21]. Available from: http://hdl.handle.net/1957/37785.

Council of Science Editors:

Ni R. Low power receivers for wireless sensor networks. [Doctoral Dissertation]. Oregon State University; 2013. Available from: http://hdl.handle.net/1957/37785

28. Jung, Seokmin. Design of a low jitter digital PLL with low input frequency.

Degree: MS, iin Electrical and Computer Engineering, 2012, Oregon State University

 Complex digital circuits such as microprocessors typically require support circuitry that has traditionally been realized using analog or mixed-signal macros. PLL circuits are used in… (more)

Subjects/Keywords: digital phase locked loop; Phase-locked loops  – Design and construction

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APA (6th Edition):

Jung, S. (2012). Design of a low jitter digital PLL with low input frequency. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/30105

Chicago Manual of Style (16th Edition):

Jung, Seokmin. “Design of a low jitter digital PLL with low input frequency.” 2012. Masters Thesis, Oregon State University. Accessed May 21, 2019. http://hdl.handle.net/1957/30105.

MLA Handbook (7th Edition):

Jung, Seokmin. “Design of a low jitter digital PLL with low input frequency.” 2012. Web. 21 May 2019.

Vancouver:

Jung S. Design of a low jitter digital PLL with low input frequency. [Internet] [Masters thesis]. Oregon State University; 2012. [cited 2019 May 21]. Available from: http://hdl.handle.net/1957/30105.

Council of Science Editors:

Jung S. Design of a low jitter digital PLL with low input frequency. [Masters Thesis]. Oregon State University; 2012. Available from: http://hdl.handle.net/1957/30105

29. Rao, Sachin B. Design techniques for high efficiency high current LED drivers.

Degree: MS, Electrical and Computer Engineering, 2011, Oregon State University

 Solid-state based lighting offers a number of advantages such as long life, high efficiency and compactness compared to a conventional halogen tube based lighting. Due… (more)

Subjects/Keywords: buck boost converters; Device drivers (Computer programs)

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APA (6th Edition):

Rao, S. B. (2011). Design techniques for high efficiency high current LED drivers. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/23481

Chicago Manual of Style (16th Edition):

Rao, Sachin B. “Design techniques for high efficiency high current LED drivers.” 2011. Masters Thesis, Oregon State University. Accessed May 21, 2019. http://hdl.handle.net/1957/23481.

MLA Handbook (7th Edition):

Rao, Sachin B. “Design techniques for high efficiency high current LED drivers.” 2011. Web. 21 May 2019.

Vancouver:

Rao SB. Design techniques for high efficiency high current LED drivers. [Internet] [Masters thesis]. Oregon State University; 2011. [cited 2019 May 21]. Available from: http://hdl.handle.net/1957/23481.

Council of Science Editors:

Rao SB. Design techniques for high efficiency high current LED drivers. [Masters Thesis]. Oregon State University; 2011. Available from: http://hdl.handle.net/1957/23481


Oregon State University

30. Bonu, Madhulatha. Noise coupling techniques in multi-cell delta-sigma modulators.

Degree: MS, Electrical and Computer Engineering, 2007, Oregon State University

 High performance multi-cell delta-sigma modulators are a preferred choice in applications which require programmability. Multi-cell delta-sigma modulators with M unit cells provide 10log10(M) SQNR improvement… (more)

Subjects/Keywords: delta-sigma; Analog-to-digital converters  – Noise

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APA (6th Edition):

Bonu, M. (2007). Noise coupling techniques in multi-cell delta-sigma modulators. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/3769

Chicago Manual of Style (16th Edition):

Bonu, Madhulatha. “Noise coupling techniques in multi-cell delta-sigma modulators.” 2007. Masters Thesis, Oregon State University. Accessed May 21, 2019. http://hdl.handle.net/1957/3769.

MLA Handbook (7th Edition):

Bonu, Madhulatha. “Noise coupling techniques in multi-cell delta-sigma modulators.” 2007. Web. 21 May 2019.

Vancouver:

Bonu M. Noise coupling techniques in multi-cell delta-sigma modulators. [Internet] [Masters thesis]. Oregon State University; 2007. [cited 2019 May 21]. Available from: http://hdl.handle.net/1957/3769.

Council of Science Editors:

Bonu M. Noise coupling techniques in multi-cell delta-sigma modulators. [Masters Thesis]. Oregon State University; 2007. Available from: http://hdl.handle.net/1957/3769

.