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You searched for +publisher:"Oregon State University" +contributor:("Hanumolu, Pavan Kumar"). Showing records 1 – 13 of 13 total matches.

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Oregon State University

1. Arakali, Abhijith. Low-power techniques for supply-noise mitigation in phase-locked loops.

Degree: PhD, Electrical and Computer Engineering, 2010, Oregon State University

 Modern day digital systems employ frequency synthesizers to provide a common clock to the system. They are undergoing large scale integration due to which, mitigation… (more)

Subjects/Keywords: Phase-locked loops

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APA (6th Edition):

Arakali, A. (2010). Low-power techniques for supply-noise mitigation in phase-locked loops. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/14281

Chicago Manual of Style (16th Edition):

Arakali, Abhijith. “Low-power techniques for supply-noise mitigation in phase-locked loops.” 2010. Doctoral Dissertation, Oregon State University. Accessed October 22, 2019. http://hdl.handle.net/1957/14281.

MLA Handbook (7th Edition):

Arakali, Abhijith. “Low-power techniques for supply-noise mitigation in phase-locked loops.” 2010. Web. 22 Oct 2019.

Vancouver:

Arakali A. Low-power techniques for supply-noise mitigation in phase-locked loops. [Internet] [Doctoral dissertation]. Oregon State University; 2010. [cited 2019 Oct 22]. Available from: http://hdl.handle.net/1957/14281.

Council of Science Editors:

Arakali A. Low-power techniques for supply-noise mitigation in phase-locked loops. [Doctoral Dissertation]. Oregon State University; 2010. Available from: http://hdl.handle.net/1957/14281


Oregon State University

2. Drost, Brian George. Time-based analog signal processing.

Degree: MS, Electrical and Computer Engineering, 2011, Oregon State University

 As CMOS processes size continues to shrink, a number of factors limit the ability of analog circuit performance to scale with the process. These issues… (more)

Subjects/Keywords: Analog Filter

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APA (6th Edition):

Drost, B. G. (2011). Time-based analog signal processing. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/21810

Chicago Manual of Style (16th Edition):

Drost, Brian George. “Time-based analog signal processing.” 2011. Masters Thesis, Oregon State University. Accessed October 22, 2019. http://hdl.handle.net/1957/21810.

MLA Handbook (7th Edition):

Drost, Brian George. “Time-based analog signal processing.” 2011. Web. 22 Oct 2019.

Vancouver:

Drost BG. Time-based analog signal processing. [Internet] [Masters thesis]. Oregon State University; 2011. [cited 2019 Oct 22]. Available from: http://hdl.handle.net/1957/21810.

Council of Science Editors:

Drost BG. Time-based analog signal processing. [Masters Thesis]. Oregon State University; 2011. Available from: http://hdl.handle.net/1957/21810


Oregon State University

3. Hu, Kangmin. Analysis and design on low-power multi-Gb/s serial links.

Degree: PhD, Electrical and Computer Engineering, 2011, Oregon State University

 High speed serial links are critical components for addressing the growing demand for I/O bandwidth in next-generation computing applications, such as many-core systems, backplane and… (more)

Subjects/Keywords: serial link; Radio  – Transmitter-receivers  – Energy consumption

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APA (6th Edition):

Hu, K. (2011). Analysis and design on low-power multi-Gb/s serial links. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/21944

Chicago Manual of Style (16th Edition):

Hu, Kangmin. “Analysis and design on low-power multi-Gb/s serial links.” 2011. Doctoral Dissertation, Oregon State University. Accessed October 22, 2019. http://hdl.handle.net/1957/21944.

MLA Handbook (7th Edition):

Hu, Kangmin. “Analysis and design on low-power multi-Gb/s serial links.” 2011. Web. 22 Oct 2019.

Vancouver:

Hu K. Analysis and design on low-power multi-Gb/s serial links. [Internet] [Doctoral dissertation]. Oregon State University; 2011. [cited 2019 Oct 22]. Available from: http://hdl.handle.net/1957/21944.

Council of Science Editors:

Hu K. Analysis and design on low-power multi-Gb/s serial links. [Doctoral Dissertation]. Oregon State University; 2011. Available from: http://hdl.handle.net/1957/21944


Oregon State University

4. Khan, Qadeer Ahmad. Digitally assisted control techniques for high performance switching DC-DC converters.

Degree: PhD, Electrical and Computer Engineering, 2012, Oregon State University

 Digitally controlled switching DC-DC converters have recently emerged as an attractive alternative to conventional switching converters based on analog control techniques. This research focuses on… (more)

Subjects/Keywords: voltage regulator; DC-to-DC converters  – Automatic control

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APA (6th Edition):

Khan, Q. A. (2012). Digitally assisted control techniques for high performance switching DC-DC converters. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/30174

Chicago Manual of Style (16th Edition):

Khan, Qadeer Ahmad. “Digitally assisted control techniques for high performance switching DC-DC converters.” 2012. Doctoral Dissertation, Oregon State University. Accessed October 22, 2019. http://hdl.handle.net/1957/30174.

MLA Handbook (7th Edition):

Khan, Qadeer Ahmad. “Digitally assisted control techniques for high performance switching DC-DC converters.” 2012. Web. 22 Oct 2019.

Vancouver:

Khan QA. Digitally assisted control techniques for high performance switching DC-DC converters. [Internet] [Doctoral dissertation]. Oregon State University; 2012. [cited 2019 Oct 22]. Available from: http://hdl.handle.net/1957/30174.

Council of Science Editors:

Khan QA. Digitally assisted control techniques for high performance switching DC-DC converters. [Doctoral Dissertation]. Oregon State University; 2012. Available from: http://hdl.handle.net/1957/30174


Oregon State University

5. Elshazly, Amr. Performance enhancement techniques for low power digital phase locked loops.

Degree: PhD, Electrical and Computer Engineering, 2012, Oregon State University

 Desire for low-power, high performance computing has been at core of the symbiotic union between digital circuits and CMOS scaling. While digital circuit performance improves… (more)

Subjects/Keywords: Phase locked loops; Phase-locked loops

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APA (6th Edition):

Elshazly, A. (2012). Performance enhancement techniques for low power digital phase locked loops. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/31116

Chicago Manual of Style (16th Edition):

Elshazly, Amr. “Performance enhancement techniques for low power digital phase locked loops.” 2012. Doctoral Dissertation, Oregon State University. Accessed October 22, 2019. http://hdl.handle.net/1957/31116.

MLA Handbook (7th Edition):

Elshazly, Amr. “Performance enhancement techniques for low power digital phase locked loops.” 2012. Web. 22 Oct 2019.

Vancouver:

Elshazly A. Performance enhancement techniques for low power digital phase locked loops. [Internet] [Doctoral dissertation]. Oregon State University; 2012. [cited 2019 Oct 22]. Available from: http://hdl.handle.net/1957/31116.

Council of Science Editors:

Elshazly A. Performance enhancement techniques for low power digital phase locked loops. [Doctoral Dissertation]. Oregon State University; 2012. Available from: http://hdl.handle.net/1957/31116


Oregon State University

6. Prabha, Praveen. Design techniques for VCO based digital sensor readout circuits.

Degree: MS, Electrical and Computer Engineering, 2014, Oregon State University

 Sensors find a variety of applications in portable electronics, automotive and biomedical solutions. The demand for low power and high dynamic range makes the design… (more)

Subjects/Keywords: VCO based ADC; Voltage-controlled oscillators

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APA (6th Edition):

Prabha, P. (2014). Design techniques for VCO based digital sensor readout circuits. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/46796

Chicago Manual of Style (16th Edition):

Prabha, Praveen. “Design techniques for VCO based digital sensor readout circuits.” 2014. Masters Thesis, Oregon State University. Accessed October 22, 2019. http://hdl.handle.net/1957/46796.

MLA Handbook (7th Edition):

Prabha, Praveen. “Design techniques for VCO based digital sensor readout circuits.” 2014. Web. 22 Oct 2019.

Vancouver:

Prabha P. Design techniques for VCO based digital sensor readout circuits. [Internet] [Masters thesis]. Oregon State University; 2014. [cited 2019 Oct 22]. Available from: http://hdl.handle.net/1957/46796.

Council of Science Editors:

Prabha P. Design techniques for VCO based digital sensor readout circuits. [Masters Thesis]. Oregon State University; 2014. Available from: http://hdl.handle.net/1957/46796


Oregon State University

7. Musah, Tawfiq. Low power design techniques for analog-to-digital converters in submicron CMOS.

Degree: PhD, Electrical and Computer Engineering, 2010, Oregon State University

 Advances in process technologies have led to the development of low-power high speed digital signal processing blocks that occupy small areas. These advances are critical… (more)

Subjects/Keywords: correlated level shifting; Analog-to-digital converters

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APA (6th Edition):

Musah, T. (2010). Low power design techniques for analog-to-digital converters in submicron CMOS. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/18826

Chicago Manual of Style (16th Edition):

Musah, Tawfiq. “Low power design techniques for analog-to-digital converters in submicron CMOS.” 2010. Doctoral Dissertation, Oregon State University. Accessed October 22, 2019. http://hdl.handle.net/1957/18826.

MLA Handbook (7th Edition):

Musah, Tawfiq. “Low power design techniques for analog-to-digital converters in submicron CMOS.” 2010. Web. 22 Oct 2019.

Vancouver:

Musah T. Low power design techniques for analog-to-digital converters in submicron CMOS. [Internet] [Doctoral dissertation]. Oregon State University; 2010. [cited 2019 Oct 22]. Available from: http://hdl.handle.net/1957/18826.

Council of Science Editors:

Musah T. Low power design techniques for analog-to-digital converters in submicron CMOS. [Doctoral Dissertation]. Oregon State University; 2010. Available from: http://hdl.handle.net/1957/18826


Oregon State University

8. Yin, Wenjing. Design techniques for high-performance digital PLLs and CDRs.

Degree: PhD, Electrical and Computer Engineering, 2010, Oregon State University

 Phase-Locked Loops (PLLs) are essential building blocks in many communication systems. Designing high performance analog PLLs in the presence of technology imposed constraints such as… (more)

Subjects/Keywords: digital PLL; Phase-locked loops

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APA (6th Edition):

Yin, W. (2010). Design techniques for high-performance digital PLLs and CDRs. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/19407

Chicago Manual of Style (16th Edition):

Yin, Wenjing. “Design techniques for high-performance digital PLLs and CDRs.” 2010. Doctoral Dissertation, Oregon State University. Accessed October 22, 2019. http://hdl.handle.net/1957/19407.

MLA Handbook (7th Edition):

Yin, Wenjing. “Design techniques for high-performance digital PLLs and CDRs.” 2010. Web. 22 Oct 2019.

Vancouver:

Yin W. Design techniques for high-performance digital PLLs and CDRs. [Internet] [Doctoral dissertation]. Oregon State University; 2010. [cited 2019 Oct 22]. Available from: http://hdl.handle.net/1957/19407.

Council of Science Editors:

Yin W. Design techniques for high-performance digital PLLs and CDRs. [Doctoral Dissertation]. Oregon State University; 2010. Available from: http://hdl.handle.net/1957/19407

9. Reddy, Karthikeyan. Design techniques for delta sigma modulators using VCO based ADCs.

Degree: PhD, Electrical and Computer Engineering, 2014, Oregon State University

 VCO-based ADCs have recently emerged as attractive alternative to conventional DeltaSigma (ΔΣ) modulator architectures. Few salient features of a VCObased ADC are: 1) the quantization… (more)

Subjects/Keywords: Delta Sigma Modulator; Modulators (Electronics)  – Design and construction

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APA (6th Edition):

Reddy, K. (2014). Design techniques for delta sigma modulators using VCO based ADCs. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/46827

Chicago Manual of Style (16th Edition):

Reddy, Karthikeyan. “Design techniques for delta sigma modulators using VCO based ADCs.” 2014. Doctoral Dissertation, Oregon State University. Accessed October 22, 2019. http://hdl.handle.net/1957/46827.

MLA Handbook (7th Edition):

Reddy, Karthikeyan. “Design techniques for delta sigma modulators using VCO based ADCs.” 2014. Web. 22 Oct 2019.

Vancouver:

Reddy K. Design techniques for delta sigma modulators using VCO based ADCs. [Internet] [Doctoral dissertation]. Oregon State University; 2014. [cited 2019 Oct 22]. Available from: http://hdl.handle.net/1957/46827.

Council of Science Editors:

Reddy K. Design techniques for delta sigma modulators using VCO based ADCs. [Doctoral Dissertation]. Oregon State University; 2014. Available from: http://hdl.handle.net/1957/46827

10. Young, Brian LeRoy. Time-based noise-shaping techniques for time-to-digital and analog-to-digital converters.

Degree: PhD, Electrical and Computer Engineering, 2013, Oregon State University

 In this dissertation, time-based signal processing techniques and their applications in oversampling and noise-shaping data converters are examined. These techniques demonstrate the ability to shift… (more)

Subjects/Keywords: Signal processing

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APA (6th Edition):

Young, B. L. (2013). Time-based noise-shaping techniques for time-to-digital and analog-to-digital converters. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/39692

Chicago Manual of Style (16th Edition):

Young, Brian LeRoy. “Time-based noise-shaping techniques for time-to-digital and analog-to-digital converters.” 2013. Doctoral Dissertation, Oregon State University. Accessed October 22, 2019. http://hdl.handle.net/1957/39692.

MLA Handbook (7th Edition):

Young, Brian LeRoy. “Time-based noise-shaping techniques for time-to-digital and analog-to-digital converters.” 2013. Web. 22 Oct 2019.

Vancouver:

Young BL. Time-based noise-shaping techniques for time-to-digital and analog-to-digital converters. [Internet] [Doctoral dissertation]. Oregon State University; 2013. [cited 2019 Oct 22]. Available from: http://hdl.handle.net/1957/39692.

Council of Science Editors:

Young BL. Time-based noise-shaping techniques for time-to-digital and analog-to-digital converters. [Doctoral Dissertation]. Oregon State University; 2013. Available from: http://hdl.handle.net/1957/39692

11. George, Edmond (Edmond Fernandez). Semi-digital PLL architecture for ultra low bandwidth applications.

Degree: MS, Electrical and Computer Engineering, 2013, Oregon State University

 Phase Locked Loops(PLLs) are an integral part of almost every electronic system. Systems involving low frequency clocks often require PLLs with low bandwidth. The area… (more)

Subjects/Keywords: PLL; Phase-locked loops

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APA (6th Edition):

George, E. (. F. (2013). Semi-digital PLL architecture for ultra low bandwidth applications. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/37710

Chicago Manual of Style (16th Edition):

George, Edmond (Edmond Fernandez). “Semi-digital PLL architecture for ultra low bandwidth applications.” 2013. Masters Thesis, Oregon State University. Accessed October 22, 2019. http://hdl.handle.net/1957/37710.

MLA Handbook (7th Edition):

George, Edmond (Edmond Fernandez). “Semi-digital PLL architecture for ultra low bandwidth applications.” 2013. Web. 22 Oct 2019.

Vancouver:

George E(F. Semi-digital PLL architecture for ultra low bandwidth applications. [Internet] [Masters thesis]. Oregon State University; 2013. [cited 2019 Oct 22]. Available from: http://hdl.handle.net/1957/37710.

Council of Science Editors:

George E(F. Semi-digital PLL architecture for ultra low bandwidth applications. [Masters Thesis]. Oregon State University; 2013. Available from: http://hdl.handle.net/1957/37710

12. Ni, Ronghua. Low power receivers for wireless sensor networks.

Degree: PhD, Electrical and Computer Engineering, 2013, Oregon State University

 Wireless sensor networks are becoming important in several monitoring and sensing applications. Ultra low power consumption in the sensor nodes is important for extending the… (more)

Subjects/Keywords: receiver; Wireless sensor networks

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APA (6th Edition):

Ni, R. (2013). Low power receivers for wireless sensor networks. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/37785

Chicago Manual of Style (16th Edition):

Ni, Ronghua. “Low power receivers for wireless sensor networks.” 2013. Doctoral Dissertation, Oregon State University. Accessed October 22, 2019. http://hdl.handle.net/1957/37785.

MLA Handbook (7th Edition):

Ni, Ronghua. “Low power receivers for wireless sensor networks.” 2013. Web. 22 Oct 2019.

Vancouver:

Ni R. Low power receivers for wireless sensor networks. [Internet] [Doctoral dissertation]. Oregon State University; 2013. [cited 2019 Oct 22]. Available from: http://hdl.handle.net/1957/37785.

Council of Science Editors:

Ni R. Low power receivers for wireless sensor networks. [Doctoral Dissertation]. Oregon State University; 2013. Available from: http://hdl.handle.net/1957/37785

13. Jung, Seokmin. Design of a low jitter digital PLL with low input frequency.

Degree: MS, iin Electrical and Computer Engineering, 2012, Oregon State University

 Complex digital circuits such as microprocessors typically require support circuitry that has traditionally been realized using analog or mixed-signal macros. PLL circuits are used in… (more)

Subjects/Keywords: digital phase locked loop; Phase-locked loops  – Design and construction

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APA (6th Edition):

Jung, S. (2012). Design of a low jitter digital PLL with low input frequency. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/30105

Chicago Manual of Style (16th Edition):

Jung, Seokmin. “Design of a low jitter digital PLL with low input frequency.” 2012. Masters Thesis, Oregon State University. Accessed October 22, 2019. http://hdl.handle.net/1957/30105.

MLA Handbook (7th Edition):

Jung, Seokmin. “Design of a low jitter digital PLL with low input frequency.” 2012. Web. 22 Oct 2019.

Vancouver:

Jung S. Design of a low jitter digital PLL with low input frequency. [Internet] [Masters thesis]. Oregon State University; 2012. [cited 2019 Oct 22]. Available from: http://hdl.handle.net/1957/30105.

Council of Science Editors:

Jung S. Design of a low jitter digital PLL with low input frequency. [Masters Thesis]. Oregon State University; 2012. Available from: http://hdl.handle.net/1957/30105

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