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You searched for +publisher:"Oregon State University" +contributor:("Fiez, Terri S."). Showing records 1 – 23 of 23 total matches.

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Oregon State University

1. Lindsley, Christopher J. A nano-power wake-up circuit for RF energy harvesting wireless sensor networks.

Degree: MS, Electrical and Computer Engineering, 2008, Oregon State University

 A fully integrated CMOS latched comparator is presented for use as a wake-up circuit that is attached to an RF energy harvester in a battery… (more)

Subjects/Keywords: Sensor networks  – Design and construction

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APA (6th Edition):

Lindsley, C. J. (2008). A nano-power wake-up circuit for RF energy harvesting wireless sensor networks. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/12115

Chicago Manual of Style (16th Edition):

Lindsley, Christopher J. “A nano-power wake-up circuit for RF energy harvesting wireless sensor networks.” 2008. Masters Thesis, Oregon State University. Accessed October 18, 2019. http://hdl.handle.net/1957/12115.

MLA Handbook (7th Edition):

Lindsley, Christopher J. “A nano-power wake-up circuit for RF energy harvesting wireless sensor networks.” 2008. Web. 18 Oct 2019.

Vancouver:

Lindsley CJ. A nano-power wake-up circuit for RF energy harvesting wireless sensor networks. [Internet] [Masters thesis]. Oregon State University; 2008. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/1957/12115.

Council of Science Editors:

Lindsley CJ. A nano-power wake-up circuit for RF energy harvesting wireless sensor networks. [Masters Thesis]. Oregon State University; 2008. Available from: http://hdl.handle.net/1957/12115


Oregon State University

2. Panitantum, Napong. Ultra-low-energy transmitters for battery-free wireless sensor networks.

Degree: PhD, Electrical and Computer Engineering, 2011, Oregon State University

 As the number of autonomous data collection applications keep increasing, the demand for wireless sensor networks (WSNs) has seen explosive growth. In this dissertation, an… (more)

Subjects/Keywords: Ultra low energy

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APA (6th Edition):

Panitantum, N. (2011). Ultra-low-energy transmitters for battery-free wireless sensor networks. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/21887

Chicago Manual of Style (16th Edition):

Panitantum, Napong. “Ultra-low-energy transmitters for battery-free wireless sensor networks.” 2011. Doctoral Dissertation, Oregon State University. Accessed October 18, 2019. http://hdl.handle.net/1957/21887.

MLA Handbook (7th Edition):

Panitantum, Napong. “Ultra-low-energy transmitters for battery-free wireless sensor networks.” 2011. Web. 18 Oct 2019.

Vancouver:

Panitantum N. Ultra-low-energy transmitters for battery-free wireless sensor networks. [Internet] [Doctoral dissertation]. Oregon State University; 2011. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/1957/21887.

Council of Science Editors:

Panitantum N. Ultra-low-energy transmitters for battery-free wireless sensor networks. [Doctoral Dissertation]. Oregon State University; 2011. Available from: http://hdl.handle.net/1957/21887


Oregon State University

3. Nasroullahi, Mohsen. Ultra-low energy digital controller for battery-free wireless sensor network nodes.

Degree: MS, Electrical and Computer Engineering, 2011, Oregon State University

 This thesis presents a low-energy application specific digital controller for a battery-free 2.4 GHz wireless sensor network (WSN) node. The digital controller has been designed… (more)

Subjects/Keywords: Wireless Sensor Network

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APA (6th Edition):

Nasroullahi, M. (2011). Ultra-low energy digital controller for battery-free wireless sensor network nodes. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/21927

Chicago Manual of Style (16th Edition):

Nasroullahi, Mohsen. “Ultra-low energy digital controller for battery-free wireless sensor network nodes.” 2011. Masters Thesis, Oregon State University. Accessed October 18, 2019. http://hdl.handle.net/1957/21927.

MLA Handbook (7th Edition):

Nasroullahi, Mohsen. “Ultra-low energy digital controller for battery-free wireless sensor network nodes.” 2011. Web. 18 Oct 2019.

Vancouver:

Nasroullahi M. Ultra-low energy digital controller for battery-free wireless sensor network nodes. [Internet] [Masters thesis]. Oregon State University; 2011. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/1957/21927.

Council of Science Editors:

Nasroullahi M. Ultra-low energy digital controller for battery-free wireless sensor network nodes. [Masters Thesis]. Oregon State University; 2011. Available from: http://hdl.handle.net/1957/21927


Oregon State University

4. Ayers, James S. Ultra-low power receivers for wireless sensor networks.

Degree: PhD, Electrical and Computer Engineering, 2010, Oregon State University

 In wireless sensor network applications, low-power operation of the wireless receiver is critical. To address this need an ultra-low power Binary Frequency Shift Keying (BFSK)… (more)

Subjects/Keywords: RF; Wireless sensor networks

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APA (6th Edition):

Ayers, J. S. (2010). Ultra-low power receivers for wireless sensor networks. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/15934

Chicago Manual of Style (16th Edition):

Ayers, James S. “Ultra-low power receivers for wireless sensor networks.” 2010. Doctoral Dissertation, Oregon State University. Accessed October 18, 2019. http://hdl.handle.net/1957/15934.

MLA Handbook (7th Edition):

Ayers, James S. “Ultra-low power receivers for wireless sensor networks.” 2010. Web. 18 Oct 2019.

Vancouver:

Ayers JS. Ultra-low power receivers for wireless sensor networks. [Internet] [Doctoral dissertation]. Oregon State University; 2010. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/1957/15934.

Council of Science Editors:

Ayers JS. Ultra-low power receivers for wireless sensor networks. [Doctoral Dissertation]. Oregon State University; 2010. Available from: http://hdl.handle.net/1957/15934

5. Zali Asl, Samira. Architectural Solutions for Analog Imperfections in ΔΣ Analog-to-Digital Based Systems: Architectural Solutions for Analog Imperfections in Delta Sigma Analog-to-Digital Based Systems.

Degree: PhD, Electrical and Computer Engineering, 2015, Oregon State University

 For today’s ubiquitous portable devices, innovative integrated circuits with high performance yet very low power are necessary. As these devices are used to communicate and… (more)

Subjects/Keywords: ADC; Analog-to-digital converters  – Design and construction

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APA (6th Edition):

Zali Asl, S. (2015). Architectural Solutions for Analog Imperfections in ΔΣ Analog-to-Digital Based Systems: Architectural Solutions for Analog Imperfections in Delta Sigma Analog-to-Digital Based Systems. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/56307

Chicago Manual of Style (16th Edition):

Zali Asl, Samira. “Architectural Solutions for Analog Imperfections in ΔΣ Analog-to-Digital Based Systems: Architectural Solutions for Analog Imperfections in Delta Sigma Analog-to-Digital Based Systems.” 2015. Doctoral Dissertation, Oregon State University. Accessed October 18, 2019. http://hdl.handle.net/1957/56307.

MLA Handbook (7th Edition):

Zali Asl, Samira. “Architectural Solutions for Analog Imperfections in ΔΣ Analog-to-Digital Based Systems: Architectural Solutions for Analog Imperfections in Delta Sigma Analog-to-Digital Based Systems.” 2015. Web. 18 Oct 2019.

Vancouver:

Zali Asl S. Architectural Solutions for Analog Imperfections in ΔΣ Analog-to-Digital Based Systems: Architectural Solutions for Analog Imperfections in Delta Sigma Analog-to-Digital Based Systems. [Internet] [Doctoral dissertation]. Oregon State University; 2015. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/1957/56307.

Council of Science Editors:

Zali Asl S. Architectural Solutions for Analog Imperfections in ΔΣ Analog-to-Digital Based Systems: Architectural Solutions for Analog Imperfections in Delta Sigma Analog-to-Digital Based Systems. [Doctoral Dissertation]. Oregon State University; 2015. Available from: http://hdl.handle.net/1957/56307

6. Ni, Ronghua. Low power receivers for wireless sensor networks.

Degree: PhD, Electrical and Computer Engineering, 2013, Oregon State University

 Wireless sensor networks are becoming important in several monitoring and sensing applications. Ultra low power consumption in the sensor nodes is important for extending the… (more)

Subjects/Keywords: receiver; Wireless sensor networks

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APA (6th Edition):

Ni, R. (2013). Low power receivers for wireless sensor networks. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/37785

Chicago Manual of Style (16th Edition):

Ni, Ronghua. “Low power receivers for wireless sensor networks.” 2013. Doctoral Dissertation, Oregon State University. Accessed October 18, 2019. http://hdl.handle.net/1957/37785.

MLA Handbook (7th Edition):

Ni, Ronghua. “Low power receivers for wireless sensor networks.” 2013. Web. 18 Oct 2019.

Vancouver:

Ni R. Low power receivers for wireless sensor networks. [Internet] [Doctoral dissertation]. Oregon State University; 2013. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/1957/37785.

Council of Science Editors:

Ni R. Low power receivers for wireless sensor networks. [Doctoral Dissertation]. Oregon State University; 2013. Available from: http://hdl.handle.net/1957/37785

7. Miller, Brian A. A DC-DC converter architecture for low-power, high-resistance thermoelectric generators for use in body-powered designs.

Degree: MS, Electrical and Computer Engineering, 2013, Oregon State University

 This thesis presents a low power DC-DC converter suitable for harvesting energy from high impedance thermoelectric generators (TEGs) for the use in body powered electronics.… (more)

Subjects/Keywords: DC-to-DC converters

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APA (6th Edition):

Miller, B. A. (2013). A DC-DC converter architecture for low-power, high-resistance thermoelectric generators for use in body-powered designs. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/37393

Chicago Manual of Style (16th Edition):

Miller, Brian A. “A DC-DC converter architecture for low-power, high-resistance thermoelectric generators for use in body-powered designs.” 2013. Masters Thesis, Oregon State University. Accessed October 18, 2019. http://hdl.handle.net/1957/37393.

MLA Handbook (7th Edition):

Miller, Brian A. “A DC-DC converter architecture for low-power, high-resistance thermoelectric generators for use in body-powered designs.” 2013. Web. 18 Oct 2019.

Vancouver:

Miller BA. A DC-DC converter architecture for low-power, high-resistance thermoelectric generators for use in body-powered designs. [Internet] [Masters thesis]. Oregon State University; 2013. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/1957/37393.

Council of Science Editors:

Miller BA. A DC-DC converter architecture for low-power, high-resistance thermoelectric generators for use in body-powered designs. [Masters Thesis]. Oregon State University; 2013. Available from: http://hdl.handle.net/1957/37393


Oregon State University

8. Smit, Adriaan. Extending the TekBots [superscript TM] Platform for Learning [superscript TM] to upper division ECE courses.

Degree: MS, Electrical and Computer Engineering, 2004, Oregon State University

 In April of 1997 it was pointed out at an NSF Engineering Education Innovators conference that “… education appears to ignore the need for connections… (more)

Subjects/Keywords: Engineering  – Study and teaching (Higher)  – Activity programs

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APA (6th Edition):

Smit, A. (2004). Extending the TekBots [superscript TM] Platform for Learning [superscript TM] to upper division ECE courses. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/11545

Chicago Manual of Style (16th Edition):

Smit, Adriaan. “Extending the TekBots [superscript TM] Platform for Learning [superscript TM] to upper division ECE courses.” 2004. Masters Thesis, Oregon State University. Accessed October 18, 2019. http://hdl.handle.net/1957/11545.

MLA Handbook (7th Edition):

Smit, Adriaan. “Extending the TekBots [superscript TM] Platform for Learning [superscript TM] to upper division ECE courses.” 2004. Web. 18 Oct 2019.

Vancouver:

Smit A. Extending the TekBots [superscript TM] Platform for Learning [superscript TM] to upper division ECE courses. [Internet] [Masters thesis]. Oregon State University; 2004. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/1957/11545.

Council of Science Editors:

Smit A. Extending the TekBots [superscript TM] Platform for Learning [superscript TM] to upper division ECE courses. [Masters Thesis]. Oregon State University; 2004. Available from: http://hdl.handle.net/1957/11545


Oregon State University

9. Owens, Brian E. Simulation, measurement, and suppression of digital noise in mixed-signal integrated circuits.

Degree: MS, Electrical and Computer Engineering, 2003, Oregon State University

 Strategies for simulation and measurement of substrate noise have been analyzed using various digital and analog circuits fabricated in the TSMC 0.35um heavily doped CMOS… (more)

Subjects/Keywords: Mixed signal circuits  – Noise

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APA (6th Edition):

Owens, B. E. (2003). Simulation, measurement, and suppression of digital noise in mixed-signal integrated circuits. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/11794

Chicago Manual of Style (16th Edition):

Owens, Brian E. “Simulation, measurement, and suppression of digital noise in mixed-signal integrated circuits.” 2003. Masters Thesis, Oregon State University. Accessed October 18, 2019. http://hdl.handle.net/1957/11794.

MLA Handbook (7th Edition):

Owens, Brian E. “Simulation, measurement, and suppression of digital noise in mixed-signal integrated circuits.” 2003. Web. 18 Oct 2019.

Vancouver:

Owens BE. Simulation, measurement, and suppression of digital noise in mixed-signal integrated circuits. [Internet] [Masters thesis]. Oregon State University; 2003. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/1957/11794.

Council of Science Editors:

Owens BE. Simulation, measurement, and suppression of digital noise in mixed-signal integrated circuits. [Masters Thesis]. Oregon State University; 2003. Available from: http://hdl.handle.net/1957/11794


Oregon State University

10. Sadate, Aline C. A substrate noise coupling model for lightly doped CMOS processes.

Degree: MS, Electrical and Computer Engineering, 2000, Oregon State University

 This thesis presents a design-oriented model for lightly doped CMOS substrates. The model predicts the substrate noise coupling between noisy digital and sensitive analog blocks… (more)

Subjects/Keywords: Metal oxide semiconductors; Complementary

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APA (6th Edition):

Sadate, A. C. (2000). A substrate noise coupling model for lightly doped CMOS processes. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/8280

Chicago Manual of Style (16th Edition):

Sadate, Aline C. “A substrate noise coupling model for lightly doped CMOS processes.” 2000. Masters Thesis, Oregon State University. Accessed October 18, 2019. http://hdl.handle.net/1957/8280.

MLA Handbook (7th Edition):

Sadate, Aline C. “A substrate noise coupling model for lightly doped CMOS processes.” 2000. Web. 18 Oct 2019.

Vancouver:

Sadate AC. A substrate noise coupling model for lightly doped CMOS processes. [Internet] [Masters thesis]. Oregon State University; 2000. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/1957/8280.

Council of Science Editors:

Sadate AC. A substrate noise coupling model for lightly doped CMOS processes. [Masters Thesis]. Oregon State University; 2000. Available from: http://hdl.handle.net/1957/8280


Oregon State University

11. Sharma, Ajit. Predictive methodologies for substrate parasitic extraction and modeling in heavily doped CMOS substrates.

Degree: MS, Electrical and Computer Engineering, 2003, Oregon State University

 This thesis presents an automated methodology to calibrate the substrate profile for accurate prediction of substrate parasitics using Green's function based extractors. The technique requires… (more)

Subjects/Keywords: Metal oxide semiconductors; Complementary

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APA (6th Edition):

Sharma, A. (2003). Predictive methodologies for substrate parasitic extraction and modeling in heavily doped CMOS substrates. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/31842

Chicago Manual of Style (16th Edition):

Sharma, Ajit. “Predictive methodologies for substrate parasitic extraction and modeling in heavily doped CMOS substrates.” 2003. Masters Thesis, Oregon State University. Accessed October 18, 2019. http://hdl.handle.net/1957/31842.

MLA Handbook (7th Edition):

Sharma, Ajit. “Predictive methodologies for substrate parasitic extraction and modeling in heavily doped CMOS substrates.” 2003. Web. 18 Oct 2019.

Vancouver:

Sharma A. Predictive methodologies for substrate parasitic extraction and modeling in heavily doped CMOS substrates. [Internet] [Masters thesis]. Oregon State University; 2003. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/1957/31842.

Council of Science Editors:

Sharma A. Predictive methodologies for substrate parasitic extraction and modeling in heavily doped CMOS substrates. [Masters Thesis]. Oregon State University; 2003. Available from: http://hdl.handle.net/1957/31842


Oregon State University

12. Ghatak, Kalyan Brata. Design of sample and holds using CCDs in a standard CMOS process.

Degree: MS, Electrical and Computer Engineering, 2002, Oregon State University

 The parasitic components of MOS switches at high speeds affect the linearity and resolution of CMOS sample and hold circuits. CCD-based circuit design can offer… (more)

Subjects/Keywords: Charge coupled devices

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APA (6th Edition):

Ghatak, K. B. (2002). Design of sample and holds using CCDs in a standard CMOS process. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/29928

Chicago Manual of Style (16th Edition):

Ghatak, Kalyan Brata. “Design of sample and holds using CCDs in a standard CMOS process.” 2002. Masters Thesis, Oregon State University. Accessed October 18, 2019. http://hdl.handle.net/1957/29928.

MLA Handbook (7th Edition):

Ghatak, Kalyan Brata. “Design of sample and holds using CCDs in a standard CMOS process.” 2002. Web. 18 Oct 2019.

Vancouver:

Ghatak KB. Design of sample and holds using CCDs in a standard CMOS process. [Internet] [Masters thesis]. Oregon State University; 2002. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/1957/29928.

Council of Science Editors:

Ghatak KB. Design of sample and holds using CCDs in a standard CMOS process. [Masters Thesis]. Oregon State University; 2002. Available from: http://hdl.handle.net/1957/29928


Oregon State University

13. Heer, Donald. TekBots [superscript TM] : a platform for learning to revitalize undergraduate engineering education.

Degree: MS, Computer Engineering, 2002, Oregon State University

 In 2000 the Electrical and Computer Engineering department at Oregon State University began a new and innovative program named TekBots[superscript TM]. This program was created… (more)

Subjects/Keywords: Engineering  – Study and teaching (Higher)  – Activity programs

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APA (6th Edition):

Heer, D. (2002). TekBots [superscript TM] : a platform for learning to revitalize undergraduate engineering education. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/31637

Chicago Manual of Style (16th Edition):

Heer, Donald. “TekBots [superscript TM] : a platform for learning to revitalize undergraduate engineering education.” 2002. Masters Thesis, Oregon State University. Accessed October 18, 2019. http://hdl.handle.net/1957/31637.

MLA Handbook (7th Edition):

Heer, Donald. “TekBots [superscript TM] : a platform for learning to revitalize undergraduate engineering education.” 2002. Web. 18 Oct 2019.

Vancouver:

Heer D. TekBots [superscript TM] : a platform for learning to revitalize undergraduate engineering education. [Internet] [Masters thesis]. Oregon State University; 2002. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/1957/31637.

Council of Science Editors:

Heer D. TekBots [superscript TM] : a platform for learning to revitalize undergraduate engineering education. [Masters Thesis]. Oregon State University; 2002. Available from: http://hdl.handle.net/1957/31637


Oregon State University

14. Chennam, Madhusudhan. Design of current-mode track and hold circuits.

Degree: MS, Electrical and Computer Engineering, 2002, Oregon State University

 A differential current-mode track-and-hold (T/H) amplifier is used to sample an analog input signal. A new closed-loop current-mode architecture has been developed that overcomes the… (more)

Subjects/Keywords: Analog-to-digital converters

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APA (6th Edition):

Chennam, M. (2002). Design of current-mode track and hold circuits. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/32062

Chicago Manual of Style (16th Edition):

Chennam, Madhusudhan. “Design of current-mode track and hold circuits.” 2002. Masters Thesis, Oregon State University. Accessed October 18, 2019. http://hdl.handle.net/1957/32062.

MLA Handbook (7th Edition):

Chennam, Madhusudhan. “Design of current-mode track and hold circuits.” 2002. Web. 18 Oct 2019.

Vancouver:

Chennam M. Design of current-mode track and hold circuits. [Internet] [Masters thesis]. Oregon State University; 2002. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/1957/32062.

Council of Science Editors:

Chennam M. Design of current-mode track and hold circuits. [Masters Thesis]. Oregon State University; 2002. Available from: http://hdl.handle.net/1957/32062


Oregon State University

15. Ranganathan, Sachin. Design of a variable gain, high linearity, low power baseband filter for WLAN transmitters.

Degree: MS, Electrical and Computer Engineering, 2003, Oregon State University

 A variable gain, high linearity, low power baseband filter for WLAN applications is implemented in a 1.5 V 3 V 0.15 μm CMOS process. This… (more)

Subjects/Keywords: Electric filters  – Design and construction

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APA (6th Edition):

Ranganathan, S. (2003). Design of a variable gain, high linearity, low power baseband filter for WLAN transmitters. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/32350

Chicago Manual of Style (16th Edition):

Ranganathan, Sachin. “Design of a variable gain, high linearity, low power baseband filter for WLAN transmitters.” 2003. Masters Thesis, Oregon State University. Accessed October 18, 2019. http://hdl.handle.net/1957/32350.

MLA Handbook (7th Edition):

Ranganathan, Sachin. “Design of a variable gain, high linearity, low power baseband filter for WLAN transmitters.” 2003. Web. 18 Oct 2019.

Vancouver:

Ranganathan S. Design of a variable gain, high linearity, low power baseband filter for WLAN transmitters. [Internet] [Masters thesis]. Oregon State University; 2003. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/1957/32350.

Council of Science Editors:

Ranganathan S. Design of a variable gain, high linearity, low power baseband filter for WLAN transmitters. [Masters Thesis]. Oregon State University; 2003. Available from: http://hdl.handle.net/1957/32350


Oregon State University

16. Ayers, James S. A comparison of substrate noise coupling in heavily doped and lightly doped substrates for mixed-signal circuits.

Degree: MS, Electrical and Computer Engineering, 2004, Oregon State University

 An analysis of substrate noise coupling in mixed-signal circuits has been performed in the TSMC 0.25 [mu]m lightly doped and heavily doped CMOS processes. Methods… (more)

Subjects/Keywords: Mixed signal circuits  – Noise

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APA (6th Edition):

Ayers, J. S. (2004). A comparison of substrate noise coupling in heavily doped and lightly doped substrates for mixed-signal circuits. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/22814

Chicago Manual of Style (16th Edition):

Ayers, James S. “A comparison of substrate noise coupling in heavily doped and lightly doped substrates for mixed-signal circuits.” 2004. Masters Thesis, Oregon State University. Accessed October 18, 2019. http://hdl.handle.net/1957/22814.

MLA Handbook (7th Edition):

Ayers, James S. “A comparison of substrate noise coupling in heavily doped and lightly doped substrates for mixed-signal circuits.” 2004. Web. 18 Oct 2019.

Vancouver:

Ayers JS. A comparison of substrate noise coupling in heavily doped and lightly doped substrates for mixed-signal circuits. [Internet] [Masters thesis]. Oregon State University; 2004. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/1957/22814.

Council of Science Editors:

Ayers JS. A comparison of substrate noise coupling in heavily doped and lightly doped substrates for mixed-signal circuits. [Masters Thesis]. Oregon State University; 2004. Available from: http://hdl.handle.net/1957/22814


Oregon State University

17. Held, Martin A. A methodology for efficient substrate noise estimation from large scale digital circuits in mixed signal SoC's.

Degree: MS, Electrical and Computer Engineering, 2005, Oregon State University

 A methodology for rapid estimation of substrate noise generated by digital circuitry in mixed-signal circuits is presented. This methodology is incorporated into the Silencer! framework,… (more)

Subjects/Keywords: Substrate noise

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APA (6th Edition):

Held, M. A. (2005). A methodology for efficient substrate noise estimation from large scale digital circuits in mixed signal SoC's. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/22935

Chicago Manual of Style (16th Edition):

Held, Martin A. “A methodology for efficient substrate noise estimation from large scale digital circuits in mixed signal SoC's.” 2005. Masters Thesis, Oregon State University. Accessed October 18, 2019. http://hdl.handle.net/1957/22935.

MLA Handbook (7th Edition):

Held, Martin A. “A methodology for efficient substrate noise estimation from large scale digital circuits in mixed signal SoC's.” 2005. Web. 18 Oct 2019.

Vancouver:

Held MA. A methodology for efficient substrate noise estimation from large scale digital circuits in mixed signal SoC's. [Internet] [Masters thesis]. Oregon State University; 2005. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/1957/22935.

Council of Science Editors:

Held MA. A methodology for efficient substrate noise estimation from large scale digital circuits in mixed signal SoC's. [Masters Thesis]. Oregon State University; 2005. Available from: http://hdl.handle.net/1957/22935


Oregon State University

18. Hazenboom, Duncan S. A comparison of substrate noise coupling in lightly and heavily doped CMOS processes for 2.4 GHz LNA's.

Degree: MS, Electrical and Computer Engineering, 2004, Oregon State University

 Three types of low noise amplifiers operating at 2.4GHz were designed. They are the commonly used single-ended and differential amplifiers as well as a new… (more)

Subjects/Keywords: Amplifiers (Electronics)  – Noise

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APA (6th Edition):

Hazenboom, D. S. (2004). A comparison of substrate noise coupling in lightly and heavily doped CMOS processes for 2.4 GHz LNA's. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/11798

Chicago Manual of Style (16th Edition):

Hazenboom, Duncan S. “A comparison of substrate noise coupling in lightly and heavily doped CMOS processes for 2.4 GHz LNA's.” 2004. Masters Thesis, Oregon State University. Accessed October 18, 2019. http://hdl.handle.net/1957/11798.

MLA Handbook (7th Edition):

Hazenboom, Duncan S. “A comparison of substrate noise coupling in lightly and heavily doped CMOS processes for 2.4 GHz LNA's.” 2004. Web. 18 Oct 2019.

Vancouver:

Hazenboom DS. A comparison of substrate noise coupling in lightly and heavily doped CMOS processes for 2.4 GHz LNA's. [Internet] [Masters thesis]. Oregon State University; 2004. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/1957/11798.

Council of Science Editors:

Hazenboom DS. A comparison of substrate noise coupling in lightly and heavily doped CMOS processes for 2.4 GHz LNA's. [Masters Thesis]. Oregon State University; 2004. Available from: http://hdl.handle.net/1957/11798


Oregon State University

19. Jiang, Ruoxin. Design of a 1.8-V 14-bit [delta] - [sigma] A/D converter with 8X oversampling and 4 MHz Nyquist output rate.

Degree: PhD, Electrical and Computer Engineering, 2001, Oregon State University

 In this dissertation, a new Δ∑ A/D converter is presented that is ideally suited for communication applications. It is based on a single-loop single-stage structure,… (more)

Subjects/Keywords: Analog-to-digital converters  – Design and construction

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APA (6th Edition):

Jiang, R. (2001). Design of a 1.8-V 14-bit [delta] - [sigma] A/D converter with 8X oversampling and 4 MHz Nyquist output rate. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/32677

Chicago Manual of Style (16th Edition):

Jiang, Ruoxin. “Design of a 1.8-V 14-bit [delta] - [sigma] A/D converter with 8X oversampling and 4 MHz Nyquist output rate.” 2001. Doctoral Dissertation, Oregon State University. Accessed October 18, 2019. http://hdl.handle.net/1957/32677.

MLA Handbook (7th Edition):

Jiang, Ruoxin. “Design of a 1.8-V 14-bit [delta] - [sigma] A/D converter with 8X oversampling and 4 MHz Nyquist output rate.” 2001. Web. 18 Oct 2019.

Vancouver:

Jiang R. Design of a 1.8-V 14-bit [delta] - [sigma] A/D converter with 8X oversampling and 4 MHz Nyquist output rate. [Internet] [Doctoral dissertation]. Oregon State University; 2001. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/1957/32677.

Council of Science Editors:

Jiang R. Design of a 1.8-V 14-bit [delta] - [sigma] A/D converter with 8X oversampling and 4 MHz Nyquist output rate. [Doctoral Dissertation]. Oregon State University; 2001. Available from: http://hdl.handle.net/1957/32677


Oregon State University

20. Bhagavatheeswaran, Shanthi, S. Design methodology for low-jitter phase-locked loops.

Degree: MS, Electrical and Computer Engineering, 2001, Oregon State University

 This thesis presents a systematic top-down methodology for simulating a phase-locked loop using a macro model in Verilog-A. The macromodel has been used to evaluate… (more)

Subjects/Keywords: Phase-locked loops  – Computer simulation

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APA (6th Edition):

Bhagavatheeswaran, Shanthi, S. (2001). Design methodology for low-jitter phase-locked loops. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/32786

Chicago Manual of Style (16th Edition):

Bhagavatheeswaran, Shanthi, S. “Design methodology for low-jitter phase-locked loops.” 2001. Masters Thesis, Oregon State University. Accessed October 18, 2019. http://hdl.handle.net/1957/32786.

MLA Handbook (7th Edition):

Bhagavatheeswaran, Shanthi, S. “Design methodology for low-jitter phase-locked loops.” 2001. Web. 18 Oct 2019.

Vancouver:

Bhagavatheeswaran, Shanthi S. Design methodology for low-jitter phase-locked loops. [Internet] [Masters thesis]. Oregon State University; 2001. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/1957/32786.

Council of Science Editors:

Bhagavatheeswaran, Shanthi S. Design methodology for low-jitter phase-locked loops. [Masters Thesis]. Oregon State University; 2001. Available from: http://hdl.handle.net/1957/32786


Oregon State University

21. Gupta, Shivani. A 1-m W, 14-bit [sigma] [delta] A/D converter with 10-KHz conversion rate.

Degree: MS, Electrical and Computer Engineering, 1995, Oregon State University

Subjects/Keywords: Analog-to-digital converters  – Design and construction

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APA (6th Edition):

Gupta, S. (1995). A 1-m W, 14-bit [sigma] [delta] A/D converter with 10-KHz conversion rate. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/35324

Chicago Manual of Style (16th Edition):

Gupta, Shivani. “A 1-m W, 14-bit [sigma] [delta] A/D converter with 10-KHz conversion rate.” 1995. Masters Thesis, Oregon State University. Accessed October 18, 2019. http://hdl.handle.net/1957/35324.

MLA Handbook (7th Edition):

Gupta, Shivani. “A 1-m W, 14-bit [sigma] [delta] A/D converter with 10-KHz conversion rate.” 1995. Web. 18 Oct 2019.

Vancouver:

Gupta S. A 1-m W, 14-bit [sigma] [delta] A/D converter with 10-KHz conversion rate. [Internet] [Masters thesis]. Oregon State University; 1995. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/1957/35324.

Council of Science Editors:

Gupta S. A 1-m W, 14-bit [sigma] [delta] A/D converter with 10-KHz conversion rate. [Masters Thesis]. Oregon State University; 1995. Available from: http://hdl.handle.net/1957/35324


Oregon State University

22. Le, Jim K. Comparison and impact of substrate noise due to clocked and clockless circuitry.

Degree: MS, Electrical and Computer Engineering, 2007, Oregon State University

 Delay insensitive asynchronous circuitry provides significant advantages with respect to substrate noise due to localized switching. The differences between the substrate noise from NULL Convention… (more)

Subjects/Keywords: substrate noise; Substrate noise

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APA (6th Edition):

Le, J. K. (2007). Comparison and impact of substrate noise due to clocked and clockless circuitry. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/3874

Chicago Manual of Style (16th Edition):

Le, Jim K. “Comparison and impact of substrate noise due to clocked and clockless circuitry.” 2007. Masters Thesis, Oregon State University. Accessed October 18, 2019. http://hdl.handle.net/1957/3874.

MLA Handbook (7th Edition):

Le, Jim K. “Comparison and impact of substrate noise due to clocked and clockless circuitry.” 2007. Web. 18 Oct 2019.

Vancouver:

Le JK. Comparison and impact of substrate noise due to clocked and clockless circuitry. [Internet] [Masters thesis]. Oregon State University; 2007. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/1957/3874.

Council of Science Editors:

Le JK. Comparison and impact of substrate noise due to clocked and clockless circuitry. [Masters Thesis]. Oregon State University; 2007. Available from: http://hdl.handle.net/1957/3874


Oregon State University

23. Hanken, Christopher. Simulation and modeling of substrate noise generation from synchronous and asynchronous digital logic circuits.

Degree: MS, Electrical and Computer Engineering, 2007, Oregon State University

 Efficient methods for simulating the substrate noise generated by complex synchronous and asynchronous digital logic circuits are presented. By simulating digital logic at the gate… (more)

Subjects/Keywords: substrate; Substrate noise

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APA (6th Edition):

Hanken, C. (2007). Simulation and modeling of substrate noise generation from synchronous and asynchronous digital logic circuits. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/6693

Chicago Manual of Style (16th Edition):

Hanken, Christopher. “Simulation and modeling of substrate noise generation from synchronous and asynchronous digital logic circuits.” 2007. Masters Thesis, Oregon State University. Accessed October 18, 2019. http://hdl.handle.net/1957/6693.

MLA Handbook (7th Edition):

Hanken, Christopher. “Simulation and modeling of substrate noise generation from synchronous and asynchronous digital logic circuits.” 2007. Web. 18 Oct 2019.

Vancouver:

Hanken C. Simulation and modeling of substrate noise generation from synchronous and asynchronous digital logic circuits. [Internet] [Masters thesis]. Oregon State University; 2007. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/1957/6693.

Council of Science Editors:

Hanken C. Simulation and modeling of substrate noise generation from synchronous and asynchronous digital logic circuits. [Masters Thesis]. Oregon State University; 2007. Available from: http://hdl.handle.net/1957/6693

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