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Oregon State University
1.
Ruggeri, Thomas L.
TIMR : Time Interleaved Multi Rail.
Degree: MS, Electrical and Computer Engineering, 2012, Oregon State University
URL: http://hdl.handle.net/1957/29070 
► This work presents a new energy saving technique for modern digital designs. We propose Time Interleaved Multi-Rail (TIMR) - a method for providing two dynamic…
(more)
▼ This work presents a new energy saving technique for modern digital designs. We propose Time Interleaved Multi-Rail (TIMR) - a method for providing two dynamic supply rails to a circuit. This technique uses the first supply rail to mask the transition delay while changing the voltage of the second rail. We examine the design of TIMR as well as the implementation and considerations. We propose a number of control schemes that range from traditional DVFS to "race to sleep". This thesis also shows simulations of the technique using a existing voltage regulator in order to find the time and energy overhead of implementing the design. We find a 100μs switching time delay and 118μJ energy overhead associated with changing the voltage rail. This work concludes with comparisons to current energy saving techniques.
Advisors/Committee Members: Chiang, Patrick Y. (advisor), Lee, Ben (committee member).
Subjects/Keywords: VLSI; Integrated circuits – Very large scale integration
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APA (6th Edition):
Ruggeri, T. L. (2012). TIMR : Time Interleaved Multi Rail. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/29070
Chicago Manual of Style (16th Edition):
Ruggeri, Thomas L. “TIMR : Time Interleaved Multi Rail.” 2012. Masters Thesis, Oregon State University. Accessed April 16, 2021.
http://hdl.handle.net/1957/29070.
MLA Handbook (7th Edition):
Ruggeri, Thomas L. “TIMR : Time Interleaved Multi Rail.” 2012. Web. 16 Apr 2021.
Vancouver:
Ruggeri TL. TIMR : Time Interleaved Multi Rail. [Internet] [Masters thesis]. Oregon State University; 2012. [cited 2021 Apr 16].
Available from: http://hdl.handle.net/1957/29070.
Council of Science Editors:
Ruggeri TL. TIMR : Time Interleaved Multi Rail. [Masters Thesis]. Oregon State University; 2012. Available from: http://hdl.handle.net/1957/29070
Oregon State University
2.
Bai, Rui.
Design techniques for low-power electrical and optical serial link receivers.
Degree: PhD, Electrical and Computer Engineering, 2014, Oregon State University
URL: http://hdl.handle.net/1957/49094
► As computation power continues to grow, the demand for data transfer bandwidth is also rising. This is reflected in the increasing data-rate of high-speed links.…
(more)
▼ As computation power continues to grow, the demand for data transfer bandwidth is also rising. This is reflected in the increasing data-rate of high-speed links. However, the increase in data-rate is sustainable only if the I/O energy efficiency improves as well. This dissertation explores several techniques to enable high-speed links with low power consumption.
First, a serial link receiver with scalable supply voltage for different data-rates for optimum energy efficiency is presented. Low-voltage operation is proven to be an effective way to reduce power consumption, but it has not been widely adopted in high-speed link design due to associated design challenges. The proposed receiver uses an injection-locked ring oscillator (ILRO) for low-power clock recovery and deskewing with wide jitter-tracking bandwidth.
Optical link has become increasingly attractive due to the potential to deliver high aggregated bandwidth over longer distance compared to electrical links. The next design applies the architecture presented previously to an optical receiver in a wavelength-division modulated (WDM) link. Per-channel adaptation is built into the front-end transimpedance amplifier (TIA), which usually accounts for the highest power consumption, to enable energy optimization in the presence of prevalent variation. Built-in monitoring and controlling circuits facilitates automatic adaptation of the link.
Lastly, a low-power decision-feedback equalizer (DFE) using charge-based latch is presented. Designing an equalizer for low-voltage links can be particularly challenging because it usually has the highest bandwidth among all components. The proposed DFE with charge-based latch retains the low power consumption of a dynamic latch while achieving comparable speed of power-hungry current-mode logic (CML) circuits.
Advisors/Committee Members: Chiang, Patrick Y. (advisor), Moon, Un-Ku (committee member).
Subjects/Keywords: serial-link; Serial communications
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APA (6th Edition):
Bai, R. (2014). Design techniques for low-power electrical and optical serial link receivers. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/49094
Chicago Manual of Style (16th Edition):
Bai, Rui. “Design techniques for low-power electrical and optical serial link receivers.” 2014. Doctoral Dissertation, Oregon State University. Accessed April 16, 2021.
http://hdl.handle.net/1957/49094.
MLA Handbook (7th Edition):
Bai, Rui. “Design techniques for low-power electrical and optical serial link receivers.” 2014. Web. 16 Apr 2021.
Vancouver:
Bai R. Design techniques for low-power electrical and optical serial link receivers. [Internet] [Doctoral dissertation]. Oregon State University; 2014. [cited 2021 Apr 16].
Available from: http://hdl.handle.net/1957/49094.
Council of Science Editors:
Bai R. Design techniques for low-power electrical and optical serial link receivers. [Doctoral Dissertation]. Oregon State University; 2014. Available from: http://hdl.handle.net/1957/49094
Oregon State University
3.
Ma, Chao.
Energy-efficient clock generation for communication and computing systems using injection locking.
Degree: MS, Electrical and Computer Engineering, 2012, Oregon State University
URL: http://hdl.handle.net/1957/33929
► The design of high-performance, high-speed clock generation and distribution becomes challenging in terms of phase noise, jitter and power consumption, due to the fast development…
(more)
▼ The design of high-performance, high-speed clock generation and distribution becomes challenging in terms of phase noise, jitter and power consumption, due to the fast development of communication and computing systems. Injection locking is a promising clocking technique since it can significantly improve the energy efficiency, suppress the phase noise of the ring oscillator, enable a fast startup and conveniently generate multiple time-interleaved phases.
A quasi-linear model of injection-locked ring oscillator (ILRO) is utilized to mathematically formulate the frequency and time domain characteristics of the system, as well as the phase noise shaping and jitter tracking behavior. The settling behavior of ILRO is also exploited and shows a strong dependence on the locking range and the initial phase difference of the injected and the resultant oscillation signals.
A forwarded-clock synchronization based on injection locking is designed for a 10 Gb/s photonic interconnect according to the specific features of optical links. A single clock recovery can be used for all the four channels, resulting in a large amount of power and area saving. The applications of sub-harmonic and super-harmonic injection locking in wireless communications for frequency multiplying and division are also discussed.
Advisors/Committee Members: Chiang, Patrick Y. (advisor), Temes, Gabor C. (committee member).
Subjects/Keywords: Clock generation; Injection-locked ring oscillators; Integrated circuits
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APA (6th Edition):
Ma, C. (2012). Energy-efficient clock generation for communication and computing systems using injection locking. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/33929
Chicago Manual of Style (16th Edition):
Ma, Chao. “Energy-efficient clock generation for communication and computing systems using injection locking.” 2012. Masters Thesis, Oregon State University. Accessed April 16, 2021.
http://hdl.handle.net/1957/33929.
MLA Handbook (7th Edition):
Ma, Chao. “Energy-efficient clock generation for communication and computing systems using injection locking.” 2012. Web. 16 Apr 2021.
Vancouver:
Ma C. Energy-efficient clock generation for communication and computing systems using injection locking. [Internet] [Masters thesis]. Oregon State University; 2012. [cited 2021 Apr 16].
Available from: http://hdl.handle.net/1957/33929.
Council of Science Editors:
Ma C. Energy-efficient clock generation for communication and computing systems using injection locking. [Masters Thesis]. Oregon State University; 2012. Available from: http://hdl.handle.net/1957/33929
Oregon State University
4.
Cheng, Jiao.
Analysis and design on low-power short-range radios for wireless body area networks.
Degree: PhD, Electrical and Computer Engineering, 2014, Oregon State University
URL: http://hdl.handle.net/1957/48942
► The release of the IEEE802.15.6 standard has led to increased interest in low-power technologies for wireless body-area-networks (WBANs). The power dissipation, supply voltage, and die…
(more)
▼ The release of the IEEE802.15.6 standard has led to increased interest in low-power technologies for wireless body-area-networks (WBANs). The power dissipation, supply voltage, and die area are some of the most important criteria for successful WBAN implementations. Digital-intensive RX architectures can potentially result in sub-1V operation with significant reductions in power consumption and area, but require system and circuit-level innovations to achieve desired sensitivity and linearity. A PSK receiver (RX) is proposed that employs a digital-intensive architecture based on sub-sampling, Q-enhancement, and digital IF to enable lowpower (1.3mW) and low-voltage (0.6V) operation. Implemented in 65nm CMOS, this work is compatible with the IEEE 802.15.6 narrowband physical layer specification and achieves -91dBm and -96dBm sensitivity at 10⁻³ BER for π/4DQPSK and π/2-DBPSK modulation, respectively. The proposed highly-digital architecture and supply voltage scaling lead to a 3x improvement in RX energy efficiency and minimize silicon area consumption (~0.35mm² in 65nm CMOS) while achieving
state-of-the-art sensitivity. While this implementation focuses on IEEE 802.15.6 narrowband demodulation, the proposed architecture and circuit techniques are generally applicable to RX targeting ultra-low power consumption for sensor networks.
Advisors/Committee Members: Chiang, Patrick Y. (advisor), Moon, Un-Ku (committee member).
Subjects/Keywords: Receiver; Body area networks (Electronics)
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APA (6th Edition):
Cheng, J. (2014). Analysis and design on low-power short-range radios for wireless body area networks. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/48942
Chicago Manual of Style (16th Edition):
Cheng, Jiao. “Analysis and design on low-power short-range radios for wireless body area networks.” 2014. Doctoral Dissertation, Oregon State University. Accessed April 16, 2021.
http://hdl.handle.net/1957/48942.
MLA Handbook (7th Edition):
Cheng, Jiao. “Analysis and design on low-power short-range radios for wireless body area networks.” 2014. Web. 16 Apr 2021.
Vancouver:
Cheng J. Analysis and design on low-power short-range radios for wireless body area networks. [Internet] [Doctoral dissertation]. Oregon State University; 2014. [cited 2021 Apr 16].
Available from: http://hdl.handle.net/1957/48942.
Council of Science Editors:
Cheng J. Analysis and design on low-power short-range radios for wireless body area networks. [Doctoral Dissertation]. Oregon State University; 2014. Available from: http://hdl.handle.net/1957/48942
5.
Meliza, Stephen W.
Ultra-low energy digital logic controller design for wireless sensor networks.
Degree: MS, Electrical and Computer Engineering, 2009, Oregon State University
URL: http://hdl.handle.net/1957/11357
► Low energy design techniques for digital circuits are examined to determine their suitability for use in a digital logic controller for wireless sensor network nodes.…
(more)
▼ Low energy design techniques for digital circuits are examined to determine their suitability for use in a digital logic controller for wireless sensor network nodes. Transistor level simulations are used to evaluate the techniques and those demonstrating an energy reduction are used to implement a digital logic controller. The digital controller for the wireless sensor node, fabricated in a 0.18μm CMOS process, operates at 350mV while consuming 336fJ per clock cycle with a 250kbps data rate. Lab measurements show a 98% reduction in energy consumption compared to an implementation that utilizes standard design techniques, making it the lowest energy digital controller for wireless sensor nodes to date.
Advisors/Committee Members: Mayaram, Kartikeya (advisor), Chiang, Patrick Y (committee member).
Subjects/Keywords: Wireless Sensor Network; Wireless sensor networks – Design and construction
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APA (6th Edition):
Meliza, S. W. (2009). Ultra-low energy digital logic controller design for wireless sensor networks. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/11357
Chicago Manual of Style (16th Edition):
Meliza, Stephen W. “Ultra-low energy digital logic controller design for wireless sensor networks.” 2009. Masters Thesis, Oregon State University. Accessed April 16, 2021.
http://hdl.handle.net/1957/11357.
MLA Handbook (7th Edition):
Meliza, Stephen W. “Ultra-low energy digital logic controller design for wireless sensor networks.” 2009. Web. 16 Apr 2021.
Vancouver:
Meliza SW. Ultra-low energy digital logic controller design for wireless sensor networks. [Internet] [Masters thesis]. Oregon State University; 2009. [cited 2021 Apr 16].
Available from: http://hdl.handle.net/1957/11357.
Council of Science Editors:
Meliza SW. Ultra-low energy digital logic controller design for wireless sensor networks. [Masters Thesis]. Oregon State University; 2009. Available from: http://hdl.handle.net/1957/11357
6.
Donkoh, Eric Kwesi.
Design and modeling of low-power register file memories.
Degree: PhD, Electrical and Computer Engineering, 2013, Oregon State University
URL: http://hdl.handle.net/1957/40405
► With the evolving popularity of new computing platforms such as Ultrabooks, Tablets, and Smart Phones, and the shift to multi-core computing, power is now the…
(more)
▼ With the evolving popularity of new computing platforms such as Ultrabooks, Tablets, and Smart Phones, and the shift to multi-core computing, power is now the key performance limiter, a departure from the traditional frequency limitation. As such, increasingly low-power design solutions feature prominently in early architectural and design space exploration in CPU/SoC design. On a high performance CPU, majority of these early studies involve memories, especially Register Files. Register Files (RF) are the preferred memory element for fast data access and are therefore ubiquitous in modern microprocessor design, contributing approximately 30% of Intel's 32nm CPU core power. The goal of this research is two-fold. First, it explores low-power design techniques to reduce RF leakage and dynamic power at minimal delay and area cost. We analyze RF power distribution, data residencies, signal activities, and logic dependencies in modern 32nm/22nm high performance microprocessors. We then propose new circuit techniques to reduce power in critical memory logic blocks such as the bitcell, write data distribution, read access data path, and decoder. We use innovative transistor stack-forcing techniques to reduce RF read bitline and decoder leakage by as much as 90% and delay by 30% at minimal to no area overhead compared to existing stacking approaches. An essential component of low-power design is an accurate predictive model (power, area, and timing) for early architectural and design space tradeoff analysis. On a high performance CPU, greater than 75% of RFs are custom designed due to design complexities and constraints (power, area, timing, low-voltage operation requirements). Existing models are particularly unsuited for custom RF because these models typically assume a generic RF circuit implementation and are therefore inaccurate for predicting unique RF topologies without requiring new model development. Furthermore, these models do not accurately address common design optimizations such as device sizing, data gating, segmentation, and device stacking that significantly impact the power profile of an RF. In the second part of this research we've developed a customizable predictive model that addresses these key limitations. The proposed model is a hybrid of empirical reference data and analytical equations. We use an empirical reference implementation data of a topology under study to capture topology-specific characteristics and analytically model the impact of cross-topology features such as changes in bit-width, entry-count, ports, and common circuit-level design optimizations such as segmentation, gating, device stacking, and sizing. We show how the proposed model can be customized for different RF topologies and other memory structures such as SRAM and ROM using the same model equations. We also demonstrate how the new predictive model, with <10% error, is used in the real world tradeoff analysis in the design of
state-of-the-art high performance CPUs and SoCs.
Advisors/Committee Members: Chiang, Patrick Y. (advisor), Lu, Shih-Lien (committee member).
Subjects/Keywords: Register File; Low voltage systems
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APA (6th Edition):
Donkoh, E. K. (2013). Design and modeling of low-power register file memories. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/40405
Chicago Manual of Style (16th Edition):
Donkoh, Eric Kwesi. “Design and modeling of low-power register file memories.” 2013. Doctoral Dissertation, Oregon State University. Accessed April 16, 2021.
http://hdl.handle.net/1957/40405.
MLA Handbook (7th Edition):
Donkoh, Eric Kwesi. “Design and modeling of low-power register file memories.” 2013. Web. 16 Apr 2021.
Vancouver:
Donkoh EK. Design and modeling of low-power register file memories. [Internet] [Doctoral dissertation]. Oregon State University; 2013. [cited 2021 Apr 16].
Available from: http://hdl.handle.net/1957/40405.
Council of Science Editors:
Donkoh EK. Design and modeling of low-power register file memories. [Doctoral Dissertation]. Oregon State University; 2013. Available from: http://hdl.handle.net/1957/40405
7.
Pawlowski, Robert (Robert Stephen).
Measurement and analysis of soft error vulnerability of low-voltage logic and memory circuits.
Degree: PhD, Electrical and Computer Engineering, 2014, Oregon State University
URL: http://hdl.handle.net/1957/50774
► Scaling the supply voltage into the sub/near-threshold domain is one of the most effective methods for improving the energy efficiency of next-generation electronic microsystems. Unfortunately,…
(more)
▼ Scaling the supply voltage into the sub/near-threshold domain is one of the most effective methods for improving the energy efficiency of next-generation electronic microsystems. Unfortunately, the relationship between low-voltage operation and radiation-induced soft error rate is not widely known, as little research has been previously performed and reported for soft-error susceptibility of on-chip memory and logic at very low supply voltages. This information is critical for low-voltage circuit designers, as many applications that would benefit from the energy efficiency of sub/near-threshold also require high reliability. This work first details the design and implementation of a portable soft error reference platform, specifically targeting very low-voltage operation. The circuit-level details of a TSMC 65nm test-chip design are given, along with an analysis of data from experiments performed at Los Alamos Neutron Science Center (LANSCE) and the OSU Radiation Center. Once this soft-error rate is known, error resiliency techniques must be utilized for increased processor reliability. The design and implementation of an error-resilient, near-threshold SIMD processor in an IBM 45nm SOI process will also be covered. This prototype demonstrates both increased reliability and improved throughput over a conventional SIMD pipeline while operating in near-threshold.
Advisors/Committee Members: Chiang, Patrick Y. (advisor), Krishnamurthy, Ram (committee member).
Subjects/Keywords: Near-Threshold; Logic circuits – Effect of radiation on
…Center, and alpha particle experiments were done at the Oregon
State University radiation…
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APA ·
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APA (6th Edition):
Pawlowski, R. (. S. (2014). Measurement and analysis of soft error vulnerability of low-voltage logic and memory circuits. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/50774
Chicago Manual of Style (16th Edition):
Pawlowski, Robert (Robert Stephen). “Measurement and analysis of soft error vulnerability of low-voltage logic and memory circuits.” 2014. Doctoral Dissertation, Oregon State University. Accessed April 16, 2021.
http://hdl.handle.net/1957/50774.
MLA Handbook (7th Edition):
Pawlowski, Robert (Robert Stephen). “Measurement and analysis of soft error vulnerability of low-voltage logic and memory circuits.” 2014. Web. 16 Apr 2021.
Vancouver:
Pawlowski R(S. Measurement and analysis of soft error vulnerability of low-voltage logic and memory circuits. [Internet] [Doctoral dissertation]. Oregon State University; 2014. [cited 2021 Apr 16].
Available from: http://hdl.handle.net/1957/50774.
Council of Science Editors:
Pawlowski R(S. Measurement and analysis of soft error vulnerability of low-voltage logic and memory circuits. [Doctoral Dissertation]. Oregon State University; 2014. Available from: http://hdl.handle.net/1957/50774
8.
Jiang, Tao.
Design techniques for low-power multi-GS/s analog-to-digital converters.
Degree: PhD, Electrical and Computer Engineering, 2013, Oregon State University
URL: http://hdl.handle.net/1957/39396
► Ultra-high-speed (>10GS/s), medium-resolution (5~6bit), low-power (<50mW) analog-to-digital converter can find it application in the areas of digital oscilloscopes and next-generation serial link receivers. There are…
(more)
▼ Ultra-high-speed (>10GS/s), medium-resolution (5~6bit), low-power (<50mW) analog-to-digital converter can find it application in the areas of digital oscilloscopes and next-generation serial link receivers. There are several challenges to enable a successful design, however. First, the time-interleaved architecture is required in order to achieve over 10GS/s sampling rate, with the trade-off of the number of the channels and the sampling rate in each channel. Phase misalignment and channel mismatch must be considered too. Second, timing accuracy, especially dynamic jitter of sampling clock becomes a major concern at ultra-high frequency, and certain techniques must be taken to address it. Finally, to achieve low power consumption, Flash architecture is not suitable to serve as the sub-ADC, and a low-power sub-ADC that can work at relatively high speed need to be designed.
A single channel, asynchronous successive approximation (SA) ADC with improved feedback delay has been fabricated in 40nm CMOS. Compared with a conventional SA structure that employs a single quantizer controlled by a digital feedback logic loop, the proposed SA-ADC employs multiple quantizers for each conversion bit, clocked by an asynchronous ripple clock that is generated after each quantization. Hence, the sampling rate of the 6-bit ADC is limited only by the six delays of the Capacitive-DAC settling and each comparator’s quantization delay, as the digital logic delay is eliminated. Measurement results of the 40nm-CMOS SA-ADC achieves peak SNDR of 32.9dB at 1GS/s and 30.5dB at 1.25GS/s, consuming 5.28mW and 6.08mW respectively, leading to FoM of 148fJ/conversion-step and 178fJ/conversion-step, in a core area less than 170µm by 85µm.
Based on the previous work of sub-ADC, a 12-GS/s 5-b 50-mW ADC is designed in 40nm CMOS with 8 time-interleaved channels of Flash-SA hybrid structure each running at 1.5GS/s. A modified bootstrapped switch is used in the track-and-hold circuit, introducing a global clock signal to synchronize the sampling instants of each individual channel, therefore improve the phase alignment and reduce distortion. The global clock is provided by a CML buffer which is injected by off-chip low-noise sine-wave signal, so that the RMS dynamic jitter is low for better ENOB performance. Measurement results show that the 12GS/s ADC can achieve a SNDR of 25.8dB with the input signal frequency around DC and 22.8dB around 2GHz, consuming 32.1mW, leading to FoM of 237.3fJ/conversion-step, in a core area less than 800µm by 500µm.
Advisors/Committee Members: Chiang, Patrick Y. (advisor), Farsoni, Abi (committee member).
Subjects/Keywords: high-speed; Successive approximation analog-to-digital converters – Design and construction
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APA ·
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APA (6th Edition):
Jiang, T. (2013). Design techniques for low-power multi-GS/s analog-to-digital converters. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/39396
Chicago Manual of Style (16th Edition):
Jiang, Tao. “Design techniques for low-power multi-GS/s analog-to-digital converters.” 2013. Doctoral Dissertation, Oregon State University. Accessed April 16, 2021.
http://hdl.handle.net/1957/39396.
MLA Handbook (7th Edition):
Jiang, Tao. “Design techniques for low-power multi-GS/s analog-to-digital converters.” 2013. Web. 16 Apr 2021.
Vancouver:
Jiang T. Design techniques for low-power multi-GS/s analog-to-digital converters. [Internet] [Doctoral dissertation]. Oregon State University; 2013. [cited 2021 Apr 16].
Available from: http://hdl.handle.net/1957/39396.
Council of Science Editors:
Jiang T. Design techniques for low-power multi-GS/s analog-to-digital converters. [Doctoral Dissertation]. Oregon State University; 2013. Available from: http://hdl.handle.net/1957/39396
. 
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