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You searched for +publisher:"Oregon State University" +contributor:("Chiang, Patrick Y."). Showing records 1 – 8 of 8 total matches.

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Oregon State University

1. Ruggeri, Thomas L. TIMR : Time Interleaved Multi Rail.

Degree: MS, Electrical and Computer Engineering, 2012, Oregon State University

 This work presents a new energy saving technique for modern digital designs. We propose Time Interleaved Multi-Rail (TIMR) - a method for providing two dynamic… (more)

Subjects/Keywords: VLSI; Integrated circuits  – Very large scale integration

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APA (6th Edition):

Ruggeri, T. L. (2012). TIMR : Time Interleaved Multi Rail. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/29070

Chicago Manual of Style (16th Edition):

Ruggeri, Thomas L. “TIMR : Time Interleaved Multi Rail.” 2012. Masters Thesis, Oregon State University. Accessed April 16, 2021. http://hdl.handle.net/1957/29070.

MLA Handbook (7th Edition):

Ruggeri, Thomas L. “TIMR : Time Interleaved Multi Rail.” 2012. Web. 16 Apr 2021.

Vancouver:

Ruggeri TL. TIMR : Time Interleaved Multi Rail. [Internet] [Masters thesis]. Oregon State University; 2012. [cited 2021 Apr 16]. Available from: http://hdl.handle.net/1957/29070.

Council of Science Editors:

Ruggeri TL. TIMR : Time Interleaved Multi Rail. [Masters Thesis]. Oregon State University; 2012. Available from: http://hdl.handle.net/1957/29070


Oregon State University

2. Bai, Rui. Design techniques for low-power electrical and optical serial link receivers.

Degree: PhD, Electrical and Computer Engineering, 2014, Oregon State University

 As computation power continues to grow, the demand for data transfer bandwidth is also rising. This is reflected in the increasing data-rate of high-speed links.… (more)

Subjects/Keywords: serial-link; Serial communications

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APA (6th Edition):

Bai, R. (2014). Design techniques for low-power electrical and optical serial link receivers. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/49094

Chicago Manual of Style (16th Edition):

Bai, Rui. “Design techniques for low-power electrical and optical serial link receivers.” 2014. Doctoral Dissertation, Oregon State University. Accessed April 16, 2021. http://hdl.handle.net/1957/49094.

MLA Handbook (7th Edition):

Bai, Rui. “Design techniques for low-power electrical and optical serial link receivers.” 2014. Web. 16 Apr 2021.

Vancouver:

Bai R. Design techniques for low-power electrical and optical serial link receivers. [Internet] [Doctoral dissertation]. Oregon State University; 2014. [cited 2021 Apr 16]. Available from: http://hdl.handle.net/1957/49094.

Council of Science Editors:

Bai R. Design techniques for low-power electrical and optical serial link receivers. [Doctoral Dissertation]. Oregon State University; 2014. Available from: http://hdl.handle.net/1957/49094


Oregon State University

3. Ma, Chao. Energy-efficient clock generation for communication and computing systems using injection locking.

Degree: MS, Electrical and Computer Engineering, 2012, Oregon State University

 The design of high-performance, high-speed clock generation and distribution becomes challenging in terms of phase noise, jitter and power consumption, due to the fast development… (more)

Subjects/Keywords: Clock generation; Injection-locked ring oscillators; Integrated circuits

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APA (6th Edition):

Ma, C. (2012). Energy-efficient clock generation for communication and computing systems using injection locking. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/33929

Chicago Manual of Style (16th Edition):

Ma, Chao. “Energy-efficient clock generation for communication and computing systems using injection locking.” 2012. Masters Thesis, Oregon State University. Accessed April 16, 2021. http://hdl.handle.net/1957/33929.

MLA Handbook (7th Edition):

Ma, Chao. “Energy-efficient clock generation for communication and computing systems using injection locking.” 2012. Web. 16 Apr 2021.

Vancouver:

Ma C. Energy-efficient clock generation for communication and computing systems using injection locking. [Internet] [Masters thesis]. Oregon State University; 2012. [cited 2021 Apr 16]. Available from: http://hdl.handle.net/1957/33929.

Council of Science Editors:

Ma C. Energy-efficient clock generation for communication and computing systems using injection locking. [Masters Thesis]. Oregon State University; 2012. Available from: http://hdl.handle.net/1957/33929


Oregon State University

4. Cheng, Jiao. Analysis and design on low-power short-range radios for wireless body area networks.

Degree: PhD, Electrical and Computer Engineering, 2014, Oregon State University

 The release of the IEEE802.15.6 standard has led to increased interest in low-power technologies for wireless body-area-networks (WBANs). The power dissipation, supply voltage, and die… (more)

Subjects/Keywords: Receiver; Body area networks (Electronics)

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APA (6th Edition):

Cheng, J. (2014). Analysis and design on low-power short-range radios for wireless body area networks. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/48942

Chicago Manual of Style (16th Edition):

Cheng, Jiao. “Analysis and design on low-power short-range radios for wireless body area networks.” 2014. Doctoral Dissertation, Oregon State University. Accessed April 16, 2021. http://hdl.handle.net/1957/48942.

MLA Handbook (7th Edition):

Cheng, Jiao. “Analysis and design on low-power short-range radios for wireless body area networks.” 2014. Web. 16 Apr 2021.

Vancouver:

Cheng J. Analysis and design on low-power short-range radios for wireless body area networks. [Internet] [Doctoral dissertation]. Oregon State University; 2014. [cited 2021 Apr 16]. Available from: http://hdl.handle.net/1957/48942.

Council of Science Editors:

Cheng J. Analysis and design on low-power short-range radios for wireless body area networks. [Doctoral Dissertation]. Oregon State University; 2014. Available from: http://hdl.handle.net/1957/48942

5. Meliza, Stephen W. Ultra-low energy digital logic controller design for wireless sensor networks.

Degree: MS, Electrical and Computer Engineering, 2009, Oregon State University

 Low energy design techniques for digital circuits are examined to determine their suitability for use in a digital logic controller for wireless sensor network nodes.… (more)

Subjects/Keywords: Wireless Sensor Network; Wireless sensor networks  – Design and construction

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APA (6th Edition):

Meliza, S. W. (2009). Ultra-low energy digital logic controller design for wireless sensor networks. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/11357

Chicago Manual of Style (16th Edition):

Meliza, Stephen W. “Ultra-low energy digital logic controller design for wireless sensor networks.” 2009. Masters Thesis, Oregon State University. Accessed April 16, 2021. http://hdl.handle.net/1957/11357.

MLA Handbook (7th Edition):

Meliza, Stephen W. “Ultra-low energy digital logic controller design for wireless sensor networks.” 2009. Web. 16 Apr 2021.

Vancouver:

Meliza SW. Ultra-low energy digital logic controller design for wireless sensor networks. [Internet] [Masters thesis]. Oregon State University; 2009. [cited 2021 Apr 16]. Available from: http://hdl.handle.net/1957/11357.

Council of Science Editors:

Meliza SW. Ultra-low energy digital logic controller design for wireless sensor networks. [Masters Thesis]. Oregon State University; 2009. Available from: http://hdl.handle.net/1957/11357

6. Donkoh, Eric Kwesi. Design and modeling of low-power register file memories.

Degree: PhD, Electrical and Computer Engineering, 2013, Oregon State University

 With the evolving popularity of new computing platforms such as Ultrabooks, Tablets, and Smart Phones, and the shift to multi-core computing, power is now the… (more)

Subjects/Keywords: Register File; Low voltage systems

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APA (6th Edition):

Donkoh, E. K. (2013). Design and modeling of low-power register file memories. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/40405

Chicago Manual of Style (16th Edition):

Donkoh, Eric Kwesi. “Design and modeling of low-power register file memories.” 2013. Doctoral Dissertation, Oregon State University. Accessed April 16, 2021. http://hdl.handle.net/1957/40405.

MLA Handbook (7th Edition):

Donkoh, Eric Kwesi. “Design and modeling of low-power register file memories.” 2013. Web. 16 Apr 2021.

Vancouver:

Donkoh EK. Design and modeling of low-power register file memories. [Internet] [Doctoral dissertation]. Oregon State University; 2013. [cited 2021 Apr 16]. Available from: http://hdl.handle.net/1957/40405.

Council of Science Editors:

Donkoh EK. Design and modeling of low-power register file memories. [Doctoral Dissertation]. Oregon State University; 2013. Available from: http://hdl.handle.net/1957/40405

7. Pawlowski, Robert (Robert Stephen). Measurement and analysis of soft error vulnerability of low-voltage logic and memory circuits.

Degree: PhD, Electrical and Computer Engineering, 2014, Oregon State University

 Scaling the supply voltage into the sub/near-threshold domain is one of the most effective methods for improving the energy efficiency of next-generation electronic microsystems. Unfortunately,… (more)

Subjects/Keywords: Near-Threshold; Logic circuits  – Effect of radiation on

…Center, and alpha particle experiments were done at the Oregon State University radiation… 

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APA (6th Edition):

Pawlowski, R. (. S. (2014). Measurement and analysis of soft error vulnerability of low-voltage logic and memory circuits. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/50774

Chicago Manual of Style (16th Edition):

Pawlowski, Robert (Robert Stephen). “Measurement and analysis of soft error vulnerability of low-voltage logic and memory circuits.” 2014. Doctoral Dissertation, Oregon State University. Accessed April 16, 2021. http://hdl.handle.net/1957/50774.

MLA Handbook (7th Edition):

Pawlowski, Robert (Robert Stephen). “Measurement and analysis of soft error vulnerability of low-voltage logic and memory circuits.” 2014. Web. 16 Apr 2021.

Vancouver:

Pawlowski R(S. Measurement and analysis of soft error vulnerability of low-voltage logic and memory circuits. [Internet] [Doctoral dissertation]. Oregon State University; 2014. [cited 2021 Apr 16]. Available from: http://hdl.handle.net/1957/50774.

Council of Science Editors:

Pawlowski R(S. Measurement and analysis of soft error vulnerability of low-voltage logic and memory circuits. [Doctoral Dissertation]. Oregon State University; 2014. Available from: http://hdl.handle.net/1957/50774

8. Jiang, Tao. Design techniques for low-power multi-GS/s analog-to-digital converters.

Degree: PhD, Electrical and Computer Engineering, 2013, Oregon State University

 Ultra-high-speed (>10GS/s), medium-resolution (5~6bit), low-power (<50mW) analog-to-digital converter can find it application in the areas of digital oscilloscopes and next-generation serial link receivers. There are… (more)

Subjects/Keywords: high-speed; Successive approximation analog-to-digital converters  – Design and construction

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APA (6th Edition):

Jiang, T. (2013). Design techniques for low-power multi-GS/s analog-to-digital converters. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/39396

Chicago Manual of Style (16th Edition):

Jiang, Tao. “Design techniques for low-power multi-GS/s analog-to-digital converters.” 2013. Doctoral Dissertation, Oregon State University. Accessed April 16, 2021. http://hdl.handle.net/1957/39396.

MLA Handbook (7th Edition):

Jiang, Tao. “Design techniques for low-power multi-GS/s analog-to-digital converters.” 2013. Web. 16 Apr 2021.

Vancouver:

Jiang T. Design techniques for low-power multi-GS/s analog-to-digital converters. [Internet] [Doctoral dissertation]. Oregon State University; 2013. [cited 2021 Apr 16]. Available from: http://hdl.handle.net/1957/39396.

Council of Science Editors:

Jiang T. Design techniques for low-power multi-GS/s analog-to-digital converters. [Doctoral Dissertation]. Oregon State University; 2013. Available from: http://hdl.handle.net/1957/39396

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