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You searched for +publisher:"NSYSU" +contributor:("Yun-Nan Chang"). Showing records 1 – 30 of 113 total matches.

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NSYSU

1. Chang, Jia-hao. Design of Tessellation Unit for 3D Graphic Processor.

Degree: Master, Computer Science and Engineering, 2017, NSYSU

 Tessellation shader is one of the advanced graphics rendering functions supported in state-of-the-art graphics standard applications programming interfaces such as OpenGL 4.x and DirextX 11.… (more)

Subjects/Keywords: tessellation; tessellation primitive generation; OpenGL 4.x; tessellation unit; primitive assembly unit

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chang, J. (2017). Design of Tessellation Unit for 3D Graphic Processor. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811117-172407

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chang, Jia-hao. “Design of Tessellation Unit for 3D Graphic Processor.” 2017. Thesis, NSYSU. Accessed July 18, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811117-172407.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chang, Jia-hao. “Design of Tessellation Unit for 3D Graphic Processor.” 2017. Web. 18 Jul 2019.

Vancouver:

Chang J. Design of Tessellation Unit for 3D Graphic Processor. [Internet] [Thesis]. NSYSU; 2017. [cited 2019 Jul 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811117-172407.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chang J. Design of Tessellation Unit for 3D Graphic Processor. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811117-172407

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

2. Lin, Wei-Sen. Design of Unified Arithmetic Units for 3D Graphics Vertex Shader.

Degree: Master, Computer Science and Engineering, 2008, NSYSU

 Vertex shader, one of the core parts in 3D graphics systems, is to speed up the operations of coordinate transformation and lighting in 3D graphics… (more)

Subjects/Keywords: Vertex Shader; higher-order approximation; throughput of the matrix computation

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APA (6th Edition):

Lin, W. (2008). Design of Unified Arithmetic Units for 3D Graphics Vertex Shader. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902108-114207

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lin, Wei-Sen. “Design of Unified Arithmetic Units for 3D Graphics Vertex Shader.” 2008. Thesis, NSYSU. Accessed July 18, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902108-114207.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lin, Wei-Sen. “Design of Unified Arithmetic Units for 3D Graphics Vertex Shader.” 2008. Web. 18 Jul 2019.

Vancouver:

Lin W. Design of Unified Arithmetic Units for 3D Graphics Vertex Shader. [Internet] [Thesis]. NSYSU; 2008. [cited 2019 Jul 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902108-114207.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lin W. Design of Unified Arithmetic Units for 3D Graphics Vertex Shader. [Thesis]. NSYSU; 2008. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902108-114207

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

3. Fu, Chien-jung. Design of Various VLSI Sorting Accelerator Architectures.

Degree: Master, Computer Science and Engineering, 2009, NSYSU

 In this thesis, various designs of VLSI sorter architectures are proposed. This thesis first presents a baseline serial sorter architecture built on a central memory… (more)

Subjects/Keywords: Sorter; Odd-Even merge sort

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APA (6th Edition):

Fu, C. (2009). Design of Various VLSI Sorting Accelerator Architectures. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0831109-115655

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Fu, Chien-jung. “Design of Various VLSI Sorting Accelerator Architectures.” 2009. Thesis, NSYSU. Accessed July 18, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0831109-115655.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Fu, Chien-jung. “Design of Various VLSI Sorting Accelerator Architectures.” 2009. Web. 18 Jul 2019.

Vancouver:

Fu C. Design of Various VLSI Sorting Accelerator Architectures. [Internet] [Thesis]. NSYSU; 2009. [cited 2019 Jul 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0831109-115655.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Fu C. Design of Various VLSI Sorting Accelerator Architectures. [Thesis]. NSYSU; 2009. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0831109-115655

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

4. Lin, Chueh-Ting. Multi-bank Memory-based Matrix-Transposer Circuit Generator.

Degree: Master, Computer Science and Engineering, 2009, NSYSU

 A novel design methodology of parallel VLSI matrix transposer circuit based on a multi-bank memory architecture is presented. The proposed transposer design is especially suitable… (more)

Subjects/Keywords: Matrix Transposer

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APA (6th Edition):

Lin, C. (2009). Multi-bank Memory-based Matrix-Transposer Circuit Generator. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0904109-113406

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lin, Chueh-Ting. “Multi-bank Memory-based Matrix-Transposer Circuit Generator.” 2009. Thesis, NSYSU. Accessed July 18, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0904109-113406.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lin, Chueh-Ting. “Multi-bank Memory-based Matrix-Transposer Circuit Generator.” 2009. Web. 18 Jul 2019.

Vancouver:

Lin C. Multi-bank Memory-based Matrix-Transposer Circuit Generator. [Internet] [Thesis]. NSYSU; 2009. [cited 2019 Jul 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0904109-113406.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lin C. Multi-bank Memory-based Matrix-Transposer Circuit Generator. [Thesis]. NSYSU; 2009. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0904109-113406

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

5. Hsu, Chao-yi. Design and implementation of a multi-thread unified SIMD graphics processor.

Degree: Master, Computer Science and Engineering, 2013, NSYSU

 This thesis presents a low-cost design and implementation of single-core multi-thread unified graphic processor unit (GPU) targeted for embedded graphics applications. The proposed GPU has… (more)

Subjects/Keywords: Multi-threading; Unified GPU; Thread control; Fill unit; Multi-texture

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APA (6th Edition):

Hsu, C. (2013). Design and implementation of a multi-thread unified SIMD graphics processor. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808113-022414

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hsu, Chao-yi. “Design and implementation of a multi-thread unified SIMD graphics processor.” 2013. Thesis, NSYSU. Accessed July 18, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808113-022414.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hsu, Chao-yi. “Design and implementation of a multi-thread unified SIMD graphics processor.” 2013. Web. 18 Jul 2019.

Vancouver:

Hsu C. Design and implementation of a multi-thread unified SIMD graphics processor. [Internet] [Thesis]. NSYSU; 2013. [cited 2019 Jul 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808113-022414.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hsu C. Design and implementation of a multi-thread unified SIMD graphics processor. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808113-022414

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

6. Chen, Han-wei. A Memory-efficient 2D-graphics rasterization scheme.

Degree: Master, Computer Science and Engineering, 2013, NSYSU

 With the increasing demand of vector graphics applications, how to develop an efficient embedded rendering system becomes a hot issue in recent years. For embedded… (more)

Subjects/Keywords: scan-line buffer; Vector Graphics; Rasterization; winding count; 2D vector graphics

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APA (6th Edition):

Chen, H. (2013). A Memory-efficient 2D-graphics rasterization scheme. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0809113-053639

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chen, Han-wei. “A Memory-efficient 2D-graphics rasterization scheme.” 2013. Thesis, NSYSU. Accessed July 18, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0809113-053639.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chen, Han-wei. “A Memory-efficient 2D-graphics rasterization scheme.” 2013. Web. 18 Jul 2019.

Vancouver:

Chen H. A Memory-efficient 2D-graphics rasterization scheme. [Internet] [Thesis]. NSYSU; 2013. [cited 2019 Jul 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0809113-053639.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen H. A Memory-efficient 2D-graphics rasterization scheme. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0809113-053639

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

7. Tang, En-shou. Design exploration of multi-core GPU architecture.

Degree: Master, Computer Science and Engineering, 2013, NSYSU

 With the rapid increase of graphics applications in mobile devices, how to develop an efficient embedded graphics processor unit (GPU) has become a very important… (more)

Subjects/Keywords: GPU; simulation platform; thread scheduling; back-face culling; clipping

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Tang, E. (2013). Design exploration of multi-core GPU architecture. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0809113-135037

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Tang, En-shou. “Design exploration of multi-core GPU architecture.” 2013. Thesis, NSYSU. Accessed July 18, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0809113-135037.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Tang, En-shou. “Design exploration of multi-core GPU architecture.” 2013. Web. 18 Jul 2019.

Vancouver:

Tang E. Design exploration of multi-core GPU architecture. [Internet] [Thesis]. NSYSU; 2013. [cited 2019 Jul 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0809113-135037.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tang E. Design exploration of multi-core GPU architecture. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0809113-135037

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

8. Wu, Cheng-Ta. SoC Integration and Verification of an AXI-Based 3D Graphics OpenGL ES2.0 SoC.

Degree: Master, Computer Science and Engineering, 2013, NSYSU

 Nowadays, due to improvement of fabrication and IP design technology, the design complexity of System on Chip is increasing very fast. Thus we need huge… (more)

Subjects/Keywords: BUS; AXI; AHB; Verification; OpenGL ES2.0; Integration

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wu, C. (2013). SoC Integration and Verification of an AXI-Based 3D Graphics OpenGL ES2.0 SoC. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1015113-190908

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wu, Cheng-Ta. “SoC Integration and Verification of an AXI-Based 3D Graphics OpenGL ES2.0 SoC.” 2013. Thesis, NSYSU. Accessed July 18, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1015113-190908.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wu, Cheng-Ta. “SoC Integration and Verification of an AXI-Based 3D Graphics OpenGL ES2.0 SoC.” 2013. Web. 18 Jul 2019.

Vancouver:

Wu C. SoC Integration and Verification of an AXI-Based 3D Graphics OpenGL ES2.0 SoC. [Internet] [Thesis]. NSYSU; 2013. [cited 2019 Jul 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1015113-190908.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wu C. SoC Integration and Verification of an AXI-Based 3D Graphics OpenGL ES2.0 SoC. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1015113-190908

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

9. Wu, Yi-lun. A High Voltage Operational Amplifier with Rail-to-rail Input and Output Ranges and an 8:1 Analog High Voltage Multiplexer.

Degree: Master, Electrical Engineering, 2014, NSYSU

 One of the key techniques of electric vehicles (EVs) is battery management systems, which demand the development of battery modules, the measurement circuits of batteries,… (more)

Subjects/Keywords: high-voltage amplifier; high-voltage switch; high-voltage analog multiplexer; battery management system; rail-to-rail input and output ranges

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wu, Y. (2014). A High Voltage Operational Amplifier with Rail-to-rail Input and Output Ranges and an 8:1 Analog High Voltage Multiplexer. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0614114-133104

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wu, Yi-lun. “A High Voltage Operational Amplifier with Rail-to-rail Input and Output Ranges and an 8:1 Analog High Voltage Multiplexer.” 2014. Thesis, NSYSU. Accessed July 18, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0614114-133104.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wu, Yi-lun. “A High Voltage Operational Amplifier with Rail-to-rail Input and Output Ranges and an 8:1 Analog High Voltage Multiplexer.” 2014. Web. 18 Jul 2019.

Vancouver:

Wu Y. A High Voltage Operational Amplifier with Rail-to-rail Input and Output Ranges and an 8:1 Analog High Voltage Multiplexer. [Internet] [Thesis]. NSYSU; 2014. [cited 2019 Jul 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0614114-133104.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wu Y. A High Voltage Operational Amplifier with Rail-to-rail Input and Output Ranges and an 8:1 Analog High Voltage Multiplexer. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0614114-133104

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

10. Wu, Tzu-chao. A Temperature Sensor with Second-Order Calibration and Process Compensation and All Digital Estimator for Battery State of Charge.

Degree: Master, Communications Engineering, 2014, NSYSU

 Battery management is one of the most important technologies for electric vehicles, since it is highly critical to safety. Notably, temperature sensors are needed to… (more)

Subjects/Keywords: temperature sensor; second-order effects; PTAT sensor; CTAT sensor; coulomb counting method; open circuit voltage method; state of charge; second-order calibration

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wu, T. (2014). A Temperature Sensor with Second-Order Calibration and Process Compensation and All Digital Estimator for Battery State of Charge. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0614114-134817

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wu, Tzu-chao. “A Temperature Sensor with Second-Order Calibration and Process Compensation and All Digital Estimator for Battery State of Charge.” 2014. Thesis, NSYSU. Accessed July 18, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0614114-134817.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wu, Tzu-chao. “A Temperature Sensor with Second-Order Calibration and Process Compensation and All Digital Estimator for Battery State of Charge.” 2014. Web. 18 Jul 2019.

Vancouver:

Wu T. A Temperature Sensor with Second-Order Calibration and Process Compensation and All Digital Estimator for Battery State of Charge. [Internet] [Thesis]. NSYSU; 2014. [cited 2019 Jul 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0614114-134817.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wu T. A Temperature Sensor with Second-Order Calibration and Process Compensation and All Digital Estimator for Battery State of Charge. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0614114-134817

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

11. Lu, Yao-Ta. Design of Low-cost BVH Construction Circuit for Ray Tracing based on Surface Area Heuristic Metric.

Degree: Master, Computer Science and Engineering, 2014, NSYSU

 The acceleration of tree construction is a very important issue for real-time ray-tracing of dynamic scenes. This paper presents a low-cost design of bounding volume… (more)

Subjects/Keywords: ray-tracing; BVH; computer graphics; BVH tree construction; ray-tracing hardware

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lu, Y. (2014). Design of Low-cost BVH Construction Circuit for Ray Tracing based on Surface Area Heuristic Metric. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0627114-221628

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lu, Yao-Ta. “Design of Low-cost BVH Construction Circuit for Ray Tracing based on Surface Area Heuristic Metric.” 2014. Thesis, NSYSU. Accessed July 18, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0627114-221628.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lu, Yao-Ta. “Design of Low-cost BVH Construction Circuit for Ray Tracing based on Surface Area Heuristic Metric.” 2014. Web. 18 Jul 2019.

Vancouver:

Lu Y. Design of Low-cost BVH Construction Circuit for Ray Tracing based on Surface Area Heuristic Metric. [Internet] [Thesis]. NSYSU; 2014. [cited 2019 Jul 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0627114-221628.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lu Y. Design of Low-cost BVH Construction Circuit for Ray Tracing based on Surface Area Heuristic Metric. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0627114-221628

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

12. Feng, Hao. A Memory-Efficient and Low-power Architecture for Tail-biting Convolution Code Decoder.

Degree: Master, Computer Science and Engineering, 2014, NSYSU

 In wireless communication system, the data will be interfered easily with noise during transmission, thus the transmitter usually uses convolution code to encode the data.… (more)

Subjects/Keywords: pre-traceback; low power; wireless communication; error detection; tail-biting convolutional code; Viterbi decoder

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APA (6th Edition):

Feng, H. (2014). A Memory-Efficient and Low-power Architecture for Tail-biting Convolution Code Decoder. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0715114-133649

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Feng, Hao. “A Memory-Efficient and Low-power Architecture for Tail-biting Convolution Code Decoder.” 2014. Thesis, NSYSU. Accessed July 18, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0715114-133649.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Feng, Hao. “A Memory-Efficient and Low-power Architecture for Tail-biting Convolution Code Decoder.” 2014. Web. 18 Jul 2019.

Vancouver:

Feng H. A Memory-Efficient and Low-power Architecture for Tail-biting Convolution Code Decoder. [Internet] [Thesis]. NSYSU; 2014. [cited 2019 Jul 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0715114-133649.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Feng H. A Memory-Efficient and Low-power Architecture for Tail-biting Convolution Code Decoder. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0715114-133649

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

13. Lu, Ren-yao. High-performance High-radix Word-based Montgomery Modular Multipliers.

Degree: Master, Computer Science and Engineering, 2014, NSYSU

 Nowadays, with the evolution of the internet,network becomes an important role in human's life. Because more and more E-commerce and electronic transaction are implemented in… (more)

Subjects/Keywords: Public-key Cryptosystems; RSA Cryptosystems; High-radix Word-based Montgomery Modular Multiplier; Montgomery Modular Multiplier

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lu, R. (2014). High-performance High-radix Word-based Montgomery Modular Multipliers. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0718114-165103

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lu, Ren-yao. “High-performance High-radix Word-based Montgomery Modular Multipliers.” 2014. Thesis, NSYSU. Accessed July 18, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0718114-165103.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lu, Ren-yao. “High-performance High-radix Word-based Montgomery Modular Multipliers.” 2014. Web. 18 Jul 2019.

Vancouver:

Lu R. High-performance High-radix Word-based Montgomery Modular Multipliers. [Internet] [Thesis]. NSYSU; 2014. [cited 2019 Jul 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0718114-165103.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lu R. High-performance High-radix Word-based Montgomery Modular Multipliers. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0718114-165103

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

14. yang, Ho-chun. Design and Implementation of a Multi-core Graphic Processing Unit based on SIMT Architecture.

Degree: Master, Computer Science and Engineering, 2014, NSYSU

 With the increasing demand of embedded graphic processing unit (GPU), how to develop an efficient GPU has become more and more important. This thesis proposed… (more)

Subjects/Keywords: Unified GPU; Multithreading; Branch divergence; Multi-core; SIMT

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

yang, H. (2014). Design and Implementation of a Multi-core Graphic Processing Unit based on SIMT Architecture. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728114-141237

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

yang, Ho-chun. “Design and Implementation of a Multi-core Graphic Processing Unit based on SIMT Architecture.” 2014. Thesis, NSYSU. Accessed July 18, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728114-141237.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

yang, Ho-chun. “Design and Implementation of a Multi-core Graphic Processing Unit based on SIMT Architecture.” 2014. Web. 18 Jul 2019.

Vancouver:

yang H. Design and Implementation of a Multi-core Graphic Processing Unit based on SIMT Architecture. [Internet] [Thesis]. NSYSU; 2014. [cited 2019 Jul 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728114-141237.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

yang H. Design and Implementation of a Multi-core Graphic Processing Unit based on SIMT Architecture. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728114-141237

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

15. Lin, Hong. Design of Ray Tracing Circuit with Hybrid Single and Packet Ray Traversal.

Degree: Master, Computer Science and Engineering, 2014, NSYSU

 Ray-tracing can render more realistic images than the traditional depth-buffer based rendering approach such that many people expect it can be gradually applied to embedded… (more)

Subjects/Keywords: Ray-tracing; Packet ray; Single ray; Hybrid traversal

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lin, H. (2014). Design of Ray Tracing Circuit with Hybrid Single and Packet Ray Traversal. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0810114-165952

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lin, Hong. “Design of Ray Tracing Circuit with Hybrid Single and Packet Ray Traversal.” 2014. Thesis, NSYSU. Accessed July 18, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0810114-165952.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lin, Hong. “Design of Ray Tracing Circuit with Hybrid Single and Packet Ray Traversal.” 2014. Web. 18 Jul 2019.

Vancouver:

Lin H. Design of Ray Tracing Circuit with Hybrid Single and Packet Ray Traversal. [Internet] [Thesis]. NSYSU; 2014. [cited 2019 Jul 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0810114-165952.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lin H. Design of Ray Tracing Circuit with Hybrid Single and Packet Ray Traversal. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0810114-165952

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

16. Li, Jin-wei. Design of some DSP circuits based on stochastic computation.

Degree: Master, Computer Science and Engineering, 2014, NSYSU

 Stochastic computing (SC) has recently gained attention due to its fault-tolerance property. Different from the ordinary binary computing, this unconventional approach represents numbers using the… (more)

Subjects/Keywords: discrete cosine transform; tail-biting convolution; low-density parity-check; stochastic decoding; stochastic computing

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Li, J. (2014). Design of some DSP circuits based on stochastic computation. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811114-025841

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Li, Jin-wei. “Design of some DSP circuits based on stochastic computation.” 2014. Thesis, NSYSU. Accessed July 18, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811114-025841.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Li, Jin-wei. “Design of some DSP circuits based on stochastic computation.” 2014. Web. 18 Jul 2019.

Vancouver:

Li J. Design of some DSP circuits based on stochastic computation. [Internet] [Thesis]. NSYSU; 2014. [cited 2019 Jul 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811114-025841.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Li J. Design of some DSP circuits based on stochastic computation. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811114-025841

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

17. Lin, Yang-yi. Integration and Verification of A Multi-Function Texture Unit with Graphics Processor Units.

Degree: Master, Computer Science and Engineering, 2014, NSYSU

 With the increasing demand of graphics applications in mobile devices, how to design an efficient embedded graphics processor unit (GPU) has become a hot issue.… (more)

Subjects/Keywords: multi-function texture unit; vector graphics accelerator; 3D graphics processor; RTL; FPGA

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lin, Y. (2014). Integration and Verification of A Multi-Function Texture Unit with Graphics Processor Units. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811114-082500

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lin, Yang-yi. “Integration and Verification of A Multi-Function Texture Unit with Graphics Processor Units.” 2014. Thesis, NSYSU. Accessed July 18, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811114-082500.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lin, Yang-yi. “Integration and Verification of A Multi-Function Texture Unit with Graphics Processor Units.” 2014. Web. 18 Jul 2019.

Vancouver:

Lin Y. Integration and Verification of A Multi-Function Texture Unit with Graphics Processor Units. [Internet] [Thesis]. NSYSU; 2014. [cited 2019 Jul 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811114-082500.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lin Y. Integration and Verification of A Multi-Function Texture Unit with Graphics Processor Units. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811114-082500

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

18. Lin, Chin-li. A Method for Automatically Creating and Using Billboards to Increase the Speed of Object Rendering.

Degree: Master, Computer Science and Engineering, 2014, NSYSU

 Although the rendering speed of modern GPUs is dramatically improved, it is still not fast enough for some applications such as real time rendering and… (more)

Subjects/Keywords: GPU; hardware; billboard; impostor

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lin, C. (2014). A Method for Automatically Creating and Using Billboards to Increase the Speed of Object Rendering. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1105114-155402

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lin, Chin-li. “A Method for Automatically Creating and Using Billboards to Increase the Speed of Object Rendering.” 2014. Thesis, NSYSU. Accessed July 18, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1105114-155402.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lin, Chin-li. “A Method for Automatically Creating and Using Billboards to Increase the Speed of Object Rendering.” 2014. Web. 18 Jul 2019.

Vancouver:

Lin C. A Method for Automatically Creating and Using Billboards to Increase the Speed of Object Rendering. [Internet] [Thesis]. NSYSU; 2014. [cited 2019 Jul 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1105114-155402.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lin C. A Method for Automatically Creating and Using Billboards to Increase the Speed of Object Rendering. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1105114-155402

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

19. Tong, Ting-Chi. Bandwidth Optimized Integrated Predictive Pixel Compensator of H.264 Decoder.

Degree: Master, Computer Science and Engineering, 2008, NSYSU

 In this thesis, a high-efficient integrated pixel compensator architecture for the H.264/AVC standard has been proposed which can provide both inter and intra prediction functions… (more)

Subjects/Keywords: Predictive Pixel Compensator; Inter Prediction; Intra Prediction

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Tong, T. (2008). Bandwidth Optimized Integrated Predictive Pixel Compensator of H.264 Decoder. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0807108-200335

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Tong, Ting-Chi. “Bandwidth Optimized Integrated Predictive Pixel Compensator of H.264 Decoder.” 2008. Thesis, NSYSU. Accessed July 18, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0807108-200335.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Tong, Ting-Chi. “Bandwidth Optimized Integrated Predictive Pixel Compensator of H.264 Decoder.” 2008. Web. 18 Jul 2019.

Vancouver:

Tong T. Bandwidth Optimized Integrated Predictive Pixel Compensator of H.264 Decoder. [Internet] [Thesis]. NSYSU; 2008. [cited 2019 Jul 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0807108-200335.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tong T. Bandwidth Optimized Integrated Predictive Pixel Compensator of H.264 Decoder. [Thesis]. NSYSU; 2008. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0807108-200335

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

20. Wang, Huei-siang. Design of stochastic LDPC decoder for IEEE 802.16e standard.

Degree: Master, Computer Science and Engineering, 2014, NSYSU

 This thesis proposed an efficient design of stochastic low-density parity code ï¼LDPCï¼ decoder for IEEE 802.16e standard. Based on the proposed majority edge memory ï¼MEMï¼… (more)

Subjects/Keywords: FPGA; stochastic computing; stochastic decoding; low-density parity-checkï¼LDPCï¼codes; iterative decoding

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wang, H. (2014). Design of stochastic LDPC decoder for IEEE 802.16e standard. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0801114-142617

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wang, Huei-siang. “Design of stochastic LDPC decoder for IEEE 802.16e standard.” 2014. Thesis, NSYSU. Accessed July 18, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0801114-142617.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wang, Huei-siang. “Design of stochastic LDPC decoder for IEEE 802.16e standard.” 2014. Web. 18 Jul 2019.

Vancouver:

Wang H. Design of stochastic LDPC decoder for IEEE 802.16e standard. [Internet] [Thesis]. NSYSU; 2014. [cited 2019 Jul 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0801114-142617.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wang H. Design of stochastic LDPC decoder for IEEE 802.16e standard. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0801114-142617

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

21. Yang, Chin-lun. A Ray Tracing Acceleration Scheme for Dynamic Scenes.

Degree: Master, Computer Science and Engineering, 2016, NSYSU

 Once restricted by its enormous computational demand, ray-tracing has regained a great deal of attention nowadays due to the fast increase of systemsâ computing power.… (more)

Subjects/Keywords: Dynamic scene; BVH update; Ray-tracing; Frame coherence; BVH

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Yang, C. (2016). A Ray Tracing Acceleration Scheme for Dynamic Scenes. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0806116-194815

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yang, Chin-lun. “A Ray Tracing Acceleration Scheme for Dynamic Scenes.” 2016. Thesis, NSYSU. Accessed July 18, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0806116-194815.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yang, Chin-lun. “A Ray Tracing Acceleration Scheme for Dynamic Scenes.” 2016. Web. 18 Jul 2019.

Vancouver:

Yang C. A Ray Tracing Acceleration Scheme for Dynamic Scenes. [Internet] [Thesis]. NSYSU; 2016. [cited 2019 Jul 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0806116-194815.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yang C. A Ray Tracing Acceleration Scheme for Dynamic Scenes. [Thesis]. NSYSU; 2016. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0806116-194815

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

22. Kuo, Chia-ting. Underwater Image Dehazing and Enhancement by Compensating Light Absorption Loss and Multi-exposure Fusion.

Degree: Master, Computer Science and Engineering, 2017, NSYSU

 In recent years, the topic of single image dehazing has received a lot of attention, and many enhancing algorithms have been proposed to efficiently alleviate… (more)

Subjects/Keywords: Image Dehazing; Underwater Image; Multi-exposure Fusion; Image Enhancement; Color Cast; Dark Channel Prior

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kuo, C. (2017). Underwater Image Dehazing and Enhancement by Compensating Light Absorption Loss and Multi-exposure Fusion. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0016117-121822

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kuo, Chia-ting. “Underwater Image Dehazing and Enhancement by Compensating Light Absorption Loss and Multi-exposure Fusion.” 2017. Thesis, NSYSU. Accessed July 18, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0016117-121822.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kuo, Chia-ting. “Underwater Image Dehazing and Enhancement by Compensating Light Absorption Loss and Multi-exposure Fusion.” 2017. Web. 18 Jul 2019.

Vancouver:

Kuo C. Underwater Image Dehazing and Enhancement by Compensating Light Absorption Loss and Multi-exposure Fusion. [Internet] [Thesis]. NSYSU; 2017. [cited 2019 Jul 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0016117-121822.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kuo C. Underwater Image Dehazing and Enhancement by Compensating Light Absorption Loss and Multi-exposure Fusion. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0016117-121822

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

23. Wang, Li-chieh. System Platform Integration and Kernel Optimizations for Some Embedded Applications Based on Altera OpenCL Framework.

Degree: Master, Computer Science and Engineering, 2017, NSYSU

 In recent years, accelerating compute-intensive applications by utilizing FPGA computing resources based on OpenCL interface has received a lot of attention. This scheme cannot only… (more)

Subjects/Keywords: Altera FPGA; convolutional neural network; HOG; CNN; human detection; OpenCL

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wang, L. (2017). System Platform Integration and Kernel Optimizations for Some Embedded Applications Based on Altera OpenCL Framework. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0016117-135946

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wang, Li-chieh. “System Platform Integration and Kernel Optimizations for Some Embedded Applications Based on Altera OpenCL Framework.” 2017. Thesis, NSYSU. Accessed July 18, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0016117-135946.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wang, Li-chieh. “System Platform Integration and Kernel Optimizations for Some Embedded Applications Based on Altera OpenCL Framework.” 2017. Web. 18 Jul 2019.

Vancouver:

Wang L. System Platform Integration and Kernel Optimizations for Some Embedded Applications Based on Altera OpenCL Framework. [Internet] [Thesis]. NSYSU; 2017. [cited 2019 Jul 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0016117-135946.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wang L. System Platform Integration and Kernel Optimizations for Some Embedded Applications Based on Altera OpenCL Framework. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0016117-135946

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

24. Chen, Zhi-wei. Design and Implementation of Highly-parallel Efficient BVH Tree Builder Architecture for Ray Tracing.

Degree: Master, Computer Science and Engineering, 2017, NSYSU

 Bounding volume hierarchy (BVH) tree construction is a very important issue for real-time ray-tracing rendering of dynamic scenes. How to accelerate this process by either… (more)

Subjects/Keywords: computer graphics; BVH tree construction; ray-tracing hardware; ray-tracing; BVH

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chen, Z. (2017). Design and Implementation of Highly-parallel Efficient BVH Tree Builder Architecture for Ray Tracing. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0016117-135254

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chen, Zhi-wei. “Design and Implementation of Highly-parallel Efficient BVH Tree Builder Architecture for Ray Tracing.” 2017. Thesis, NSYSU. Accessed July 18, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0016117-135254.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chen, Zhi-wei. “Design and Implementation of Highly-parallel Efficient BVH Tree Builder Architecture for Ray Tracing.” 2017. Web. 18 Jul 2019.

Vancouver:

Chen Z. Design and Implementation of Highly-parallel Efficient BVH Tree Builder Architecture for Ray Tracing. [Internet] [Thesis]. NSYSU; 2017. [cited 2019 Jul 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0016117-135254.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen Z. Design and Implementation of Highly-parallel Efficient BVH Tree Builder Architecture for Ray Tracing. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0016117-135254

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

25. Liu, Min-Hua. An Optimized Semi-parallel Architecture Design of Successive-cancellation Polar Decoder.

Degree: Master, Computer Science and Engineering, 2017, NSYSU

 This thesis proposes a high-efï¬cient VLSI decoder architecture for polar code which is capable of achieving channel capacity and ï¬exibly realizing various code rates. The… (more)

Subjects/Keywords: Polar code; FPGA; Partial sum generator; Recursion decoding; Successive-cancellation algorithm

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Liu, M. (2017). An Optimized Semi-parallel Architecture Design of Successive-cancellation Polar Decoder. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0016117-154531

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Liu, Min-Hua. “An Optimized Semi-parallel Architecture Design of Successive-cancellation Polar Decoder.” 2017. Thesis, NSYSU. Accessed July 18, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0016117-154531.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Liu, Min-Hua. “An Optimized Semi-parallel Architecture Design of Successive-cancellation Polar Decoder.” 2017. Web. 18 Jul 2019.

Vancouver:

Liu M. An Optimized Semi-parallel Architecture Design of Successive-cancellation Polar Decoder. [Internet] [Thesis]. NSYSU; 2017. [cited 2019 Jul 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0016117-154531.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Liu M. An Optimized Semi-parallel Architecture Design of Successive-cancellation Polar Decoder. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0016117-154531

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

26. Tsai, Ping-Che. A high-resolution vector graphics processor with Efficiently integrated hierarchical buffer architecture.

Degree: Master, Computer Science and Engineering, 2017, NSYSU

 This thesis proposes a high-performance and high-resolution vector graphics processor by extending a previous design. The thesis not only modifies the old design to increase… (more)

Subjects/Keywords: 2D graphics; scan-line buffer; vector graphics; stroke; tessellation

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Tsai, P. (2017). A high-resolution vector graphics processor with Efficiently integrated hierarchical buffer architecture. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0113117-154119

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Tsai, Ping-Che. “A high-resolution vector graphics processor with Efficiently integrated hierarchical buffer architecture.” 2017. Thesis, NSYSU. Accessed July 18, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0113117-154119.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Tsai, Ping-Che. “A high-resolution vector graphics processor with Efficiently integrated hierarchical buffer architecture.” 2017. Web. 18 Jul 2019.

Vancouver:

Tsai P. A high-resolution vector graphics processor with Efficiently integrated hierarchical buffer architecture. [Internet] [Thesis]. NSYSU; 2017. [cited 2019 Jul 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0113117-154119.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tsai P. A high-resolution vector graphics processor with Efficiently integrated hierarchical buffer architecture. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0113117-154119

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

27. Chen, Jyun-Nan. GPU Compilation and Simulation for a Specialized Embedded System GPU.

Degree: Master, Computer Science and Engineering, 2015, NSYSU

 This thesis presents a compiler for a GLSL programs targeted to a novel Graphics Processor Unit (GPU)developed at NSYSU. The NSYSU GPU project has developed… (more)

Subjects/Keywords: GPU; NSYSUâs GPU project; OpenGLES 2.0; LLVM; shader compiler

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chen, J. (2015). GPU Compilation and Simulation for a Specialized Embedded System GPU. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0719115-133931

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chen, Jyun-Nan. “GPU Compilation and Simulation for a Specialized Embedded System GPU.” 2015. Thesis, NSYSU. Accessed July 18, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0719115-133931.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chen, Jyun-Nan. “GPU Compilation and Simulation for a Specialized Embedded System GPU.” 2015. Web. 18 Jul 2019.

Vancouver:

Chen J. GPU Compilation and Simulation for a Specialized Embedded System GPU. [Internet] [Thesis]. NSYSU; 2015. [cited 2019 Jul 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0719115-133931.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen J. GPU Compilation and Simulation for a Specialized Embedded System GPU. [Thesis]. NSYSU; 2015. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0719115-133931

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

28. Wu, Chun-Lin. Design of ray tracing circuit with hierarchical traversal.

Degree: Master, Computer Science and Engineering, 2015, NSYSU

 Fast rendering of computer graphics has gradually become an essential requirement for many embedded electronic devices. Ray-tracing can render more realistic graphics than the conventional… (more)

Subjects/Keywords: BVH; Frustum culling; Hierarchical traversal; Ray-tracing; Packet ray

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wu, C. (2015). Design of ray tracing circuit with hierarchical traversal. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808115-120610

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wu, Chun-Lin. “Design of ray tracing circuit with hierarchical traversal.” 2015. Thesis, NSYSU. Accessed July 18, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808115-120610.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wu, Chun-Lin. “Design of ray tracing circuit with hierarchical traversal.” 2015. Web. 18 Jul 2019.

Vancouver:

Wu C. Design of ray tracing circuit with hierarchical traversal. [Internet] [Thesis]. NSYSU; 2015. [cited 2019 Jul 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808115-120610.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wu C. Design of ray tracing circuit with hierarchical traversal. [Thesis]. NSYSU; 2015. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808115-120610

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

29. Hsu, Chien-te. Design of parallel computing processor based on OpenCL architecture.

Degree: Master, Computer Science and Engineering, 2015, NSYSU

 In addition to pursuing more shader cores for better rendering performance, another important trend in the evolution of modern graphic processing units (GPU) is to… (more)

Subjects/Keywords: Scalar Processor; Multi-core; GPU; General Computing; OpenCL

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APA (6th Edition):

Hsu, C. (2015). Design of parallel computing processor based on OpenCL architecture. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808115-113525

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hsu, Chien-te. “Design of parallel computing processor based on OpenCL architecture.” 2015. Thesis, NSYSU. Accessed July 18, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808115-113525.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hsu, Chien-te. “Design of parallel computing processor based on OpenCL architecture.” 2015. Web. 18 Jul 2019.

Vancouver:

Hsu C. Design of parallel computing processor based on OpenCL architecture. [Internet] [Thesis]. NSYSU; 2015. [cited 2019 Jul 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808115-113525.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hsu C. Design of parallel computing processor based on OpenCL architecture. [Thesis]. NSYSU; 2015. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808115-113525

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

30. Wang, Ching-Hui. Lane, Vehicle, and Human Detections in Intelligent Driver Assistance Systems.

Degree: Master, Computer Science and Engineering, 2015, NSYSU

 In this thesis, we present an integrated driver assistance system with lane detection, vehicle detection, and human detection based on camera image sequences. After image… (more)

Subjects/Keywords: HOG; Pedestrian Detection; Human Detection; Driver Assistance Systems; Lane Detection; Vehicle Detection

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wang, C. (2015). Lane, Vehicle, and Human Detections in Intelligent Driver Assistance Systems. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808115-222352

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wang, Ching-Hui. “Lane, Vehicle, and Human Detections in Intelligent Driver Assistance Systems.” 2015. Thesis, NSYSU. Accessed July 18, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808115-222352.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wang, Ching-Hui. “Lane, Vehicle, and Human Detections in Intelligent Driver Assistance Systems.” 2015. Web. 18 Jul 2019.

Vancouver:

Wang C. Lane, Vehicle, and Human Detections in Intelligent Driver Assistance Systems. [Internet] [Thesis]. NSYSU; 2015. [cited 2019 Jul 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808115-222352.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wang C. Lane, Vehicle, and Human Detections in Intelligent Driver Assistance Systems. [Thesis]. NSYSU; 2015. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808115-222352

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

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