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You searched for +publisher:"NSYSU" +contributor:("Tso-Bing Juang"). Showing records 1 – 16 of 16 total matches.

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NSYSU

1. Lee, Cheng-Han. Design, Analysis and Applications of Hybrid CORDIC Processor Architectures.

Degree: Master, Computer Science and Engineering, 2010, NSYSU

 In this thesis, we propose different CORDIC architectures which solve the problems of long-latency in traditional pipeline CORDIC and the large-area cost in table-based CORDIC.… (more)

Subjects/Keywords: Arithmetic Function Units; CORDIC; Taylor-series expansion

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lee, C. (2010). Design, Analysis and Applications of Hybrid CORDIC Processor Architectures. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0831110-160513

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lee, Cheng-Han. “Design, Analysis and Applications of Hybrid CORDIC Processor Architectures.” 2010. Thesis, NSYSU. Accessed September 29, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0831110-160513.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lee, Cheng-Han. “Design, Analysis and Applications of Hybrid CORDIC Processor Architectures.” 2010. Web. 29 Sep 2020.

Vancouver:

Lee C. Design, Analysis and Applications of Hybrid CORDIC Processor Architectures. [Internet] [Thesis]. NSYSU; 2010. [cited 2020 Sep 29]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0831110-160513.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lee C. Design, Analysis and Applications of Hybrid CORDIC Processor Architectures. [Thesis]. NSYSU; 2010. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0831110-160513

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

2. Tsai, Cheng-Hsuan. Design of Hybrid CMOS/Pass-Transistor-Logic Standard Cell Library.

Degree: Master, Computer Science and Engineering, 2010, NSYSU

 The mainstream of current VLSI design and logic synthesis is based on traditional CMOS logic circuits. However, various new logic circuit design styles based on… (more)

Subjects/Keywords: CMOS logic; Logic Synthesizer; Standard Cell Library; ASIC Design Flow; Pass-Transition-Logic(PTL)

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APA (6th Edition):

Tsai, C. (2010). Design of Hybrid CMOS/Pass-Transistor-Logic Standard Cell Library. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0830110-152704

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Tsai, Cheng-Hsuan. “Design of Hybrid CMOS/Pass-Transistor-Logic Standard Cell Library.” 2010. Thesis, NSYSU. Accessed September 29, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0830110-152704.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Tsai, Cheng-Hsuan. “Design of Hybrid CMOS/Pass-Transistor-Logic Standard Cell Library.” 2010. Web. 29 Sep 2020.

Vancouver:

Tsai C. Design of Hybrid CMOS/Pass-Transistor-Logic Standard Cell Library. [Internet] [Thesis]. NSYSU; 2010. [cited 2020 Sep 29]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0830110-152704.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tsai C. Design of Hybrid CMOS/Pass-Transistor-Logic Standard Cell Library. [Thesis]. NSYSU; 2010. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0830110-152704

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

3. Chiu, Chan-Feng. Design, Implementation, and Verification of a Programmable Low-Cost Vertex Shader Based on Logarithmic Number System.

Degree: Master, Computer Science and Engineering, 2010, NSYSU

 This thesis focuses on efficient design of a vertex shader for per-vertex operations such as Transformation and Lighting in the OpenGL ES 2.0 graphics pipeline.… (more)

Subjects/Keywords: 3D Graph; Logarithmic Number System; Vertex Shader

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chiu, C. (2010). Design, Implementation, and Verification of a Programmable Low-Cost Vertex Shader Based on Logarithmic Number System. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0830110-170101

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chiu, Chan-Feng. “Design, Implementation, and Verification of a Programmable Low-Cost Vertex Shader Based on Logarithmic Number System.” 2010. Thesis, NSYSU. Accessed September 29, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0830110-170101.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chiu, Chan-Feng. “Design, Implementation, and Verification of a Programmable Low-Cost Vertex Shader Based on Logarithmic Number System.” 2010. Web. 29 Sep 2020.

Vancouver:

Chiu C. Design, Implementation, and Verification of a Programmable Low-Cost Vertex Shader Based on Logarithmic Number System. [Internet] [Thesis]. NSYSU; 2010. [cited 2020 Sep 29]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0830110-170101.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chiu C. Design, Implementation, and Verification of a Programmable Low-Cost Vertex Shader Based on Logarithmic Number System. [Thesis]. NSYSU; 2010. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0830110-170101

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

4. Chen, Li-Yao. Software and Hardware Integration of a Programmable Floating- and Fixed-Point Vertex Shader.

Degree: Master, Computer Science and Engineering, 2010, NSYSU

 OpenGL ES 2.0 programmable 3D graphics pipeline is the current new standard for embedded graphics processor designs. The programmable vertex shader replaces the geometry operations… (more)

Subjects/Keywords: Integration; SOC; Programmable; SIMD; Vertex Shader

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APA (6th Edition):

Chen, L. (2010). Software and Hardware Integration of a Programmable Floating- and Fixed-Point Vertex Shader. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902110-213943

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chen, Li-Yao. “Software and Hardware Integration of a Programmable Floating- and Fixed-Point Vertex Shader.” 2010. Thesis, NSYSU. Accessed September 29, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902110-213943.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chen, Li-Yao. “Software and Hardware Integration of a Programmable Floating- and Fixed-Point Vertex Shader.” 2010. Web. 29 Sep 2020.

Vancouver:

Chen L. Software and Hardware Integration of a Programmable Floating- and Fixed-Point Vertex Shader. [Internet] [Thesis]. NSYSU; 2010. [cited 2020 Sep 29]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902110-213943.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen L. Software and Hardware Integration of a Programmable Floating- and Fixed-Point Vertex Shader. [Thesis]. NSYSU; 2010. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902110-213943

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

5. Zhang Jian, Jun-Hong. Design of Low Cost Finite-Impulse Response (FIR) Filters Using Multiple Constant Truncated Multipliers.

Degree: Master, Computer Science and Engineering, 2012, NSYSU

 Finite impulse response (FIR) digital filters are frequently used in many digital signal processing and communication applications, such as IS-95 CDMA, Digital Mobile Phone Systems… (more)

Subjects/Keywords: Common Sub-expression Elimination (CSE); Booth recoding; error analysis; truncated multiplier; FIR filter; multiple constant multiplication (MCM); VLSI design; Canonical Signed Digit (CSD) encoding

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zhang Jian, J. (2012). Design of Low Cost Finite-Impulse Response (FIR) Filters Using Multiple Constant Truncated Multipliers. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0910112-142752

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Zhang Jian, Jun-Hong. “Design of Low Cost Finite-Impulse Response (FIR) Filters Using Multiple Constant Truncated Multipliers.” 2012. Thesis, NSYSU. Accessed September 29, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0910112-142752.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Zhang Jian, Jun-Hong. “Design of Low Cost Finite-Impulse Response (FIR) Filters Using Multiple Constant Truncated Multipliers.” 2012. Web. 29 Sep 2020.

Vancouver:

Zhang Jian J. Design of Low Cost Finite-Impulse Response (FIR) Filters Using Multiple Constant Truncated Multipliers. [Internet] [Thesis]. NSYSU; 2012. [cited 2020 Sep 29]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0910112-142752.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zhang Jian J. Design of Low Cost Finite-Impulse Response (FIR) Filters Using Multiple Constant Truncated Multipliers. [Thesis]. NSYSU; 2012. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0910112-142752

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

6. Wang, Wen-Ling. Hardware Design for Disparity Estimation Using Dynamic Programming.

Degree: Master, Computer Science and Engineering, 2012, NSYSU

 Recently, stereo vision has been widely used in many applications, and depth map is important information in stereo vision. In general, depth map can be… (more)

Subjects/Keywords: depth map; disparity; stereo vision; dynamic programming; stereo correspondence; stereo matching

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wang, W. (2012). Hardware Design for Disparity Estimation Using Dynamic Programming. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0911112-120201

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wang, Wen-Ling. “Hardware Design for Disparity Estimation Using Dynamic Programming.” 2012. Thesis, NSYSU. Accessed September 29, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0911112-120201.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wang, Wen-Ling. “Hardware Design for Disparity Estimation Using Dynamic Programming.” 2012. Web. 29 Sep 2020.

Vancouver:

Wang W. Hardware Design for Disparity Estimation Using Dynamic Programming. [Internet] [Thesis]. NSYSU; 2012. [cited 2020 Sep 29]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0911112-120201.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wang W. Hardware Design for Disparity Estimation Using Dynamic Programming. [Thesis]. NSYSU; 2012. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0911112-120201

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

7. Lin, Shin-hung. Improved Bit-Level Truncation with Joint Error Analysis for Table-Based Function Evaluation.

Degree: Master, Computer Science and Engineering, 2012, NSYSU

 Function evaluation is often used in many science and engineering applications. In order to reduce the computation time, different hardware implementations have been proposed to… (more)

Subjects/Keywords: non-uniform segmentation; piecewise polynomial approximation; error analysis; table-based function evaluation; truncated multipliers; uniform segmentation

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lin, S. (2012). Improved Bit-Level Truncation with Joint Error Analysis for Table-Based Function Evaluation. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0912112-092221

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lin, Shin-hung. “Improved Bit-Level Truncation with Joint Error Analysis for Table-Based Function Evaluation.” 2012. Thesis, NSYSU. Accessed September 29, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0912112-092221.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lin, Shin-hung. “Improved Bit-Level Truncation with Joint Error Analysis for Table-Based Function Evaluation.” 2012. Web. 29 Sep 2020.

Vancouver:

Lin S. Improved Bit-Level Truncation with Joint Error Analysis for Table-Based Function Evaluation. [Internet] [Thesis]. NSYSU; 2012. [cited 2020 Sep 29]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0912112-092221.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lin S. Improved Bit-Level Truncation with Joint Error Analysis for Table-Based Function Evaluation. [Thesis]. NSYSU; 2012. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0912112-092221

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

8. Hsu, Wei-Cheng. Design of a CORDIC Function Generator Using Table-Driven Function Evaluation with Bit-Level Truncation.

Degree: Master, Computer Science and Engineering, 2012, NSYSU

 Functional evaluation is one of key arithmetic operations in many applications including 3D graphics and stereo. Among various designs of hardware-based function evaluation methods, piecewise… (more)

Subjects/Keywords: arithmetic function units.; CORDIC; uniform segmentation; polynomial approximation; truncated multipliers; error analysis; function evaluation

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hsu, W. (2012). Design of a CORDIC Function Generator Using Table-Driven Function Evaluation with Bit-Level Truncation. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0910112-150743

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hsu, Wei-Cheng. “Design of a CORDIC Function Generator Using Table-Driven Function Evaluation with Bit-Level Truncation.” 2012. Thesis, NSYSU. Accessed September 29, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0910112-150743.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hsu, Wei-Cheng. “Design of a CORDIC Function Generator Using Table-Driven Function Evaluation with Bit-Level Truncation.” 2012. Web. 29 Sep 2020.

Vancouver:

Hsu W. Design of a CORDIC Function Generator Using Table-Driven Function Evaluation with Bit-Level Truncation. [Internet] [Thesis]. NSYSU; 2012. [cited 2020 Sep 29]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0910112-150743.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hsu W. Design of a CORDIC Function Generator Using Table-Driven Function Evaluation with Bit-Level Truncation. [Thesis]. NSYSU; 2012. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0910112-150743

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

9. Yeh, Kuan-Fu. Software and Hardware Designs of a Vehicle Detection System Based on Single Camera Image Sequence.

Degree: Master, Computer Science and Engineering, 2012, NSYSU

 In this thesis, we present a vehicle detection and tracking system based on image processing and pattern recognition of single camera image sequences. Both software… (more)

Subjects/Keywords: Machine Learning; Vehicle Detection; Pattern Recognition; Image Processing; Driving Assistance System; Support Vector Machine (SVM)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Yeh, K. (2012). Software and Hardware Designs of a Vehicle Detection System Based on Single Camera Image Sequence. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0910112-140351

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yeh, Kuan-Fu. “Software and Hardware Designs of a Vehicle Detection System Based on Single Camera Image Sequence.” 2012. Thesis, NSYSU. Accessed September 29, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0910112-140351.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yeh, Kuan-Fu. “Software and Hardware Designs of a Vehicle Detection System Based on Single Camera Image Sequence.” 2012. Web. 29 Sep 2020.

Vancouver:

Yeh K. Software and Hardware Designs of a Vehicle Detection System Based on Single Camera Image Sequence. [Internet] [Thesis]. NSYSU; 2012. [cited 2020 Sep 29]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0910112-140351.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yeh K. Software and Hardware Designs of a Vehicle Detection System Based on Single Camera Image Sequence. [Thesis]. NSYSU; 2012. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0910112-140351

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

10. Li, Shang-Yu. Design and Implementation of a Vision Processor Based on the OpenVX Specification.

Degree: Master, Computer Science and Engineering, 2016, NSYSU

 Embedded computer vision applications emphasizes fast and real-time processing speed with low power consumption. To face these challenge, we need more suitable hardware accelerator for… (more)

Subjects/Keywords: Computer vision applications; OpenVX; SIMD; Vision Processor

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Li, S. (2016). Design and Implementation of a Vision Processor Based on the OpenVX Specification. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0731116-151556

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Li, Shang-Yu. “Design and Implementation of a Vision Processor Based on the OpenVX Specification.” 2016. Thesis, NSYSU. Accessed September 29, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0731116-151556.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Li, Shang-Yu. “Design and Implementation of a Vision Processor Based on the OpenVX Specification.” 2016. Web. 29 Sep 2020.

Vancouver:

Li S. Design and Implementation of a Vision Processor Based on the OpenVX Specification. [Internet] [Thesis]. NSYSU; 2016. [cited 2020 Sep 29]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0731116-151556.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Li S. Design and Implementation of a Vision Processor Based on the OpenVX Specification. [Thesis]. NSYSU; 2016. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0731116-151556

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

11. Yang, Jyun-sheng. Design and Implementation of Multi-Port Shared Cache in Multi-core Systems.

Degree: Master, Computer Science and Engineering, 2016, NSYSU

 Multi-port shared cache memory plays an important role in multi-core systems. Although single/dual-port SRAM can be realized using commercial standard cell library, multi-port shared cache… (more)

Subjects/Keywords: multi-port shared cache memory; multi-port shared cache memory generator; multi-core system

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Yang, J. (2016). Design and Implementation of Multi-Port Shared Cache in Multi-core Systems. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0731116-150758

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yang, Jyun-sheng. “Design and Implementation of Multi-Port Shared Cache in Multi-core Systems.” 2016. Thesis, NSYSU. Accessed September 29, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0731116-150758.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yang, Jyun-sheng. “Design and Implementation of Multi-Port Shared Cache in Multi-core Systems.” 2016. Web. 29 Sep 2020.

Vancouver:

Yang J. Design and Implementation of Multi-Port Shared Cache in Multi-core Systems. [Internet] [Thesis]. NSYSU; 2016. [cited 2020 Sep 29]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0731116-150758.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yang J. Design and Implementation of Multi-Port Shared Cache in Multi-core Systems. [Thesis]. NSYSU; 2016. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0731116-150758

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

12. Chen, Yi-Hau. Hierarchical Multipartite Function Evaluation.

Degree: Master, Computer Science and Engineering, 2016, NSYSU

 Function evaluation is an important arithmetic computation in many signal processing applications, such as special function units in modern graphics processing units (GPUs). Hardware implementations… (more)

Subjects/Keywords: bipartite table methods; lossless compression; arithmetic units; table-based function evaluation; VLSI; multipartite table methods

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chen, Y. (2016). Hierarchical Multipartite Function Evaluation. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0801116-135632

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chen, Yi-Hau. “Hierarchical Multipartite Function Evaluation.” 2016. Thesis, NSYSU. Accessed September 29, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0801116-135632.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chen, Yi-Hau. “Hierarchical Multipartite Function Evaluation.” 2016. Web. 29 Sep 2020.

Vancouver:

Chen Y. Hierarchical Multipartite Function Evaluation. [Internet] [Thesis]. NSYSU; 2016. [cited 2020 Sep 29]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0801116-135632.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen Y. Hierarchical Multipartite Function Evaluation. [Thesis]. NSYSU; 2016. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0801116-135632

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

13. Tseng, I-Ping. Design of the Tail-biting Convolution Code Decoder with Error Detection Ability.

Degree: Master, Computer Science and Engineering, 2012, NSYSU

 In wireless communication system, convolution code has been one of the most popular error-correcting code. To prevent from the interference of noise during transmission, the… (more)

Subjects/Keywords: Tail-biting convolution code; power consumption; Viterbi decoder; code rate; wireless communication

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Tseng, I. (2012). Design of the Tail-biting Convolution Code Decoder with Error Detection Ability. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725112-101332

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Tseng, I-Ping. “Design of the Tail-biting Convolution Code Decoder with Error Detection Ability.” 2012. Thesis, NSYSU. Accessed September 29, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725112-101332.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Tseng, I-Ping. “Design of the Tail-biting Convolution Code Decoder with Error Detection Ability.” 2012. Web. 29 Sep 2020.

Vancouver:

Tseng I. Design of the Tail-biting Convolution Code Decoder with Error Detection Ability. [Internet] [Thesis]. NSYSU; 2012. [cited 2020 Sep 29]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725112-101332.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tseng I. Design of the Tail-biting Convolution Code Decoder with Error Detection Ability. [Thesis]. NSYSU; 2012. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725112-101332

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

14. Su, Chuan-Shen. Energy-Efficient Scalable Serial-Parallel Multiplication Architecture for Elliptic Curve Cryptosystem.

Degree: Master, Computer Science and Engineering, 2012, NSYSU

 In asymmetric cryptosystems, an important advantage of Elliptic Curve Cryptosystem (ECC) is the shorter key lengths than other cryptosystems. It can provide a level of… (more)

Subjects/Keywords: Shift Registers; Serial/Parallel Multiplier; Montgomery Scalar Multiplication Algorithm; Frequency Divider Circuit; Elliptic Curve Cryptosystem

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Su, C. (2012). Energy-Efficient Scalable Serial-Parallel Multiplication Architecture for Elliptic Curve Cryptosystem. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725112-145006

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Su, Chuan-Shen. “Energy-Efficient Scalable Serial-Parallel Multiplication Architecture for Elliptic Curve Cryptosystem.” 2012. Thesis, NSYSU. Accessed September 29, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725112-145006.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Su, Chuan-Shen. “Energy-Efficient Scalable Serial-Parallel Multiplication Architecture for Elliptic Curve Cryptosystem.” 2012. Web. 29 Sep 2020.

Vancouver:

Su C. Energy-Efficient Scalable Serial-Parallel Multiplication Architecture for Elliptic Curve Cryptosystem. [Internet] [Thesis]. NSYSU; 2012. [cited 2020 Sep 29]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725112-145006.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Su C. Energy-Efficient Scalable Serial-Parallel Multiplication Architecture for Elliptic Curve Cryptosystem. [Thesis]. NSYSU; 2012. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725112-145006

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

15. Tsai, Ming-Yu. An Efficient Hybrid CMOS/PTL (Pass-Transistor-Logic) Synthesizer and Its Applications to the Design of Arithmetic Units and 3D Graphics Processors.

Degree: PhD, Computer Science and Engineering, 2009, NSYSU

 The mainstream of current VLSI design and logic synthesis is based on traditional CMOS logic circuits. However, in the past two decades, various new logic… (more)

Subjects/Keywords: 3D Graphics Processors; Arithmetic Units; Standard Cell Library; ASIC Cell-Based Design Flow; Logic Synthesizer; Pass-Transistor-Logic (PTL); CMOS logic

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Tsai, M. (2009). An Efficient Hybrid CMOS/PTL (Pass-Transistor-Logic) Synthesizer and Its Applications to the Design of Arithmetic Units and 3D Graphics Processors. (Doctoral Dissertation). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1020109-194529

Chicago Manual of Style (16th Edition):

Tsai, Ming-Yu. “An Efficient Hybrid CMOS/PTL (Pass-Transistor-Logic) Synthesizer and Its Applications to the Design of Arithmetic Units and 3D Graphics Processors.” 2009. Doctoral Dissertation, NSYSU. Accessed September 29, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1020109-194529.

MLA Handbook (7th Edition):

Tsai, Ming-Yu. “An Efficient Hybrid CMOS/PTL (Pass-Transistor-Logic) Synthesizer and Its Applications to the Design of Arithmetic Units and 3D Graphics Processors.” 2009. Web. 29 Sep 2020.

Vancouver:

Tsai M. An Efficient Hybrid CMOS/PTL (Pass-Transistor-Logic) Synthesizer and Its Applications to the Design of Arithmetic Units and 3D Graphics Processors. [Internet] [Doctoral dissertation]. NSYSU; 2009. [cited 2020 Sep 29]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1020109-194529.

Council of Science Editors:

Tsai M. An Efficient Hybrid CMOS/PTL (Pass-Transistor-Logic) Synthesizer and Its Applications to the Design of Arithmetic Units and 3D Graphics Processors. [Doctoral Dissertation]. NSYSU; 2009. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1020109-194529


NSYSU

16. Wen, Chia-Sheng. Table Based Design for Function Evaluation and Error Correcting Codes.

Degree: PhD, Computer Science and Engineering, 2012, NSYSU

 Lookup-table (LUT)-based method is a common approach used in all kinds of research topics. In this dissertation, we present several new designs for table-based function… (more)

Subjects/Keywords: function evaluation; piecewise polynomial approximation; Reed-Solomon code; table-based methods; error correcting coding

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wen, C. (2012). Table Based Design for Function Evaluation and Error Correcting Codes. (Doctoral Dissertation). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0723112-012802

Chicago Manual of Style (16th Edition):

Wen, Chia-Sheng. “Table Based Design for Function Evaluation and Error Correcting Codes.” 2012. Doctoral Dissertation, NSYSU. Accessed September 29, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0723112-012802.

MLA Handbook (7th Edition):

Wen, Chia-Sheng. “Table Based Design for Function Evaluation and Error Correcting Codes.” 2012. Web. 29 Sep 2020.

Vancouver:

Wen C. Table Based Design for Function Evaluation and Error Correcting Codes. [Internet] [Doctoral dissertation]. NSYSU; 2012. [cited 2020 Sep 29]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0723112-012802.

Council of Science Editors:

Wen C. Table Based Design for Function Evaluation and Error Correcting Codes. [Doctoral Dissertation]. NSYSU; 2012. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0723112-012802

.