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You searched for +publisher:"NSYSU" +contributor:("Tong-Yu Hsieh"). Showing records 1 – 30 of 98 total matches.

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NSYSU

1. Lin, Ding-Zhi. Integrated Circuit Designs for a Multi-signal Biomedical Signal Recording Chip.

Degree: Master, Electrical Engineering, 2018, NSYSU

 With the advance of mobile healthcare and the Internet-of-things increasing numbers of applications incorporate low-power miniature sensing devices for various types of input signal. In… (more)

Subjects/Keywords: biomedical chip; adjustable gain; switched capacitor amplifier; integrated circuit; temperature monitoring circuit

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lin, D. (2018). Integrated Circuit Designs for a Multi-signal Biomedical Signal Recording Chip. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0029118-150639

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lin, Ding-Zhi. “Integrated Circuit Designs for a Multi-signal Biomedical Signal Recording Chip.” 2018. Thesis, NSYSU. Accessed February 23, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0029118-150639.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lin, Ding-Zhi. “Integrated Circuit Designs for a Multi-signal Biomedical Signal Recording Chip.” 2018. Web. 23 Feb 2020.

Vancouver:

Lin D. Integrated Circuit Designs for a Multi-signal Biomedical Signal Recording Chip. [Internet] [Thesis]. NSYSU; 2018. [cited 2020 Feb 23]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0029118-150639.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lin D. Integrated Circuit Designs for a Multi-signal Biomedical Signal Recording Chip. [Thesis]. NSYSU; 2018. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0029118-150639

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

2. Lin, Sheng-En. Design and Evaluation of an Improved 10-bit Integrating CMOS ADC.

Degree: Master, Electrical Engineering, 2017, NSYSU

 The analog-to-digital converter (ADC) is an essential component in modern mixed-signal system applications. This thesis presents the design and evaluation of a single-slope integrating ADC… (more)

Subjects/Keywords: single-slope integrating ADC; voltage-to-time converter; low power circuit design; application-specific integrated circuit (ASIC); biological-signal recording system

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lin, S. (2017). Design and Evaluation of an Improved 10-bit Integrating CMOS ADC. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0113117-143835

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lin, Sheng-En. “Design and Evaluation of an Improved 10-bit Integrating CMOS ADC.” 2017. Thesis, NSYSU. Accessed February 23, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0113117-143835.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lin, Sheng-En. “Design and Evaluation of an Improved 10-bit Integrating CMOS ADC.” 2017. Web. 23 Feb 2020.

Vancouver:

Lin S. Design and Evaluation of an Improved 10-bit Integrating CMOS ADC. [Internet] [Thesis]. NSYSU; 2017. [cited 2020 Feb 23]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0113117-143835.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lin S. Design and Evaluation of an Improved 10-bit Integrating CMOS ADC. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0113117-143835

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

3. Chao, Chih-Hsun. The performance evaluation of MPI program running at Kernel Distributed Computing Management.

Degree: Master, Electrical Engineering, 2017, NSYSU

 In order to meet the operational requirements of cloud computing, how to improve the performance of parallel applications on a cloud platform is a hot… (more)

Subjects/Keywords: Cloud Computing; parallel program; Kernel Driver; MPI; Task mapping; Communication-Intensive

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chao, C. (2017). The performance evaluation of MPI program running at Kernel Distributed Computing Management. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0724117-182652

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chao, Chih-Hsun. “The performance evaluation of MPI program running at Kernel Distributed Computing Management.” 2017. Thesis, NSYSU. Accessed February 23, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0724117-182652.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chao, Chih-Hsun. “The performance evaluation of MPI program running at Kernel Distributed Computing Management.” 2017. Web. 23 Feb 2020.

Vancouver:

Chao C. The performance evaluation of MPI program running at Kernel Distributed Computing Management. [Internet] [Thesis]. NSYSU; 2017. [cited 2020 Feb 23]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0724117-182652.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chao C. The performance evaluation of MPI program running at Kernel Distributed Computing Management. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0724117-182652

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

4. Chao, Shu-jung. Improving ILP with Semantic-Based Loop Unrolling Mechanism in the Hyperscalar Architecture.

Degree: Master, Electrical Engineering, 2017, NSYSU

 In an age of multi-core computing architecture, exploiting ILP of loops can enhance the computing efficiency in the multi-core computing architecture since loop structure is… (more)

Subjects/Keywords: ILP of loop; hyperscalar; semantic of loop; loop unrolling

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chao, S. (2017). Improving ILP with Semantic-Based Loop Unrolling Mechanism in the Hyperscalar Architecture. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0724117-184404

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chao, Shu-jung. “Improving ILP with Semantic-Based Loop Unrolling Mechanism in the Hyperscalar Architecture.” 2017. Thesis, NSYSU. Accessed February 23, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0724117-184404.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chao, Shu-jung. “Improving ILP with Semantic-Based Loop Unrolling Mechanism in the Hyperscalar Architecture.” 2017. Web. 23 Feb 2020.

Vancouver:

Chao S. Improving ILP with Semantic-Based Loop Unrolling Mechanism in the Hyperscalar Architecture. [Internet] [Thesis]. NSYSU; 2017. [cited 2020 Feb 23]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0724117-184404.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chao S. Improving ILP with Semantic-Based Loop Unrolling Mechanism in the Hyperscalar Architecture. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0724117-184404

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

5. Wu, Mei-Jung. An Efficient Method to Assess Audio Quality and Its Hardware Implementation.

Degree: Master, Electrical Engineering, 2017, NSYSU

 To facilitate storage and transmission, lossy compression is usually used for audio signals despite the possible quality degradation. On the other hand, scaling down of… (more)

Subjects/Keywords: audio processing circuits; audio acceptability evaluation; error-tolerance; PEAQ; erroneous audio

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wu, M. (2017). An Efficient Method to Assess Audio Quality and Its Hardware Implementation. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0801117-101956

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wu, Mei-Jung. “An Efficient Method to Assess Audio Quality and Its Hardware Implementation.” 2017. Thesis, NSYSU. Accessed February 23, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0801117-101956.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wu, Mei-Jung. “An Efficient Method to Assess Audio Quality and Its Hardware Implementation.” 2017. Web. 23 Feb 2020.

Vancouver:

Wu M. An Efficient Method to Assess Audio Quality and Its Hardware Implementation. [Internet] [Thesis]. NSYSU; 2017. [cited 2020 Feb 23]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0801117-101956.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wu M. An Efficient Method to Assess Audio Quality and Its Hardware Implementation. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0801117-101956

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

6. Chung, Chen-Chia. Error-Tolerability Enhancement for Videos by Adaptive I-Frame Insertion.

Degree: Master, Electrical Engineering, 2017, NSYSU

 With the advances in semiconductor technology, Internet of Things (IoT) devices and applications have been developing rapidly. Among these devices and applications, surveillance systems play… (more)

Subjects/Keywords: quality improvement; video quality assessment; error-tolerability; erroneous video; video repair

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chung, C. (2017). Error-Tolerability Enhancement for Videos by Adaptive I-Frame Insertion. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808117-123522

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chung, Chen-Chia. “Error-Tolerability Enhancement for Videos by Adaptive I-Frame Insertion.” 2017. Thesis, NSYSU. Accessed February 23, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808117-123522.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chung, Chen-Chia. “Error-Tolerability Enhancement for Videos by Adaptive I-Frame Insertion.” 2017. Web. 23 Feb 2020.

Vancouver:

Chung C. Error-Tolerability Enhancement for Videos by Adaptive I-Frame Insertion. [Internet] [Thesis]. NSYSU; 2017. [cited 2020 Feb 23]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808117-123522.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chung C. Error-Tolerability Enhancement for Videos by Adaptive I-Frame Insertion. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808117-123522

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

7. Chung, Yu-Min. Efficient Noise Detection and Elimination Method for Voice Recognition Applications.

Degree: Master, Electrical Engineering, 2017, NSYSU

 In recent years, voice recognition has been widely used in many smart home and smart phone applications. By recognizing human beingâs voices, more convenient operations… (more)

Subjects/Keywords: additive Gaussian white noise (AWGN); quality improvement; voice recognition; noise elimination; noise detection

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chung, Y. (2017). Efficient Noise Detection and Elimination Method for Voice Recognition Applications. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0812117-095430

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chung, Yu-Min. “Efficient Noise Detection and Elimination Method for Voice Recognition Applications.” 2017. Thesis, NSYSU. Accessed February 23, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0812117-095430.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chung, Yu-Min. “Efficient Noise Detection and Elimination Method for Voice Recognition Applications.” 2017. Web. 23 Feb 2020.

Vancouver:

Chung Y. Efficient Noise Detection and Elimination Method for Voice Recognition Applications. [Internet] [Thesis]. NSYSU; 2017. [cited 2020 Feb 23]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0812117-095430.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chung Y. Efficient Noise Detection and Elimination Method for Voice Recognition Applications. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0812117-095430

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

8. Cheng, Tai-ang. Error-Tolerability Test and Enhancement Methods for Images in Face Detection Applications.

Degree: Master, Electrical Engineering, 2017, NSYSU

 Face detection is mainly used to determinate wherther the face in the image can be detected or not. Accordingly the identity of the person can… (more)

Subjects/Keywords: error-tolerance; face detection; image repair; image processing; image qulity evaluation

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Cheng, T. (2017). Error-Tolerability Test and Enhancement Methods for Images in Face Detection Applications. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811117-180159

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Cheng, Tai-ang. “Error-Tolerability Test and Enhancement Methods for Images in Face Detection Applications.” 2017. Thesis, NSYSU. Accessed February 23, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811117-180159.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Cheng, Tai-ang. “Error-Tolerability Test and Enhancement Methods for Images in Face Detection Applications.” 2017. Web. 23 Feb 2020.

Vancouver:

Cheng T. Error-Tolerability Test and Enhancement Methods for Images in Face Detection Applications. [Internet] [Thesis]. NSYSU; 2017. [cited 2020 Feb 23]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811117-180159.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Cheng T. Error-Tolerability Test and Enhancement Methods for Images in Face Detection Applications. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811117-180159

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

9. Chan, Shang-En. An Efficient No-Reference Error-Tolerability Test Method for Videos.

Degree: Master, Electrical Engineering, 2017, NSYSU

 Since the IoT (Internet of Things) and home security is more and more common as technology progresses, the security that can be provided by surveillance… (more)

Subjects/Keywords: video processing circuits; video quality evaluation; no-reference quality assessment; erroneous video; error-tolerance

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chan, S. (2017). An Efficient No-Reference Error-Tolerability Test Method for Videos. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811117-180509

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chan, Shang-En. “An Efficient No-Reference Error-Tolerability Test Method for Videos.” 2017. Thesis, NSYSU. Accessed February 23, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811117-180509.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chan, Shang-En. “An Efficient No-Reference Error-Tolerability Test Method for Videos.” 2017. Web. 23 Feb 2020.

Vancouver:

Chan S. An Efficient No-Reference Error-Tolerability Test Method for Videos. [Internet] [Thesis]. NSYSU; 2017. [cited 2020 Feb 23]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811117-180509.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chan S. An Efficient No-Reference Error-Tolerability Test Method for Videos. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811117-180509

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

10. Liou, Yu-Ting. Design and Implementation of Wireless Sensor Network Architecture with Optimizing Energy Management Strategy.

Degree: Master, Electrical Engineering, 2013, NSYSU

 With the advances and integration of wireless communications, embedded microprocessors and battery technology, the application of wireless sensor network (WSN) has become diversified and widely… (more)

Subjects/Keywords: routing path; network topology; AODV; embedded microprocessors; wireless sensor networks

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Liou, Y. (2013). Design and Implementation of Wireless Sensor Network Architecture with Optimizing Energy Management Strategy. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0721113-011151

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Liou, Yu-Ting. “Design and Implementation of Wireless Sensor Network Architecture with Optimizing Energy Management Strategy.” 2013. Thesis, NSYSU. Accessed February 23, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0721113-011151.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Liou, Yu-Ting. “Design and Implementation of Wireless Sensor Network Architecture with Optimizing Energy Management Strategy.” 2013. Web. 23 Feb 2020.

Vancouver:

Liou Y. Design and Implementation of Wireless Sensor Network Architecture with Optimizing Energy Management Strategy. [Internet] [Thesis]. NSYSU; 2013. [cited 2020 Feb 23]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0721113-011151.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Liou Y. Design and Implementation of Wireless Sensor Network Architecture with Optimizing Energy Management Strategy. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0721113-011151

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

11. Wang, Sheng-Hao. An Integrated Development Platform for Heterogeneous Multicore Constructed on Windows CE Operating System.

Degree: Master, Electrical Engineering, 2013, NSYSU

 Heterogeneous multicore systems with highly parallel computing are the significant trends for being used to improve the performances of processors in computing. They are provided… (more)

Subjects/Keywords: Synchronous machanism; DSP; Heterogeneous; Driver; WinCE

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wang, S. (2013). An Integrated Development Platform for Heterogeneous Multicore Constructed on Windows CE Operating System. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725113-211646

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wang, Sheng-Hao. “An Integrated Development Platform for Heterogeneous Multicore Constructed on Windows CE Operating System.” 2013. Thesis, NSYSU. Accessed February 23, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725113-211646.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wang, Sheng-Hao. “An Integrated Development Platform for Heterogeneous Multicore Constructed on Windows CE Operating System.” 2013. Web. 23 Feb 2020.

Vancouver:

Wang S. An Integrated Development Platform for Heterogeneous Multicore Constructed on Windows CE Operating System. [Internet] [Thesis]. NSYSU; 2013. [cited 2020 Feb 23]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725113-211646.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wang S. An Integrated Development Platform for Heterogeneous Multicore Constructed on Windows CE Operating System. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725113-211646

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

12. KU, CHIA-CHI. A Yield and Reliability Improvement Methodology and Its Hardware Design for Image Processing Circuits Applications.

Degree: Master, Electrical Engineering, 2013, NSYSU

 With the shrinking of the feature size of transistors, chips become more sensible to manufacturing defects and/or external noises, which may cause low manufacturing yield.… (more)

Subjects/Keywords: yield improvement; VLSI testing; error-tolerance; built-in self-test; image enhancement

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

KU, C. (2013). A Yield and Reliability Improvement Methodology and Its Hardware Design for Image Processing Circuits Applications. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726113-181850

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

KU, CHIA-CHI. “A Yield and Reliability Improvement Methodology and Its Hardware Design for Image Processing Circuits Applications.” 2013. Thesis, NSYSU. Accessed February 23, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726113-181850.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

KU, CHIA-CHI. “A Yield and Reliability Improvement Methodology and Its Hardware Design for Image Processing Circuits Applications.” 2013. Web. 23 Feb 2020.

Vancouver:

KU C. A Yield and Reliability Improvement Methodology and Its Hardware Design for Image Processing Circuits Applications. [Internet] [Thesis]. NSYSU; 2013. [cited 2020 Feb 23]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726113-181850.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

KU C. A Yield and Reliability Improvement Methodology and Its Hardware Design for Image Processing Circuits Applications. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726113-181850

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

13. Huang, Yin-jou. Design of the Optimized Group Management Unit by Detecting Thread Parallelism on the Hyperscalar Architecture.

Degree: Master, Electrical Engineering, 2013, NSYSU

 Current trends in processor design have migrated toward chip multiprocessors (CMPs). CMPs are designed to exploit both instruction-level parallelism (ILP) within processors and thread-level parallelism… (more)

Subjects/Keywords: superscalar; hyper-scalar; chip multiprocessors; reconfigure; ILP

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Huang, Y. (2013). Design of the Optimized Group Management Unit by Detecting Thread Parallelism on the Hyperscalar Architecture. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726113-030940

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Huang, Yin-jou. “Design of the Optimized Group Management Unit by Detecting Thread Parallelism on the Hyperscalar Architecture.” 2013. Thesis, NSYSU. Accessed February 23, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726113-030940.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Huang, Yin-jou. “Design of the Optimized Group Management Unit by Detecting Thread Parallelism on the Hyperscalar Architecture.” 2013. Web. 23 Feb 2020.

Vancouver:

Huang Y. Design of the Optimized Group Management Unit by Detecting Thread Parallelism on the Hyperscalar Architecture. [Internet] [Thesis]. NSYSU; 2013. [cited 2020 Feb 23]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726113-030940.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Huang Y. Design of the Optimized Group Management Unit by Detecting Thread Parallelism on the Hyperscalar Architecture. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726113-030940

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

14. Wang, Zih-Ang. Design and Implementation of the Optimized Architecture for Modbus and DNP 3.0 on the CAN Bus.

Degree: Master, Electrical Engineering, 2013, NSYSU

 The CAN bus uses the message identifier as a priority by-bit arbitration mechanism, message can be delivered within a limited delay, suitable for use in… (more)

Subjects/Keywords: Controller Area Network; Modbus and DNP3 Protocol on the CAN Bus; Automation Network; SCADA Area Network; CAN-to-TCP/IP on Ethernet Gateway

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wang, Z. (2013). Design and Implementation of the Optimized Architecture for Modbus and DNP 3.0 on the CAN Bus. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725113-235040

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wang, Zih-Ang. “Design and Implementation of the Optimized Architecture for Modbus and DNP 3.0 on the CAN Bus.” 2013. Thesis, NSYSU. Accessed February 23, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725113-235040.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wang, Zih-Ang. “Design and Implementation of the Optimized Architecture for Modbus and DNP 3.0 on the CAN Bus.” 2013. Web. 23 Feb 2020.

Vancouver:

Wang Z. Design and Implementation of the Optimized Architecture for Modbus and DNP 3.0 on the CAN Bus. [Internet] [Thesis]. NSYSU; 2013. [cited 2020 Feb 23]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725113-235040.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wang Z. Design and Implementation of the Optimized Architecture for Modbus and DNP 3.0 on the CAN Bus. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725113-235040

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

15. Kao, Tien-Tsai. Error Tolerability Analysis and Error-Tolerant Design Investigation of A JPEG2000 Image Encoder.

Degree: Master, Electrical Engineering, 2013, NSYSU

 JPEG2000 is a new image compression standard formulated by Joint Photographic Experts Group in 2000. There are two modes for image compression in JPEG2000 standard:… (more)

Subjects/Keywords: quantization; acceptability of faults; error tolerance; yield; discrete wavelet transform; JPEG2000

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kao, T. (2013). Error Tolerability Analysis and Error-Tolerant Design Investigation of A JPEG2000 Image Encoder. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0805113-011126

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kao, Tien-Tsai. “Error Tolerability Analysis and Error-Tolerant Design Investigation of A JPEG2000 Image Encoder.” 2013. Thesis, NSYSU. Accessed February 23, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0805113-011126.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kao, Tien-Tsai. “Error Tolerability Analysis and Error-Tolerant Design Investigation of A JPEG2000 Image Encoder.” 2013. Web. 23 Feb 2020.

Vancouver:

Kao T. Error Tolerability Analysis and Error-Tolerant Design Investigation of A JPEG2000 Image Encoder. [Internet] [Thesis]. NSYSU; 2013. [cited 2020 Feb 23]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0805113-011126.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kao T. Error Tolerability Analysis and Error-Tolerant Design Investigation of A JPEG2000 Image Encoder. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0805113-011126

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

16. Chi, Ya-Hsiu. Design and Analysis of A New Cache to Support Performance Degradation Tolerance.

Degree: Master, Electrical Engineering, 2013, NSYSU

 As the feature size of transistors becomes smaller, chip is more sensitive to external disturbances such as defects during the manufacturing process and process variation.… (more)

Subjects/Keywords: performance degrading fault; performance degradation tolerance; fault tolerance; cache; functionality fault; performance fault

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chi, Y. (2013). Design and Analysis of A New Cache to Support Performance Degradation Tolerance. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0810113-160440

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chi, Ya-Hsiu. “Design and Analysis of A New Cache to Support Performance Degradation Tolerance.” 2013. Thesis, NSYSU. Accessed February 23, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0810113-160440.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chi, Ya-Hsiu. “Design and Analysis of A New Cache to Support Performance Degradation Tolerance.” 2013. Web. 23 Feb 2020.

Vancouver:

Chi Y. Design and Analysis of A New Cache to Support Performance Degradation Tolerance. [Internet] [Thesis]. NSYSU; 2013. [cited 2020 Feb 23]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0810113-160440.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chi Y. Design and Analysis of A New Cache to Support Performance Degradation Tolerance. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0810113-160440

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

17. DOW, HSU-KANG. A Simulator for a Novel GPU to Support the Verifying and Profiling in Real World Applications.

Degree: Master, Computer Science and Engineering, 2014, NSYSU

 This is a simulator created base on Attila, a modern GPU architecture and open source project with the power to run games and benchmarks. This… (more)

Subjects/Keywords: GPU; OpenGL ES; GLSL ES; Simulator; Attila

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

DOW, H. (2014). A Simulator for a Novel GPU to Support the Verifying and Profiling in Real World Applications. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0027114-173404

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

DOW, HSU-KANG. “A Simulator for a Novel GPU to Support the Verifying and Profiling in Real World Applications.” 2014. Thesis, NSYSU. Accessed February 23, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0027114-173404.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

DOW, HSU-KANG. “A Simulator for a Novel GPU to Support the Verifying and Profiling in Real World Applications.” 2014. Web. 23 Feb 2020.

Vancouver:

DOW H. A Simulator for a Novel GPU to Support the Verifying and Profiling in Real World Applications. [Internet] [Thesis]. NSYSU; 2014. [cited 2020 Feb 23]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0027114-173404.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

DOW H. A Simulator for a Novel GPU to Support the Verifying and Profiling in Real World Applications. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0027114-173404

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

18. Chen, Ting-An. A Tool for Static WCET Analysis with Accurate Memory Modeling for ARM Programs that Use Scratchpad Memory.

Degree: Master, Computer Science and Engineering, 2014, NSYSU

 In order to guarantee the reliability of the real-time system, each process should be complete before the deadline. Therefore, providing accurate WCET for scheduler would… (more)

Subjects/Keywords: WCET; memory module; SPM; SWEET; ARM

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chen, T. (2014). A Tool for Static WCET Analysis with Accurate Memory Modeling for ARM Programs that Use Scratchpad Memory. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0211114-131015

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chen, Ting-An. “A Tool for Static WCET Analysis with Accurate Memory Modeling for ARM Programs that Use Scratchpad Memory.” 2014. Thesis, NSYSU. Accessed February 23, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0211114-131015.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chen, Ting-An. “A Tool for Static WCET Analysis with Accurate Memory Modeling for ARM Programs that Use Scratchpad Memory.” 2014. Web. 23 Feb 2020.

Vancouver:

Chen T. A Tool for Static WCET Analysis with Accurate Memory Modeling for ARM Programs that Use Scratchpad Memory. [Internet] [Thesis]. NSYSU; 2014. [cited 2020 Feb 23]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0211114-131015.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen T. A Tool for Static WCET Analysis with Accurate Memory Modeling for ARM Programs that Use Scratchpad Memory. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0211114-131015

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

19. Chen, Rou-Jia. A Study of the Limits of Parallelism Available in SIMD Processors Through Register Packing.

Degree: Master, Computer Science and Engineering, 2014, NSYSU

 This thesis designed an instruction-level-parallelism processor for the embedded system with general purpose computations. The hardware of the embedded system is small-scalar then currently popular… (more)

Subjects/Keywords: register allocation; loop unrolling; SIMD and vector processing; instruction scheduling

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chen, R. (2014). A Study of the Limits of Parallelism Available in SIMD Processors Through Register Packing. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0224114-122630

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chen, Rou-Jia. “A Study of the Limits of Parallelism Available in SIMD Processors Through Register Packing.” 2014. Thesis, NSYSU. Accessed February 23, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0224114-122630.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chen, Rou-Jia. “A Study of the Limits of Parallelism Available in SIMD Processors Through Register Packing.” 2014. Web. 23 Feb 2020.

Vancouver:

Chen R. A Study of the Limits of Parallelism Available in SIMD Processors Through Register Packing. [Internet] [Thesis]. NSYSU; 2014. [cited 2020 Feb 23]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0224114-122630.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen R. A Study of the Limits of Parallelism Available in SIMD Processors Through Register Packing. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0224114-122630

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

20. Wu, Yi-lun. A High Voltage Operational Amplifier with Rail-to-rail Input and Output Ranges and an 8:1 Analog High Voltage Multiplexer.

Degree: Master, Electrical Engineering, 2014, NSYSU

 One of the key techniques of electric vehicles (EVs) is battery management systems, which demand the development of battery modules, the measurement circuits of batteries,… (more)

Subjects/Keywords: high-voltage amplifier; high-voltage switch; high-voltage analog multiplexer; battery management system; rail-to-rail input and output ranges

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wu, Y. (2014). A High Voltage Operational Amplifier with Rail-to-rail Input and Output Ranges and an 8:1 Analog High Voltage Multiplexer. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0614114-133104

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wu, Yi-lun. “A High Voltage Operational Amplifier with Rail-to-rail Input and Output Ranges and an 8:1 Analog High Voltage Multiplexer.” 2014. Thesis, NSYSU. Accessed February 23, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0614114-133104.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wu, Yi-lun. “A High Voltage Operational Amplifier with Rail-to-rail Input and Output Ranges and an 8:1 Analog High Voltage Multiplexer.” 2014. Web. 23 Feb 2020.

Vancouver:

Wu Y. A High Voltage Operational Amplifier with Rail-to-rail Input and Output Ranges and an 8:1 Analog High Voltage Multiplexer. [Internet] [Thesis]. NSYSU; 2014. [cited 2020 Feb 23]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0614114-133104.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wu Y. A High Voltage Operational Amplifier with Rail-to-rail Input and Output Ranges and an 8:1 Analog High Voltage Multiplexer. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0614114-133104

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

21. Hou, Zong-you. Transmitter with Over-Voltage Protection and Bus Driver Controller with Hazard Detection for FlexRay Systems.

Degree: Master, Electrical Engineering, 2014, NSYSU

 FlexRay is a high-speed automotive bus standard designed to integrate ECUs, sensors, and discretes within an in-car network. The research of this thesis is mainly… (more)

Subjects/Keywords: Bus Driver (BD); state transition; hazard detection; FlexRay transmitter; over-voltage detector

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hou, Z. (2014). Transmitter with Over-Voltage Protection and Bus Driver Controller with Hazard Detection for FlexRay Systems. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0614114-163105

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hou, Zong-you. “Transmitter with Over-Voltage Protection and Bus Driver Controller with Hazard Detection for FlexRay Systems.” 2014. Thesis, NSYSU. Accessed February 23, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0614114-163105.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hou, Zong-you. “Transmitter with Over-Voltage Protection and Bus Driver Controller with Hazard Detection for FlexRay Systems.” 2014. Web. 23 Feb 2020.

Vancouver:

Hou Z. Transmitter with Over-Voltage Protection and Bus Driver Controller with Hazard Detection for FlexRay Systems. [Internet] [Thesis]. NSYSU; 2014. [cited 2020 Feb 23]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0614114-163105.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hou Z. Transmitter with Over-Voltage Protection and Bus Driver Controller with Hazard Detection for FlexRay Systems. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0614114-163105

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

22. Tsai, Tsung-Yi. A Process Compensation and Non-linear Calibration Temperature Detector and A Hysteresis Current-Controlled Boost Converter for Battery Management Systems.

Degree: Master, Electrical Engineering, 2014, NSYSU

 The reaserch in the thesis is mainly associated with Battery Management Systems (BMS) in Electronic Vehicles(EV), especially regarding thermal sensor and boost converter design. In… (more)

Subjects/Keywords: temperature detector; non-linear calibration; hysteresis; boost converter

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Tsai, T. (2014). A Process Compensation and Non-linear Calibration Temperature Detector and A Hysteresis Current-Controlled Boost Converter for Battery Management Systems. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0614114-135226

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Tsai, Tsung-Yi. “A Process Compensation and Non-linear Calibration Temperature Detector and A Hysteresis Current-Controlled Boost Converter for Battery Management Systems.” 2014. Thesis, NSYSU. Accessed February 23, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0614114-135226.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Tsai, Tsung-Yi. “A Process Compensation and Non-linear Calibration Temperature Detector and A Hysteresis Current-Controlled Boost Converter for Battery Management Systems.” 2014. Web. 23 Feb 2020.

Vancouver:

Tsai T. A Process Compensation and Non-linear Calibration Temperature Detector and A Hysteresis Current-Controlled Boost Converter for Battery Management Systems. [Internet] [Thesis]. NSYSU; 2014. [cited 2020 Feb 23]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0614114-135226.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tsai T. A Process Compensation and Non-linear Calibration Temperature Detector and A Hysteresis Current-Controlled Boost Converter for Battery Management Systems. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0614114-135226

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

23. Wu, Tzu-chao. A Temperature Sensor with Second-Order Calibration and Process Compensation and All Digital Estimator for Battery State of Charge.

Degree: Master, Communications Engineering, 2014, NSYSU

 Battery management is one of the most important technologies for electric vehicles, since it is highly critical to safety. Notably, temperature sensors are needed to… (more)

Subjects/Keywords: temperature sensor; second-order effects; PTAT sensor; CTAT sensor; coulomb counting method; open circuit voltage method; state of charge; second-order calibration

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wu, T. (2014). A Temperature Sensor with Second-Order Calibration and Process Compensation and All Digital Estimator for Battery State of Charge. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0614114-134817

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wu, Tzu-chao. “A Temperature Sensor with Second-Order Calibration and Process Compensation and All Digital Estimator for Battery State of Charge.” 2014. Thesis, NSYSU. Accessed February 23, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0614114-134817.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wu, Tzu-chao. “A Temperature Sensor with Second-Order Calibration and Process Compensation and All Digital Estimator for Battery State of Charge.” 2014. Web. 23 Feb 2020.

Vancouver:

Wu T. A Temperature Sensor with Second-Order Calibration and Process Compensation and All Digital Estimator for Battery State of Charge. [Internet] [Thesis]. NSYSU; 2014. [cited 2020 Feb 23]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0614114-134817.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wu T. A Temperature Sensor with Second-Order Calibration and Process Compensation and All Digital Estimator for Battery State of Charge. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0614114-134817

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

24. Lu, Yao-Ta. Design of Low-cost BVH Construction Circuit for Ray Tracing based on Surface Area Heuristic Metric.

Degree: Master, Computer Science and Engineering, 2014, NSYSU

 The acceleration of tree construction is a very important issue for real-time ray-tracing of dynamic scenes. This paper presents a low-cost design of bounding volume… (more)

Subjects/Keywords: ray-tracing; BVH; computer graphics; BVH tree construction; ray-tracing hardware

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lu, Y. (2014). Design of Low-cost BVH Construction Circuit for Ray Tracing based on Surface Area Heuristic Metric. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0627114-221628

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lu, Yao-Ta. “Design of Low-cost BVH Construction Circuit for Ray Tracing based on Surface Area Heuristic Metric.” 2014. Thesis, NSYSU. Accessed February 23, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0627114-221628.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lu, Yao-Ta. “Design of Low-cost BVH Construction Circuit for Ray Tracing based on Surface Area Heuristic Metric.” 2014. Web. 23 Feb 2020.

Vancouver:

Lu Y. Design of Low-cost BVH Construction Circuit for Ray Tracing based on Surface Area Heuristic Metric. [Internet] [Thesis]. NSYSU; 2014. [cited 2020 Feb 23]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0627114-221628.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lu Y. Design of Low-cost BVH Construction Circuit for Ray Tracing based on Surface Area Heuristic Metric. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0627114-221628

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

25. Feng, Hao. A Memory-Efficient and Low-power Architecture for Tail-biting Convolution Code Decoder.

Degree: Master, Computer Science and Engineering, 2014, NSYSU

 In wireless communication system, the data will be interfered easily with noise during transmission, thus the transmitter usually uses convolution code to encode the data.… (more)

Subjects/Keywords: pre-traceback; low power; wireless communication; error detection; tail-biting convolutional code; Viterbi decoder

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Feng, H. (2014). A Memory-Efficient and Low-power Architecture for Tail-biting Convolution Code Decoder. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0715114-133649

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Feng, Hao. “A Memory-Efficient and Low-power Architecture for Tail-biting Convolution Code Decoder.” 2014. Thesis, NSYSU. Accessed February 23, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0715114-133649.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Feng, Hao. “A Memory-Efficient and Low-power Architecture for Tail-biting Convolution Code Decoder.” 2014. Web. 23 Feb 2020.

Vancouver:

Feng H. A Memory-Efficient and Low-power Architecture for Tail-biting Convolution Code Decoder. [Internet] [Thesis]. NSYSU; 2014. [cited 2020 Feb 23]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0715114-133649.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Feng H. A Memory-Efficient and Low-power Architecture for Tail-biting Convolution Code Decoder. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0715114-133649

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

26. Lu, Ren-yao. High-performance High-radix Word-based Montgomery Modular Multipliers.

Degree: Master, Computer Science and Engineering, 2014, NSYSU

 Nowadays, with the evolution of the internet,network becomes an important role in human's life. Because more and more E-commerce and electronic transaction are implemented in… (more)

Subjects/Keywords: Public-key Cryptosystems; RSA Cryptosystems; High-radix Word-based Montgomery Modular Multiplier; Montgomery Modular Multiplier

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lu, R. (2014). High-performance High-radix Word-based Montgomery Modular Multipliers. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0718114-165103

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lu, Ren-yao. “High-performance High-radix Word-based Montgomery Modular Multipliers.” 2014. Thesis, NSYSU. Accessed February 23, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0718114-165103.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lu, Ren-yao. “High-performance High-radix Word-based Montgomery Modular Multipliers.” 2014. Web. 23 Feb 2020.

Vancouver:

Lu R. High-performance High-radix Word-based Montgomery Modular Multipliers. [Internet] [Thesis]. NSYSU; 2014. [cited 2020 Feb 23]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0718114-165103.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lu R. High-performance High-radix Word-based Montgomery Modular Multipliers. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0718114-165103

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

27. yang, Ho-chun. Design and Implementation of a Multi-core Graphic Processing Unit based on SIMT Architecture.

Degree: Master, Computer Science and Engineering, 2014, NSYSU

 With the increasing demand of embedded graphic processing unit (GPU), how to develop an efficient GPU has become more and more important. This thesis proposed… (more)

Subjects/Keywords: Unified GPU; Multithreading; Branch divergence; Multi-core; SIMT

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

yang, H. (2014). Design and Implementation of a Multi-core Graphic Processing Unit based on SIMT Architecture. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728114-141237

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

yang, Ho-chun. “Design and Implementation of a Multi-core Graphic Processing Unit based on SIMT Architecture.” 2014. Thesis, NSYSU. Accessed February 23, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728114-141237.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

yang, Ho-chun. “Design and Implementation of a Multi-core Graphic Processing Unit based on SIMT Architecture.” 2014. Web. 23 Feb 2020.

Vancouver:

yang H. Design and Implementation of a Multi-core Graphic Processing Unit based on SIMT Architecture. [Internet] [Thesis]. NSYSU; 2014. [cited 2020 Feb 23]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728114-141237.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

yang H. Design and Implementation of a Multi-core Graphic Processing Unit based on SIMT Architecture. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728114-141237

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

28. Lin, Chin-li. A Method for Automatically Creating and Using Billboards to Increase the Speed of Object Rendering.

Degree: Master, Computer Science and Engineering, 2014, NSYSU

 Although the rendering speed of modern GPUs is dramatically improved, it is still not fast enough for some applications such as real time rendering and… (more)

Subjects/Keywords: GPU; hardware; billboard; impostor

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lin, C. (2014). A Method for Automatically Creating and Using Billboards to Increase the Speed of Object Rendering. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1105114-155402

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lin, Chin-li. “A Method for Automatically Creating and Using Billboards to Increase the Speed of Object Rendering.” 2014. Thesis, NSYSU. Accessed February 23, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1105114-155402.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lin, Chin-li. “A Method for Automatically Creating and Using Billboards to Increase the Speed of Object Rendering.” 2014. Web. 23 Feb 2020.

Vancouver:

Lin C. A Method for Automatically Creating and Using Billboards to Increase the Speed of Object Rendering. [Internet] [Thesis]. NSYSU; 2014. [cited 2020 Feb 23]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1105114-155402.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lin C. A Method for Automatically Creating and Using Billboards to Increase the Speed of Object Rendering. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1105114-155402

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

29. Lai, Yu-Long. Implementation of Core Element for Hyper-scalar Architecture.

Degree: Master, Electrical Engineering, 2016, NSYSU

 To meet the needs of a diverse range of programs and workloads, the design of multi-core processors is a major issue. Asymmetric multi-core processors (AMPs)… (more)

Subjects/Keywords: out-of-order; reconfigurable; hyper-scalar; in-order commit; Asymmetric multicore processors

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lai, Y. (2016). Implementation of Core Element for Hyper-scalar Architecture. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0719116-164809

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lai, Yu-Long. “Implementation of Core Element for Hyper-scalar Architecture.” 2016. Thesis, NSYSU. Accessed February 23, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0719116-164809.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lai, Yu-Long. “Implementation of Core Element for Hyper-scalar Architecture.” 2016. Web. 23 Feb 2020.

Vancouver:

Lai Y. Implementation of Core Element for Hyper-scalar Architecture. [Internet] [Thesis]. NSYSU; 2016. [cited 2020 Feb 23]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0719116-164809.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lai Y. Implementation of Core Element for Hyper-scalar Architecture. [Thesis]. NSYSU; 2016. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0719116-164809

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

30. Guo, Bao-Ren. Implementation of MPI Cloud Computing Platform Build upon System Kernel Environment.

Degree: Master, Electrical Engineering, 2016, NSYSU

 With the age of Big Data coming, the three defining characteristics of Big Data – Volume, variety and Velocity, make Cloud Computing facing new challenges. In… (more)

Subjects/Keywords: MPI; Big Data; Kernel Driver; Distributed Computing Cluster; Cloud Computing

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Guo, B. (2016). Implementation of MPI Cloud Computing Platform Build upon System Kernel Environment. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0721116-203822

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Guo, Bao-Ren. “Implementation of MPI Cloud Computing Platform Build upon System Kernel Environment.” 2016. Thesis, NSYSU. Accessed February 23, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0721116-203822.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Guo, Bao-Ren. “Implementation of MPI Cloud Computing Platform Build upon System Kernel Environment.” 2016. Web. 23 Feb 2020.

Vancouver:

Guo B. Implementation of MPI Cloud Computing Platform Build upon System Kernel Environment. [Internet] [Thesis]. NSYSU; 2016. [cited 2020 Feb 23]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0721116-203822.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Guo B. Implementation of MPI Cloud Computing Platform Build upon System Kernel Environment. [Thesis]. NSYSU; 2016. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0721116-203822

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

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