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You searched for +publisher:"NSYSU" +contributor:("Sying-Jyan Wang"). Showing records 1 – 14 of 14 total matches.

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NSYSU

1. Wang, Ching-lin. FlexRay Automotive Communication System Physical Layer Chip Design and A High Efficiency DC/DC Buck Converter with Sub-3 Ã VDD.

Degree: Master, Electrical Engineering, 2009, NSYSU

 This thesis comprises two topics : the first one is the design and implementation of FlexRay automotive communication system physical layer. The second part is… (more)

Subjects/Keywords: Buck converter; DC/DC; Physical layer; FlexRay; Automotive communication system

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wang, C. (2009). FlexRay Automotive Communication System Physical Layer Chip Design and A High Efficiency DC/DC Buck Converter with Sub-3 Ã VDD. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0701109-200715

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wang, Ching-lin. “FlexRay Automotive Communication System Physical Layer Chip Design and A High Efficiency DC/DC Buck Converter with Sub-3 Ã VDD.” 2009. Thesis, NSYSU. Accessed March 31, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0701109-200715.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wang, Ching-lin. “FlexRay Automotive Communication System Physical Layer Chip Design and A High Efficiency DC/DC Buck Converter with Sub-3 Ã VDD.” 2009. Web. 31 Mar 2020.

Vancouver:

Wang C. FlexRay Automotive Communication System Physical Layer Chip Design and A High Efficiency DC/DC Buck Converter with Sub-3 Ã VDD. [Internet] [Thesis]. NSYSU; 2009. [cited 2020 Mar 31]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0701109-200715.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wang C. FlexRay Automotive Communication System Physical Layer Chip Design and A High Efficiency DC/DC Buck Converter with Sub-3 Ã VDD. [Thesis]. NSYSU; 2009. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0701109-200715

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

2. Liu, Yi-cheng. Mixed-Voltage-Tolerant I/O Cell With Dynamic Biasing and Sub 3ÃVDD Wide Range Mixed-Voltage-Tolerant I/O Cell.

Degree: Master, Electrical Engineering, 2009, NSYSU

 The thesis is composed of tow topics: a fully bidirectional mixed- voltage-tolerant I/O cell using a new output stage circuit and a sub-3ÃVDD wide range… (more)

Subjects/Keywords: I/O cell; Mixed-Voltage-Tolerant; Dynamic Biasing; Sub 3ÃVDD

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APA (6th Edition):

Liu, Y. (2009). Mixed-Voltage-Tolerant I/O Cell With Dynamic Biasing and Sub 3ÃVDD Wide Range Mixed-Voltage-Tolerant I/O Cell. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0701109-205501

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Liu, Yi-cheng. “Mixed-Voltage-Tolerant I/O Cell With Dynamic Biasing and Sub 3ÃVDD Wide Range Mixed-Voltage-Tolerant I/O Cell.” 2009. Thesis, NSYSU. Accessed March 31, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0701109-205501.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Liu, Yi-cheng. “Mixed-Voltage-Tolerant I/O Cell With Dynamic Biasing and Sub 3ÃVDD Wide Range Mixed-Voltage-Tolerant I/O Cell.” 2009. Web. 31 Mar 2020.

Vancouver:

Liu Y. Mixed-Voltage-Tolerant I/O Cell With Dynamic Biasing and Sub 3ÃVDD Wide Range Mixed-Voltage-Tolerant I/O Cell. [Internet] [Thesis]. NSYSU; 2009. [cited 2020 Mar 31]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0701109-205501.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Liu Y. Mixed-Voltage-Tolerant I/O Cell With Dynamic Biasing and Sub 3ÃVDD Wide Range Mixed-Voltage-Tolerant I/O Cell. [Thesis]. NSYSU; 2009. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0701109-205501

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

3. Yen, Shao-Fu. A Charger Circuit of Li-ion Batteries and a Capacitor-less LDO for Wireless Biomedical Systems.

Degree: Master, Electrical Engineering, 2009, NSYSU

 The thesis is composed of two topics : a charger circuit of Li-ion batteries for wireless biomedical systems and a capacitor-less low dropout regulatorï¼LDOï¼. The… (more)

Subjects/Keywords: regulator; capacitor-less; Li-ion; ldo; biomedical

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Yen, S. (2009). A Charger Circuit of Li-ion Batteries and a Capacitor-less LDO for Wireless Biomedical Systems. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0706109-135451

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yen, Shao-Fu. “A Charger Circuit of Li-ion Batteries and a Capacitor-less LDO for Wireless Biomedical Systems.” 2009. Thesis, NSYSU. Accessed March 31, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0706109-135451.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yen, Shao-Fu. “A Charger Circuit of Li-ion Batteries and a Capacitor-less LDO for Wireless Biomedical Systems.” 2009. Web. 31 Mar 2020.

Vancouver:

Yen S. A Charger Circuit of Li-ion Batteries and a Capacitor-less LDO for Wireless Biomedical Systems. [Internet] [Thesis]. NSYSU; 2009. [cited 2020 Mar 31]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0706109-135451.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yen S. A Charger Circuit of Li-ion Batteries and a Capacitor-less LDO for Wireless Biomedical Systems. [Thesis]. NSYSU; 2009. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0706109-135451

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

4. Tseng, Shao-Bin. Design of One-Time Implantable SCS System SOC and Inter-chip Capacitance Coupling Circuit.

Degree: Master, Electrical Engineering, 2011, NSYSU

 The thesis is composed of two topics: A SOC design for one-time implantable spinal cord stimulation system ï¼SCSï¼, and the design of an inter-chip capacitance… (more)

Subjects/Keywords: bidirectional communication; capacitive coupling; multiple modes; SCS; high-speed data transceiver; ASK demodulator

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Tseng, S. (2011). Design of One-Time Implantable SCS System SOC and Inter-chip Capacitance Coupling Circuit. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0815111-233024

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Tseng, Shao-Bin. “Design of One-Time Implantable SCS System SOC and Inter-chip Capacitance Coupling Circuit.” 2011. Thesis, NSYSU. Accessed March 31, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0815111-233024.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Tseng, Shao-Bin. “Design of One-Time Implantable SCS System SOC and Inter-chip Capacitance Coupling Circuit.” 2011. Web. 31 Mar 2020.

Vancouver:

Tseng S. Design of One-Time Implantable SCS System SOC and Inter-chip Capacitance Coupling Circuit. [Internet] [Thesis]. NSYSU; 2011. [cited 2020 Mar 31]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0815111-233024.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tseng S. Design of One-Time Implantable SCS System SOC and Inter-chip Capacitance Coupling Circuit. [Thesis]. NSYSU; 2011. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0815111-233024

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

5. Yeh, Tai-Hao. A High Speed Transceiver Front-end Design with Fault Detection and Temperature Detector for FlexRay-based Automotive Communication Systems.

Degree: Master, Communications Engineering, 2011, NSYSU

 This thesis is composed of two parts: a high-speed transceiver front-end design with fault detection for FlexRay-based automative communication systems, and a temperature detector. In… (more)

Subjects/Keywords: FlexRay; transceiver; automobile electronics; failure detection; temperature detection

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Yeh, T. (2011). A High Speed Transceiver Front-end Design with Fault Detection and Temperature Detector for FlexRay-based Automotive Communication Systems. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0817111-152114

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yeh, Tai-Hao. “A High Speed Transceiver Front-end Design with Fault Detection and Temperature Detector for FlexRay-based Automotive Communication Systems.” 2011. Thesis, NSYSU. Accessed March 31, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0817111-152114.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yeh, Tai-Hao. “A High Speed Transceiver Front-end Design with Fault Detection and Temperature Detector for FlexRay-based Automotive Communication Systems.” 2011. Web. 31 Mar 2020.

Vancouver:

Yeh T. A High Speed Transceiver Front-end Design with Fault Detection and Temperature Detector for FlexRay-based Automotive Communication Systems. [Internet] [Thesis]. NSYSU; 2011. [cited 2020 Mar 31]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0817111-152114.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yeh T. A High Speed Transceiver Front-end Design with Fault Detection and Temperature Detector for FlexRay-based Automotive Communication Systems. [Thesis]. NSYSU; 2011. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0817111-152114

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

6. Lin, Yain-Reu. Low Power Half-Run RC5 Cipher Circuit for Portable Biomedical Device and A Frequency-Shift Readout Circuit for FPW-Based Biosensors.

Degree: Master, Electrical Engineering, 2011, NSYSU

 This thesis consists of two topics. We proposed a low power half-run RC5 cipher for portable biomedical devices in the first part of this thesis.… (more)

Subjects/Keywords: frequency-shift readout system; RC5; flexural plate wave; biomedical system; low power; ZigBee

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lin, Y. (2011). Low Power Half-Run RC5 Cipher Circuit for Portable Biomedical Device and A Frequency-Shift Readout Circuit for FPW-Based Biosensors. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808111-162539

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lin, Yain-Reu. “Low Power Half-Run RC5 Cipher Circuit for Portable Biomedical Device and A Frequency-Shift Readout Circuit for FPW-Based Biosensors.” 2011. Thesis, NSYSU. Accessed March 31, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808111-162539.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lin, Yain-Reu. “Low Power Half-Run RC5 Cipher Circuit for Portable Biomedical Device and A Frequency-Shift Readout Circuit for FPW-Based Biosensors.” 2011. Web. 31 Mar 2020.

Vancouver:

Lin Y. Low Power Half-Run RC5 Cipher Circuit for Portable Biomedical Device and A Frequency-Shift Readout Circuit for FPW-Based Biosensors. [Internet] [Thesis]. NSYSU; 2011. [cited 2020 Mar 31]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808111-162539.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lin Y. Low Power Half-Run RC5 Cipher Circuit for Portable Biomedical Device and A Frequency-Shift Readout Circuit for FPW-Based Biosensors. [Thesis]. NSYSU; 2011. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808111-162539

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

7. Hsueh, Ya-Hsin. IC Design and Implementation of Fast Bipolar Inner Product Processor and Analog to Digital Converter.

Degree: Master, Electrical Engineering, 2000, NSYSU

 This thesis is composed of three independent parts, which are respectively focused on three different applications. 1. A Circuit Design of Fast Bipolar Inner Product… (more)

Subjects/Keywords: Smart Battery Monitor Emulator System; Analog to Digital Converter; Fast Bipolar Inner Product Processor

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hsueh, Y. (2000). IC Design and Implementation of Fast Bipolar Inner Product Processor and Analog to Digital Converter. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0620100-231307

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hsueh, Ya-Hsin. “IC Design and Implementation of Fast Bipolar Inner Product Processor and Analog to Digital Converter.” 2000. Thesis, NSYSU. Accessed March 31, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0620100-231307.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hsueh, Ya-Hsin. “IC Design and Implementation of Fast Bipolar Inner Product Processor and Analog to Digital Converter.” 2000. Web. 31 Mar 2020.

Vancouver:

Hsueh Y. IC Design and Implementation of Fast Bipolar Inner Product Processor and Analog to Digital Converter. [Internet] [Thesis]. NSYSU; 2000. [cited 2020 Mar 31]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0620100-231307.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hsueh Y. IC Design and Implementation of Fast Bipolar Inner Product Processor and Analog to Digital Converter. [Thesis]. NSYSU; 2000. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0620100-231307

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

8. Wu, Hsin-Long. IC Design and Implementation of Fast Tagged Sorter and Dynamic 64-Bit Comparator.

Degree: Master, Electrical Engineering, 2000, NSYSU

 Three different topics associated with their respective applications are proposed in this thesis. The first application is the implementation of a fast tagged sorter. A… (more)

Subjects/Keywords: Tagged Sorter; Power Demand Monitor System; Comparator

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APA (6th Edition):

Wu, H. (2000). IC Design and Implementation of Fast Tagged Sorter and Dynamic 64-Bit Comparator. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0623100-173156

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wu, Hsin-Long. “IC Design and Implementation of Fast Tagged Sorter and Dynamic 64-Bit Comparator.” 2000. Thesis, NSYSU. Accessed March 31, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0623100-173156.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wu, Hsin-Long. “IC Design and Implementation of Fast Tagged Sorter and Dynamic 64-Bit Comparator.” 2000. Web. 31 Mar 2020.

Vancouver:

Wu H. IC Design and Implementation of Fast Tagged Sorter and Dynamic 64-Bit Comparator. [Internet] [Thesis]. NSYSU; 2000. [cited 2020 Mar 31]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0623100-173156.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wu H. IC Design and Implementation of Fast Tagged Sorter and Dynamic 64-Bit Comparator. [Thesis]. NSYSU; 2000. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0623100-173156

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

9. Chen, Ying-Pei. A Area-Saving ROM Decoder and Design of Network Interface Controller.

Degree: Master, Electrical Engineering, 2000, NSYSU

 The thesis is composed of two different IC design projects, which are briefly introduced as follows. The first topic is an area-saving decoder structure for… (more)

Subjects/Keywords: Network Interface Controller; A Area-Saving ROM Decoder

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chen, Y. (2000). A Area-Saving ROM Decoder and Design of Network Interface Controller. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0626100-134230

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chen, Ying-Pei. “A Area-Saving ROM Decoder and Design of Network Interface Controller.” 2000. Thesis, NSYSU. Accessed March 31, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0626100-134230.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chen, Ying-Pei. “A Area-Saving ROM Decoder and Design of Network Interface Controller.” 2000. Web. 31 Mar 2020.

Vancouver:

Chen Y. A Area-Saving ROM Decoder and Design of Network Interface Controller. [Internet] [Thesis]. NSYSU; 2000. [cited 2020 Mar 31]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0626100-134230.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen Y. A Area-Saving ROM Decoder and Design of Network Interface Controller. [Thesis]. NSYSU; 2000. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0626100-134230

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

10. Chien, Yu-Tsun. A Load-Optimized 500 MHz VCO Design for Phase-Locked Loop and Half-Swing PLA and The Applications for High-Speed Circuit Design.

Degree: Master, Electrical Engineering, 2000, NSYSU

 The first topic of this thesis is a practical load-optimized VCO design for low-jitter 5V 500 MHz digital phase-locked loop. Besides the low jitter advantage,… (more)

Subjects/Keywords: Half-Swing; Phase-Locked Loop

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chien, Y. (2000). A Load-Optimized 500 MHz VCO Design for Phase-Locked Loop and Half-Swing PLA and The Applications for High-Speed Circuit Design. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0627100-162514

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chien, Yu-Tsun. “A Load-Optimized 500 MHz VCO Design for Phase-Locked Loop and Half-Swing PLA and The Applications for High-Speed Circuit Design.” 2000. Thesis, NSYSU. Accessed March 31, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0627100-162514.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chien, Yu-Tsun. “A Load-Optimized 500 MHz VCO Design for Phase-Locked Loop and Half-Swing PLA and The Applications for High-Speed Circuit Design.” 2000. Web. 31 Mar 2020.

Vancouver:

Chien Y. A Load-Optimized 500 MHz VCO Design for Phase-Locked Loop and Half-Swing PLA and The Applications for High-Speed Circuit Design. [Internet] [Thesis]. NSYSU; 2000. [cited 2020 Mar 31]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0627100-162514.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chien Y. A Load-Optimized 500 MHz VCO Design for Phase-Locked Loop and Half-Swing PLA and The Applications for High-Speed Circuit Design. [Thesis]. NSYSU; 2000. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0627100-162514

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

11. Lin, Wun-Ji. A High Speed Phase Adjustable ROM-less DDFS and Low-Power SRAM Design.

Degree: Master, Electrical Engineering, 2004, NSYSU

 This thesis includes two topics. The first topic is a high speed phase adjustable ROM-less DDFS (Direct Digital Frequency Synthesizer). The second one is a… (more)

Subjects/Keywords: Low Power; SRAM; DDFS

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lin, W. (2004). A High Speed Phase Adjustable ROM-less DDFS and Low-Power SRAM Design. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0710104-220316

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lin, Wun-Ji. “A High Speed Phase Adjustable ROM-less DDFS and Low-Power SRAM Design.” 2004. Thesis, NSYSU. Accessed March 31, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0710104-220316.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lin, Wun-Ji. “A High Speed Phase Adjustable ROM-less DDFS and Low-Power SRAM Design.” 2004. Web. 31 Mar 2020.

Vancouver:

Lin W. A High Speed Phase Adjustable ROM-less DDFS and Low-Power SRAM Design. [Internet] [Thesis]. NSYSU; 2004. [cited 2020 Mar 31]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0710104-220316.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lin W. A High Speed Phase Adjustable ROM-less DDFS and Low-Power SRAM Design. [Thesis]. NSYSU; 2004. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0710104-220316

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

12. Lee, Tzung-Je. Low-Variation 1 MHz Clock Generator,High Sensitivity Linear Voltage-to-Frequency Converter,and High-PSR Bias Circuit for NTSC SYNC Separation.

Degree: Master, Electrical Engineering, 2004, NSYSU

 This thesis includes three topics. The first topic is a low-variation 1 MHz clock generator. The second one is a high sensitivity linear voltage-to-frequency converter.… (more)

Subjects/Keywords: NTSC SYNC separation; PSR; VFC; voltage-to-frequency converter; power supply rejection; clock generator

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lee, T. (2004). Low-Variation 1 MHz Clock Generator,High Sensitivity Linear Voltage-to-Frequency Converter,and High-PSR Bias Circuit for NTSC SYNC Separation. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0713104-153009

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lee, Tzung-Je. “Low-Variation 1 MHz Clock Generator,High Sensitivity Linear Voltage-to-Frequency Converter,and High-PSR Bias Circuit for NTSC SYNC Separation.” 2004. Thesis, NSYSU. Accessed March 31, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0713104-153009.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lee, Tzung-Je. “Low-Variation 1 MHz Clock Generator,High Sensitivity Linear Voltage-to-Frequency Converter,and High-PSR Bias Circuit for NTSC SYNC Separation.” 2004. Web. 31 Mar 2020.

Vancouver:

Lee T. Low-Variation 1 MHz Clock Generator,High Sensitivity Linear Voltage-to-Frequency Converter,and High-PSR Bias Circuit for NTSC SYNC Separation. [Internet] [Thesis]. NSYSU; 2004. [cited 2020 Mar 31]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0713104-153009.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lee T. Low-Variation 1 MHz Clock Generator,High Sensitivity Linear Voltage-to-Frequency Converter,and High-PSR Bias Circuit for NTSC SYNC Separation. [Thesis]. NSYSU; 2004. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0713104-153009

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

13. Chio, U-Fat. Analog Frontend of an Implantable Biological Nerve Micro-stimulation Chip.

Degree: Master, Communications Engineering, 2004, NSYSU

 An analog frontend of an implantable baseband SOC (System-on-a-chip) chip design for the interface of neural micro-stimulation is present in this thesis. The mentioned neural… (more)

Subjects/Keywords: Micro-stimulation

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chio, U. (2004). Analog Frontend of an Implantable Biological Nerve Micro-stimulation Chip. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0710104-232604

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chio, U-Fat. “Analog Frontend of an Implantable Biological Nerve Micro-stimulation Chip.” 2004. Thesis, NSYSU. Accessed March 31, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0710104-232604.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chio, U-Fat. “Analog Frontend of an Implantable Biological Nerve Micro-stimulation Chip.” 2004. Web. 31 Mar 2020.

Vancouver:

Chio U. Analog Frontend of an Implantable Biological Nerve Micro-stimulation Chip. [Internet] [Thesis]. NSYSU; 2004. [cited 2020 Mar 31]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0710104-232604.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chio U. Analog Frontend of an Implantable Biological Nerve Micro-stimulation Chip. [Thesis]. NSYSU; 2004. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0710104-232604

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

14. Huang, Chenn-Jung. Hardware Realization of Fast Arithmetic Elements for Signal Processing Applications.

Degree: PhD, Electrical Engineering, 2000, NSYSU

 Abstract The tremendous progress in all aspects of signal processing technology has naturally been accompanied by a corresponding development of arithmetic techniques to provide high-speed… (more)

Subjects/Keywords: Carry lookahead adder; integer divider; inner product processor

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Huang, C. (2000). Hardware Realization of Fast Arithmetic Elements for Signal Processing Applications. (Doctoral Dissertation). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0516100-103030

Chicago Manual of Style (16th Edition):

Huang, Chenn-Jung. “Hardware Realization of Fast Arithmetic Elements for Signal Processing Applications.” 2000. Doctoral Dissertation, NSYSU. Accessed March 31, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0516100-103030.

MLA Handbook (7th Edition):

Huang, Chenn-Jung. “Hardware Realization of Fast Arithmetic Elements for Signal Processing Applications.” 2000. Web. 31 Mar 2020.

Vancouver:

Huang C. Hardware Realization of Fast Arithmetic Elements for Signal Processing Applications. [Internet] [Doctoral dissertation]. NSYSU; 2000. [cited 2020 Mar 31]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0516100-103030.

Council of Science Editors:

Huang C. Hardware Realization of Fast Arithmetic Elements for Signal Processing Applications. [Doctoral Dissertation]. NSYSU; 2000. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0516100-103030

.